ICS8432BY-21LFT [IDT]
Clock Generator, 500MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32;
| 型号： | ICS8432BY-21LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 500MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32 时钟 外围集成电路 晶体 |
| 文件： | 总10页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
ICS8432-21
700/87.5MHZ, LOW PHASE NOISE
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8432-21 is a general purpose, dual out- • Fully integrated PLL
,&6
put high frequency synthesizer and a member of
• FOUT and FOUT/P differential 3.3V LVPECL outputs
HiPerClockS™
the HiPerClockS™ family of High Performance
Clocks Solutions from ICS. The VCO operates at
a frequency range of 250MHz to 700MHz. Out-
• FOUT frequency up to 700MHz
• FOUT/P frequency up to 175MHz
• Low phase noise
put frequencies up to 700MHz for FOUT and 175MHz for
FOUT/P can be programmed using the serial or parallel inter-
faces to the confiquration logic. The low phase noise and dual
output frequency range of the ICS8432-21 makes it an ideal
clock generator for Infiniband applications.
• Parallel interface for programming counter and VCO
frequency multiplier and dividers during power-up
• Serial 3 wire interface
• Selectable crystal oscillator interface and LVCMOS refer-
ence input
• LVCMOS control inputs
• 3.3V supply voltage
• 32 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.8mm package lead pitch
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
XTAL_SEL
REF_IN
0
32 31 30 29 28 27 26 25
XTAL1
1
OSC
M5
M6
M7
M8
N0
N1
P0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL1
XTAL2
REF_IN
XTAL_SEL
VDDA
ICS8432-21
PLL
S_LOAD
S_DATA
S_CLOCK
MR
PHASE DETECTOR
0
VCO
FOUT
VEE
÷ N
nFOUT
FOUT/P
nFOUT/P
÷ M
1
9
10 11 12 13 14 15 16
MR
÷P
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
Y Package
Top View
M0:M8
N0:N1
P0
The Advance Information presented herein represents a product currently in design or being considered for design. The noted characteristics are
design targets. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8432-21
www.icst.com/products/hiperclocks.html
APRIL 2, 2001
1
ADVANCE INFORMATION
ICS8432-21
700/87.5MHZ, LOW PHASE NOISE
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1.
The ICS8432-21 features a fully integrated PLL and therefore requires no external component for setting the loop bandwidth.
A parallel-resonant , fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is fed into the
phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over
a range of 250MHz to 700MHz. The output of the loop divider is also applied to the phase detector.
The phase detector and the loop filter divider force the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to the LVPECL output buffer FOUT. The output of this divider is
scaled by a second divider prior to being sent to the LVPECL output buffer FOUT/P. These dividers provide a 50% output duty
cycle.
The programmable features of the ICS8432-21 support two input modes and programmable PLL loop divider and output
divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel
mode the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0, N1, and P0 is passed directly to the
ripple counter and the output dividers. On the LOW-to-HIGH transition of the nP_LOAD input the data is latched and the ripple
counter and output dividers remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a
result the M, N, and P bits can be hardwired to set the ripple counter and output dividers to a specific default state that will
automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship
between the VCO frequency, the crystal frequency and the loop divider is defined as follows:
fVCO = fxtal x M
The M count and the required values of M0 through M8 are shown in Table 4B, Programmable VCO Frequency Function.
Valid M values for which the PLL will achieve lock are defined as 10 ≤ M ≤ 28. The frequency out is defined as follows:
fVCO
N
M __
N
fVCO
N x P
M __
N x P
fxtal
fxtal
x
=
FOUT
FOUT/P
x
=
=
=
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the ripple counter and output dividers
when S_LOAD transitions from LOW-to-HIGH. The ripple counter and output divider values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH data at the S_DATA input is passed directly to the ripple counter and output
dividers on each rising edge of S_CLOCK. The serial mode can be used to program the M, N, and P bits and test bits T1 and
T0. The internal registers T0 and T1 determine the state of the TEST output as follows:
T1 T0
TEST Output
LOW
0
0
1
1
0
1
0
1
S_Data
Output of M divider
CMOS Fout
T1
T0
P0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_DATA
S_CLOCK
S_LOAD
M0:M8, N0:N2
nP_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
8432-21
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APRIL 2, 2001
2
ADVANCE INFORMATION
ICS8432-21
700/87.5MHZ, LOW PHASE NOISE
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Description
1
M5
Input
Input
M counter/divider inputs. Data latched on LOW-to-HIGH transistion
of nP_LOAD input. LVCMOS / LVTTL interface levels.
2, 3, 4,
28, 29,
M6, M7, M8,
M0, M1,
Pulldown
30, 31, 32
M2, M3, M4
Determines output divider value as defined in Table 4C Function
table. LVCMOS / LVTTL interface levels.
Determines output divider value for FOUT/P output as defined in
Table 4C Function table. LVCMOS/LVTTL interface levels.
5, 6
N0, N1
Input
Pulldown
Pulldown
7
8, 16
9
P0
Input
Power
Output
Power
VEE
TEST
VDD
Power supply ground pin. Connect to ground.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS interface levels.
10
Core power supply pin.
Differential output for the synthesizer.
3.3V LVPECL interface levels.
11, 12
13
FOUT/P, nFOUT/P Output
VDDO
Power
Output
Output power supply connection. Connect to 3.3V.
Differential output for the synthesizer.
3.3V LVPECL interface levels.
14, 15
FOUT, nFOUT
Resets the M, N, and P dividers. Forces FOUT and FOUT/P low.
LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLK.
Shift register serial input. Data sampled on the rising edge of
S_CLK.
Controls transition of data from shift register into the ripple counter.
LVCMOS / LVTTL interface levels.
17
18
19
MR
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pulldown
S_CLOCK
S_DATA
20
21
S_LOAD
VDDA
Input
Power
Analog power supply pin. Connect to 3.3V.
Selects between crystal or reference inputs as the PLL reference
source. LVCMOS / LVTTL interface levels. Selects XTAL inputs
when HIGH. Selects REF_IN when LOW.
22
XTAL_SEL
Input
Pullup
23
REF_CLK
Input
Input
Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator inputs.
24, 25
XTAL1, XTAL2
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into ripple counter, and when data present at N1:N0, P0
sets the output divide value. LVCMOS / LVTTL interface levels.
26
27
nP_LOAD
VCO_SEL
Input
Input
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS / LVTTL interface levels.
8432-21
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APRIL 2, 2001
3
ADVANCE INFORMATION
ICS8432-21
700/87.5MHZ, LOW PHASE NOISE
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
REF_CLK,
pF
XTAL1, XTAL2
M0:M8, N0:N1,
VCO_SEL,
CIN
Input Capacitance
XTAL_SEL,
S_LOAD,
pF
S_DATA, MR,
S_CLOCK,
nP_LOAD, P0
RPULLUP
Input Pullup Resistor
51
51
KΩ
KΩ
RPULLDOWN Input Pulldown Resistor
TABLE 3. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Crystal Cut / Mode of Oscillation
Frequency
AT / Fundamental
14
-50
25
50
MHz
ppm
ppm
mW
Ω
Frequency Tolerance
Frequency Stability
Drive Level
-100
100
0.1
18
Equivalent Series Resistance (ESR)
Shunt Capacitiance
Load Capaacitance
Series Pin Inductance
Operating Temperature Range
Aging
50
80
7
pF
10
3
32
7
pF
nH
0
70
5
°C
Per year @ 25°C
-5
ppm
8432-21
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APRIL 2, 2001
4
ADVANCE INFORMATION
ICS8432-21
700/87.5MHZ, LOW PHASE NOISE
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 4A. PARALLEL AND SERIAL MODES FUNCTION TABLE
Inputs
Conditions
nP_LOAD
M
N
P0
S_LOAD S_CLOCK S_DATA
X
X
X
X
X
X
X
Data on M, N, and P0 inputs passed directly to
ripple counter and output dividers.
TEST output forced LOW.
Data is latched into input registers and remains
loaded until next LOW transition or until a serial
event occurs.
L
Data Data Data
Data Data Data
X
X
X
↑
X
X
X
Serial input mode. Shift register is loaded with
data on S_DATA on each rising edge of
S_CLOCK.
Contents of the shift register are passed to the
ripple counter and output dividers.
Ripple counter and output divider vlaues are
latched.
H
H
X
X
X
X
X
X
L
↑
Data
Data
↑
L
H
H
X
X
X
X
X
X
↓
L
Data
X
L
X
Parallel or serial input do not affect shift registers.
TABLE 4B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
0
32
M5
0
16
M4
0
8
M3
1
4
M2
0
2
M1
1
1
M0
0
VCO Frequency
(MHz)
M Count
250
275
300
325
•
10
11
12
13
•
0
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
675
700
26
27
28
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
1
1
1
0
0
NOTE 1: These M count values and the resulting frequency correspond to crystal or reference frequency of 25MHz.
TABLE 4C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Output Frequency
(MHz)
Inputs
N Divider
Value
P Divider
Value
FOUT
FOUT/P
N1
0
N0
0
P0
0
Minimum
250
Maximum
700
Minimum
62.5
Maximum
175
1
2
4
8
1
2
4
8
4
4
4
4
8
8
8
8
0
1
0
125
350
31.25
87.5
1
0
0
62.5
175
15.625
7.8125
31.25
43.75
1
1
0
31.25
250
87.5
700
21.875
87.5
0
0
1
0
1
1
125
350
15.625
7.8125
3.90625
43.75
1
0
1
62.5
175
21.875
10.9375
1
1
1
31.25
87.5
8432-21
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APRIL 2, 2001
5
ADVANCE INFORMATION
ICS8432-21
700/87.5MHZ, LOW PHASE NOISE
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Inputs
4.6V
-0.5V to VDD+0.5 V
-0.5V to VDD+0.5V
Outputs
Ambient Operating Temperature 0°C to 70°C
Storage Temperature -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any conditions beyond those listed in the DC Character-
istics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VDD, VDDA, VDDO Power Supply Voltage
3.135
3.3
3.465
110
V
IEE
Power Supply Current
mA
Quiescent Analog
Power Supply Current
IDDA
mA
TABLE 5B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
VCO_SEL, XTAL_SEL, S_LOAD,
S_DATA, S_CLOCK, nP_LOAD,
N0:N1, M0:M8, P0, MR
VDDI = 3.465V
VDDI = 3.465V
VDDI = 3.135V
VDDI = 3.135V
2
3.765
3.765
0.8
V
V
Input
VIH
High Voltage
REF_CLK
1.7
-0.3
VCO_SEL, XTAL_SEL, S_LOAD,
S_DATA, S_CLOCK, nP_LOAD,
N0:N1, M0:M8, P0, MR
V
Input
VIL
Low Voltage
REF_CLK
1.3
V
M0-M4, M6-M8, N0, N1,
S_CLOCK, S_DATA, S_LOAD,
REF_CLK, nP_LOAD, P0, MR
VDDx = VIN =
3.465V
150
µA
Input
IIH
High Current
VDDx = VIN =
3.465V
M5, XTAL_SEL, VCO_SEL
5
µA
µA
M0-M4, M6-M8, N0, N1,
S_CLOCK, S_DATA, S_LOAD,
REF_CLK, nP_LOAD, P0, MR
VDDx = 3.465V,
VIN = 0V
-5
Input
IIL
Low Current
VDDx = 3.465V,
VIN = 0V
VDDx = 3.135V,
IOH = -36mA
VDDx = 3.135V,
IOL = 36mA
M5, XTAL_SEL, VCO_SEL
-150
2.6
µA
V
Output
VOH
TEST
TEST
High Voltage
Output
Low Voltage
VOL
0.5
V
8432-21
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APRIL 2, 2001
6
ADVANCE INFORMATION
ICS8432-21
700/87.5MHZ, LOW PHASE NOISE
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 5C. LVPECL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT,
Output High Voltage;
NOTE 1, 2
nFOUT,
FOUT/P,
nFOUT/P
FOUT,
nFOUT,
FOUT/P,
nFOUT/P
FOUT,
VOH
VDDx = 3.3V
2.1
V
V
V
Output Low Voltage;
NOTE 1, 2
VOL
VDDx = 3.3V
1.6
Peak-to-Peak
Output Voltage Swing FOUT/P,
nFOUT/P
nFOUT,
VSWING
3.135V ≤ VDDx ≤ 3.465V
0.6
0.85
NOTE 1: FOUT, nFOUT, FOUT/P, nFOUT/P outputs terminated with 50 Ω to VDDO - 2V.
NOTE 2: These levels are specified for VDDO = 3.3V. Output levels will vary 1:1 with VDDO.
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
REF_CLK;
NOTE 1
XTAL1, XTAL2;
NOTE 1
14
14
25
25
MHz
MHz
Maximum Input
Frequency
fIN
S_CLOCK
TBD
TBD
TBD
MHz
ns
tR
tF
Input Rise Time REF_CLK
Measured at 20% to 80% points
Measured at 20% to 80% point
Input Fall Time
REF_CLK
REF_CLK
ns
Input Reference
Duty Cycle
tDC
TBD
TBD
%
NOTE 1: For the input crystal and reference frequency range the M value must be set for the VCO to operate within the
250MHz to 700MHz range. Using the minimum input frequency of 14MHz valid values of M are 18≤ M ≤ 50. Using the
maximum frequency of 25MHz valid values of M are 10≤ M ≤ 28.
8432-21
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APRIL 2, 2001
7
ADVANCE INFORMATION
ICS8432-21
700/87.5MHZ, LOW PHASE NOISE
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 7. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
Units
MHz
FOUT
Output Frequency
3.135 ≤ VDDx ≤ 3.465V
125MHZ, 1KHz offset
125MHZ, 10KHz offset
125MHZ, 100KHz offset
31.25
500
dBc/Hz
dBc/Hz
dBc/Hz
ps
ØNOISE Single Side Band Phase Noise
tsk(o)
tDC
Output Skew
Output Duty Cycle
47
53
%
Output Rise
Time
Output Fall
Time
FOUT, nFOUT
FOUT/P, nFOUT/P
FOUT, nFOUT
tR
tF
20% to 80%
20% to 80%
300
800
ps
300
TBD
TBD
800
ps
ns
ns
FOUT/P, nFOUT/P
M, N to nP_LOAD
S_DATA to
S_CLOCK
S_CLOCK to
S_LOAD
tS
tH
Setup Time
Hold Time
TBD
TBD
TBD
ns
ns
ns
M, N to nP_LOAD
S_DATA to
S_CLOCK
S_CLOCK to
S_LOAD
TBD
ns
tLOCK
tPW
PLL Lock Time
Pulse Width
TBD
TBD
TBD
ms
ns
ns
nP_LOAD
S_LOAD
fXTAL = 16MHz,
Parallel Resonant Crystal
oscTOL Crystal Oscillator Tolerance
-50
50
ppm
8432-21
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APRIL 2, 2001
8
ADVANCE INFORMATION
ICS8432-21
700/87.5MHZ, LOW PHASE NOISE
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - Y SUFFIX
D
D2
θ
32
25
24
1
2
3
L
E
E1
E2
N
8
17
16
9
e
D1
A
C
A2
SEATING
-C-
PLANE
ccc
b
A1
c
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
D1
D2
E
9.00 BASIC
7.00 BASIC
5.60 Ref.
E1
E2
e
0.80 BASIC
0.60
L
0.45
0.75
7°
0°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
8432-21
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APRIL 2, 2001
9
ADVANCE INFORMATION
ICS8432-21
700/87.5MHZ, LOW PHASE NOISE
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
ORDERING INFORMATION
Part/Order Number
ICS8432BY-21
Marking
Package
32 Lead LQFP
Count
250 per tray
500
Temperature
0°C to 70°C
0°C to 70°C
ICS8432BY-21
ICS8432BY-21
ICS8432BY-21T
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8432-21
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APRIL 2, 2001
10
相关型号：
ICS8432BY-21T
Clock Generator, 500MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32
IDT
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Clock Generator, 700MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32
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