ICS843204AGI-01LF [IDT]
Clock Generator, 156.25MHz, PDSO48, 6.10 X 12.50 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-48;
| 型号： | ICS843204AGI-01LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 156.25MHz, PDSO48, 6.10 X 12.50 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-48 光电二极管 |
| 文件： | 总13页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843204I-01
GENERAL DESCRIPTION
FEATURES
The ICS843204I-01 is a 4 output LVPECL Synthe-
• Four 3.3V LVPECL outputs
ICS
sizer optimized to generate Gigabit Ethernet and
SONET reference clock frequencies and is a
member of the HiPerClocksTM family of high
performance clock solutions from IDT. Using a
• Selectable crystal oscillator interface or clock inputs
HiPerClockS™
• Supports the following output frequencies: 155.52MHz
and 156.25MHz
19.44MHz and 25MHz, 18pF parallel resonant crystal,
155.52MHz and 156.25MHz frequencies can be generated.
The ICS843204I-01 uses IDT’s FemtoClockTM low phase noise
VCO technology and can achieve 1ps or lower typical RMS
phase jitter.
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz - 13MHz): 0.6ps (typical)
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.7ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
nPLL_BYPASS_A
nQA1
QA1
nQA0
QA0
nc
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
IN_SELA
CLK0
XTAL_IN0
XTAL_OUT0
nc
VEE
OEA0
OEA1
VCC
VCCA
nPLL_BYPASS_B
nc
SELB0
VEE
OEB0
OEB1
VCC
SELB1
VCCA
nc
nc
nc
nc
nc
Pullup
IN_SELA
Pulldown
CLK0
SELA0
OEA0
OEA1
VCCO_A
SELA1
SELA0
nPLL_BYPASS_A
nc
25MHz
XTAL_IN0
QA0
÷4
PLL
0
1
OSC
9
nQA0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
XTAL_OUT0
156.25MHz
nc
nc
nc
SELA1
625MHz
XTAL_IN1
XTAL_OUT1
CLK1
QA1
Pullup
Pullup
nPLL_BYPASS_B
IN_SELB
0
1
nQA1
nCLK1
IN_SELB
VCCO_B
nc
Pulldown
CLK1
SELB0
Pullup/pulldown
nCLK1
QB0
nQB0
QB1
nQB1
OEB0
OEB1
QB0
19.44MHz
0
1
XTAL_IN1
nQB0
OSC
÷4
PLL
ICS843204I-01
48 Lead TSSOP
6.1mm x 12.5mm x 0.925mm
package body
XTAL_OUT1
SELB0
155.52MHz
622.08MHz
QB1
0
1
G Package
Top View
nQB1
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
1
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Type
Description
nQA1, QA1
nQA0, QA0
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
3, 4
5, 10, 11, 12,
13, 20, 25, 26,
27, 28, 29, 37,
44
nc
Unused
No connect.
6
VCCO_A
Power
Input
Output supply pin for Bank A outputs.
Select pin. When HIGH, selects QA1/nQA1 at 155.52MHz. When LOW,
selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels.
Select pin. When HIGH, selects QA0/nQA0 at 155.52MHz. When LOW,
selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels.
7
SELA1
Pulldown
8
9
SELA0
Input
Input
Input
Input
Input
Pulldown
Pullup
nPLL_BYPASS_A
When LOW, PLL is bypassed. When HIGH, PLL output is active.
14,
15
XTAL_IN1,
XTAL_OUT1
Parallel resonant crystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
16
CLK1
Pulldown Non-inverting differential clock input.
Pullup/
17
nCLK1
Inverting differential clock input. VDD/2 bias voltage when left floating.
Pulldown
Select pin. When HIGH, selects XTAL1 inputs. When LOW, selects
CLK1, nCLK1 inputs. LVCMOS/LVTTL interface levels.
18
IN_SELB
Input
Pullup
19
VCCO_B
QB0, nQB0
QB1, nQB1
VCCA
Power
Ouput
Ouput
Power
Output supply pin for Bank B outputs.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Analog supply pins.
21, 22
23, 24
30, 39
Select pin. When HIGH, selects QB1/nQB1 at 155.52MHz. When LOW,
Pullup
31
32, 40
33
SELB1
VCC
Input
Power
Input
selects QB1/nQB1 at 156.25MHz. LVCMOS/LVTTL interface levels.
Core supply pins.
Output enable pin. QB1/nQB1 outputs are enable.
LVCMOS/LVTTL interface levels.
OEB1
Pullup
Output enable pin. QB0/nQB0 outputs are enabled.
LVCMOS/LVTTL interface levels.
34
35, 43
36
OEB0
VEE
Input
Power
Input
Input
Input
Pullup
Negative supply pins.
Select pin. When HIGH, selects QB0/nQB0 at 155.52MHz. When LOW,
Pullup
SELB0
selects QB0/nQB0 at 156.25MHz. LVCMOS/LVTTL interface levels.
38
nPLL_BYPASS_B
OEA1
Pullup
Pullup
When LOW, PLL is bypassed. When HIGH, PLL output is active.
Output enable pin. QA1/nQA1 outpus are enabled.
LVCMOS/LVTTL interface levels.
41
Output enable pin. QA0/nQA0 outputs are enabled.
LVCMOS/LVTTL interface levels.
42
OEA0
Input
Pullup
45,
46
XTAL_OUT0,
XTAL_IN0
Parallel resonant crystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
Input
Input
Input
47
CLK0
Pulldown LVCMOS/LVTTL clock input.
Select pin. When HIGH, selects XTAL0 inputs. When LOW, selects
CLK0 input. LVCMOS/LVTTL interface levels.
48
IN_SELA
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
RPULLUP Input Pullup Resistor
51
51
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
54.8°C/W (0 mps)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V 10ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.97
Typical
3.3
Maximum Units
VCC
Core Supply Voltage
3.63
VCC
V
V
VCCA
Analog Supply Voltage
VCC – 0.22
3.3
VCCO_A,
VCCO_B
Output Supply Voltage
2.97
3.3
3.63
V
IEE
Power Supply Current
Analog Supply Current
165
22
mA
mA
ICCA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V 10ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
CLK0, SELA0, SELA1
2
VCC + 0.3
0.8
V
V
-0.3
VCC = VIN = 3.63V
VCC = VIN = 3.63V
150
µA
nPLL_BYPASS_A,
nPLL_BYPASS_B,
IN_SELA, IN_SELB,
SELB1, SELB0, OEB0,
OEB1, OEA0, OEA1
Input
High Current
IIH
5
µA
µA
µA
CLK0, SELA0, SELA1
VCC = 3.63V, VIN = 0V
-5
nPLL_BYPASS_A,
nPLL_BYPASS_B,
IN_SELA, IN_SELB,
SELB1, SELB0, OEB0,
OEB1, OEA0, OEA1
Input
Low Current
IIL
V
CC = 3.63V, VIN = 0V
-150
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
3
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±±10% VEE = 1V% TA = -41°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VCC = 3.63V
IN = 1V% VCC = 3.63V
Minimum Typical Maximum Units
CLK±%
nCLK±
±51
µA
nCLK±
CLK±
V
-±51
-5
µA
µA
V
IIL
Input Low Current
VIN = 1V% VCC = 3.63V
VPP
Peak-to-Peak Input Voltage; NOTE ±
1.±5
±.3
Common Mode Input Voltage;
NOTE ±% 2
VCMR
V
EE + 1.5
VCC - 1.85
V
NOTE ±: VIL should not be less than -1.3V
NOTE 2: Common mode voltage is defined as VIH.
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±±10% VEE = 1V% TA = -41°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE ±
VCCO - ±.4
VCCO - 2.1
1.6
VCCO - 1.9
VCCO - ±.7
±.1
V
V
V
VOL
Output Low Voltage; NOTE ±
VSWING
Peak-to-Peak Output Voltage Swing
NOTE ±: Outputs terminated with 51Ω to VCCO - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Fundamental
25
±9.44
Typical Maximum Units
Mode of Oscillation
XTAL1
MHz
MHz
Ω
Frequency
XTAL±
Equivalent Series Resistance (ESR)
Shunt Capacitance
51
7
pF
Drive Level
±
mW
NOTE: Characterized using an ±8pF parallel resonant crystal.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±±10% VEE = 1V% TA = -41°C TO 85°C
Symbol Parameter
Test Conditions
SELB1 = ±; OEB1 = ±
SELA1 = 1; OEA1 = ±
Minimum Typical Maximum Units
±55.52
±56.25
MHz
MHz
ps
fOUT
Output Frequency
tsk(b)
tjit(Ø)
Bank Skew; NOTE ±% 2
61
±55.52MHz% (±2kHz - ±.3MHz)
±56.25MHz% (±.875MHz - 21MHz)
210 to 810
1.6
1.7
ps
RMS Phase Jitter (Random);
NOTE 3
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
251
47
611
53
ps
0
NOTE ±: Defined as skew within a bank of outputs at the same supply voltags and with equal load conditions.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: See Phase Noise plot.
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
4
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
2V
VCC
SCOPE
VCC
VCCO_A
VCCO_B
,
Qx
,
VCCA
nCLK1
CLK1
LVPECL
VPP
VCMR
Cross Points
nQx
VEE
-1.3V 0.33V
VEE
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
Phase Noise Plot
nQXx
QXx
Phase Noise Mask
nQXy
QXy
Offset Frequency
f1
f2
tsk(b)
RMS Jitter = Area Under the Masked Phase Noise Plot
Where X = A or B
RMS PHASE JITTER
BANK SKEW
nQA0, nQA1
nQB0, nQB1
80ꢀ
tF
80ꢀ
QA0, QA1
QB0, QB1
VSWING
20ꢀ
tPW
Clock
20ꢀ
tPERIOD
Outputs
tR
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
5
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843204I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_x
should be individually connected to the power supply plane
through vias, and bypass capacitors should be used for each
pin. To achieve optimum jitter performance, power supply iso-
lation is required. Figure 1 illustrates how a 10Ω resistor along
with a 10µF and a .01μF bypass capacitor should be connected
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
to each VCCA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843204I-01 has been characterized with 18pF parallel
were determined using an 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
resonant crystals. The capacitor values shown in Figure 2 below
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
XTAL_OUT
C2
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
6
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise.This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω.This can also be accomplished by removing
R1 and making R2 50Ω.
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 4 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V /2 is
generated by the bias resistors R1, R2 and C1. This bias CcCircuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
CC
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 4. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
7
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUTS
OUTPUTS:
LVPECL OUTPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
CLK INPUT
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
CLK/nCLK INPUTS
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating fre-
quency and minimize signal distortion. Figures 5A and 5B
show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
8
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843204I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843204I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 10ꢀ = 3.63V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.63V * 165mA = 598.95mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power
(3.63V, with all outputs switching) = 598.95mW + 120mW = 718.95mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assumig no air
flow and a multi-layer board, the appropriate value is 54.8°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.719W * 54.8°C/W = 124.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 48-PIN TSSOP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
54.8°C/W
51.0°C/W
49.1°C/W
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
9
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 0.9V
OUT
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
10
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 48 LEAD TSSOP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
54.8°C/W
51.0°C/W
49.1°C/W
TRANSISTOR COUNT
The transistor count for ICS843204I-01 is: 3974
PACKAGE OUTLINE - G SUFFIX FOR 48 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
Maximum
N
A
48
--
1.20
0.15
1.05
0.27
0.20
12.60
A1
A2
b
0.05
0.80
0.17
0.09
12.40
c
D
E
8.10 BASIC
0.50 BASIC
E1
e
6.00
6.20
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
11
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS843204AGI-01
Marking
TBD
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
48 Lead TSSOP
ICS843204AGI-01T
ICS843204AGI-01LF
ICS843204AGI-01LFT
TBD
48 Lead TSSOP
1000 tape & reel
tube
ICS843204AI01L
ICS843204AI01L
48 Lead "Lead-Free" TSSOP
48 Lead "Lead-Free" TSSOP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
12
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
ICS843207AY-350LF
Clock Generator, 375MHz, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-48
IDT
ICS843207AY-350LFT
Clock Generator, 375MHz, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-48
IDT
ICS843207CY-350LF
Clock Generator, 375MHz, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, LQFP-48
IDT
ICS843207CY-350LFT
Clock Generator, 375MHz, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, LQFP-48
IDT
©2020 ICPDF网 联系我们和版权申明