ICS84320A01N [IDT]
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER; 780MHZ ，水晶- TO- 3.3V的差分LVPECL频率合成器
| 型号： | ICS84320A01N |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总21页 (文件大小：343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS84320-01 is a general purpose, dual out- • Dual differential 3.3V LVPECL outputs
ICS
HiPerClockS™
put Crystal-to-3.3V Differential LVPECL High Fre-
quency Synthesizer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS84320-01 has a se-
• Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
• Output frequency range: 77.5MHz to 780MHz
• Crystal input frequency range: 14MHz to 40MHz
• VCO range: 620MHz to 780MHz
lectable TEST_CLK or crystal inputs. The VCO operates at a
frequency range of 620MHz to 780MHz. The VCO frequency
is programmed in steps equal to the value of the input refer-
ence or crystal frequency. The VCO and output frequency
can be programmed using the serial or parallel interfaces to
the configuration logic. The low phase noise characteristics
of the ICS84320-01 make it an ideal clock source for 10 Gigabit
Ethernet, SONET, and Serial Attached SCSI applications.
• Parallel or serial interface for programming counter
and output dividers
• Duty cycle: 49% - 51% (N > 1)
• RMS period jitter: 2ps (typical)
• RMS phase jitter at 155.52MHz, using a 38.88MHz crystal
(12kHz to 20MHz): 2.5ps (typical)
Offset
Noise Power
100Hz ................. -90.5 dBc/Hz
1kHz ............... -114.2 dBc/Hz
10kHz ............... -123.6 dBc/Hz
100kHz ............... -128.1 dBc/Hz
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free RoHS (6)
packages
BLOCK DIAGRAM
VCO_SEL
PIN ASSIGNMENT
XTAL_SEL
32 31 30 29 28 27 26 25
TEST_CLK
0
M5
M6
M7
M8
N0
N1
nc
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL2
XTAL1
TEST_CLK
XTAL_SEL
VCCA
1
OSC
XTAL2
ICS84320-01
10 11 12 13 14 15 16
32-Lead LQFP
S_LOAD
S_DATA
S_CLOCK
MR
PLL
÷ N
PHASE DETECTOR
VEE
÷ 1
÷ 2
÷ 4
÷ 8
9
MR
0
1
VCO
FOUT0
nFOUT0
FOUT1
nFOUT1
÷ M
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
7mm x 7mm x 1.4mm package body
Y Package
TopView
M0:M8
N0:N1
32-LeadVFQFN
5mm x 5mm x 0.925 package body
K Package
Top View
84320AY-01
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REV. C OCTOBER 22, 2007
ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op- matically occur during power-up.TheTEST output is LOW when
eration using a 25MHz crystal. Valid PLL loop divider values operating in the parallel input mode.The relation-ship between
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
the VCO frequency, the crystal frequency and the M divider is
defined as follows:
fVCO = fxtal x M
The ICS84320-01 features a fully integrated PLL and there-
fore requires no external components for setting the loop band- The M value and the required values of M0 through M8 are
width. A fundamental crystal is used as the input to the on- shown in Table 3B to program the VCO Frequency Function
chip oscillator.The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 620MHz to 780MHz. The output of the M divider is
also applied to the phase detector.
Table.Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 25 ≤ M ≤ 31. The frequency
out is defined as follows:
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock.The output of the vider when S_LOAD transitions from LOW-to-HIGH. The M
VCO is scaled by a divider prior to being sent to each of the LVPECL divide and N output divide values are latched on the HIGH-to-
output buffers.The divider provides a 50% output duty cycle.
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
The programmable features of the ICS84320-01 support two
input modes to program the M divider and N output divider. The
two input operational modes are parallel and serial. Figure 1 shows T1 and T0.The internal registersT0 and T1 determine the state
the timing diagram for each mode. In parallel mode, the nP_LOAD of the TEST output as follows:
input is initially LOW. The data on inputs M0 through M8 and N0
T1 T0
TEST Output
LOW
and N1 is passed directly to the M divider and N output divider.
On the LOW-to-HIGH transition of the nP_LOAD input, the data
is latched and the M divider remains loaded until the next
LOW transition on nP_LOAD or until a serial event occurs. As a
result, the M and N bits can be hardwired to set the M divider
and N output divider to a specific default state that will auto-
0
0
1
1
0
1
0
1
S_Data, Shift Register Input
Output of M divider
CMOS Fout
S
ERIAL
L
OADING
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
T 1
T0
*
NULL N1
N0
M8
M7
M6
M5
M4 M3
M2
M1
M0
t
t
H
S
t
S
PARALLEL LOADING
M, N
M0:M8, N0:N1
nP_LOAD
t
t
H
S
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Description
1
M5
Input
Input
M divider inputs. Data latched on LOW-to-HIGH transition of
nP_LOAD input. LVCMOS / LVTTL interface levels.
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Pulldown
Pulldown
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
5, 6
N0, N1
Input
7
nc
Unused
Power
No connect.
8, 16
VEE
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode.
LVCMOS/LVTTL interface levels.
9
TEST
Output
Power
10
VCC
Core supply pin.
11, 12
13
FOUT1, nFOUT1 Output
VCCO Power
FOUT0, nFOUT0 Output
Differential output for the synthesizer. LVPECL interface levels.
Output supply pin.
14, 15
Differential output for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, forces the internal
dividers are reset causing the true outputs FOUTx to go low and the
17
MR
Input
Pulldown inverted outputs nFOUTx to go high. When logic LOW, the internal
dividers and the outputs are enabled. Assertion of MR does not
affect loaded M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS/LVTTL interface levels.
18
19
S_CLOCK
S_DATA
Input
Input
Pulldown
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
20
21
S_LOAD
VCCA
Input
Pulldown
Power
Analog supply pin.
Selects between crystal or test inputs as the PLL reference source.
22
XTAL_SEL
Input
Pullup
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels.
23
TEST_CLK
Input
Input
Pulldown Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
24, 25
XTAL2, XTAL1
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
26
nP_LOAD
Input
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
27
VCO_SEL
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
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REV. C OCTOBER 22, 2007
ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
L
Data Data
Data Data
X
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
↑
L
L
↑
X
↑
L
X
H
H
X
X
X
X
Data
Data
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
0
32
M5
0
16
M4
1
8
M3
1
4
M2
0
2
M1
0
1
M0
1
VCO Frequency
(MHz)
M Divide
625
•
25
•
•
•
•
•
•
•
•
•
•
700
•
28
•
0
0
0
0
1
1
1
0
0
•
•
•
•
•
•
•
•
•
775
31
0
0
0
0
1
1
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency
of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Frequency (MHz)
N Divider Value
N1
N0
0
Minimum
620
Maximum
780
0
0
1
1
1
2
4
8
1
310
390
0
155
195
1
77.5
97.5
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REV.C OCTOBER 22, 2007
ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5 V
I
Outputs, VO (LVCMOS)
-0.5V to VCCO + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
JA
32 Lead LQFP
47.9°C/W (0 lfpm)
34.8°C/W (0 lfpm)
32 Lead VFQFN
Storage Temperature, T
-65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
3.465
3.465
155
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
VCC – 0.22
3.135
3.3
3.3
V
mA
mA
ICCA
22
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, N0:N1,
S_DATA, S_CLOCK, M0:M8
2
VCC + 0.3
V
V
Input
VIH
High Voltage
TEST_CLK
2
V
CC + 0.3
0.8
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, N0:N1,
S_DATA, S_CLOCK, M0:M8
-0.3
-0.3
V
Input
VIL
Low Voltage
TEST_CLK
1.3
V
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
V
CC = VIN = 3.465V
150
µA
Input
IIH
High Current
M5, XTAL_SEL, VCO_SEL
VCC = VIN = 3.465V
5
µA
µA
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
VCC = 3.465V,
VIN = 0V
-5
Input
IIL
Low Current
VCC = 3.465V,
VIN = 0V
M5, XTAL_SEL, VCO_SEL
TEST; NOTE 1
-150
2.6
µA
V
Output
VOH
High Voltage
Output
VOL
TEST; NOTE 1
0.5
V
Low Voltage
NOTE 1:Outputs terminated with 50Ω toVCCO/2.
84320AY-01
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REV. C OCTOBER 22, 2007
ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"3.3V Output Load Test Circuit".
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK; NOTE 1
14
14
40
40
50
MHz
MHz
MHz
fIN
Input Frequency XTAL1, XTAL2; NOTE 1
S_CLOCK
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the
620MHz to780MHz range. Using the minimum input frequency of 14MHz, valid values of M are 45 ≤ M ≤ 55. Using the
maximum frequency of 40MHz, valid values of M are 16 ≤ M ≤ 19.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
14
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
780
Units
FOUT
Output Frequency
77.5
MHz
ps
tjit(per)
Period Jitter, RMS; NOTE 1
fOUT > 100MHz
2.0
2.5
2.6
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
155.52MHz,
12kHz - 20MHz
tjit
ps
tsk(o)
Output Skew; NOTE 2, 3
Output Rise/Fall Time
M, N to nP_LOAD
15
ps
ps
ns
ns
ns
ns
ns
ns
%
tR / tF
20% to 80%
150
600
5
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
5
5
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
N > 1
fOUT ≤ 625
ƒ> 625
49
45
51
55
odc
Output Duty Cycle
%
tPW
Output Pulse Width
PLL Lock Time
tPERIOD/2 - 150
tPERIOD/2 + 150
1
ps
ms
tLOCK
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 155.52MHZ
0
-10
-20
-30
-40
OC-48 Sonet Bandpass Filter
155.52MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 2.5ps (typical)
-50
-60
-70
-80
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Sonet Bandpass Filter to raw data
1
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 622.08MHZ
0
-10
-20
OC-48 Sonet Bandpass Filter
-30
-40
622.08MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 2.48ps (typical)
-50
-60
Raw Phase Noise Data
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Sonet Bandpass Filter to raw data
1
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
2V
nFOUTx
FOUTx
SCOPE
VCC,
VCCO
Qx
VCCA
nFOUTy
FOUTy
LVPECL
VEE
nQx
tsk(o)
-1.3V 0.165V
OUTPUT SKEW
3.3V OUTPUT LOAD AC TEST CIRCUIT
VOH
VREF
nFOUTx
FOUTx
Pulse Width
tPERIOD
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
tPW
odc =
tPERIOD
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
80%
VSWING
Clock
20%
20%
Outputs
tF
tR
OUTPUT RISE/FALL TIME
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84320-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 24Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin. The 24Ω
resistor can also be replaced by a ferrite bead.
3.3V
VCC
.01μF
.01μF
24Ω
VCCA
10μF
FIGURE 2. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUTS
OUTPUTS:
LVPECL OUTPUTS
For applications not requiring the use of the crystal oscillator All unused LVPECL outputs can be left floating. We
input, both XTAL_IN and XTAL_OUT can be left floating. recommend that there is no trace attached. Both sides of the
Though not required, but for additional protection, a 1kΩ differential output pair should either be left floating or
resistor can be tied from XTAL_IN to ground.
terminated.
TEST_CLK INPUT
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the TEST_CLK to
ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
suitable for most applications. Additional accuracy can be
achieved by adding two small capacitors C1 and C2 as shown in
Figure 3.
A crystal can be characterized for either series or parallel mode
operation.The ICS84320-01 has a built-in crystal oscillator circuit.
This interface can accept either a series or parallel crystal without
additional components and generate frequencies with accuracy
25
XTAL1
C1
18p
X1
18pF Parallel Crystal
24
XTAL2
C2
22p
ICS84320-01
FIGURE 3. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram
series resistance (Rs) equals the transmission line
impedance. In addition, matched termination at the crystal
is shown in Figure 4. The XTAL_OUT pin can be left floating. input will attenuate the signal in half. This can be done in one
of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by
removing R1 and making R2 50Ω.
The input edge rate can be as slow as 10ns. For LVCMOS
inputs, it is recommended that the amplitude be reduced from
full swing to half swing in order to prevent signal interference
with the power rail and to reduce noise. This configuration
requires that the output impedance of the driver (Ro) plus the
VDD
VDD
R1
0.1µf
50Ω
Ro
Rs
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 5A and
5B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 5A. LVPECL OUTPUTTERMINATION
FIGURE 5B. LVPECL OUTPUTT ERMINATION
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
The schematic of the ICS84320-01 layout example used in
this layout guideline is shown in Figure 6A. The ICS84320-
01 recommended PCB board layout for this example is
shown in Figure 6B. This layout example is used as a gen-
eral guideline. The layout in the actual system will depend
on the selected component types, the density of the compo-
nents, the density of the traces, and the stack up of the P.C.
board.
C1
C2
X1
U1
VCC
R7
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
M5
M6
M7
M8
N0
N1
nc
XTAL2
T_CLK
nXTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
REF_IN
XTAL_SEL
24
VCCA
S_LOAD
S_DATA
S_CLOCK
C11
C16
10u
0.01u
VEE
ICS84320-01
VCC
R1
125
R3
125
Zo = 50 Ohm
IN+
C14
0.1u
TL1
+
-
C15
0.1u
Zo = 50 Ohm
IN-
TL2
R2
84
R4
84
FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
• The differential 50Ω output traces should have the
same length.
The following component footprints are used in this layout
example:
• Avoid sharp angles on the clock trace.Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Maximize the power and ground pad sizes and number of vias
capacitors.This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
• Make sure no other signal traces are routed between the
clock trace pair.
CLOCK TRACES AND TERMINATION
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure.The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
25 (XTAL1) and 24 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
GND
X1
C1
C2
VCC
VIA
U1
PIN 1
C16
C11
VCCA
R7
Close to the input
pins of the
receiver
R1
R3
R2
R4
C15
TL1
C14
TL1N
TL1, TL21N are 50 Ohm
traces and equal length
FIGURE 6B. PCB BOARD LAYOUT FOR ICS84320-01
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LVPECL FREQUENCY SYNTHESIZER
VFQFN EPADTHERMAL RELEASE PATH
In order to maximize both the removal of heat from the package “heat pipes”) are application specific and dependent upon
and the electrical performance, a land pattern must be the package power dissipation as well as electrical
conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the
incorporated on the Printed Circuit Board (PCB) within the
footprint of the package corresponding to the exposed metal
pad or exposed heat slug on the package, as shown in Figure minimum number needed. Maximum thermal and electrical
7. The solderable area on the PCB, as defined by the solder performance is achieved when an array of vias is incorporated
mask, should be at least the same size/shape as the exposed in the land pattern. It is recommended to use as many vias
pad/slug area on the package to maximize the thermal/ connected to ground as possible. It is also recommended that
the via diameter should be 12 to 13mils (0.30 to 0.33mm) with
1oz copper via barrel plating. This is desirable to avoid any
electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land
pattern and the inner edges of pad pattern for the leads to solder wicking inside the via during the soldering process
avoid any shorts.
which may result in voids in solder between the exposed
pad/slug and the thermal land. Precautions should be taken
While the land pattern on the PCB provides a means of heat to eliminate any solder voids between the exposed heat slug
and the land pattern. Note:These recommendations are to be
used as a guideline only. For further information, refer to the
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). Application Note on the Surface Mount Assembly of Amkor’s
The land pattern must be connected to ground through these Thermally/Electrically Enhance Leadfame Base Package,
vias. The vias act as “heat pipes”. The number of vias (i.e. Amkor Technology.
SOLDER
SOLDER
PIN
EXPOSED HEAT SLUG
PIN
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
FIGURE 7. P.C.ASSEMBLY FOR EXPOSED PADTHERMAL RELEASE PATH –SIDEVIEW (DRAWING NOT TO SCALE)
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84320-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84320-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 155mA = 537.08mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 537.1mW + 60mW = 597.1mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per
Table 8A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.597W * 42.1°C/W = 95.1°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8A. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 8B. THERMAL RESISTANCE θJA FOR 32-PINVFQFN FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8C/W
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT ANDT ERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω) * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
[(2V - 1.7V)/50Ω) * 1.7V = 10.2mW L
L
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 9A. θJAVS. AIR FLOW T ABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
50.1°C/W
47.9°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 9B. θJAVS. AIR FLOWT ABLE FOR 32 LEAD VFQFN PACKAGE
θJA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8°C/W
TRANSISTOR COUNT
The transistor count for ICS84320-01 is: 3776
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REV. C OCTOBER 22, 2007
ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE -Y SUFFIX FOR 32 LEAD LQFP
TABLE 10A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
18
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ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - 32 LEAD K PACKAGE
(Ref.)
N & N
Even
Seating Plane
(N -1)x e
(Ref.)
A1
IndexArea
N
L
A3
E2
e
N
(Ty p.)
2
If N & N
are Even
Anvil
Singulation
1
2
(N -1)x e
(Ref.)
OR
E2
2
TopView
b
e
Thermal
Base
A
(Ref.)
D2
2
D
N &N
Odd
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This
drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the
front page. The package dimensions are in Table 10B below.
TABLE 10B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
Minimum
Maximum
N
A
32
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
NE
D
8
8
5.0
D2
E
1.25
3.25
5.0
E2
L
1.25
0.30
3.25
0.50
Reference Document: JEDEC Publication 95, MO-220
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REV. C OCTOBER 22, 2007
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
TABLE 11. ORDERING INFORMATION
Part/Order Number
ICS84320AY-01
Marking
Package
Shipping Packaging Temperature
ICS84320AY-01
ICS84320AY-01
ICS84320A01N
ICS84320A01N
ICS84320AK01
ICS84320AK01
ICS4320A01L
ICS4320A01L
32 Lead LQFP
32 Lead LQFP
tray
1000 tape & reel
tray
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS84320AY-01T
ICS84320AY-01LN
ICS84320AY-01LNT
ICS84320AK-01
32 Lead "Lead-Free/Annealed" LQFP
32 Lead "Lead-Free/Annealed" LQFP
32 Lead VFQFN
1000 tape & reel
tray
ICS84320AK-01T
ICS84320AK-01LF
ICS84320AK-01LFT
32 Lead VFQFN
2500 tape & reel
tray
32 Lead "Lead-Free" VFQFN
32 Lead "Lead-Free" VFQFN
2500 tape & reel
NOTE: Parts that are ordered with an "LF" or LN" suffix to the part number are the Pb-Free configuration and are RoHS
compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT.IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
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REV.C OCTOBER 22, 2007
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Description of Change
Rev
A
Table
Page
7
Date
7/2/04
8/24/04
Updated Typical Phase Noise plots and format.
A
T11
16
Ordering Information Table - added Lead Free Part/Order Number.
1
5
Features Section - added Lead-Free bullet.
Power Supply DC Characteristics - updated VCCA min. from 3.135V to
VCC – 0.22.
Crystal Characteristics Table - added Drive Level.
Corrected 3.3V Output Load AC Test Circuit diagram.
Added Recommendations for Unused Input and Output Pins.
Added LVCMOS to XTAL Interface.
Ordering Information Table - added lead-free part number.
Added VFQFN package throughout the datasheet.
LVPECL DC Characteristics Table -corrected VOH max. from VCCO – 1.0V to
T4A
T6
6
8
9
10
18
B
4/14/06
T11
T4C
6
V
CCO – 0.9V.
C
C
4/10/07
14 - 15 Power Considerations - corrected power dissipation to reflect VOH max in Table
4C.
14
19
Added VFQFN EPAD Thermal Release Path section.
Ordering Information Table - added lead-free marking.
10/22/07
T11
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REV. C OCTOBER 22, 2007
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