ICS843001BGI-23 [IDT]
Clock Generator, 650MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24;
| 型号： | ICS843001BGI-23 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 650MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总24页 (文件大小：1091K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
FemtoClock Crystal/LVCMOS-to-
ICS843001I-23
LVPECL/ LVCMOS Frequency Synthesizer
DATA SHEET
General Description
Features
The ICS843001I-23 is a highly versatile, low phase noise
LVPECL/LVCMOS Synthesizer which can generate low jitter
reference clocks for a variety of communication applications. The
dual crystal interface allows the synthesizer to support up to three
communication standards in a given application (i.e. SONET with a
19.44MHz crystal, 1Gb/10Gb Ethernet and Fibre Channel using a
25MHz crystal). The RMS phase jitter performance is typically less
than 1ps, thus making the device acceptable for use in demanding
applications such as OC48 SONET, GbE/10Gb Ethernet and SAN
applications. The ICS843001I-23 is packaged in a small 24-pin
TSSOP, E-Pad package.
• One 3.3Vdifferential LVPECL output pair and
one LVCMOS/LVTTL single-ended reference clock output
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Crystal and CLK range: 19.44MHz – 27MHz
• Able to generate GbE/10GbE/12GbE, Fibre Channel
(1Gb/4Gb/10Gb), PCI-E and SATA from a 25MHz crystal
• VCO range: 1.12GHz – 1.275GHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.9ps (typical), 3.3V
• Supply modes
VCC/VCCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
package
Pin Assignment
Block Diagram
3
REF_OUT
1
24
VCCO_LVCMOS
N2:N0
2
23
VEE
N0
OE_REF
M2
3
4
22
21
N1
N2
Pulldown
SEL0
Pulldown
SEL1
5
6
7
20
19
18
17
M1
M0
MR
VCCO_LVPECL
Q
N
nQ
VEE
VCCA
VCC
SEL1
8
9
10
11
12
XTAL_IN0
000 ÷2
SEL0
CLK
XTAL_IN0
XTAL_OUT0
16
15
14
13
001 ÷4
OSC
00
01
11
010 ÷5
Q
XTAL_OUT1
XTAL_IN1
011 ÷6
XTAL_OUT0
XTAL_IN1
10
01
00
nQ
100 ÷8 (default)
101 ÷10
110 ÷12
111 ÷16
Phase
Detector
VCO
ICS843001I-23
OSC
24-Lead TSSOP, E-Pad
4.4mm x 7.8mm x 0.925mm
package body
XTAL_OUT1
CLK
M
000 ÷44
10
11
Pulldown
001 ÷45
G Package
Top View
010 ÷48
011 ÷50
100 ÷51
111 ÷64 (default)
Pulldown
Pullup
MR
3
M2:M0
REF_OUT
Pulldown
OE_REF
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
1
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
VCCO_LVCMOS
N0, N1
N2
Type
Description
1
2, 3
4
Power
Input
Output supply pin for REF_CLK output.
Pulldown
Output divider select pins. LVCMOS/LVTTL interface levels. See Table 3C.
Input
Pullup
5
VCCO_LVPECL
Q, nQ
Power
Output
Power
Power
Power
Output supply pin for LVPECL output.
Differential output pair. LVPECL interface levels.
Negative supply pins.
6, 7
8, 23
9
VEE
VCCA
Analog supply pin.
10
VCC
Core supply pin.
11,
12
XTAL_OUT1,
XTAL_IN1
Parallel resonant crystal interface.
XTAL_OUT1 is the output, XTAL_IN1 is the input.
Input
Input
13,
14
XTAL_OUT0,
XTAL_IN0
Parallel resonant crystal interface.
XTAL_OUT0 is the output, XTAL_IN0 is the input.
15
CLK
Input
Input
Pulldown
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
16, 17
SEL0, SEL1
Input MUX select pins. LVCMOS/LVTTL interface levels. See Table 3D.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true output Q to go low and the inverted output nQ to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
18
MR
Input
Pulldown
19, 20, 21
M0, M1, M2
OE_REF
Input
Input
Pullup
Feedback divider select pins. LVCMOS/LVTTL interface levels. See Table 3B.
Reference clock output enable. Default LOW. See Table 3E.
LVCMOS/LVTTL interface levels.
22
24
Pulldown
REF_OUT
Output
Reference clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
21
25
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
VCCO = 3.3V
VCCO = 2.5V
ROUT Output Impedance
REF_OUT
Ω
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
2
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Function Tables
Table 3A. Common Configuration Table
VCO
Frequency
(MHz)
Input Frequency
(MHz)
M Feedback Divider
Value
N Output Divider
Value
16
16
8
Output Frequency (MHz)
Application
HDTV
27
24.75
19.44
19.44
19.44
25
44
48
64
64
64
50
50
50
50
50
45
48
48
48
51
51
51
1188
1188
74.25
74.25
155.52
622.08
311.04
125
HDTV
1244.16
1244.16
1244.16
1250
SONET
2
SONET
4
SONET
10
8
GigE
25
1250
156.25
250
10 GigE
25
1250
5
GigE
25
1250
4
312.5
625
XGMII
25
1250
2
10 GigE
25
1125
6
187.5
100
12 GigE
25
1200
12
8
PCI Express
SATA
25
1200
150
25
1200
16
12
8
75
SATA
25
1275
106.25
159.375
212.5
Fibre Channel
10 Gig Fibre Channel
4 Gig Fibre Channel
25
1275
25
1275
6
Table 3B. Programmable M Feedback Divider Function Table
Inputs
Input Frequency (MHz)
M Feedback Divider
Value
M2
0
M1
0
M0
0
Minimum
25.5
Maximum
27
44
0
0
1
45
24.9
27
0
1
0
48
50
23.3
26.56
25.5
25
0
1
1
22.4
1
0
0
51
22.0
1
0
1
64 (default)
19.44
19.92
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
3
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Table 3C. Programmable N Output Divider Function Table
Inputs
N2
0
N1
0
N0
0
N Divider Value
2
0
0
1
4
0
1
0
5
0
1
1
6
8 (default)
10
1
0
0
1
0
1
1
1
0
12
1
1
1
16
Table 3D. Select Mode Function Table
Inputs
SEL1
SEL0
Reference Input
XTAL0
PLL Mode
Active (default)
Active
0
0
1
1
0
1
0
1
XTAL1
CLK
Active
CLK
Bypass
Table 3E. OE_REF Output Function Table
Input
Output
REF_OUT
OE_REF
0
1
High-Impedance (default)
Active
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
4
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
XTAL_IN
Other Input
0V to VCC
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, VO (LVCMOS)
-0.5V to VCCO_LVCMOS + 0.5V
32.1°C/W (0 mps)
Package Thermal Impedance, θJA
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V = V
= V
= 3.3V 5%, V = 0V,
CCO_LVPECL EE
CC
CCO_LVCMOS
T = -40°C to 85°C
A
Symbol
VCC
Parameter
Test Conditions
Minimum
Typical
Maximum
3.465
Units
Core Supply Voltage
3.135
3.3
3.3
V
V
VCCA
Analog Supply Voltage
VCC – 0.11
VCC
VCCO_LVPECL,
VCCO_LVCMOS
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
Analog Supply Current
140
11
mA
mA
ICCA
Outputs Unterminated
Table 4B. Power Supply DC Characteristics, V = 3.3V 5%, V
= V
= 2.5V 5%, V = 0V,
CCO_LVPECL EE
CC
CCO_LVCMOS
T = -40°C to 85°C
A
Symbol
VCC
Parameter
Test Conditions
Minimum
3.135
Typical
Maximum
3.465
Units
Core Supply Voltage
3.3
3.3
V
V
VCCA
Analog Supply Voltage
VCC – 0.11
VCC
VCCO_LVPECL,
VCCO_LVCMOS
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
Analog Supply Current
139
11
mA
mA
ICCA
Outputs Unterminated
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
5
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Table 4C. Power Supply DC Characteristics, V = V
= V
= 2.5V 5%, V = 0V,
CCO_LVPECL EE
CC
CCO_LVCMOS
T = -40°C to 85°C
A
Symbol
VCC
Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
Units
Core Supply Voltage
2.625
VCC
V
V
VCCA
Analog Supply Voltage
VCC – 0.10
2.375
2.5
VCCO_PECL,
VCCO_CMOS
Output Supply Voltage
2.5
2.625
V
IEE
Power Supply Current
Analog Supply Current
133
10
mA
mA
ICCA
Outputs Unterminated
Table 4D. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C
Symbol Parameter Test Conditions
Minimum
Typical
Maximum
VCC + 0.3
VCC + 0.3
0.8
Units
VCC = 3.3V
VCC = 2.5V
2
V
V
V
V
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
V
CC = 3.3V
CC = 2.5V
Input Low Voltage
Input High Current
V
0.7
CLK, OE_REF, MR,
N0, N1 SEL0, SEL1
V
CC = VIN = 3.465V or
2.625V
150
5
µA
µA
µA
µA
V
IIH
V
CC = VIN = 3.465V or
2.625V
N2, M[2:0]
CLK, OE_REF, MR,
N0, N1 SEL0, SEL1
V
CC = 3.465V or 2.625V,
-5
-150
2.6
VIN = 0V
IIL
Input Low Current
VCC = 3.465V or 2.625V,
VIN = 0V
N2, M[2:0]
VCCO_LVCMOS = 3.465V,
IOH = -12mA
VOH
Output High Voltage REF_OUT
Output Low Voltage REF_OUT
VCCO_LVCMOS = 2.625V,
IOH = -12mA
1.8
V
VCCO_LVCMOS = 3.465V or
2.625V, IOL = 12mA
VOL
0.5
V
.
Table 4E. LVPECL DC Characteristics, VCC = VCCO_LVPECL = 3.3V 5%, V = 0V, TA = -40°C to 85°C
EE
Symbol Parameter
Test Conditions
Minimum
VCCO_LVPECL – 1.4
VCCO_LVPECL – 2.0
0.6
Typical
Maximum
Units
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VCCO_LVPECL – 0.9
VCCO_LVPECL – 1.7
1.0
V
V
V
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL – 2V.
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
6
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Table 4F. LVPECL DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VCCO_LVPECL = 2.5V 5%, V = 0V,
EE
TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VCCO_LVPECL – 1.4
VCCO_LVPECL – 2.0
0.4
Typical
Maximum
VCCO_LVPECL – 0.9
VCCO_LVPECL – 1.5
1.0
Units
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
V
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL – 2V.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Fundamental
Maximum
Units
Mode of Oscillation
Frequency
19.44
27
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
AC Electrical Characteristics
Table 6A. AC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 3.3V 5%, V = 0V, TA = -40°C to 85°C
EE
Symbol
Parameter
Test Conditions
Minimum
70
Typical
Maximum
637.5
27
Units
MHz
MHz
Q, nQ
fOUT
Output Frequency
REF_OUT
19.44
Propagation Delay; CLK to
tPD
2.2
2.7
ns
ps
NOTE 1
REF_OUT
RMS Phase Jitter, (Random);
NOTE 2
622.08MHz,
(12kHz – 20MHz)
tjit(Ø)
0.97
fVCO
PLL VCO Lock Range
1.12
200
1.275
700
GHz
ps
Q, nQ
20% to 80%
20% to 80%
Output
Rise/Fall Time
tR / tF
REF_OUT,
NOTE 3
250
46
650
54
ps
%
Q, nQ
odc
Output Duty Cycle
PLL Lock Time
REF_OUT;
NOTE 3
Using Clock Input
48
52
%
tLOCK
60
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%.
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
7
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Table 6B. AC Characteristics, VCC = 3.3V 5%, VCCO_LVCMOS = VCCO_LVPECL = 2.5V 5%, V = 0V, TA = -40°C to 85°C
EE
Symbol
Parameter
Test Conditions
Minimum
70
Typical
Maximum
637.5
27
Units
MHz
MHz
Q, nQ
fOUT
Output Frequency
REF_OUT
19.44
Propagation Delay; CLK to
tPD
2.3
2.9
ns
ps
NOTE 1
REF_OUT
RMS Phase Jitter, (Random);
NOTE 2
622.08MHz,
(12kHz – 20MHz)
tjit(Ø)
1
fVCO
PLL VCO Lock Range
1.12
200
350
46
1.275
700
750
54
GHz
ps
Q, nQ
20% to 80%
20% to 80%
Output
Rise/Fall Time
tR / tF
REF_OUT
Q, nQ
ps
%
odc
Output Duty Cycle
PLL Lock Time
REF_OUT;
NOTE 3
Using Clock Input
48
52
60
%
tLOCK
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%.
Table 6C. AC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 2.5V 5%, V = 0V, TA = -40°C to 85°C
EE
Symbol
Parameter
Test Conditions
Minimum
70
Typical
Maximum
637.5
27
Units
MHz
MHz
Q, nQ
fOUT
Output Frequency
REF_OUT
19.44
Propagation Delay; CLK to
tPD
2.3
2.9
ns
ps
NOTE 1
REF_OUT
RMS Phase Jitter, (Random);
NOTE 2
622.08MHz,
(12kHz – 20MHz)
tjit(Ø)
1.1
fVCO
PLL VCO Lock Range
1.12
200
350
46
1.275
700
750
54
GHz
ps
Q, nQ
20% to 80%
20% to 80%
Output
Rise/Fall Time
tR / tF
REF_OUT
Q, nQ
ps
%
odc
Output Duty Cycle
PLL Lock Time
REF_OUT;
NOTE 3
Using Clock Input
48
52
60
%
tLOCK
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%.
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
8
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Typical Phase Noise at 622.08MHz
.
622.08MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.97ps (typical)
Offset Frequency (Hz)
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
9
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Parameter Measurement Information
2V
1.65V 5%
1.65V 5%
2V
SCOPE
SCOPE
V
V
CC,
Qx
CCO_LVCMOS
V
V
CC,
CCO_LVPECL
V
CCA
Qx
V
CCA
VEE
nQx
VEE
-1.65V 5%
-1.3V 0.165V
3.3V LVPECL Output Load AC Test Circuit
3.3V LVCMOS Output Load AC Test Circuit
2V
1.25V 5%
1.25V 5%
2V
SCOPE
SCOPE
V
V
CC,
Qx
CCO_LVCMOS
V
Qx
CCA
V
CCA
V
CC,
V
CCO_LVPECL
VEE
nQx
VEE
-1.25V 5%
-0.5V 0.125V
2.5V LVPECL Output Load AC Test Circuit
2.5V LVCMOS Output Load AC Test Circuit
2.8V 0.04V
2V
2.05V 5%
1.25V 5%
2.05V 5%
2.8V 0.04V
V
CC
SCOPE
SCOPE
V
Qx
CC
V
CCO_LVPECL
V
CCO_LVPECL
V
Qx
CCA
V
CCA
nQx
VEE
VEE
-1.25V 5%
-0.5V 0.125V
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
3.3 Core/2.5V LVPECL Output Load AC Test Circuit
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
10
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Parameter Measurement Information, continued
Phase Noise Plot
VCCO_CMOS
2
REF_OUT
tPW
tPERIOD
tPW
odc =
x 100%
Offset Frequency
f1
f2
tPERIOD
RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers
RMS Phase Jitter
LVCMOS Output Duty Cycle/Pulse Width/Period
nQ
Q
80%
tF
80%
tR
tPW
tPERIOD
20%
20%
REF_OUT
tPW
odc =
x 100%
tPERIOD
LVPECL Output Duty Cycle/Pulse Width/Period
LVCMOS Output Rise/Fall Time
nQ
80%
tF
80%
tR
VSWING
20%
20%
Q
LVPECL Output Rise/Fall Time
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
11
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
LVPECL Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
The unused LVPECL output pair can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS Output
CLK Input
All unused LVCMOS output can be left floating. We recommend that
there is no trace attached.
For applications not requiring the use of the clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
12
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 1A. The XTAL_OUT pin can be left floating. The
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50Ω
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
applications, R1 and R2 can be 100Ω. This can also be accomplished
by removing R1 and making R2 50Ω. By overdriving the crystal
oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
resistance (Rs) equals the transmission line impedance. In addition,
3.3V
3.3V
R1
100
C1
Ro
~ 7 Ohm
Zo = 50 Ohm
XTAL_I N
RS
43
0.1uF
R2
Driver_LVCMOS
100
XTAL_OU T
Crystal Input Interf ace
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC=3.3V
C1
Zo = 50 Ohm
XTAL_IN
0.1uF
R1
Zo = 50 Ohm
50
XTAL_OUT
LVPECL
Cry stal Input Interface
R2
50
R3
50
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
13
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
R3
R4
3.3V
125Ω
125Ω
3.3V
3.3V
Z
o = 50Ω
3.3V
+
_
Z
o = 50Ω
+
_
Input
LVPECL
Zo = 50Ω
LVPECL
Input
Zo = 50Ω
R1
R2
50Ω
50Ω
R1
84Ω
R2
84Ω
VCC - 2V
1
RTT =
* Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
Figure 2A. 3.3V LVPECL Output Termination
Figure 2B. 3.3V LVPECL Output Termination
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
14
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Termination for 2.5V LVPECL Outputs
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in Figure 3C.
2.5V
VCCO = 2.5V
2.5V
2.5V
VCCO = 2.5V
R1
R3
50Ω
250
250
+
50Ω
50Ω
+
–
50Ω
–
2.5V LVPECL Driver
R1
50
R2
50
2.5V LVPECL Driver
R2
62.5
R4
62.5
R3
18
Figure 3A. 2.5V LVPECL Driver Termination Example
Figure 3B. 2.5V LVPECL Driver Termination Example
2.5V
VCCO = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50
R2
50
Figure 3C. 2.5V LVPECL Driver Termination Example
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
15
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Schematic Layout
Figure 6 (next page) shows an example of ICS843001I-23 application
0.1uF capacitor in each power pin filter should be placed on the
device side. The other components can be on the opposite side of the
PCB.
schematic. In this example, the device is operated VCC
=
VCCO_LVCMOS = VCCO_LVPECL = 3.3V. The 18pF parallel resonant
17.5-29.54MHz crystal is used. The load capacitance C1 = 22pF and
C2 = 22pF are recommended for frequency accuracy. Depending on
the parasitic of the printed circuit board layout, these values might
require a slight adjustment to optimize the frequency accuracy.
Crystals with other load capacitance specifications can be used. This
will require adjusting C1 and C2. For this device, the crystal load
capacitors are required for proper operation.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequency. This
low-pass filter starts to attenuate noise at approximately 10kHz. If a
specific frequency noise component with high amplitude interference
is known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally general design practice for
power plane voltage stability suggests adding bulk capacitances in
the general area of all devices.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS843001I-23 provides
separate power supplies to isolate any high switching noise from
coupling into the internal PLL.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
16
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
R
1
33
Z o = 50 Ohm
RE F_O UT
3. 3V
LV CMOS
U
1
R2
R 3
V CCO
133
133
Zo
Zo
=
=
50 Ohm
Q
1
24
V CCO_LV CMOS RE F_OUT
VCCO
N0
2
3
23
22
TL2
N0
N1
VE E
+
-
N1
N2
OE _RE F
M2
O E_RE F
V CC
R4
4
21
50 Ohm
N2
M2
M1
M0
10
V CCA
5
6
20
19
/Q
V CCO_LV PE CL
Q
M1
M0
Q
MR
C6
nQ
7
18
TL3
nQ
MR
C4
0. 1u
8
9
17
16
SE L1
SE L0
V EE
S EL1
S EL0
10u
VC C
V CCA
10
11
12
15
14
13
CLK
R5
R 6
V CC
CLK
XTA L_IN0
XTA L_O UT1
XTAL_I N 1
XTAL_IN0
V CC=3.3V
82. 5
82.5
XTA L_OU T1
XTA L_O U T0
XTA L_IN
1
XTAL_OU T0
V CCO_LV CMOS=3.3V
V CCO_LV PECL=3.3V
X1
29.54MH
18p F
C
3
C2
X2
18p F
22pF
17. 5MHz
-
z
22pF
17. 5MHz - 29. 54MHz
Zo
Zo
=
=
50 O hm
50 O hm
Q
+
-
C5
22 p F
C1
22pF
/Q
V DD
R7
50
R8
50
Logic Control Input Examples
Q1
Ro
~ 7 Ohm
R
9
Z o = 50 Ohm
Set Logic
Input to
'1'
Set Logic
Optional
LVPECL
VC C
VC C
Input to
'0'
R10
50
43
Y-Termination
R
U1
RU2
Driv er_LVCMO S
1K
Not Install
To Logic
Input
To Logic
Input
pins
3. 3V
pins
m urAta, BLM18B B221S N1
2
R
N
D1
RD2
1K
(U1:10)
ot Install
1
V CC
F B1
C
8
C9
C7
0. 1uF
10uF 0. 1uF
3. 3V
m urAta, BLM18B B221S N1
2
(U1:1)
(U1:5)
1
V CCO
F B2
C
11
C12
C
13
C10
0. 1uF
10uF 0. 1uF
0. 1 u F
Figure 6. ICS843001I-23 Layout Example
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
17
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 7. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, refer to the Application Note
on the Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
SOLDER
SOLDER
EXPOSED HEAT SLUG
PIN
PIN
LAND PATTERN
(GROUND PAD)
PIN PAD
GROUND PLANE
PIN PAD
THERMAL VIA
Figure 7. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
18
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS843001I-23.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843001I-23 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.1mW
Power (outputs)MAX = 30mW/Loaded Output pair
LVCMOS Output Power Dissipation
•
Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDDO/2
Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 21Ω)] = 24.4mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 21Ω * (24.4mA)2 = 12.5mW per output
Total Power Dissipation
•
Total Power
= Power (core) + Power (LVPECL output) + Power (ROUT
)
= 485.1mW + 30mW + 12.5mW = 527.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 32.1°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.528W * 32.1°C/W = 102°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resitance θJA for 24 Lead TSSOP, E-Pad Forced Convection
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
32.1°C/W
25.5°C/W
24.0°C/W
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
19
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of
VCCO – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCOO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX– 2V))/RL] * (VCCO_MAX– VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX– VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX (VCCO_MAX– 2V))/RL] * (VCCO_MAX– VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX– VOL_MAX) =
–
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
20
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Reliability Information
Table 8. θJA vs. Air Flow Table for a 24 Lead TSSOP, E-pad
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
32.1°C/W
25.5°C/W
24.0°C/W
Transistor Count
The transistor count for ICS843001I-23 is: 4165
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
21
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Package Outline and Package Dimensions
Package Outline - G Suffix for 24 Lead TSSOP, E-Pad
Table 9. Package Dimensions
All Dimensions in Millimeters
Symbol
N
Minimum
Maximum
24
A
1.10
0.15
0.95
0.30
0.25
0.20
0.16
7.90
A1
A2
b
0.05
0.85
0.19
0.19
0.09
0.09
7.70
b1
c
c1
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.50
5.0
3.0
0°
0.70
5.5
3.2
8°
P
P1
α
aaa
bbb
0.076
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
22
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Ordering Information
Table 10. Ordering Information
Part/Order Number
843001CGI-23
Marking
Package
24 Lead TSSOP, E-Pad
Shipping Packaging
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS843001CI23
ICS843001CI23
ICS43001CI23L
ICS43001CI23L
843001CGI-23T
843001CGI-23LF
843001CGI-23LFT
24 Lead TSSOP, E-Pad
2500 Tape & Reel
Tube
“Lead-Free” 24 Lead TSSOP, E-Pad
“Lead-Free” 24 Lead TSSOP, E-Pad
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS843001CGI-23 REVISION A OCTOBER 4, 2011
23
©2011 Integrated Device Technology, Inc.
ICS843001I-23 Data Sheet
FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER
We’ve Got Your Timing Solution
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
San Jose, California 95138
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2011. All rights reserved.
相关型号：
ICS843001BGI-23LF
Clock Generator, 650MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
IDT
ICS843001BGI-23T
Clock Generator, 650MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
IDT
©2020 ICPDF网 联系我们和版权申明