ICS843001I-22 [ICSI]
FEMTOCLOCKS? CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER; FEMTOCLOCKS ？ CRYSTAL / LVCMOS - TO- 3.3V ， 2.5V LVPECL频率合成器
| 型号： | ICS843001I-22 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总17页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS843001I-22
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS843001I-22 is a a highly versatile, low
• One 3.3V or 2.5V LVPECL output pair and
one LVCMOS/LVTTL output
ICS
phase noise LVPECL/LVCMOS Synthesizer
which can generate low jitter reference clocks for
a variety of communications applications and is
a member of the HiPerClocksTM family of high
performance clock solutions from ICS.The dual
HiPerClockS™
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• VCO range: 490MHz - 640MHz
crystal interface allows the synthesizer to support up to two
communications standards in a given application (i.e. 1GB
Ethernet with a 25MHz crystal and 1Gb Fibre Channel
using a 25.5625MHz crystal). The rms phase jitter
performance is typically less than 1ps, thus making the
device acceptable for use in demanding applications such
as OC48 SONET and 10Gb Ethernet. The ICS843001I-22
is packaged in a small 24-pin TSSOP package.
• Output frequency range: 490MHz - 640MHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 125MHz (1.875MHz - 20MHz):
0.5ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free
compliant packages
CONTROL INPUT FUNCTION TABLE
Control Input
Outputs
PIN ASSIGNMENT
OE
Q/nQ
High-Z
High-Z
Active
REF_OUT
High-Z
1
VCCO_LVCMOS
REF_OUT
VEE
24
23
22
21
20
19
18
17
16
15
14
13
0
1
2
3
N0
N1
OE
Active
N2
4
M2
FLOAT
High-Z
5
VCCO_LVPECL
Q
M1
M0
6
7
MR
nQ
8
SEL1
SEL0
CLK
VEE
VCCA
BLOCK DIAGRAM
9
3
10
11
12
VCC
N2:N0
XTAL_IN0
XTAL_OUT0
XTAL_OUT1
XTAL_IN1
Pulldown
SEL0
ICS843001I-22
Pulldown
SEL1
24-LeadTSSOP
4.40mm x 7.8mm x 0.92mm
package body
N
000 ÷1
XTAL_IN0
OSC
G Package
001 ÷2
00
01
11
Top View
010 ÷3
Q
XTAL_OUT0
011 ÷4 (default)
100 ÷5
10
01
00
nQ
VCO
Phase
Detector
490MHz -640MHz
XTAL_IN1
OSC
101 ÷6
110 ÷8
111 ÷10
XTAL_OUT1
M
000 ÷18
Pulldown
CLK
10
11
001 ÷22
010 ÷24
011 ÷25
100 ÷32 (default)
101 ÷40
Pulldown
MR
3
M2:M0
REF_OUT
Pullup/Pulldown
OE
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ICS843001I-22
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
VCCO_LVCMOS,
VCCO_LVPECL
1, 5
Power
Output supply pins.
2, 3
4
N0, N1
N2
Input
Input
Pullup
Pulldown
Output divider select pins. Default value = ÷4.
LVCMOS/LVTTL interface levels. See Table 3C.
6, 7
8, 23
9
Q, nQ
VEE
Ouput
Power
Power
Power
Differential output pair. LVPECL interface levels.
Negative supply pin.
VCCA
VCC
Analog supply pin.
10
Core supply pin.
11
12
13
14
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
Parallel resonant crystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Parallel resonant crystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
Input
Input
15
CLK
Input
Input
Pulldown LVCMOS/LVTTL clock input.
16, 17
SEL0, SEL1
Pulldown Input MUX select pins. LVCMOS/LVTTL interface levels. See Table 3D.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true output Q to go low and the inverted output nQ
to go high. When logic LOW, the internal dividers and the outputs are
18
MR
Input
Pulldown
enabled. LVCMOS/LVTTL interface levels.
19, 20
21
M0, M1
M2
Input
Input
Pulldown
Pullup
Feedback divider select pins. Default value = ÷32.
LVCMOS/LVTTL interface levels. See Table 3B.
3-State clock output enable, (High/Low/Float).
See page 1, Control Input Function Table.
22
24
OE
Input
REF_OUT
Output
Reference clock output. LVCMOS/LVTTL interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
51
51
15
RPULLUP
Rout
Input Pullup Resistor
Output Impedance
REF_CLK
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ICS843001I-22
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 3A. COMMON CONFIGURATIONS TABLE
Input
Output Frequency
M Divider Value N Divider Value VCO (MHz)
Application
(MHz)
Reference Clock (MHz)
27
22.4
22
25
24
24
40
32
32
32
32
32
25
25
25
24
24
24
24
24
24
18
8
8
8
3
8
4
8
1
2
4
2
5
10
6
4
8
6
3
4
3
594
560
74.25
70
HDTV
24.75
25
594
74.25
200
HDTV
Processor
HDTV
600
14.8351649
19.44
19.44
19.44
19.44
19.53125
20
593.4066
622.08
622.08
622.08
622.08
625
74.1758245
155.52
77.76
622.08
311.04
156.25
250
SONET
SONET
SONET
SONET
10 GigE
500
Ethernet
25
625
125
1 GigE
25
625
62.5
1 GigE
25
600
100
PCI Express
SATA
25
600
150
25
600
75
SATA
26.5625
26.5625
26.5625
31.25
637.5
637.5
637.5
562.5
106.25
212.5
159.375
187.5
Fibre Channel 1
4 Gig Fibre Channel
10 Gig Fibre Channel
12 Gig Ethernet
TABLE 3C. PROGRAMMABLE N OUTPUT DIVIDER
FUNCTION TABLE
TABLE 3B. PROGRAMMABLE M OUTPUT DIVIDER
FUNCTION TABLE
Inputs
Input Frequency (MHz)
Minimum Maximum
Inputs
M Divider
Value
N Divide Value
M2
0
M1
0
M0
0
N2
0
N1
0
N0
0
18
22
24
25
32
40
27.22
22.27
20.41
19.6
35.56
29.09
26.67
25.6
20
1
2
3
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
4 (default)
1
0
0
15.31
12.25
1
0
0
5
6
1
0
1
1
0
1
16
1
1
0
8
1
1
1
10
TABLE 3D. BYPASS MODE FUNCTION TABLE
Inputs
Reference
Input
PLL Mode
SEL1 SEL0
0
0
1
1
0
1
0
1
XTAL0
XTAL1
CLK
Active
Active
Active
Bypass
CLK
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ICS843001I-22
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, VO (LVCMOS)
-0.5V to VCCO + 0.5V
PackageThermal Impedance, θ
70°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature,T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL= 3.3V 10ꢀ, TA = -40°C TO 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum Typical Maximum Units
Core Supply Voltage
Analog Supply Voltage
2.97
2.97
3.3
3.3
3.63
3.63
V
V
VCCA
VCCO_LVPECL,
VCCO_LVCMOS
Output Supply Voltage
2.97
3.3
3.63
V
IEE
Power Supply Current
Output Supply Current
160
8
mA
mA
ICCO
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum Typical
Maximum Units
Core Supply Voltage
Analog Supply Voltage
2.375
2.375
2.5
2.5
2.625
2.625
V
V
VCCA
VCCO_LVPECL,
VCCO_LVCMOS
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
Output Supply Current
155
8
mA
mA
ICCO
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ICS843001I-22
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS = 3.3V 10ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCC = 3.3V 10ꢀ
2
VCC + 0.3
VCC + 0.3
V
V
V
V
V
V
VIH
VIM
VIL
Input High Voltage
VCC = 2.5V 5ꢀ
1.7
Input Medium Voltage
Input Low Voltage
V
CC = 3.3V 10ꢀ
-0.3
-0.3
0.8
0.7
V
V
CC = 2.5V 5ꢀ
CC = VIN = 3.63V
or 2.625V
CLK, SEL0, SEL1, MR,
M0, M1, N2, OE
150
5
µA
Input
High Current
IIH
VCC = VIN = 3.63V
M2, N0, N1
µA
µA
or 2.625V
Input
Medium Current
IIM
V
CC = 3.63V or 2.625V,
VIN = 0V
CLK, SEL0, SEL1, MR,
M0, M1, N2, OE
-5
µA
µA
Input
Low Current
IIL
VCC = 3.63V or 2.625V,
VIN = 0V
M2, N0, N1, OE
-150
VCCO_LVCMOS = 3.63V
2.6
1.8
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage: Note 1
V
CCO_LVCMOS = 2.625V
VCCO_LVCMOS = 3.63V
0.5
V
or 2.625V
NOTE 1: Outputs terminated with 50Ω to VCCO _LVCMOS/2. See Parameter Measurement Information Section,
"Output Load Test Circuit Diagram".
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL = 3.3V 10ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Mode of Oscillation
Fundamental
MHz
MHz
Ω
Frequency
14
35.55
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
Drive Level
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
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FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC =VCCA =VCCO_LVCMOS, VCCO_LVPECL= 3.3V 10ꢀ, TA = -40°C TO 85°C
Symbol Parameter
fIN Input Frequency CLK
Test Conditions
SEL1 = 1, SEL0 = 0
SEL1 = 1, SEL0 = 0
Minimum Typical Maximum Units
14
35.55
250
MHz
MHz
DC
TABLE 7A. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL = 3.3V 10ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
49
640
MHz
RMS Phase Jitter, (Random);
NOTE 1
tjit(Ø)
fVCO
125MHz (1.875MHz - 20MHz)
0.5
ps
PLL VCO Lock Range
490
200
200
45
640
500
700
55
MHz
ps
Q/nQ
Output Rise/Fall
Time
tR / tF
odc
20ꢀ to 80ꢀ
REF_OUT
Q/nQ
ps
ꢀ
Output Duty Cycle
REF_OUT
IJ 250MHz
44
56
ꢀ
NOTE 1: Phase jitter using a crystal interface.
TABLE 7B. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL= 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
49
640
MHz
RMS Phase Jitter, (Random);
NOTE 1
tjit(Ø)
fVCO
125MHz (1.875MHz - 20MHz)
0.5
ps
PLL VCO Lock Range
490
200
300
45
640
500
800
55
MHz
ps
Q/nQ
Output Rise/Fall
Time
tR / tF
odc
20ꢀ to 80ꢀ
REF_OUT
Q/nQ
ps
ꢀ
Output Duty Cycle
REF_OUT
IJ 250MHz
44
56
ꢀ
NOTE 1: Phase jitter using a crystal interface.
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ICS843001I-22
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TYPICAL PHASE NOISE AT 125MHZ
0
-10
10Gb Ethernet Filter
-20
-30
-40
-50
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.5ps (typical)
-60
-70
-80
-90
-100
Raw Phase Noise Data
-110
-120
-130
-140
-150
-160
-170
Phase Noise Result by adding a
10Gb Ethernet Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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ICS843001I-22
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.65 10ꢀ
2V
SCOPE
VCC,
VCCA,
VCCO_LVPECL
Qx
SCOPE
VCC,
VCCA,
VCCO_LVCMOS
Qx
LVPECL
LVCMOS
VEE
nQx
VEE
-1.3V 0.33V
-1.65V 10ꢀ
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
2V
1.25V 5ꢀ
SCOPE
VCC,
VCCA,
VCCO_LVPECL
Qx
SCOPE
VCC,
VCCA,
VCCO_LVCMOS
LVPECL
Qx
LVCMOS
nQx
VEE
VEE
-0.5V 0.125V
-1.25V 5ꢀ
2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
VCCO_LVCMOS
2
REF_OUT
tPW
tPERIOD
Phase Noise Mask
tPW
odc =
x 100ꢀ
Offset Frequency
tPERIOD
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
nQ
Q
80ꢀ
tF
80ꢀ
tR
tPW
20ꢀ
20ꢀ
tPERIOD
Clock
Outputs
tPW
odc =
x 100ꢀ
tPERIOD
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVCMOS OUTPUT RISE/FALL TIME
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
Clock
Outputs
20ꢀ
LVPECL OUTPUT RISE/FALL TIME
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ICS843001I-22
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS843001I-22 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, andVCCO_x
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V or 2.5V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
capacitor should be connected to each VCCA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843001I-22 has been characterized with 18pF paral-
lel resonant crystals. The capacitor values shown in Figure 2
below were determined using a 26.5625MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
ICS843001I-22
Figure 2. CRYSTAL INPUt INTERFACE
843001AGI-22
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ICS843001I-22
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVCMOS OUTPUT:
For applications not requiring the use of the crystal oscillator All unused LVCMOS output can be left floating. We
input, both XTAL_IN and XTAL_OUT can be left floating. recommend that there is no trace attached.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
CLK INPUT:
For applications not requiring the use of the test clock, it can differential output pair should either be left floating or
be left floating. Though not required, but for additional terminated.
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
outputs are designed to drive 50Ω transmission lines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUTT ERMINATION
FIGURE 3B. LVPECL OUTPUTT ERMINATION
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FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for close to ground level. The R3 in Figure 4B can be eliminated
and the termination is shown in Figure 4C.
2.5V LVPECL driver.These terminations are equivalent to ter-
minating 50Ω to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
R3
250
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
Zo = 50 Ohm
2,5V LVPECL
2,5V LVPECL
Driv er
Driver
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 4B. 2.5V LVPECL DRIVERTERMINATION EXAMPLE
FIGURE 4A. 2.5V LVPECL DRIVERTERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 4C. 2.5V LVPECLTERMINATION EXAMPLE
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843001I-22.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843001I-22 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 160mA = 554.4mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 554.4mW + 30mW = 584.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 8
below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.584W * 65°C/W = 123°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 8.THERMAL RESISTANCE θJA FOR 24-PINTSSOP, FORCED CONVECTION
θ
JA by Velocity (Meters per Second)
0
1
2.5
62°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT ANDTERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination
voltage of V - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
CCO
OH_MAX
CCO_MAX
OH_MAX
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW L
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
CCO
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
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Systems, Inc.
RELIABILITY INFORMATION
TABLE 9. θJAVS. AIR FLOWTABLE FOR 24 LEADTSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS843001I-22 is: 3881
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PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 10. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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TABLE 11. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS843001AGI-22
ICS843001AGI-22T
ICS843001AGI-22LF
ICS843001AGI-22LFT
ICS843001AI22
ICS843001AI22
ICS43001AI22L
ICS43001AI22L
24 Lead TSSOP
24 Lead TSSOP
2500 tape & reel
tube
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
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