ICS557G-06 [IDT]
1 TO 4 HCSL CLOCK BUFFER; 1至4 HCSL时钟缓冲器
| 型号： | ICS557G-06 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 1 TO 4 HCSL CLOCK BUFFER |
| 文件： | 总11页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
1 TO 4 HCSL CLOCK BUFFER
ICS557-06
Description
Features
The ICS557-06 is a one to four differential clock buffer
designed for use in PCI-Express applications. The device
selects one of the two differential HCSL or LVDS input pairs
and fans out to four pairs of differential HCSL or LVDS
outputs.
• Packaged in 20-pin TSSOP
• Available in Pb (lead) free package
• Operating voltage of 3.3 V
• Low power consumption
• Input differential clock of up to 200 MHz for HCSL and up
to 100 MHz for LVDS
• Jitter 60 ps (cycle-to-cycle)
• Output-to-output skew of 50 ps
• Available in industrial temperature range (-40 to +85°C)
Block Diagram
OE
VDD
2
CLKA
CLKA
CLKB
IN1
IN1
CLKB
CLKC
MUX
2 to 1
IN2
IN2
CLKC
CLKD
CLKD
2
Rr (IREF)
SEL
GND
PD
IDT™ / ICS™ 1 TO 4 HCSL CLOCK BUFFER
1
ICS557-06
REV F 090407
ICS557-06
1 TO 4 HCSL CLOCK BUFFER
PCIE FAN OUT BUFFER
Pin Assignment
Select Table
SEL
VDDIN
IN1
1
2
20
19
18
17
16
15
14
13
12
11
CLKA
CLKA
CLKB
CLKB
GND
SEL
Input Pair
selected
IN2/ IN2
IN1/ IN1
3
0
1
IN1
4
5
PD
6
IN2
VDD
7
CLKC
IN2
8
OE
CLKC
CLKD
CLKD
9
GND
IREF
10
20-pin (173 mil) TSSOP
Pin Descriptions
Pin
Pin
Pin
Pin Description
Name
Type
1
2
3
4
5
6
7
8
SEL
VDDIN
IN1
Input SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor.
Power Connect to +3.3 V. Supply voltage for Input clocks.
Input HCSL/LVDS true input signal 1.
IN1
Input HCSL/LVDS complimentary input signal 1.
PD
Input Powers down the chip and tri-states outputs when low. Internal pull-up
Input HCSL/LVDS true input signal 2.
IN2
IN2
Input HCSL/LVDS complimentary input signal 2.
OE
Input Provides fast output on, tri-states output (High = enable outputs; Low =
disable). Internal pull-up resistor outputs.
9
GND
Rr(IREF)
CLKD
Power Connect to ground.
10
11
12
13
14
15
16
Output Precision resistor attached to this pin is connected to the internal current
Output Differential Complimentary output clock D.
Output Differential True output clock D.
CLKD
CLKC
Output Differential Complimentary output clock C.
Output Differential True output clock C.
CLKC
VDDOUT
GND
Power Connect to +3.3 V. Supply Voltage for Output Clocks.
Power Connect to ground.
17
18
19
20
CLKB
CLKB
CLKA
CLKA
Output Differential Complimentary output clock B.
Output Differential True output clock B.
Output Differential Complimentary output clock A.
Output Differential True output clock A.
IDT™ / ICS™ 1 TO 4 HCSL CLOCK BUFFER
2
ICS557-06
REV F 090407
ICS557-06
1 TO 4 HCSL CLOCK BUFFER
PCIE FAN OUT BUFFER
Application Information
Decoupling Capacitors
External Components
As with any high-performance mixed-signal IC, the
ICS557-06 must be isolated from system power supply
noise to perform optimally.
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01 µF should
be connected between VDD and GND pairs (2,9 and 15,16)
as close to the device as possible.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
Current Reference Source Rr (Iref)
If board target trace impedance (Z) is 50Ω, then Rr = 475Ω
PCB Layout Recommendations
(1%), providing IREF of 2.32 mA, output current (I ) is
OH
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
equal to 6*IREF.
Load Resistors RL
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
Since the clock outputs are open source outputs, 50 ohm
external resistors to ground are to be connected at each
clock output.
Output Termination
The PCI-Express differential clock outputs of the ICS557-06
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines section.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS557-06.
The ICS557-06 can also be configured for LVDS compatible
voltage levels. See the LVDS Compatible Layout
Guidelines section.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
IDT™ / ICS™ 1 TO 4 HCSL CLOCK BUFFER
3
ICS557-06
REV F 090407
ICS557-06
1 TO 4 HCSL CLOCK BUFFER
PCIE FAN OUT BUFFER
Output Structures
6*IREF
IREF
=2.3 mA
See Output Termination
Sections - Pages 3 ~ 5
RR 475
W
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the ICS557-06.This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
IDT™ / ICS™ 1 TO 4 HCSL CLOCK BUFFER
4
ICS557-06
REV F 090407
ICS557-06
1 TO 4 HCSL CLOCK BUFFER
PCIE FAN OUT BUFFER
PCI-Express Layout Guidelines
Common Recommendations for Differential Routing
Dimension or Value Unit
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
RS
RT
0.5 max
0.2 max
0.2 max
33
inch
inch
inch
ohm
ohm
49.9
Differential Routing on a Single PCB
Dimension or Value Unit
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
2 min to 16 max
1.8 min to 14.4 max
inch
inch
Differential Routing to a PCI Express Connector
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value Unit
0.25 to 14 max inch
0.225 min to 12.6 max inch
PCI-Express Device Routing
L1
L2
L4
RS
RS
L4’
L1’
L2’
RT
RT
PCI-Express
Load or
Connector
ICS557-06
Output
L3’ L3
Clock
Typical PCI-Express (HCSL) Waveform
700 mV
0
500 ps
500 ps
tOR
tOF
0.52 V
0.175 V
0.52 V
0.175 V
IDT™ / ICS™ 1 TO 4 HCSL CLOCK BUFFER
5
ICS557-06
REV F 090407
ICS557-06
1 TO 4 HCSL CLOCK BUFFER
PCIE FAN OUT BUFFER
LVDS Compatible Layout Guidelines
LVDS Recommendations for Differential Routing
Dimension or Value Unit
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
RP
RQ
0.5 max
0.2 max
100
100
150
inch
inch
ohm
ohm
ohm
RT
L3 length, Route as coupled 50 ohm differential trace.
L3 length, Route as coupled 50 ohm differential trace.
LVDS Device Routing
L1
L3
L3’
RQ
RP
L1’
RT
RT
ICS557-06
Clock
Output
LVDS
Device
Load
L2’ L2
Typical LVDS Waveform
1325 mV
1000 mV
500 ps
500 ps
tOR
tOF
1250 mV
1150 mV
1250 mV
1150 mV
IDT™ / ICS™ 1 TO 4 HCSL CLOCK BUFFER
6
ICS557-06
REV F 090407
ICS557-06
1 TO 4 HCSL CLOCK BUFFER
PCIE FAN OUT BUFFER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-06. These ratings are stress
ratings only. Functional operation of the device at these or any other conditions above those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Item
Rating
Supply Voltage, VDD, VDDA
5.5 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
0 to +70° C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
-40 to +85° C
-65 to +150° C
125°C
Junction Temperature
Soldering Temperature
260°C
ESD Protection (Input)
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
3.135
2.0
Typ.
Max.
Units
Supply Voltage
V
3.465
1
Input High Voltage
V
OE, SEL, PD
VDD +0.3
V
IH
1
Input Low Voltage
Input Leakage Current
V
I
OE, SEL, PD
VSS-0.3
-5
0.8
5
V
IL
2
0 < Vin < VDD
50Ω, 2pF
µA
mA
mA
µA
pF
pF
nH
kΩ
kΩ
IL
Operating Supply Current
I
55
20
400
7
DD
I
OE =Low
DDOE
I
No load, PD =Low
Input pin capacitance
Output pin capacitance
DDPD
Input Capacitance
Output Capacitance
Pin Inductance
C
IN
C
6
OUT
L
5
PIN
Output Resistance
Pull-up Resistor
R
CLK outputs
SEL, OE, PD
3.0
OUT
PUP
R
110
1. Single edge is monotonic when transitioning through region.
2. Inputs with pull-ups/-downs are not included.
IDT™ / ICS™ 1 TO 4 HCSL CLOCK BUFFER
7
ICS557-06
REV F 090407
ICS557-06
1 TO 4 HCSL CLOCK BUFFER
PCIE FAN OUT BUFFER
AC Electrical Characteristics - CLKOUTA/CLKOUTB
Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Output Frequency
Symbol
Conditions
Min.
Typ.
Max.
200
200
100
850
Units
MHz
HCSL termination
MHz
LVDS termination
HCSL
1,2
Input High Voltage
V
660
-150
250
700
0
mV
mV
mV
IH
1,2
Input Low Voltage
V
HCSL
IL
Differential Input
Voltages
(V )
LVDS
350
450
ID
Input Offset Voltage
Output High Voltage
(V )
LVDS
1.125
660
1.25
700
0
1.375
850
27
V
IS
1,2
1,2
V
HCSL
HCSL
Absolute
mV
mV
mV
OH
Output Low Voltage
Crossing Point
V
-150
250
OL
350
550
1,2
Voltage
Crossing Point
Voltage
Variation over all edges
140
mV
1,2,4
1,3
Jitter, Cycle-to-Cycle
60
ps
ps
ps
ps
1,2
Rise Time
t
From 0.175 V to 0.525 V
From 0.525 V to 0.175 V
175
175
332
344
700
700
125
OR
1,2
Fall Time
t
OF
Rise/Fall Time
1,2
Variation
Skew between Outputs
Measured at crossing point
50
55
ps
%
1,3
Duty Cycle
45
5
Output Enable Time
All outputs
All outputs
10
10
3
us
us
ns
5
Output Disable Time
Input to Output Delay
Input differential clock to output
differential clock delay measured at
mid point of input levels to mid pint of
output levels
1
Test setup is R =50 ohms with 2 pF, Rr = 475Ω (1%).
L
2
3
4
5
Measurement taken from a single-ended waveform.
Measurement taken from a differential waveform.
Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.
CLKOUT pins are tri-stated when OE is Low asserted. CLKOUT is driven differential when OE is High unless its
PD = low.
IDT™ / ICS™ 1 TO 4 HCSL CLOCK BUFFER
8
ICS557-06
REV F 090407
ICS557-06
1 TO 4 HCSL CLOCK BUFFER
PCIE FAN OUT BUFFER
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
Still air
93
78
65
20
° C/W
° C/W
° C/W
° C/W
JA
θ
1 m/s air flow
3 m/s air flow
JA
θ
JA
Thermal Resistance Junction to Case
θ
JC
Marking Diagrams
(ICS557GI-06LF)
(ICS557G-06)
20
11
20
11
######
YYWW
557G-06
######
YYWW
557GI06LF
ICS
ICS
1
10
1
10
(ICS557G-06LF)
20
11
######
YYWW
ICS
557G06LF
1
10
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. “LF” denotes Pb free package.
4. Bottom marking: (origin). Origin = country of origin if not USA.
IDT™ / ICS™ 1 TO 4 HCSL CLOCK BUFFER
9
ICS557-06
REV F 090407
ICS557-06
1 TO 4 HCSL CLOCK BUFFER
PCIE FAN OUT BUFFER
Package Outline and Package Dimensions (20-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches*
20
Symbol
Min
Max
1.20
0.15
1.05
0.30
0.20
6.60
Min
Max
0.047
0.006
0.041
0.012
A
A1
A2
b
0.05
0.80
0.19
0.09
6.40
0.002
0.032
0.007
E1
E
INDEX
AREA
c
0.0035 0.008
0.252 0.260
0.252 BASIC
0.169 0.177
0.0256 Basic
D
E
6.40 BASIC
1
2
E1
e
4.30
4.50
0.65 Basic
D
L
0.45
0°
0.75
8°
0.018
0°
0.030
8°
a
aaa
--
0.10
--
0.004
A
*For reference only. Controlling dimensions in mm.
A2
A1
c
- C -
e
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
ICS557G-06
ICS557G-06T
See Page 9
20-pin TSSOP
20-pin TSSOP
20-pin TSSOP
20-pin TSSOP
20-pin TSSOP
20-pin TSSOP
Tape and Reel
Tubes
ICS557G-06LF
ICS557G-06LFT
ICS557GI-06LF
ICS557GI-06LFT
Tape and Reel
Tubes
Tape and Reel
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technologu (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 1 TO 4 HCSL CLOCK BUFFER
10
ICS557-06
REV F 090407
ICS557-06
1 TO 4 HCSL CLOCK BUFFER
PCIE FAN OUT BUFFER
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www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
408-284-4522
www.idt/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
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