ICS557G-07LF [IDT]
Low Skew Clock Driver, 557 Series, 1 True Output(s), 0 Inverted Output(s), PDSO16, 0.173 INCH, ROHS COMPLIANT, TSSOP-16;
| 型号： | ICS557G-07LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 557 Series, 1 True Output(s), 0 Inverted Output(s), PDSO16, 0.173 INCH, ROHS COMPLIANT, TSSOP-16 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P R E L I M I N A R Y I N F O R M A T I O N
ICS557-07
2:1 MULTIPLEXER CHIP FOR PCI-E
Description
Features
The ICS557-07 is a 2:1 HCSL multiplexer chip that
allows the user to select one of the two input pairs of
HCSL (Host Clock Signal Level) or LVDS inputs and
fans out to one pair of differential HCSL outputs. This
chip is suited especially for PCI-Express applications,
where there is a need to select the PCI-Express clock
locally from the PCI-E card or from the motherboard.
• Packaged in 16-pin TSSOP
• Available in Pb (lead) free package
• Operating voltage of 3.3 V
• Low power consumption
• Input differential clock of up to 200 MHz (can accept
LVDS, HCSL)
• Output, one pair (HCSL, 0.7 V Current mode
differential pair)
• Jitter 60 ps (peak-to-peak)
• Operating frequency of 80 MHz to 200 MHz
Block Diagram
OE
VDD
3
IN1
CLK
CLK
IN1
MUX
2 to 1
IN2
IN2
3
Rr (IREF)
PD
SEL
GND
MDS 557-07 B
1
Revision 041405
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS557-07
2:1 Multiplexer Chip for PCI-E
Pin Assignment
Select Table
Input Pair
selected
1
SEL
16
15
14
13
12
11
10
9
VDD
IN1
SEL
2
3
4
5
6
7
8
GND
GND
VDD
VDD
CLK
0
1
IN2/ IN2
IN1/ IN1
IN1
PD
IN2
IN2
OE
CLK
GND
IREF
16-pin (173 mil) TSSOP
Pin Descriptions
Pin
Pin
Pin
Type
Pin Description
Name
1
2
3
4
5
6
7
VDD
IN1
IN1
PD
Power Connect to +3.3 V. Supply voltage for Input clocks.
Input
Input
Input
Input
Input
Input
HCSL/LVDS true input signal 1.
HCSL/LVDS complimentary input signal 1.
Powers down the chip and tri-states outputs when low. Internal pull-up resistor.
HCSL/LVDS true input signal 2.
IN2
IN2
OE
HCSL/LVDS complimentary input signal 2.
Provides fast output on, tri-states output (High = enable outputs; Low = disable).
Internal pull-up resistor.
8
GND
Power Connect to ground.
9
Rr(IREF)
CLK
Output Precision resistor attached to this pin is connected to the internal current reference.
Output HCSL differential complimentary clock .
Output HCSL True clock.
10
11
12
13
14
15
16
CLK
VDD
VDD
GND
GND
SEL
Power Connect to +3.3 V. Supply Voltage for output clocks.
Power Connect to +3.3 V. Supply Voltage for output clocks.
Power Connect to ground.
Power Connect to ground.
Input
SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor.
MDS 557-07 B
2
Revision 041405
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS557-07
2:1 Multiplexer Chip for PCI-E
Applications Information
External Components
A minimum number of external components are
required for proper operation.
Output Structures
6*IREF
IREF
=2.3 mA
Decoupling Capacitors
Decoupling capacitors of 0.01 µF should be connected
between VDD and the ground plane (pin 4) as close to
the VDD pin as possible. Do not share ground vias
between components. Route power from power source
through the capacitor pad and then into ICS pin.
Crystal
See Output Termination
Sections - Pages 3 ~ 5
A 25 MHz fundamental mode parallel resonant crystal
Ω
RR 475
with C = 16 pF should be used. This crystal must have
L
less than 300 ppm of error across temperature in order
for the ICS557-07 to meet PCI Express specifications.
General PCB Layout Recommendations
Crystal Capacitors
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Crystal capacitors are connected from pins X1 to
ground and X2 to ground to optimize the accuracy of
the output frequency.
1. Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible.
C = Crystal’s load capacitance in pF
L
Crystal Capacitors (pF) = (C - 8) * 2
L
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
2. No vias should be used between decoupling
capacitor and VDD pin.
Current Source (Iref) Reference Resistor - RR
3. The PCB trace to VDD pin should be kept as short
as possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from
the device is less critical.
If board target trace impedance (Z) is 50Ω, then R =
R
475Ω (1%), providing IREF of 2.32 mA. The output
current (I ) is equal to 6*IREF.
OH
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (any ferrite beads and bulk decoupling
capacitors can be mounted on the back). Other signal
traces should be routed away from the ICS557-07.This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-07 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown
in detail in the PCI-Express Layout Guidelines
section.
The ICS557-07can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section
MDS 557-07 B
3
Revision 041405
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS557-07
2:1 Multiplexer Chip for PCI-E
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-07. These ratings are
stress ratings only. Functional operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed
only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
5.5 V
-0.5 V to VDD+0.5 V
0 to +70°C
Ambient Operating Temperature
Storage Temperature
-65 to +150°C
125°C
Junction Temperature
Soldering Temperature
ESD Protection (Input)
260°C
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70°C
Parameter
Supply Voltage
Input High Voltage
Symbol
Conditions
Min.
3.135
2.0
Typ.
Max.
Units
V
3.465
1
V
OE, SEL, PD
VDD +0.3
V
IH
1
Input Low Voltage
V
OE, SEL, PD
VDD-0.3
-5
0.8
5
V
IL
2
Input Leakage Current
I
0 < Vin < VDD
50Ω, 2 pF
µA
mA
mA
µA
pF
pF
nH
kΩ
kΩ
IL
Operating Supply Current
I
40
20
400
7
DD
I
OE =Low
DDOE
I
No load, PD =Low
Input pin capacitance
Output pin capacitance
DDPD
Input Capacitance
Output Capacitance
Pin Inductance
C
IN
C
6
OUT
L
5
PIN
Output Resistance
Pull-up Resistor
R
CLK, each output
3.0
OUT
R
110
PU
1 Single edge is monotonic when transitioning through region.
2 Inputs with pull-ups/-downs are not included.
MDS 557-07 B
4
Revision 041405
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS557-07
2:1 Multiplexer Chip for PCI-E
AC Electrical Characteristics - CLKOUTA/CLKOUTB
Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature 0 to +70°C
Parameter
Input Frequency
Output Frequency
Input High Voltage
Symbol
Conditions
Min.
80
Typ.
Max.
200
200
850
Units
MHz
MHz
mV
80
1,2
1,2
V
HCSL
HCSL
LVDS
660
-150
250
700
0
IH
Input Low Voltage
V
mV
IL
Differential Input
Voltages
(V )
350
450
mV
ID
Input Offset Voltage
Output High Voltage
(V )
LVDS
1.125
660
1.25
700
0
1.375
850
V
IS
1,2
1,2
V
HCSL
mV
mV
mV
OH
Output Low Voltage
V
HCSL
Absolute
-150
250
OL
Crossing Point
350
550
140
1,2
Voltage
Crossing Point
Variation over all edges
mV
1,2,4
Voltage
1,3
Jitter, Cycle-to-Cycle
60
ps
ps
ps
ps
1,2
Rise Time
t
From 0.175 V to 0.525 V
From 0.525 V to 0.175 V
175
175
332
344
700
700
125
OR
1,2
Fall Time
t
OF
Rise/Fall Time
1,2
Variation
1,3
Duty Cycle
45
55
%
µs
µs
ms
ns
5
Output Enable Time
Output Disable Time
Stabilization Time
All outputs
10
10
3.0
4
5
All outputs
t
From power-up VDD=3.3 V
Measured at crossing points
STABLE
Input to Output Delay
1
2
3
4
5
Test setup is R =50 ohms with 2 pF, Rr = 475Ω (1%).
L
Measurement taken from a single-ended waveform.
Measurement taken from a differential waveform.
Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.
CLK and CLK pins are tri-stated when OE is Low. CLK and CLK are driven differential when OE is High unless its
PD = low.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
Still air
93
78
65
20
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
θ
MDS 557-07 B
5
Revision 041405
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS557-07
2:1 Multiplexer Chip for PCI-E
HCSL Output Loads
6*IREF
IREF
=2.3 mA
RL
50.2
RL
50.2
Ω
RL 475
Ω
Ω
700 mV
0
500 ps
500 ps
tOR
tOF
0.52 V
0.175 V
0.52 V
0.175 V
MDS 557-07 B
6
Revision 041405
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS557-07
2:1 Multiplexer Chip for PCI-E
Marking Diagram
Marking Diagram (Pb free)
16
9
16
9
557G07LF
######
557G-07
######
YYWW
YYWW$$
1
8
1
8
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. “LF” denotes Pb free package.
4. Bottom marking: (origin). Origin = country of origin if not USA.
MDS 557-07 B
7
Revision 041405
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS557-07
2:1 Multiplexer Chip for PCI-E
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Min Max
Inches
Max
Symbol
Min
--
Index
Area
A
a
--
1.20
0.15
0.30
0.20
5.10
4.50
0.047
0.006
0.012
E
0.05
0.19
0.09
4.90
4.30
0.002
0.007
H
b
c
0.0035 0.008
D
E
e
0.193
0.169
0.201
0.177
0.65 Basic
6.40 Basic
0.45 0.75
0.0256 Basic
0.252 Basic
Pin 1
H
L
D
0.018
0.030
A
a
c
e
b
L
Ordering Information
Part / Order Number
ICS557G-07
Marking
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
ICS557G-07T
Tape and Reel
Tubes
See Page 4
ICS557G-07LF
ICS557G-07LFT
Tape and Reel
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 557-07 B
8
Revision 041405
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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