8537AY-01T [IDT]
Clock Driver, 5V Series, 2 True Output(s), 2 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48;
| 型号： | 8537AY-01T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, 5V Series, 2 True Output(s), 2 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48 驱动 逻辑集成电路 |
| 文件： | 总14页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8537-01
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8537-01 is a Hex low skew, high performance 1-to-2 • Twelve LVPECL outputs
Differential-to-3.3V/2.5 LVPECL Clock Buffer. The ICS8537-
• Selectable differential CLKx, nCLKx inputs
01 has six selectable clock inputs. The CLKx, nCLKx pairs
can accept most differential input levels and translate them to
3.3V or 2.5V LVPECL output levels.Guaranteed output and
part-to-part skew specifications make the ICS8537-01 ideal
for those applications demanding well defined performance
and repeatability.
• CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Maximum output frequency: 700MHz
• Translates any differential input signal (LVHSTL, SSTL,
DCM) to LVPECL levels without external bias networks
• Translates any single-ended input signal to LVPECL
with resistor bias on nCLKx input
• Output skew: 130ps (maximum)
• Bank skew: 20ps (maximum)
• Part-to-part skew: 350ps (maximum)
• Propagation delay: 1.5ns (maximum)
• 3.3V or 2.5V operating supply
• 0°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free
(RoHS 6) packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0A
nQ0A
CLK0
nCLK0
Q0B
nQ0B
Q1A
48 47 46 45 44 43 42 41 40 39 38 37
nQ1A
Q1B
nQ4A
Q4A
VCCO
Q4B
nQ4B
VCC
1
CLK1
nCLK1
36
35
34
33
32
31
30
29
28
27
26
25
nQ1B
Q1B
VCCO
Q1A
nQ1A
VCC
2
nQ1B
3
4
Q2A
5
nQ2A
Q2B
CLK2
nCLK2
6
ICS8537-01
VEE
7
VEE
nQ2B
nQ5B
Q5B
VCCO
Q5A
nQ5A
8
nQ0B
Q0B
VCCO
Q0A
nQ0A
9
Q3A
nQ3A
Q3B
10
11
12
CLK3
nCLK3
nQ3B
13 14 15 16 17 18 19 20 21 22 23 24
Q4A
nQ4A
Q4B
CLK4
nCLK4
nQ4B
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Q5A
nQ5A
CLK5
nCLK5
Q5B
nQ5B
TopView
8537AY-01
www.idt.com
REV.B NOVEMBER 22, 2010
1
ICS8537-01
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
nQ4A, Q4A
Output
Power
Differential output pair. LVPECL interface levels.
3, 10, 27, 34,
39, 46
VCCO
Output supply pins.
4, 5
6, 31, 42
7, 30, 43
8, 9
Q4B, nQ4B
VCC
Output
Power
Power
Output
Output
Input
Differential output pair. LVPECL interface levels.
Core supply pins.
VEE
Negative supply pins.
nQ5B, Q5B
Q5A, nQ5A
CLK5
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
11, 12
13
Pullup
Pulldown Non-inverting differential clock input.
Pullup Non-inverting differential clock input.
Pulldown Inverting differential clock input.
Pullup Non-inverting differential clock input.
Pulldown Inverting differential clock input.
Pullup Non-inverting differential clock input.
Pulldown Inverting differential clock input.
Pullup Non-inverting differential clock input.
Pulldown Inverting differential clock input.
Pullup Non-inverting differential clock input.
Pulldown Inverting differential clock input.
Differential output pair. LVPECL interface levels.
Inverting differential clock input.
14
nCLK5
Input
15
CLK4
Input
16
nCLK4
Input
17
CLK3
Input
18
nCLK3
Input
19
CLK2
Input
20
nCLK2
Input
21
CLK1
Input
22
nCLK1
Input
23
CLK0
Input
24
nCLK0
Input
25, 26
28, 29
32, 33
35, 36
37, 38
40, 41
44, 45
47, 48
nQ0A, Q0A
Q0B, nQ0B
nQ1A, Q1A
Q1B, nQ1B
nQ2A, Q2A
Q2B, nQ2B
nQ3A, Q3A
Q3B, nQ3B
Output
Output
Output
Output
Output
Output
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8537AY-01
www.idt.com
REV.B NOVEMBER 22, 2010
2
ICS8537-01
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
kΩ
kΩ
RPULLUP
RPULLDOWN
51
51
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
Q0A:Q5A,
Q0B:Q5B
nQ0A:nQ5A,
nQ5B:nQ5B
CLKx
nCLKx
0
1
LOW
HIGH
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single ended levels".
8537AY-01
www.idt.com
REV.B NOVEMBER 22, 2010
3
ICS8537-01
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
CC
Inputs, V
-0.5V to VCC + 0.5 V
-0.5V to VCCO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.465V, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
3.3
Maximum Units
VCC
VCCO
IEE
Core Supply Voltage
3.465
3.465
130
V
V
Output Supply Voltage
Power Supply Current
2.375
3.3
mA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.465V, TA = 0°C TO 85°C
Symbol Parameter
Input High Current
Test Conditions
VIN = VCC = 3.465V
VIN = VCC = 3.465V
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
Minimum
Typical
Maximum Units
CLKx
150
5
µA
µA
µA
µA
V
IIH
nCLKx
CLKx
-5
-150
IIL
Input Low Current
nCLKx
VPP
Peak-to-Peak Voltage
0.15
1.3
VCMR
Common Mode Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: For single ended appliations, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.465V, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VCCO - 1.4
VCCO - 2.0
0.6
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
8537AY-01
www.idt.com
REV.B NOVEMBER 22, 2010
4
ICS8537-01
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.465V, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
700
1.5
130
20
MHz
ns
ps
ps
ps
ps
%
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
Bank Skew; NOTE 3, 5
IJ 700MHz
1.1
1.3
tsk(o)
tsk(b)
tsk(pp)
tR / tF
Part-to-Part Skew; NOTE 4, 5
Output Rise/Fall Time
350
600
53
20% to 80%
IJ 300MHz
ƒ> 300MHz, ƒ≤ 500MHz
200
47
odc
Output Duty Cycle
45
55
%
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured from at the output differential cross points.
NOTE 3: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 4: Defined as between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8537AY-01
www.idt.com
REV.B NOVEMBER 22, 2010
5
ICS8537-01
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCO = 2V
VCC
SCOPE
Qx
nCLKx
CLKx
LVPECL
VPP
VCMR
Cross Points
nQx
VEE
V
EE = -0.375V to -1.465V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
nQx
Qx
PART 1
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nQxA
QxA
80%
80%
VSWING
20%
20%
nQxB
Clock Outputs
t
t
F
R
QxB
tsk(b)
BANK SKEW
OUTPUT RISE/FALL TIME
nQx
nCLKx
CLKx
Qx
Pulse Width
tPERIOD
nQx
Qx
tPW
tPD
odc =
tPERIOD
odc & tPERIOD
PROPAGATION DELAY
8537AY-01
www.idt.com
REV.B NOVEMBER 22, 2010
6
ICS8537-01
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- 50Ω transmission lines. Matched impedance techniques should
tion for LVPECL outputs.The two different layouts mentioned be used to maximize operating frequency and minimize signal
are recommended only as guidelines.
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
5
2
5
Zo
Zo
2
FIN
FOUT
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
➤
VCC - 2V
RTT
1
3
2
3
2
Zo
RTT =
Zo
Zo
(VOH + VOL / VCC –2) –2
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
8537AY-01
www.idt.com
REV.B NOVEMBER 22, 2010
7
ICS8537-01
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8537-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8537-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 130mA = 450.5mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 12 * 30mW = 360mW
Total Power_MAX (3.465V, with all outputs switching) = 450.5mW + 360mW = 810.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = junction-to-ambient thermal resistance
Pd_total =Total device power dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.811W * 42.1°C/W = 119.1°C. This is well below the limit of 125°C
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 48-PIN LQFP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
8537AY-01
www.idt.com
REV.B NOVEMBER 22, 2010
8
ICS8537-01
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 3.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 3. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V ) =
OH_MAX
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
8537AY-01
www.idt.com
REV.B NOVEMBER 22, 2010
9
ICS8537-01
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8537-01 is: 1201
8537AY-01
www.idt.com
REV.B NOVEMBER 22, 2010
10
ICS8537-01
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
8537AY-01
www.idt.com
REV.B NOVEMBER 22, 2010
11
ICS8537-01
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
8537AY-01
8537AY-01T
8537AY-01LF
8537AY-01LFT
ICS8537AY-01
ICS8537AY-01
ICS8537AY01L
ICS8537AY01L
48 Lead LQFP
tray
0°C to 85°C
0°C to 85°C
0°C to 85°C
0°C to 85°C
48 Lead LQFP
1000 tape & reel
tray
Lead-Free, 48 Lead LQFP
Lead-Free, 48 Lead LQFP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc.(IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications.Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
8537AY-01
www.idt.com
REV.B NOVEMBER 22, 2010
12
ICS8537-01
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Features Section - added lead-free bullet.
Date
1
3
4
T2
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
T4C
LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to
V
CCO - 0.9V.
B
4/12/07
8 - 9
12
Power Considerations - corrected power dissipation to reflect VOH max in Table
3D.
T9
T9
Ordering Information Table - added lead-free Part/Order Number, marking and
note.
Updated datasheet's header/footer with IDT from ICS.
Ordering Information Table - removed ICS prefix from Part/Order Number
column. Added lead-free marking.
12
14
B
11/22/10
Added Contact Page.
8537AY-01
www.idt.com
REV.B NOVEMBER 22, 2010
13
ICS8537-01
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
netcom@idt.com
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
Printed in USA
8537AY-01
www.idt.com
REV.B NOVEMBER 22, 2010
14
相关型号：
8537EF
Inside DC Block, 0.007MHz Min, 45000MHz Max, 1.25dB Insertion Loss-Max, ROHS COMPLIANT PACKAGE
APITECH
8537EM
Inside DC Block, 0.007MHz Min, 45000MHz Max, 1.25dB Insertion Loss-Max, ROHS COMPLIANT PACKAGE
APITECH
8537KF
Inside DC Block, 0.007MHz Min, 45000MHz Max, 1.25dB Insertion Loss-Max, ROHS COMPLIANT PACKAGE
APITECH
8537KM
Inside DC Block, 0.007MHz Min, 45000MHz Max, 1.25dB Insertion Loss-Max, ROHS COMPLIANT PACKAGE
APITECH
8537VM
Inside DC Block, 0.025MHz Min, 50000MHz Max, 1.25dB Insertion Loss-Max, ROHS COMPLIANT PACKAGE
APITECH
8538BGI-26LF
Clock Generator, 266MHz, PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
IDT
8538BGI-26LFT
Clock Generator, 266MHz, PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
IDT
©2020 ICPDF网 联系我们和版权申明