8538BGI-26LF [IDT]
Clock Generator, 266MHz, PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24;
| 型号： | 8538BGI-26LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 266MHz, PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总21页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-
TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER
ICS8538I-26
GENERAL DESCRIPTION
FEATURES
The ICS8538I-26 is a low skew, high performance
• Two differential 3.3V or 2.5V LVPECL outputs and
ICS
HiPerClockS™
1-to-8 Crystal Oscillator/LVCMOS-to-3.3V, 2.5V
LVPECL/LVCMOS Fanout Buffer and a member of
the HiPerClockS™family of High Performance Clock
Solutions from IDT. The ICS8538I-26 has select-
six single-ended 3.3V or 2.5V LVCMOS/LVTTL outputs
• Selectable LVCMOS/LVTTL CLK or crystal inputs
• CLK can accept the following input levels: LVCMOS, LVTTL
• Maximum output frequency: 266MHz
able single ended clock or crystal inputs.The single ended clock
input accepts LVCMOS or LVTTL input levels and translate
them to 3.3V LVPECL levels. The output enable is internally
synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin.
• Output skew: 60ps (maximum), LVPECL outputs
• Part-to-part skew: 800ps (maximum)
• Propagation delay: 2.05ns (maximum), LVPECL outputs
• Additive phase jitter, RMS: 0.19ps (typical)
Guaranteed output and part-to-part skew characteristics make
the ICS8538I-26 ideal for those applications demanding well
defined performance and repeatability.
• Operating supply modes:
LVPECL outputs:
Core/Output
3.3V/3.3V
2.5V/2.5V
LVCMOS outputs:
Core/Output
3.3V/3.3V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_EN
XTAL_IN
XTAL_OUT
VCC
Q7
1
2
3
4
24
23
22
21
20
19
18
17
16
15
14
13
Pullup
CLK_EN
D
VCCO_LVCMOS
Q6
LE
VEE
Q5
VCCO_LVCMOS
Q4
CLK
5
6
7
8
Pulldown
CLK
LVPECL
Q0
0
1
CLK_SEL
VEE
nQ0
Q0
VEE
25MHz
XTAL_IN
9
nQ0
VCCO_LVPECL
Q1
Q3
Q1
10
11
12
VCCO_LVCMOS
Q2
OSC
nQ1
XTAL_OUT
nQ1
VEE
Pullup
ICS8538I-26
24-Lead TSSOP
CLK_SEL
Q2
4.40mm x 7.8mm x 0.925mm package body
G Package
Top View
LVCMOS
Q7
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
1
ICS8538BGI-26 REV. B APRIL 14, 2009
ICS8538I-26
LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Description
Synchronizing clock enable. When HIGH, clock outputs follow clock
input. When LOW, Q outputs are forced low, nQ outputs are forced high.
See Table 3B. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
1
CLK_EN
Input
Input
2,
3
XTAL_IN,
XTAL_OUT
4
5
VCC
Power
Input
Positive supply pin.
CLK
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects XTAL inputs.
Pullup
6
CLK_SEL
VEE
Input
When LOW, selects CLK input. LVCMOS / LVTTL interface levels.
7, 13,
17, 21
Power
Negative supply pins.
8, 9
Q0, nQ0
VCCO_LVPECL
Q1, nQ1
Output
Power
Output
Differential clock outputs. LVPECL interface levels.
Output power supply mode for LVPECL clock outputs.
Differential clock outputs. LVPECL interface levels.
10
11, 12
14, 16,
18, 20,
22, 24
Q2, Q3,
Q4, Q5,
Q6, Q7
Output
Single ended clock outputs. LVCMOS / LVTTL interface levels.
15, 19, 23
VCCO_LVCMOS
Power
Output power supply mode for LVCMOS / LVTTL clock outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
Power Dissipation
Capacitance
VCC, VCCO_LVCMOS = 3.465V
VCC, VCCO_LVCMOS = 2.625V
10
CPD
Q2:Q7
Q2:Q7
(per LVCMOS output)
Input Pullup Resistor
8
pF
kΩ
kΩ
Ω
RPULLUP
51
51
15
20
RPULLDOWN Input Pulldown Resistor
VCCO_LVCMOS = 3.465V
ROUT Output Impedance
VCCO_LVCMOS = 2.625V
Ω
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
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ICS8538BGI-26 REV. B APRIL 14, 2009
ICS8538I-26
LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
CLK_SEL
Outputs
nQ0, nQ1
CLK_EN
Selected Source
CLK
Q0, Q1
Disabled; LOW
Disabled; LOW
Enabled
Q2:Q7
Disabled; LOW
Disabled; LOW
Enabled
0
0
1
1
0
1
0
1
Disabled; HIGH
Disabled; HIGH
Enabled
XTAL_IN, XTAL_OUT
CLK
XTAL_IN, XTAL_OUT
Enabled
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or
crystal oscillator edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK input as described in Table 3B.
Enabled
Disabled
CLK
CLK_EN
nQ0, nQ1
Q0:Q7
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
nQ0, nQ1
CLK
Q0, Q1
LOW
Q2:Q7
LOW
0
1
HIGH
LOW
HIGH
HIGH
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
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ICS8538BGI-26 REV. B APRIL 14, 2009
ICS8538I-26
LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
CC
Inputs, V (LVCMOS)
-0.5V to VCC + 0.5 V
I
Outputs, VO (LVCMOS)
-0.5V to VCCO_LVCMOS + 0.5V
-0.5V to VCC + 0.5V
Inputs, V (LVPECL)
I
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA 87.8°C/W (0 mps)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_LVPECL = VCCO_LVCMOS = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VCC
Power Supply Voltage
3.135
3.3
3.465
V
VCCO_LVPECL,
VCCO_LVCMOS
Power Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
Power Supply Current
60
12
10
mA
mA
mA
ICCO_LVPECL
ICCO_LVCMOS Power Supply Current
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_LVPECL = VCCO_LVCMOS = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VCC
Power Supply Voltage
2.375
2.5
2.625
V
VCCO_LVPECL,
VCCO_LVCMOS
Power Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
Power Supply Current
60
12
10
mA
mA
mA
ICCO_LVPECL
ICCO_LVCMOS Power Supply Current
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
4
ICS8538BGI-26 REV. B APRIL 14, 2009
ICS8538I-26
LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
CC = 3.3V
Minimum Typical Maximum Units
V
2
VCC + 0.3
VCC + 0.3
0.8
V
V
V
V
VIH
Input High Voltage
VCC = 2.5V
VCC = 3.3V
1.7
-0.3
-0.3
VIL
Input Low Voltage
V
CC = 2.5V
0.7
Input
Hysteresis
CLK_EN,
CLK_SEL
VHYS
100
mV
µA
µA
µA
µA
CLK
VCC = VIN = 3.465V or 2.625V
VCC = VIN = 3.465V or 2.625V
VCC = 3.465V or 2.625V, VIN = 0V
VCC = 3.465V or 2.625V, VIN = 0V
150
5
Input
High Current
IIH
CLK_EN,
CLK_SEL
CLK
-5
Input
Low Current
IIL
CLK_EN,
CLK_SEL
-150
V
V
CCO_LVCMOS = 3.465V
CCO_LVCMOS = 2.625V
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VCCO_LVCMOS = 3.465V or 2.625V
0.5
NOTE 1: Outputs terminated with 50Ω to VCCO_LVCMOS/2. See Parameter Measurement Information Section. "LVCMOS Output
Load Test circuit" diagrams.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO_LVPECL = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VCCO_LVPECL - 1.4
VCCO_LVPECL - 2.0
0.6
Typical
Maximum
VCCO_LVPECL - 0.9
VCCO_LVPECL - 1.7
1.0
Units
VOH
Output High Voltage; NOTE 1
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL - 2V.
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = VCCO_LVPECL = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VCCO_LVPECL - 1.4
VCCO_LVPECL - 2.0
0.4
Typical
Maximum
VCCO_LVPECL - 0.9
VCCO_LVPECL - 1.5
1.0
Units
VOH
Output High Voltage; NOTE 1
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
12
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
5
ICS8538BGI-26 REV. B APRIL 14, 2009
ICS8538I-26
LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER
TABLE 6A. LVPECL AC CHARACTERISTICS, VCC = VCCO_LVPECL = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
fOUT Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
266
MHz
ns
Propagation Delay; NOTE 1
1.15
2.05
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
RMS Phase Jitter, Random;
NOTE 2
155.52MHz,
(Integration Range: 12kHz - 20MHz)
tjit
0.19
0.25
ps
25MHz Crystal,
(Integration Range: 1kHz - 1MHz)
tjit(Ø)
tsk(o)
tsk(pp)
ps
ps
ps
Output Skew; NOTE 3, 5
60
Part-to-Part Skew;
NOTE 4, 5
800
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
175
45
925
55
ps
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE: All parameters measured at IJ 266MHz unless noted otherwise.
NOTE 1: Measured from the VCC/2 of the input to the differential output crossing point.
NOTE 2: See phase jitter plot.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. LVPECL AC CHARACTERISTICS, VCC = VCCO_LVPECL = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
fOUT Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
266
MHz
ns
Propagation Delay; NOTE 1
1.15
2.05
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
RMS Phase Jitter, Random;
NOTE 2
155.52MHz,
(Integration Range: 12kHz - 20MHz)
tjit
0.37
0.27
ps
25MHz Crystal,
(Integration Range: 1kHz - 1MHz)
tjit(Ø)
tsk(o)
tsk(pp)
ps
ps
ps
Output Skew; NOTE 3, 5
60
Part-to-Part Skew;
NOTE 4, 5
800
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
175
45
815
55
ps
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE: All parameters measured at IJ 266MHz unless noted otherwise.
NOTE 1: Measured from the VCC/2 of the input to the differential output crossing point.
NOTE 2: See phase jitter plot.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
6
ICS8538BGI-26 REV. B APRIL 14, 2009
ICS8538I-26
LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER
TABLE 6C. LVCMOS AC CHARACTERISTICS, VCC = VCCO_LVCMOS = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
fOUT Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
266
MHz
ns
Propagation Delay; NOTE 1
2.5
3.75
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
RMS Phase Jitter, Random;
NOTE 2
155.52MHz,
(Integration Range: 12kHz - 20MHz)
tjit
0.24
0.25
ps
25MHz Crystal,
(Integration Range: 1kHz - 1MHz)
tjit(Ø)
tsk(o)
tsk(pp)
ps
ps
ps
Output Skew; NOTE 3, 5
112
800
Part-to-Part Skew;
NOTE 4, 5
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
0.250
45
1.125
55
ns
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE: All parameters measured at IJ 266MHz unless noted otherwise.
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: See phase jitter plot.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VCCO_LVCMOS/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VCCO_LVCMOS/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6D. LVCMOS AC CHARACTERISTICS, VCC = VCCO_LVCMOS = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
fOUT Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
266
4.0
MHz
ns
Propagation Delay; NOTE 1
2.55
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
RMS Phase Jitter, Random;
NOTE 2
155.52MHz,
(Integration Range: 12kHz - 20MHz)
tjit
0.22
0.27
ps
25MHz Crystal,
(Integration Range: 1kHz - 1MHz)
tjit(Ø)
ps
tsk(o)
tsk(pp)
tR / tF
Output Skew; NOTE 3, 5
Part-to-Part Skew; NOTE 4, 5
Output Rise/Fall Time
Output Duty Cycle
112
800
1.45
60
ps
ps
ns
ꢀ
20ꢀ to 80ꢀ
0.225
40
odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE: All parameters measured at IJ 266MHz unless noted otherwise.
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: See phase jitter plot.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VCCO_LVCMOS/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VCCO_LVCMOS/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
7
ICS8538BGI-26 REV. B APRIL 14, 2009
ICS8538I-26
LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER
TYPICAL PHASE NOISE AT 100MHZ @3.3V
100MHz
RMS Phase Jitter (Random)
1kHz – 1MHz = 0.25ps (typical)
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
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ICS8538BGI-26 REV. B APRIL 14, 2009
ICS8538I-26
LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
2V
SCOPE
SCOPE
VCC,
VCC,
Qx
Qx
VCCO_LVPECL
VCCO_LVPECL
LVPECL
LVPECL
nQx
nQx
VEE
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/ 2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
1.25V 5ꢀ
1.65V 5ꢀ
SCOPE
SCOPE
VCC,
VCCO_LVCMOS
VCC,
VCCO_LVCMOS
Qx
Qx
LVCMOS
LVCMOS
VEE
VEE
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V CORE/3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/ 2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
VCC
VCC
2
CLK
2
CLK
nQ0, nQ1
Q0, Q1
VCCO_LVCMOS
Q2:Q7
2
t
tPD
PD
LVPECL PROPAGATION DELAY
LVCMOS PROPAGATION DELAY
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
9
ICS8538BGI-26 REV. B APRIL 14, 2009
ICS8538I-26
LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION, CONTINUED
nQx
Qx
Qx
Qy
nQy
Qy
tsk(o)
tsk(o)
LVPECL OUTPUT SKEW
LVCMOS OUTPUT SKEW
Part 1
nQx
Part 1
VCCO_LVCMOS
Qx
Qy
2
Qx
Part 2
nQy
Part 2
VCCO_LVCMOS
2
Qy
tsk(pp)
tsk(pp)
LVPECL PART-TO-PART SKEW
LVCMOS PART-TO-PART SKEW
nQ0, nQ1
VCCO_LVCMOS
2
Q0, Q1
Q2:Q7
tPW
tPW
tPERIOD
tPERIOD
tPW
odc =
x 100ꢀ
tPW
odc =
x 100ꢀ
tPERIOD
tPERIOD
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nQ0, nQ1
80ꢀ
tF
80ꢀ
tR
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
20ꢀ
20ꢀ
20ꢀ
Q0, Q1
Q2:Q7
LVCMOS OUTPUT RISE/FALL TIME
LVPECL OUTPUT RISE/FALL TIME
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
10
ICS8538BGI-26 REV. B APRIL 14, 2009
ICS8538I-26
LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION, CONTINUED
Phase Noise Plot
Offset Frequency
f1
f2
RMS Jitter = Area Under Offset Frequency Markers
RMS PHASE JITTER
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS OUTPUTS
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
All unused LVCMOS output can be left floating. There should be
no trace attached.
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
CLK INPUT
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
LVCMOS CONTROL PINS
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
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LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER
CRYSTAL INPUT INTERFACE
The ICS8538I-26 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using an 18pF parallel resonant
crystal and were chosen to minimize the ppm error.These same
capacitor values will tune any 18pF parallel resonant crystal
over the frequency range and other parameters specified in
this data sheet. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
XTAL_OUT
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
C2
27p
FIGURE 2. CRYSTAL INPUT INTERFACE
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance.In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω.This can also be accomplished by removing
R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS signals, it
is recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise.This configuration requires that the output
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
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TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended that the
board designers simulate to guarantee compatibility across all
printed circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
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TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 5A and Figure 5B show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to
very close to _LVCMOSground level. The R3 in Figure 5B can
be eliminated and the termination is shown in Figure 5C.
terminating 50Ω to V – 2V. For V = 2.5V, the V
– 2V is
CC
CCO
CCO_LVCMOS
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
R3
250
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
+
-
Zo = 50 Ohm
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8538I-26.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8538I-26 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Core and LVPECL Output Power Dissipation
•
•
Power (core) = V
* I
= 3.465V * 60mA = 207.9mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 2 * 30mW = 60mW
LVCMOS Output Power Dissipation
•
Output Impedance R Power Dissipation due to Loading 50Ω to V
/2
CCO_LVCMOS
OUT
Output Current IOUT = VCCO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 15Ω)] = 26.7mA
•
•
•
Power Dissipation on the ROUT per LVCMOS output
2
Power (ROUT) = ROUT * (IOUT
)
= 15Ω * (26.7mA)2 = 10.7mW per output
Total Power Dissipation on the ROUT
Total Power (ROUT) = 10.7mW * 6 = 64.2mW
Dynamic Power Dissipation at 25MHz
2
Power (25MHz) = CPD * Frequency * (VCCO_LVCMOS
)
= 10pF * 25MHz * (3.465V)2 = 3mW per output
Total Power (25MHz) = 3mW * 6 = 18mW
Total Power Dissipation
Total Power
•
= Power (core) + Power (LVPECL output) + Total Power (ROUT) + Total Power (25MHz)
= 207.9mW + 60mW + 64.2mW + 18mW
= 350.1mW
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
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2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used. Assuming no air
JA
flow and a multi-layer board, the appropriate value is 87.8°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.350W * 87.8°C/W = 115.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 24-PIN TSSOP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
81.3°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
87.8°C/W
83.5°C/W
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V – 2V.
CCO
•
•
For logic high, V = V
= V
– 0.9V
OUT
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
– V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
– V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
– 2V))/R ] * (V
– V
) = [(2V – (V
– V
– V
/R ] * (V
– V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
CCO
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
– 2V))/R ] * (V
– V
) = [(2V – (V
/R ] * (V
– V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
OL_MAX
CCO_MAX
OL_MAX
L
CCO
L
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
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RELIABILITY INFORMATION
TABLE 8. θ VS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
81.3°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
87.8°C/W
83.5°C/W
TRANSISTOR COUNT
The transistor count for ICS8538I-26 is: 726
PACKAGE OUTLINE AND PACKAGE DIMENSIONS
TABLE 9. PACKAGE DIMENSIONS
SYMBOL
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
Millimeters
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
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TABLE 10. ORDERING INFORMATION
Part/Order Number
8538BGI-26LF
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
8538BGI26L
8538BGI26L
24 lead "Lead-Free" TSSOP
24 lead "Lead-Free" TSSOP
8538BGI-26LFT
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FANOUT BUFFER
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REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
1
Features section - LVPECL operating supply modes, added full 2.5; for
LVCMOS outputs, changed 3.3V/2.5V to full 2.5V mode.
Pin Characteristics - updated table to accommodate 2.5V for CPD and ROUT and
added specs.
T2
2
T4A - T4B
T4C
4
5
5
6
7
Power Supply Table - updated power supply tables to new supply mode.
LVCMOS Table - updated table with new supply mode.
Added 2.5V LVPECL DC Characteristics Table.
Added 2.5V LVPECL AC Characteristics Table.
Added 3.3V LVCMOS AC Characteristics Table.
Changed LVCMOS AC Characteristics Table from 3.3V/2.5V to 2.5V/2.5V.
Added RMS Phase Jitter Plot.
T5E
T6B
T6C
T6D
B
4/14/09
7
8
11
Parameter Measurement Information Section - added RMS Phase JItter
diagram.
T7
T8
16
18
Recalucated junction temperature equation and updated Thermal Resistance
table.
Updated Thermal Resistance Table.
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+408-284-8200 (outside USA)
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
8538BGI-26LFT
Clock Generator, 266MHz, PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
IDT
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