8538BG-31T [IDT]
Clock Generator, PDSO28;
| 型号： | 8538BG-31T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO28 光电二极管 外围集成电路 |
| 文件： | 总14页 (文件大小：1454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
ICS8538-31
General Description
Features
The ICS8538-31 is a low skew, high performance
• Eight differential 3.3V LVPECL outputs
S
IC
1-to-8 Crystal Oscillator/LVCMOS-to-3.3V LVPECL
Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
IDT. The ICS8538-31 has selectable single ended
• Selectable LVCMOS/LVTTL clock or crystal inputs
• CLK can accept the following input levels: LVCMOS, LVTTL
• Maximum output frequency: 266MHz
HiPerClockS™
clock or crystal inputs. The single ended clock input accepts
LVCMOS or LVTTL input levels and translate them to 3.3V
LVPECL levels. The output enable is internally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
• Crystal frequency range: 14MHz - 40MHz
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 2.2ns (maximum)
• 3.3V operating supply mode
Guaranteed output and part-to-part skew characteristics make the
ICS8538-31 ideal for those applications demanding well defined
performance and repeatability.
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pin Assignment
CLK
CLK_SEL
CLK_EN
VEE
1
2
3
4
5
6
7
8
28
VCC
Pullup
CLK_EN
D
27 XTAL_IN
26 XTAL_OUT
Q
LE
25
24
23
22
21
20
19
18
17
16
VEE
Q0
nQ0
VCCO
Q1
nQ1
Q2
nQ2
VCCO
Q3
Pulldown
CLK
0
1
nQ7
Q7
VCCO
nQ6
Q6
nQ5
Q5
VEE
nQ4
Q0
nQ0
XTAL_IN
Q1
nQ1
OSC
9
XTAL_OUT
CLK_SEL
10
11
12
13
Q2
nQ2
Pulldown
Q3
nQ3
Q4 14
15 nQ3
Q4
nQ4
28-Lead TSSOP, 173MIL
4.4mm x 9.7mm x 0.925mm package body
G Package
Q5
nQ5
Top View
Q6
nQ6
Q7
nQ7
IDT™ / ICS™ LVPECL FANOUT BUFFER
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LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
CLK
Type
Description
1
2
Input
Input
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
CLK_SEL
CLK_EN
VEE
Pulldown
3
Input
Pullup
4, 12, 25
5, 6
Power
Output
Power
Output
Negative supply pins.
Differential output pair. LVPECL interface levels.
Output supply pins.
nQ7, Q7
VCCO
7, 17, 22
8, 9
Differential output pair. LVPECL interface levels.
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
10, 11
13, 14
15, 16
18, 19
20, 21
23, 24
Output
Output
Output
Output
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
26,
27
XTAL_OUT
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Positive supply pin.
28
VCC
Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
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Function Tables
Table 3A. Control Input Function Table
Inputs
CLK_SEL
Outputs
CLK_EN
Selected Source
CLK
Q0:Q7
Disabled; Low
Disabled; Low
Enabled
nQ0:nQ7
Disabled; High
Disabled; High
Enabled
0
0
1
1
0
1
0
1
XTAL_IN, XTAL_OUT
CLK
XTAL_IN, XTAL_OUT
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or crystal oscillator edge as
shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK input as described in Table 3B.
Enabled
Disabled
CLK
CLK_EN
nQ0:nQ7
Q0:Q7
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
nQ0:nQ7
CLK
Q0:Q7
LOW
0
1
HIGH
LOW
HIGH
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC+ 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
49.8°C/W (0 lfpm)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
3.465
110
Units
V
VCC
VCCO
IEE
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
3.135
3.3
V
mA
mA
ICCO
50
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
VIH
VIL
Input High Voltage
2
VCC + 0.3
Input Low Voltage
-0.3
0.8
150
5
V
CLK, CLK_SEL
CLK_EN
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
µA
µA
µA
µA
Input
High Current
IIH
CLK, CLK_SEL
CLK_EN
-5
Input
Low Current
IIL
V
CC = 3.465V, VIN = 0V
-150
Table 4C. LVPECL DC Characteristics, VCC = VCCO = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCCO – 1.4
VCCO– 2.0
0.6
Typical
Maximum
VCCO – 0.9
VCCO – 1.7
1.0
Units
µA
Output High Current; NOTE 1
Output Low Current; NOTE 1
Peak-to-Peak Output Voltage Swing
VOL
µA
VSWING
V
NOTE 1: Outputs terminated with 50Ω to VCCO – 2V.
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Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Frequency
Fundamental
14
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = VCCO = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Parameter Symbol
fMAX Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum
266
Units
MHz
ns
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
2.2
tsk(o)
tsk(pp)
tR / tF
odc
50
ps
250
ps
20% to 80%
200
45
700
ps
Output Duty Cycle
55
%
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VCC/2 input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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Parameter Measurement Information
2V
Part 1
nQx
SCOPE
V
CC,
Qx
Qx
V
CCO
Part 2
nQy
Qy
LVPECL
nQx
VEE
tsk(pp)
-
-1.3V 0.165V
3.3/3.3V LVPECL Output Load AC Test Circuit
Part-to-Part Skew
nQx
Qx
CLK
nQy
nQ0:nQ7
Q0:Q7
Qy
tPD
tsk(o)
Output Skew
Propagation Delay
nQ0:nQ7
Q0:Q7
80%
tF
80%
tR
tPW
tPERIOD
VSWING
20%
Clock
Outputs
20%
tPW
odc =
x 100%
tPERIOD
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
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LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Application Information
Crystal Input Interface
The ICS8538-31 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using an 18pF parallel resonant
crystal and were chosen to minimize the ppm error. These same
capacitor values will tune any 18pF parallel resonant crystal over
the frequency range and other parameters specified in this data
sheet. The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
XTAL_IN
C1
18p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VCC
VCC
R1
0.1µf
50Ω
Ro
Rs
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
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LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
CLK Input
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
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LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8538-31.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8538-31 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 110mA = 381.15mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 8 * 30mW = 240mW
Total Power_MAX (3.3V, with all outputs switching) = 381.15mW + 240mW = 621.15mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 49.8°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.621W * 49.8°C/W = 100.9°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 7. Thermal Resistance θJA for 28 Lead TSSOP, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
82.9°C/W
49.8°C/W
68.7°C/W
43.9°C/W
60.5°C/W
41.2°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
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LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 5. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of VCCO – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Reliability Information
Table 8. θJA vs. Air Flow Table for a 282 Lead TSSOP
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
82.9°C/W
49.8°C/W
68.7°C/W
43.9°C/W
60.5°C/W
41.2°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS8430-62 is: 4258
Package Outline and Package Dimension
Package Outline - G Suffix for 28 Lead TSSOP
Table 9. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
28
1.20
0.15
1.05
0.30
0.20
9.80
A1
A2
b
0.5
0.80
0.19
0.09
9.60
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 10. Ordering Information
Part/Order Number
ICS8538BG-31
ICS8538BG-31T
ICS8538BG-31LF
ICS8538BG-31LFT
Marking
Package
28 Lead TSSOP
28 Lead TSSOP
Shipping Packaging
Tube
1000 Tape & Reel
Tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS8538BG-31
ICS8538BG-31
ICS8538BG-31LF
ICS8538BG-31LF
“Lead-Free” 28 Lead TSSOP
“Lead-Free” 28 Lead TSSOP
1000 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev
Table
Page
13
Description of Change
Date
A
T10
Ordering Information table - added Lead-Free marking.
1/18/08
5
AC Characteristics Table - changed Output Rise/Fall parameters from 500ps min. to
200ps min., and 850ps max. to 700ps max.
B
T6
2/5/08
9
Power Considerations - updated Junction Temperature equation with worst case
thermal resistance of 0 lfpm at 49.8°C/W.
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LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
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