85211AMI-01 [IDT]
Clock Driver, 85211 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, MS-012, SOIC-8;
| 型号： | 85211AMI-01 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, 85211 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, MS-012, SOIC-8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总14页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85211I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
FEATURES
GENERAL DESCRIPTION
• Two differential HSTL compatible outputs
• One differential CLK, nCLK input pair
The ICS85211I-01 is a low skew, high performance 1-to-2
Differential-to-HSTL Fanout Buffer. The CLK, nCLK pair can
accept most standarddifferential input levels.The ICS85211I-
01 is characterized to operate from a 3.3V power supply.
Guaranteed output and part-to-part skew characteristics
make the ICS85211I-01 ideal for those clock distribution
applications demanding well defined performance and
repeatability. For optimal performance, terminate all outputs.
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
• Translates any single-ended input signal to HSTL
levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1ns (maximum)
• Output crossover Voltage: 0.68V to 0.9V
• Output duty cycle: 49% - 51% up to 266.6MHz
• VOH = 1.4V (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
VDD
1
2
3
4
8
7
6
5
Q0
nQ0
CLK
nCLK
GND
CLK
nCLK
Q1
nQ1
nQ1
ICS85211I-01
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
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ICS85211I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
GND
Type
Description
Output
Output
Power
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Power supply ground.
3, 4
5
Pullup/
Pulldown
6
nCLK
Input
Inverting differential clock input. VDD/2 default when left floating.
7
8
CLK
VDD
Input
Pulldown Non-inverting differential clock input.
Positive supply pin.
Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Q0, Q1 nQ0, nQ1
Input to Output Mode
Polarity
CLK
nCLK
0
0
LOW
HIGH
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
1
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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ICS85211I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
Outputs, VDD
Package Thermal Impedance, θJA 112.7°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
IDD
Power Supply Voltage
Power Supply Current
3.135
3.3
3.465
22
V
mA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
nCLK
CLK
V
DD = VIN = 3.465V
150
150
µA
µA
µA
µA
V
IIH
Input High Current
V
DD = VIN = 3.465V
nCLK
CLK
V
V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VDD - 0.85
V
NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 4C. HSTL DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
1.0
0
1.4
0.4
0.9
1.4
V
V
V
V
VOL
Output Low Voltage; NOTE 1
Output Crossover Voltage
VOX
0.68
0.6
VSWING
Peak-to-Peak Output Voltage Swing
1.0
NOTE 1: All outputs must be terminated with 50Ω to ground.
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TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
700
1.0
30
MHz
ns
ps
ps
ps
%
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
IJ 600MHz
0.7
tsk(o)
tsk(pp)
tR / tF
250
500
52
20% to 80%
200
48
odc
Output Duty Cycle
IJ 266.6MHz
49
51
%
All parameters measured at 600MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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PARAMETER MEASUREMENT INFORMATION
3.3V 5%
VDD
VDD
SCOPE
Qx
nCLK
CLK
HSTL
VPP
VCMR
Cross Points
nQx
GND
GND
0V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
Qx
PART 1
nQx
Qy
nQy
PART 2
nQy
Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK
CLK
80%
tF
80%
VSWING
20%
Clock
20%
nQ0, nQ1
Outputs
tR
Q0, Q1
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0, nQ1
Q0, Q1
tPW
tPERIOD
tPW
odc =
x 100%
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS85211I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1. This bias circuit clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin. The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of ICS85211I-01. In this the power pin. For ICS85211I-01, the unused outputs
example, the input is driven by an ICS HiPerClockS HSTL driver. need to be terminated.
The decoupling capacitors should be physically located near
Zo = 50 Ohm
1.8V
-
U1
Zo = 50 Ohm
Zo = 50 Ohm
5
6
7
8
4
3
2
1
Zo = 50 Ohm
GND
nCLK
CLK
VDD
nQ1
Q1
nQ0
Q0
+
R1
50
R2
50
LVHSTL Input
VDD=3.3V
LVHSTL
ICS
ICS85211-01
R6
50
R5
50
C1
0.1u
HiPerClockS
LVHSTL Driv er
Unused
Output
Need To
Be
R3
50
R4
50
Terminated
FIGURE 2. ICS85211I-01 HSTL BUFFER SCHEMATIC EXAMPLE
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RECOMMENDATIONS FOR UNUSED OUTPUT PINS
OUTPUTS:
HSTL OUTPUT
All unused HSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
CLOCK INPUT INTERFACE
The CLK /nCLK accepts differential input signals of both VSWING vendor of the driver components to confirm the driver
andVOH to meet theVPP andVCMR input requirements. Figures 3A termination requirement. For example in Figure 3, the input
to 3D show interface examples for the ICS85211I-01 clock input termination applies for HSTL drivers. If you are using an HSTL
driven by most common driver types. The input interfaces driver from another vendor, use their termination
suggested here are examples only. Please consult with the recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. ICS85211I-01 CLK/NCLK INPUT DRIVEN BY
HSTL DRIVER
FIGURE 3B. ICS85211I-01 CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER (INTERFACE 1)
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
nCLK
HiPerClockS
Input
nCLK
HiPerClockS
Input
LVPECL
R5
100-200
R6
100-200
R1
84
R2
84
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3C. ICS85211I-01 CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER (INTERFACE 2)
FIGURE 3D. ICS85211I-01 CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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ICS85211I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85211I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85211I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 22mA = 76.2mW
Power (outputs)MAX = 82.34mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 82.34mW = 164.7mW
Total Power_MAX (3.465V, with all outputs switching) = 76.2mW + 164.7mW = 240.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.241W * 103.3°C/W = 110°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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LOW SKEW, 1-TO-2
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 4.
VDD
Q1
VOUT
RL
50Ω
FIGURE 4. HSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (VOH_MAX /R ) * (VDD_MAX - V
)
L
OH_MAX
Pd_L = (VOL_MAX /R ) * (VDD_MAX - VOL_MAX
)
L
Pd_H = (1.4V/50Ω) * (3.465V - 1.4V) = 57.82mW
Pd_L = (0.4V/50Ω) * (3.465V - 0.4V) = 24.52mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 82.34mW
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RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85211I-01 is: 411
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PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MINIMUN
MAXIMUM
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
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DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
85211AMI-01
Marking
5211AI01
5211AI01
211AI01L
211AI01L
Package
8 lead SOIC
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
85211AMI-01T
8 lead SOIC
2500 tape & reel
tube
85211AMI-01LF
85211AMI-01LFT
8 lead "Lead-Free" SOIC
8 lead "Lead-Free" SOIC
2500 tape & reel
NOTE: Parts thar are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS
compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
Throughout data sheet changed LVHSTL to HSTL.
Changed nCLK Type from VDD/2 to Pullup/Pulldown.
1
2
2
2
A
7/16/03
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
Changed RPULLUP to RPULLUP/RPULLDOWN, Pullup/Pulldown Resistors.
1
7
12
Features section - added Lead Free/RoHS bullet.
Added Recommendations for Unused Output Pins.
Ordering Information Table - added Lead-Free part number and marking.
Updated datasheet's header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
A
B
11/01/05
8/4/10
T9
T9
12
14
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LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
netcom@idt.com
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
Printed in USA
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