85211AMI-03T [IDT]
Low Skew Clock Driver, PDSO8;
| 型号： | 85211AMI-03T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, PDSO8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85211I-03
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
FEATURES
GENERAL DESCRIPTION
• 2 differential LVHSTL compatible outputs
The ICS85211I-03 is a low skew, high perfor-
ICS
mance 1-to-2 Differential-to-LVHSTL Fanout
Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions
from IDT. The CLK, nCLK pair can accept most
• 1 differential CLK, nCLK input pair
HiPerClockS™
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
standard differential input levels.The ICS85211I-03 is char-
acterized to operate from a 3.3V power supply. Guar-
anteed output and part-to-part skew characteristics
make the ICS85211I-03 ideal for those clock distribution
applications demanding well defined performance and
repeatability. For optimal performance, terminate all outputs.
• Maximum output frequency: 700MHz
• Translates any single-ended input signal to
LVHSTL levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1ns (maximum)
• Output duty cycle: 49% - 51% up to 266.6MHz
• VOH = 1V (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS
6) packages.
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
VDD
1
2
3
4
8
7
6
5
Q0
nQ0
CLK
nCLK
GND
CLK
nCLK
Q1
nQ1
nQ1
ICS85211I-03
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
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DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Q0, nQ0
Q1, nQ1
GND
Type
Description
1, 2
3, 4
5
Output
Output
Power
Input
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Power supply ground.
6
nCLK
CLK
VDD/2
Inverting differential clock input. VDD/2 default when left floating.
7
Input
Pulldown Non-inverting differential clock input.
Positive supply pin.
8
VDD
Power
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
KΩ
KΩ
RPULLUP
RPULLDOWN
51
51
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Q0, Q1 nQ0, nQ1
Input to Output Mode
Polarity
CLK
nCLK
0
0
LOW
HIGH
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
1
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VDD
Inputs, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
Outputs,VDD
PackageThermal Impedance, θJA 112.7°C/W (0 lfpm)
StorageTemperature,TSTG -65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
IDD
Power Supply Voltage
Power Supply Current
3.135
3.3
3.465
50
V
mA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum Typical Maximum Units
nCLK
CLK
VDD = VIN = 3.465V
150
150
µA
µA
µA
µA
V
V
DD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
nCLK
CLK
-150
-5
IIL
Input Low Current
V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VDD - 0.85
V
NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 4C. LVHSTL DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
0.7
0
1.0
0.4
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
0.3
0.65
NOTE 1: All outputs must be terminated with 50Ω to ground.
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TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
700
1
MHz
ns
ps
ps
ps
%
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
IJ 600MHz
0.7
tsk(o)
tsk(pp)
tR / tF
30
250
450
53
20% to 80%
185
47
odc
Output Duty Cycle
IJ 266.6MHz
49
51
%
All parameters measured at 600MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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PARAMETER MEASUREMENT INFORMATION
VDD = 3.3V 5%
VDD
SCOPE
Qx
nCLK
CLK
LVHSTL
VPP
VCMR
Cross Points
nQx
GND
GND = 0V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
Qx
PART 1
nQx
Qy
nQy
PART 2
nQy
Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK
CLK
80%
tF
80%
VSWING
20%
Clock
20%
nQ0, nQ1
Outputs
tR
Q0, Q1
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0, nQ1
Q0, Q1
tPW
tPERIOD
tPW
odc =
x 100%
tPERIOD
odc & tPERIOD
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APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of ICS85211I-03. In this near the power pin. For ICS85211I-03, the unused outputs need
example, the input is driven by an ICS HiPerClockS LVHSTL to be terminated.
driver. The decoupling capacitors should be physically located
Zo = 50 Ohm
1.8V
-
U1
Zo = 50 Ohm
Zo = 50 Ohm
5
6
7
8
4
3
2
1
Zo = 50 Ohm
GND
nCLK
CLK
nQ1
Q1
nQ0
Q0
+
VDD
R1
50
R2
50
LVHSTL Input
VDD=3.3V
LVHSTL
ICS
ICS85211-03
R6
50
R5
50
C1
0.1u
HiPerClockS
LVHSTL Driv er
Unused
Output
Need To
Be
R3
50
R4
50
Terminated
FIGURE 2. ICS85211I-03 LVHSTL BUFFER SCHEMATIC EXAMPLE
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CLOCK INPUT INTERFACE
The CLK /nCLK accepts differential input signals of both VSWING driver components to confirm the driver termination requirement.
andVOH to meet theVPP andVCMR input requirements.Figures 3 to For example in Figure 3, the input termination applies for ICS
6show interface examples for the ICS85211I-03 clock input driven HiPerClockS LVHSTL drivers.If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
by most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
LVHSTL Driver
R1
50
R2
50
R3
50
FIGURE 3. ICS85211I-03 CLK/NCLK INPUT DRIVEN BY
HIPERCLOCKS LVHSTL DRIVER
FIGURE 4. ICS85211I-03 CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER (INTERFACE 1)
3.3V
3.3V
3.3V
3.3V
3.3V
R3
R4
3.3V
125
125
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
nCLK
HiPerClockS
Input
nCLK
HiPerClockS
Input
LVPECL
R5
100-200
R6
100-200
R1
84
R2
84
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 5. ICS85211I-03 CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER (INTERFACE 2)
FIGURE 6. ICS85211I-03 CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85211I-03.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85211I-03 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.3mW
Power (outputs)MAX = 73.82mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 73.82mW = 147.6mW
Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 147.6mW = 320.9mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.321W * 103.3°C/W = 118.2°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in Figure 7.
VDD
Q1
VOUT
RL
50
Ω
FIGURE 7. LVHSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (VOH_MAX /R ) * (VDD_MAX - V
)
L
OH_MAX
Pd_L = (VOL_MAX /R ) * (VDD_MAX - VOL_MAX
)
L
Pd_H = (1.0V/50Ω) * (3.465V - 1.0V) = 49.3mW
Pd_L = (0.4V (50Ω) * (3.465V - 0.4V) = 24.52mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 73.82mW
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DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
θJA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85211I-03 is: 411
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PACKAGE OUTLINE - M SUFFIX
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MINIMUN
MAXIMUM
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
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DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS85211AMI-03
Marking
5211AI03
5211AI03
211AI03L
211AI03L
Package
8 lead SOIC
Shipping Packaging
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS85211AMI-03T
ICS85211AMI-03LF
ICS85211AMI-03LFT
8 lead SOIC
2500 Tape & Reel
Tube
Lead-Free, 8 lead SOIC
Lead-Free, 8 lead SOIC
2500 Tape & Reel
NOTE: Parts that are ordered with an ""LF"" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT.IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
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DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
B
Table
T4A
Page
3
8
Date
4/8/03
Power Supply table, changed maximum IDD spec to 50mA from 40mA.
Power Considerations, changed IDD_MAX to 50mA from 40mA and recalculated
equations.
12
B
T9
Ordering Information Table - Added Lead Free part numbers and marking
11/14/07
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相关型号：
85211AMIT
Low Skew Clock Driver, 85211 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, MS-012, SOIC-8
IDT
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