85211BMI-03T [IDT]
Clock Driver, PDSO8;
| 型号： | 85211BMI-03T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, PDSO8 光电二极管 |
| 文件： | 总15页 (文件大小：765K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-2, Differential-to-LVHSTL
Fanout Buffer
ICS85211BI-03
DATA SHEET
General Description
Features
The ICS85211BI-03 is a low skew, high performance
1-to-2 Differential-to-LVHSTL Fanout Buffer. The CLK,
nCLK pair can accept most standard differential input
levels.The ICS85211BI-03 is characterized to operate
from a 3.3V power supply. Guaranteed output and
• Two differential LVHSTL compatible outputs
• One differential CLK, nCLK input pair
S
IC
HiPerClockS™
• CLK, nCLK pair can accept the following differential input levels:
LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
part-to-part skew characteristics make the ICS85211BI-03 ideal for
those clock distribution applications demanding well defined
performance and repeatability.
• Translates any single ended input signal to LVHSTL levels with
resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.3ns (maximum)
• Output duty cycle: 49% – 51% up to 266.6MHz
• VOH = 1.15V (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pin Assignment
Q0
nQ0
Q0
nQ0
Q1
VDD
1
2
3
4
8
7
6
5
Pullup
CLK
nCLK
CLK
nCLK
GND
Pulldown
Q1
nQ1
nQ1
ICS85211BI-03
8-Lead SOIC
3.90mm x 4.903mm x 1.37mm package body
M Package
Top View
ICS85211BMI-03 REVISION C MARCH 12, 2010
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©2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
GND
Type
Description
Output
Output
Power
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Power supply ground.
3, 4
5
6
nCLK
Input
Pulldown
Pullup
Inverting differential clock input.
7
8
CLK
VDD
Input
Non-inverting differential clock input.
Positive supply pin.
Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
Function Tables
Table 3. Clock Input Function Table
Inputs
Outputs
CLK
nCLK
Q0, Q1
nQ0, nQ1
HIGH
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
0
0
LOW
HIGH
LOW
HIGH
HIGH
LOW
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
1
1
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section, ""Wiring the Differential Input to Accept Single Ended Levels"".
ICS85211BMI-03 REVISION C MARCH 12, 2010
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©2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Storage Temperature, TSTG
-65°C to 150°C
Package Thermal Impedance, θJA
112.7°C/W (0 lfpm)
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
Typical
Maximum
3.465
55
Units
V
Positive Supply Voltage
Power Supply Current
3.135
3.3
IDD
mA
Table 4B. Differential DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol Parameter Test Conditions
Minimum
Typical
Maximum
Units
µA
CLK
V
DD = VIN = 3.465V
5
IIH
Input High Current
nCLK
CLK
VDD = VIN = 3.465V
150
µA
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-150
-5
µA
IIL
Input Low Current
nCLK
µA
Peak-to-Peak Input Voltage;
NOTE 1
VPP
0.15
1.3
V
V
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
VDD – 0.85
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
ICS85211BMI-03 REVISION C MARCH 12, 2010
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©2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Table 4C. LVHSTL DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol Parameter Test Conditions
Minimum
Typical
Maximum
1.15
Units
VOH
Output High Current; NOTE 1
0.7
0
V
V
V
VOL
Output Low Current; NOTE 1
0.4
VSWING
Peak-to-Peak Output Voltage Swing
0.3
0.65
1.15
NOTE 1: Outputs terminated with 50Ω to ground.
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
700
1.3
Units
MHz
ns
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
ƒ ≤ 600MHz
0.9
tsk(o)
tsk(pp)
tR / tF
30
ps
250
450
53
ps
20% to 80%
185
47
ps
%
odc
Output Duty Cycle
ƒ ≤ 266.6MHz
49
51
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
All parameters are measured 600MHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS85211BMI-03 REVISION C MARCH 12, 2010
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©2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Parameter Measurement Information
3.3V 5%
V
DD
nCLK
CLK
SCOPE
VDD
Qx
VPP
VCMR
Cross Points
LVHSTL
nQx
GND
GND
0V
Output Load AC Test Circuit
Differential Input Level
nQx
Qx
Part 1
nQx
Qx
nQy
Part 2
nQy
Qy
Qy
tsk(o)
tsk(pp)
Part-to-Part Skew
Output Skew
nCLK
CLK
nQ[0:1]
80%
80%
VSWING
20%
nQ[0:1]
20%
Q[0:1]
tF
tR
Q[0:1]
tPD
Output Rise/Fall Time
Propagation Delay
ICS85211BMI-03 REVISION C MARCH 12, 2010
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©2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Parameter Measurement Information, continued
nQ[0:1]
Q[0:1]
tPW
tPERIOD
tPW
odc =
x 100%
tPERIOD
Output Duty Cycle/Pulse Width/Period
ICS85211BMI-03 REVISION C MARCH 12, 2010
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©2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Application Information
Recommendations for Unused Output Pins
Outputs:
LVHSTL Outputs
All unused LVHSTL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the VREF in the center of the input voltage swing.
For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and
R2 value should be adjusted to set VREF at 1.25V. The values below
are for when both the single ended swing and VCC are at the same
voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads should
be placed in the layout. They can be utilized for debugging purposes.
The datasheet specifications are characterized and guaranteed by
using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS85211BMI-03 REVISION C MARCH 12, 2010
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©2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 2A to 2F show interface
examples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 2A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
Differential
Input
LVPECL
nCLK
R1
50
R2
50
Differential
Input
LVHSTL
R1
50
R2
50
IDT
HiPerClockS
LVHSTL Driver
R2
50
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECLDriver
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
nCLK
nCLK
Zo = 50Ω
Differential
Input
LVPECL
Receiver
LVDS
R1
84
R2
84
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
3.3V
2.5V
R3
R4
120
120
Zo = 50Ω
Zo = 60Ω
Zo = 60Ω
*R3
*R4
33
33
CLK
CLK
Zo = 50Ω
nCLK
nCLK
Differential
Input
SSTL
Differential
Input
HCSL
R1
120
R2
120
R1
50
R2
50
*Optional – R3 and R4 can be 0Ω
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 2F. CLK/nCLK Input Driven by a 2.5V SSTL Driver
ICS85211BMI-03 REVISION C MARCH 12, 2010
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©2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Schematic Example
Figure 3 shows a schematic example of ICS85211BI-03. In this
example, the input is driven by an IDT HiPerClockS LVHSTL driver.
The decoupling capacitors should be physically located near the
power pin.
Zo = 50 Ohm
1.8V
-
U1
Zo = 50 Ohm
Zo = 50 Ohm
5
6
7
8
4
3
2
1
Zo = 50 Ohm
GND
nCLK
CLK
nQ1
Q1
+
nQ0
Q0
VDD
R1
50
R2
50
LVHSTL Input
VDD=3.3V
LVHSTL
ICS
ICS85211BMI-03
R6
50
R5
50
C1
0.1u
HiPerClockS
Zo = 50 Ohm
Zo = 50 Ohm
LVHSTL Driv er
-
+
Unused Output
Can Be Floated
R3
50
R4
50
LVHSTL Input
Figure 3. ICS85211BI-03 LVHSTL Buffer Schematic Example
ICS85211BMI-03 REVISION C MARCH 12, 2010
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©2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS85211BI-03.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85211BI-03 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 55mA = 190.6mW
Power (outputs)MAX = 77.76mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 77.76mW = 155.52mW
Total Power_MAX (3.3V, with all outputs switching) =190.6mW + 155.52mW = 346.12mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air
flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.346W * 103.3°C/W = 120.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θJA for 8 Lead SOIC, Forced Convection
θJA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS85211BMI-03 REVISION C MARCH 12, 2010
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©2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVHSTL output pairs.
LVHSTL output driver circuit and termination are shown in Figure 4.
VDD
Q1
VOUT
RL
50Ω
Figure 4. LVHSTL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (VOH_MAX/ RL) * (VDD_MAX – (VOH_MAX
)
Pd_L = (VOL_MAX/ RL) * (VDD_MAX – (VOL_MAX
)
Pd_H = (1.15V/50Ω) * (3.465V – 1.15V) = 53.24mW
Pd_L = (0.4V/50Ω) * (3.465V – 0.4V) = 24.52mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 77.76mW
ICS85211BMI-03 REVISION C MARCH 12, 2010
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©2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Reliability Information
Table 7. θJA vs. Air Flow Table for a 8 Lead SOIC
θJA by Velocity
0
Linear Feet per Minute
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS85211BI-03 is: 472
Package Outline and Package Dimensions
Package Outline - M Suffix for 8 Lead SOIC
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
A1
B
C
D
E
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
e
1.27 Basic
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
ICS85211BMI-03 REVISION C MARCH 12, 2010
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©2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Ordering Information
Table 9. Ordering Information
Part/Order Number
85211BMI-03
85211BMI-03T
85211BMI-03LN
85211BMI-03LNT
Marking
Package
8 Lead SOIC
8 Lead SOIC
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
211BMI03
211BMI03
211BI03N
211BI03N
“Lead-Free” 8 Lead SOIC
“Lead-Free” 8 Lead SOIC
2500 Tape & Reel
NOTE: Parts that are ordered with an "N" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS85211BMI-03 REVISION C MARCH 12, 2010
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©2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
T4A
3
8
Power Supply Table - changed IDD max. from 50mA to 55mA.
B
10/15/03
9/14/04
Power Considerations - changed the IDD limit from 50mA to 55mA to reflect Table 4A.
Recalculated Power Dissipation and Junction Temperature formulas.
1
7
Features Section - add Lead-Free bullet.
B
Updated Differential Clock Input Interface section.
Added Lead-Free part number to Ordering Information table.
T8
T8
T8
12
B
B
12
12
Ordering Information Table - corrected Lead-Free P/N from "LF" to "LN".
Ordering Information Table - corrected marking to read "211BMI02".
10/11/04
10/18/04
6
Added Recommendations for Unused Input and Output Pins.
Corrected Power Considerations, Power Dissipation calculation.
Ordering Information Table - added lead-free note.
B
B
9-10
13
11/15/05
8/23/06
T9
T9
13
Ordering Information Table - corrected lead-free marking.
T1
2
3
Pin Description Table - changed pin 6 resistor (nCLK) from a Pullup/Pulldown to Pulldown.
T4B
Differential DC Characteristics Table - changed IIH CLK from 150uA to 5uA max.
Changed IIL nCLK from -150uA to -5uA min., and CLK from -5uA to -150uA min.
Updated NOTES.
C
C
12/11/09
3/3/10
T5
T9
4
7
AC Characteristics Table - added thermal note.
Ordering Information Table - deleted ICS prefix from the Part/Order Numbers.
Converted datasheet format.
13
7
Updated “Wiring the Differential to Accept Single Ended Levels”.
ICS85211BMI-03 REVISION C MARCH 12, 2010
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©2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
San Jose, California 95138
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2010. All rights reserved.
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IDT
85214AGIT
Low Skew Clock Driver, 85214 Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
IDT
85214AGT
Low Skew Clock Driver, 85214 Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
IDT
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