85210AY-31T [IDT]
Low Skew Clock Driver, 85210 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32;型号: | 85210AY-31T |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Low Skew Clock Driver, 85210 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32 驱动 逻辑集成电路 |
文件: | 总15页 (文件大小:235K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ICS85210-31
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS85210-31 is a low skew, high performance
dual 1-to-5 Differential-to-HSTL Fanout Buffer.The
CLKx, nCLKx pairs can accept most standard differential
input levels. The ICS85210-31 is characterized to
operate from a 3.3V power supply. Guaranteed
output and part-to-part skew characteristics make
the ICS85210-31 ideal for those clock distribution
applications demanding well defined performance
and repeatability.
• Dual 1-to-5 HSTL compatible bank outputs
• 2 selectable differential clock input pairs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
• Maximum output frequency: 650MHz
• Translates any single ended input signal to
LVHSTL levels with resistor bias on nCLKx inputs
• Output skew: 50ps (maximum)
• Part-to-part skew: 350ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free
(RoHS 6) packages
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
QA0
nQA0
CLK0
nCLK0
QA1
nQA1
32 31 30 29 28 27 26 25
CLK0_EN
QA2
nQA2
D
VDD
CLK0_EN
CLK0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QA3
Q
nQA3
QA4
LE
QA3
nQA3
nCLK0
nQA4
QB0
ICS85210-31
QA4
nQA4
CLK1_EN
CLK1
nQB0
QB1
nCLK1
nQB1
GND
QB0
nQB0
CLK1
9
10 11 12 13 14 15 16
nCLK1
QB1
nQB1
CLK1_EN
QB2
nQB2
D
32-Lead LQFP
Q
7mm x 7mm x 1.4mm package body
LE
QB3
nQB3
Y Package
TopView
QB4
nQB4
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ICS85210-31
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDD
Type
Description
1
2
3
4
5
6
7
8
Power
Pullup
Input
Core supply pin.
CLK0_EN
CLK0
Pullup
Synchronizing clock enable.
Pulldown Non-inverting differential clock input.
nCLK0
CLK1_EN
CLK1
Input
Pullup
Pullup
Inverting differential clock input.
Synchronizing clock enable.
Pullup
Input
Pulldown Non-inverting differential clock input.
nCLK1
GND
Input
Pullup
Inverting differential clock input.
Power supply ground.
Power
9, 16,
25, 32
VDDO
Power
Output supply pins.
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
nQB4, QB4
nQB3, QB3
nQB2, QB2
nQB1, QB1
nQB0, QB0
nQA4, QA4
nQA3, QA3
nQA2, QA2
nQA1, QA1
nQA0, QA0
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK0_EN, CLK1_EN
QA0:QA4, QB0:QB4
Disabled; LOW
Enabled
nQA0:QA4, nQB0: nQB4
Disabled; HIGH
Enabled
0
1
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 inputs
as described in Table 3B.
Enabled
Disabled
nCLK0, nCLK1
CLK0, CLK1
CLK0_EN,
CLK1_EN
nQA0:nQA4,
nQB0:nQB4
QA0:QA4,
QB0:QB4
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
QA0:QA4,
QB0:QB4
nQA0:nQA4,
nQB0:nQB4
CLK0 or CLK1
nCLK0 or nCLK1
0
0
LOW
HIGH
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
Differential to Differential
Differential to Differential
Non Inverting
Non Inverting
1
1
0
Biased; NOTE 1
Single Ended to Differential Non Inverting
Single Ended to Differential Non Inverting
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Single Ended to Differential
Single Ended to Differential
Inverting
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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ICS85210-31
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
47.9°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.4V TO 2.0V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Input Power Supply Voltage
3.465
2.0
V
Output Power Supply Voltage
Power Supply Current
1.4
1.8
V
120
mA
mA
IDDO
Output Supply Current
No Load
0
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.4V TO 2.0V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage CLK0_EN, CLK1_EN
2
VDD + 0.3
V
V
Input Low Voltage CLK0_EN, CLK1_EN
Input High Current CLK0_EN, CLK1_EN
Input Low Current CLK0_EN, CLK1_EN
-0.3
0.8
5
VDD = VIN = 3.465V
µA
µA
IIL
VDD = 3.465V, VIN = 0V
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.4V TO 2.0V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
V
DD = VIN = 3.465V
5
µA
µA
µA
µA
V
IIH
Input High Current
VDD = VIN = 3.465V
150
V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-150
-5
IIL
Input Low Current
V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VDD - 0.85
V
NOTE 1: For single ended applications the maximum input voltage for CLKx and nCLKx is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 4D. HSTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.4V TO 2.0V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Output High Voltage;
NOTE 1
VOH
1
1.4
V
Output Low Voltage;
NOTE 1
VOL
0
40ꢀ x (VOH - VOL) + VOL
0.6
0.4
60ꢀ x (VOH - VOL) + VOL
1.1
V
V
V
VOX
Output Crossover Voltage
Peak-to-Peak
Output Voltage Swing
VSWING
NOTE 1: Outputs terminated with 50Ω to ground.
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.4V TO 2.0V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
650
2
MHz
ns
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
IJ 650MHz
1.4
tsk(o)
tsk(pp)
tR / tF
odc
50
ps
350
700
53
ps
30ꢀ to 70ꢀ @ 50MHz
300
47
ps
Output Duty Cycle
ꢀ
All parameters measured at 400MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.4V to 2.0V
3.3V 5ꢀ
VDD
VDD
SCOPE
Qx
nCLK0,
nCLK1
VDDO
VPP
VCMR
Cross Points
HSTL
CLK0,
CLK1
GND
nQx
GND
0V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
Qx
PART 1
nQx
Qy
nQy
PART 2
nQy
Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK0,
nCLK1
80ꢀ
tF
80ꢀ
CLK0,
CLK1
VSWING
20ꢀ
Clock
20ꢀ
nQAx,
nQBx
QAx,
Outputs
tR
QBx
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQAx,
nQBx
QAx,
QBx
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V,V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL are examples only. Please consult with the vendor of the driver
and other differential signals.BothVSWING andVOH must meet the component to confirm the driver termination requirements. For
VPP and VCMR input requirements. Figures 3A to 3E show example in Figure 3A, the input termination applies for HSTL
interface examples for the CLK/nCLK input driven by the most drivers. If you are using an HSTL driver from another vendor,
common driver types. The input interfaces suggested here use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. CLK/nCLK INPUT DRIVEN BY
HSTL DRIVER
FIGURE 3B. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
C2
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85210-31.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85210-31 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 120mA = 416mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 32.8mW = 328mW
Total Power_MAX (3.465V, with all outputs switching) = 416mW + 328mW = 744mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.744W * 42.1°C/W = 101°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC StandardTest Boards
Multi-Layer PCB, JEDEC StandardTest Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 4.
VDDO
Q1
VOUT
RL
50Ω
FIGURE 4. HSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
- V
)
)
OH_MIN
L
DDO_MAX
OH_MIN
/R ) * (V
OL_MAX
L
DDO_MAX
OL_MAX
Pd_H = (1V/50Ω) * (2V - 1V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85210-31 is: 1216
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
85210AY-31
Marking
Package
Shippping Packaging
Tray
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS85210AY-31
ICS85210AY-31
ICS85210A31L
ICS85210A31L
32 lead LQFP
85210AY-31T
32 lead LQFP
Tape and Reel
Tray
85210AY-31LF
85210AY-31LFT
Lead-Free, 32 lead LQFP
Lead-Free, 32 lead LQFP
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
Throughout data sheet changed LVHSTL to HSTL.
2
2
7
8
Pin Description Table changed VDD description from Positive to Core.
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
Revised Single Ended Signal Driving Differential Input diagram.
Added Differential Clock Input Interface section.
1
2
A
9/29/03
Updated data sheet format.
4 & 5
All DC & AC Chararcteristics tables changed VDDO to 1.4V to 2.0V from
1.8V 0.2V.
T4A
T5
4
5
6
Power Supply DC Characteristics Table - changed VDDO min. from 1.6V to 1.4V.
AC Characteristics Table - changed tPD min. from 1.5ns to 1.4ns.
B
3/19/04
Parameter Measurement Information section - corrected 3.3V Output Load AC
Test Circuit diagram adding VDDO
.
Updated datasheet's header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
Features section - added lead-free bullet.
Ordering Information Table - added lead-free marking.
C
C
T9
T9
13
15
1
7/25/10
7/10/12
13
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Printed in USA
85210AY-31
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REV.C JULY 10, 2012
15
相关型号:
85211AMI-01
Clock Driver, 85211 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, MS-012, SOIC-8
IDT
85211AMI-01T
Clock Driver, 85211 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, MS-012, SOIC-8
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85211AMI-03LF
Clock Driver, 85211 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, ROHS COMPLIANT, MS-012, SOIC-8
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85211AMI-03LFT
Clock Driver, 85211 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, ROHS COMPLIANT, MS-012, SOIC-8
IDT
85211AMIT
Low Skew Clock Driver, 85211 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, MS-012, SOIC-8
IDT
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