83940DY-01LFT [IDT]
Low Skew, 1-to-18 LVPECL-TO-LVCMOS / LVTTL Fanout Buffer;
| 型号： | 83940DY-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew, 1-to-18 LVPECL-TO-LVCMOS / LVTTL Fanout Buffer |
| 文件： | 总15页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-18
LVPECL-TO-LVCMOS / LVTTL Fanout Buffer
83940-01
DATASHEET
FEATURES
GENERAL DESCRIPTION
• Eighteen LVCMOS/LVTTL outputs, 23Ω typical output impedance
• Selectable LVCMOS_CLK or LVPECL clock inputs
The ICS83940-01 is a low skew, 1-to-18 LVPECL-to-LVCMOS/LVTTL
Fanout Buffer. The ICS83940-01 has two selectable clock inputs. The
PCLK, nPCLK pair can accept LVPECL, CML or SSTL input levels.The
single ended clock input accepts LVCMOS or LVTTL input levels.The low
impedance LVCMOS/LVTTL outputs are designed
to drive 50Ω series or parallel terminated transmis-
sion lines. The effective fanout can be increased from 18 to
36 by utilizing the ability of the outputs to drive two series
terminated lines.
• LVCMOS_CLK supports the following input types:
LVCMOS or LVTTL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 250MHz
• Output skew: 85ps (maximum)
The ICS83940-01 is characterized at full 3.3V, full 2.5V
a n d m i xe d 3 . 3 V i n p u t a n d 2 . 5 V o u t p u t o p e r a t -
ing supply modes. Guaranteed output and part-to-part skew
characteristics make the ICS83940-01 ideal for those clock
distr ibution applications demanding well defined
performance and repeatability.
• Part-to-part skew: 750ps (maximum)
• Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Available in lead-free RoHS compliant package
BLOCK DIAGRAM
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
Q6
1
2
3
4
5
6
7
24
23
22
21
20
19
18
17
GND
GND
CLK_SEL
Q7
Q8
PCLK
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
18
VDDO
Q9
Q0:Q17
ICS83940-01
LVCMOS_CLK
Q10
Q11
GND
nPCLK
VDD
VDDO
8
9
10 11 12 13 14 15 16
32-Lead LQFP
Y Pacakge
7mm x 7mm x 1.4mm package body
Top View
83940-01 REVISION A NOVEMBER 4, 2014
1
©2014 Integrated Device Technology, Inc.
83940-01 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
1, 2, 12, 17, 25
3
Name
GND
Type
Description
Power
Power supply ground.
LVCMOS_CLK
Input Pulldown Clock input. LVCMOS / LVTTL interface levels.
Clock select input. Selects LVCMOS / LVTTL clock
Input Pulldown input when HIGH. Selects PCLK, nPCLK inputs when
LOW. LVCMOS / LVTTL interface levels.
4
CLK_SEL
5
6
PCLK
Input Pulldown Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
nPCLK
Input
VDD/2 default when left floating.
7
VDD
Power
Power
Power supply pin.
Output supply pins.
8, 16, 21, 29
VDDO
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
Q17, Q16, Q15, Q14, Q13,
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Output
Clock outputs. LVCMOS / LVTTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
6
pF
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
51
kΩ
18
28
Ω
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
PCLK, nPCLK
Selected
LVCMOS_CLK
De-selected
Selected
0
1
De-selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK_SEL LVCMOS_CLK
PCLK
nPCLK
Q0:Q17
LOW
0
0
—
—
0
1
1
0
Differential to Single Ended
Differential to Single Ended
Non Inverting
Non Inverting
HIGH
Biased;
NOTE 1
0
0
—
—
0
1
LOW
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
Biased;
NOTE 1
HIGH
0
0
1
1
—
—
0
Biased; NOTE 1
0
1
HIGH
LOW
LOW
HIGH
Single Ended to Single Ended
Single Ended to Single Ended
Inverting
Inverting
Biased; NOTE 1
—
—
—
—
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
2
REVISION A 11/4/14
83940-01 DATA SHEET
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute
Supply Voltage, V
3.6V
DD
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied.Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Inputs, V
-0.3V to VDD + 0.3V
-0.3V to VDDO + 0.3V
20mA
I
Outputs, VO
Input Current, IIN
Storage Temperature, T
-40°C to 125°C
STG
TABLE 4A. DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0° TO 70°
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
PCLK, nPCLK
2.4
VDD
0.8
V
V
Input Low Voltage
VPP
Peak-to-Peak Input Voltage
500
1000
mV
Input Common Mode Voltage;
NOTE 1, 2
VCMR
PCLK, nPCLK
V
DD - 1.4
VDD - 0.6
200
V
IIN
Input Current
µA
V
VOH
VOL
IDD
Output High Voltage
Output Low Voltage
Power Supply Current
IOH = -20mA
IOL = 20mA
2.4
0.5
25
V
mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK isVDD + 0.3V.
NOTE 2: Common mode voltage is defined asVIH.
TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
PCLK, nPCLK
2.4
VDD
0.8
V
V
Input Low Voltage
VPP
Peak-to-Peak Input Voltage
300
1000
mV
Input Common Mode Voltage;
NOTE 1, 2
VCMR
PCLK, nPCLK
V
DD - 1.4
VDD - 0.6
200
V
IIN
Input Current
µA
V
VOH
VOL
IDD
Output High Voltage
Output Low Voltage
Power Supply Current
IOH = -20mA
IOL = 20mA
1.8
0.5
25
V
mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK isVDD + 0.3V.
NOTE 2: Common mode voltage is defined asVIH.
REVISION A 11/4/14
3
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
83940-01 DATA SHEET
TABLE 4C. DC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
2
VDD
0.8
V
V
Input Low Voltage
Peak-to-Peak
Input Voltage
VPP
PCLK, nPCLK
PCLK, nPCLK
300
1000
mV
V
Input Common Mode Voltage;
NOTE 1, 2
VCMR
V
DD - 1.4
VDD - 0.6
200
IIN
Input Current
µA
V
VOH
VOL
IDD
Output High Voltage
Output Low Voltage
Power Supply Current
IOH = -12mA
IOL = 12mA
1.8
0.5
25
V
mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK isVDD + 0.3V.
NOTE 2: Common mode voltage is defined asVIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
250
MHz
PCLK, nPCLK;
NOTE 1, 5
f 150MHz
f 150MHz
f > 150MHz
f > 150MHz
1.6
1.8
1.6
1.8
3.0
ns
tpLH
Propagation Delay
Propagation Delay
LVCMOS_CLK;
NOTE 2, 5
3.0
3.3
3.2
ns
ns
ns
PCLK, nPCLK;
NOTE 1, 5
tpLH
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
85
85
ps
ps
ns
ns
ns
ns
ps
ps
ps
ꢀ
Output Skew;
NOTE 3, 5
Measured on
rising edge @VDDO/2
tsk(o)
f 150MHz
f 150MHz
f > 150MHz
f > 150MHz
1.4
1.2
1.7
1.4
850
750
800
55
Part-to-Part Skew;
NOTE 6
tsk(pp)
tsk(pp)
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 4, 5
Measured on
rising edge @VDDO/2
tsk(pp)
tR, tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
f 150MHz
400
45
odc
Output Duty Cycle
150MHz < f 250MHz
40
60
ꢀ
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
4
REVISION A 11/4/14
83940-01 DATA SHEET
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
250
MHz
PCLK, nPCLK;
NOTE 1, 5
f 150MHz
f 150MHz
f > 150MHz
f > 150MHz
1.7
1.7
1.6
1.8
3.2
ns
tpLH
Propagation Delay
Propagation Delay
LVCMOS_CLK;
NOTE 2, 5
3.0
3.4
3.3
ns
ns
ns
PCLK, nPCLK;
NOTE 1, 5
tpLH
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
150
150
1.5
1.3
1.8
1.5
850
750
800
55
ps
ps
ns
ns
ns
ns
ps
ps
ps
ꢀ
Output Skew;
NOTE 3, 5
Measured on
rising edge @VDDO/2
tsk(o)
f 150MHz
f 150MHz
f > 150MHz
f > 150MHz
Part-to-Part Skew;
NOTE 6
tsk(pp)
tsk(pp)
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 4, 5
Measured on
rising edge @VDDO/2
tsk(pp)
tR, tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
f < 134MHz
134MHz f < 250MHz
400
45
odc
Output Duty Cycle
40
60
ꢀ
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
REVISION A 11/4/14
5
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
83940-01 DATA SHEET
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
200
MHz
PCLK, nPCLK;
NOTE 1, 5
f 150MHz
f 150MHz
f > 150MHz
f > 150MHz
1.2
1.5
1.5
2
3.8
ns
tpLH
Propagation Delay;
LVCMOS_CLK;
NOTE 2, 5
3.2
3.7
3.6
ns
ns
ns
PCLK, nPCLK;
NOTE 1, 5
tpLH
Propagation Delay;
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
150
150
2.6
1.7
2.2
1.7
1.2
1.0
800
55
ps
ps
ns
ns
ns
ns
ns
ns
ps
ꢀ
Output Skew;
NOTE 3, 5
Measured on
rising edge @VDDO/2
tsk(o)
f 150MHz
f 150MHz
f > 150MHz
f > 150MHz
Part-to-Part Skew;
NOTE 6
tsk(pp)
tsk(pp)
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 4, 5
Measured on
rising edge @VDDO/2
tsk(pp)
tR, tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
f < 134MHz
134MHz f 200MHz
400
45
odc
Output Duty Cycle
40
60
ꢀ
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
6
REVISION A 11/4/14
83940-01 DATA SHEET
PARAMETER MEASUREMENT INFORMATION
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART-TO-PART SKEW
OUTPUT SKEW
REVISION A 11/4/14
7
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
83940-01 DATA SHEET
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
8
REVISION A 11/4/14
83940-01 DATA SHEET
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
in the center of the input voltage swing.For example, if the input
clock swing is only 2.5V andVDD = 3.3V,V_REF should be 1.25V
and R2/R1 = 0.609.
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position the V_REF
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK INPUT:
LVCMOS OUTPUT:
For applications not requiring the use of a clock input, it can be All unused LVCMOS output can be left floating.We recommend
left floating.Though not required, but for additional protection, a that there is no trace attached.
1kΩ resistor can be tied from the CLK input to ground.
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input,
both the PCLK and nPCLK pins can be left floating.Though not
required, but for additional protection, a 1kΩ resistor can be tied
from PCLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
REVISION A 11/4/14
9
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
83940-01 DATA SHEET
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and oth-
suggested here are examples only. If the driver is from
another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the
driver termination requirements.
SWING
OH
er differential signals. Both V
and V must meet the
PP
CMR
V
and V
input requirements. Figures 2A to 2E show
interface examples for the PCLK/nPCLK input driven
by the most common driver types. The input interfaces
3.3V
3.3V
3.3V
R1
50
R2
50
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
FIGURE 2A. PCLK/nPCLK INPUT DRIVEN
FIGURE 2B. PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
BY AN OPEN COLLECTOR CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
84
R4
84
R3
125
R4
125
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84
R2
84
FIGURE 2C. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2D. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
Zo = 50 Ohm
R3
1K
R4
1K
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
C1
C2
LVDS
PCLK
PCLK
R5
100
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
R1
1K
R2
1K
FIGURE 2E. PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 2F. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
10
REVISION A 11/4/14
83940-01 DATA SHEET
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θ
JA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
500
50.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83940-01 is: 819
REVISION A 11/4/14
11
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
83940-01 DATA SHEET
PACKAGE OUTLINE -Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0°
0.75
7°
θ
--
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
12
REVISION A 11/4/14
83940-01 DATA SHEET
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
83940DY-01LF
83940DY-01LFT
ICS83940D01L
ICS83940D01L
32 Lead “Lead-Free” LQFP
32 Lead “Lead-Free” LQFP
tray
reel
0°C to 70°C
0°C to 70°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS complaint.
REVISION A 11/4/14
13
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
83940-01 DATA SHEET
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
1
9
10
13
Added Lead-Free bullet.
Added Recommendations for Unused Input and Output Pins.
Updated LVPECL Clock Input Interface section.
T8
A
11/18/05
Added Lead-Free part number, marking and note.
Updated datasheet’s header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
A
A
T8
T
13
15
8/4/10
13
Removed Leaded devices
Updated Datasheet format
11/4/14
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
14
REVISION A 11/4/14
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