83947AYI-147LFT [IDT]
Low Skew, 1-to-9 LVCMOS/LVTTL Fanout Buffer;
| 型号： | 83947AYI-147LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew, 1-to-9 LVCMOS/LVTTL Fanout Buffer 驱动 逻辑集成电路 |
| 文件： | 总12页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-9
LVCMOS/LVTTL Fanout Buffer
83947I-147
Data Sheet
GENERAL DESCRIPTION
FEATURES
The 83947I-147 is a low skew, 1-to-9 LVCMOS/LVTTL
Fanout Buffer. The low impedance LVCMOS/LVTTL outputs
are designed to drive 50 series or parallel terminated
transmission lines. The effective fanout can be increased from
9 to 18 by utilizing the ability of the outputs to drive two series
terminated lines.
• Nine LVCMOS/LVTTL outputs
• Selectable CLK0 and CLK1 can accept the following
input levels: LVCMOS and LVTTL
• Maximum output frequency: 250MHz
• Output skew: 115ps (maximum)
Guaranteed output and part-to-part skew characteristics make
the 83947I-147 ideal for high performance, 3.3V or 2.5V single
ended applications.
• Part-to-part skew: 500ps (maximum)
• Additive phase jitter, RMS: 0.02ps (typical) @ 3.3V
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
BLOCK DIAGRAM
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
GND
Q3
GND
CLK_SEL
CLK0
1
2
3
4
5
6
7
24
23
22
21
20
19
18
17
VDDO
Q4
CLK1
ICS83947I-147
GND
Q5
CLK_EN
OE
VDDO
GND
VDD
GND
8
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A March 18, 2016
83947I-147 Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Power
Input Pullup
Description
1, 8, 9, 12, 16, 17, 20,
24, 25, 29, 32
GND
Power supply ground.
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
2
CLK_SEL
3, 4
CLK0, CLK1
CLK_EN
OE
Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
Input Pullup Clock enable. LVCMOS / LVTTL interface levels.
Input Pullup Output enable. LVCMOS / LVTTL interface levels.
5
6
7
VDD
Power
Power
Core supply pin.
10, 14, 18, 22, 27, 31
VDDO
Output supply pins.
11, 13, 15, 19, 21, 23, Q8, Q7, Q6, Q5, Q4,
Q0 thru Q8 clock outputs.
LVCMOS / LVTTL interface levels.
Output
26, 28, 30
Q3, Q2, Q1, Q0
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
12
pF
RPULLUP
ROUT
Input Pullup Resistor
Output Impedance
51
7
KΩ
Ω
TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE
Control Inputs
Output
Q0:Q8
OE
0
CLK_EN
X
0
1
Hi-Z
1
LOW
1
Follows CLK input
©2016 Integrated Device Technology, Inc
2
Revision A March 18, 2016
83947I-147 Data Sheet
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute
Supply Voltage, V
4.6V
DD
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied.Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
Package Thermal Impedance, θ
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.0
Typical
3.3
Maximum Units
3.6
2.625
3.6
V
V
VDD
Core Supply Voltage
2.375
3.0
2.5
3.3
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
50
V
IDD
Input Supply Current
Output Supply Current
mA
mA
IDDO
9
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
CLK0, CLK1, OE,
CLK_SEL, CLK_EN
2
3.6
0.8
V
V
IIN
Input Current
-100
2.5
µA
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
IOH = -20mA
IOL = 20mA
V
V
0.4
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section, 3.3V Output Load Test
Circuit Diagram.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
Input High Voltage
2
VDD + 0.3
1.3
V
V
V
CLK0, CLK1
-0.3
-0.3
VIL
Input Low Voltage
Input High Current
Input Low Current
CLK_SEL, CLK_EN, OE
0.8
CLK0, CLK1, OE, CLK_
SEL, CLK_EN
IIH
IIL
VDD = VIN = 2.625V
5
µA
µA
CLK0, CLK1, OE, CLK_
SEL, CLK_EN
VDD = 32.625V,
VIN = 0V
-150
1.8
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section, 2.5V Output Load Test
Circuit Diagram.
©2016 Integrated Device Technology, Inc
3
Revision A March 18, 2016
83947I-147 Data Sheet
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum
Units
MHz
ns
250
4.2
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 5
f ≤ 250MHZ
Measured on
rising edge @VDDO/2
2
tsk(o)
115
500
ps
ps
Measured on
rising edge @VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
tjit(Ø)
(12KHz to 20MHz)
ps
0.2
tR / tF
tPW
odc
tEN
Output Rise/Fall Time
0.8V to 2.0V
f > 133MHz
f ≤ 133MHz
0.2
tPeriod/2 - 1
40
1
tPeriod/2 + 1
60
ns
ns
ꢀ
Output Pulse Width
Output Duty Cycle
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
Clock Enable Setup Time
Clock Enable Hold Time
10
ns
ns
ns
ns
tDIS
tS
10
0
1
tS
All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum
250
Units
MHz
ns
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 5
f ≤ 250MHZ
Measured on
rising edge @VDDO/2
2.4
4.5
tsk(o)
130
600
ps
ps
Measured on
rising edge @VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
tjit(Ø)
(12KHz to 20MHz)
20ꢀ - 80ꢀ
0.1
ps
tR / tF
tPW
tEN
tDIS
tS
Output Rise/Fall Time
300
800
tPeriod/2 + 1.2
10
ps
ns
ns
ns
ns
ns
Output Pulse Width
tPeriod/2 - 1.2
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
Clock Enable Setup Time
Clock Enable Hold Time
10
0
1
tS
All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
4
Revision A March 18, 2016
83947I-147 Data Sheet
ADDITIVE PHASE JITTER
1Hz band to the power in the fundamental. When the required
The spectral purity in a band at a specific offset from the fun-
offset is specified, the phase noise is called a dBc value, which
simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
damental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using
a Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in the
0
-10
-20
-30
-40
-50
-60
-70
-80
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz)
= 0.02ps typical @ 3.3V
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
0
-10
-20
-30
-40
-50
-60
-70
-80
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz)
= 0.01ps typical @ 2.5V
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements device meets the noise floor of what is shown, but can actually
have issues. The primary issue relates to the limitations of the be lower.The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher measurement equipment.
than the noise floor of the device. This is illustrated above. The
©2016 Integrated Device Technology, Inc
5
Revision A March 18, 2016
83947I-147 Data Sheet
PARAMETER MEASUREMENT INFORMATION
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
3.3V OUTPUT RISE/FALL TIME
2.5V OUTPUT RISE/FALL TIME
©2016 Integrated Device Technology, Inc
6
Revision A March 18, 2016
83947I-147 Data Sheet
APPLICATION SCHEMATIC EXAMPLE
Figure 1 shows an example of 83947I-147 application sche- For the LVCMOS output drivers, only one termination example
matic. In this example, the device is operated at VCC=3.3V. The is shown in this schematic. Additional termination approaches
decoupling capacitors should be located as close as possible are shown in the LVCMOS Termination Application Note (refer
to the power pin.The input is driven by a 3.3V LVCMOS driver. to ICS website).
VDDO
R1
43
Zo = 50
VCC
R3
43
Zo = 50 Ohm
U1
ICS83947I-147
LVCMOS
1
2
3
4
5
6
7
8
24
GND
GND
23
CLK_SEL
CLK0
CLK1
CLK_EN
OE
Q3
22
VCC
VDDO
21
Q4
20
GND
19
Q5
18
R3
43
Zo = 50 Ohm
VDD
GND
VDDO
17
GND
VDD
LVCMOS
C5
0.1u
VDD=3.3V
VDDO=3.3V
VDDO
(U1-10) (U1-14)
(U1-18)
(U1-22)
(U1-27)
(U1-31)
R2
43
Zo = 50
C1
0.1u
C2
0.1u
C3
0.1u
C4
0.1u
C2
0.1u
C3
0.1u
FIGURE 1. 83947I-147 SCHEMATIC LAYOUT
©2016 Integrated Device Technology, Inc
7
Revision A March 18, 2016
83947I-147 Data Sheet
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θ
JA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
500
50.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 83947I-147 is: 1040
©2016 Integrated Device Technology, Inc
8
Revision A March 18, 2016
83947I-147 Data Sheet
PACKAGE OUTLINE -Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0°
0.75
7°
--
θ
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
©2016 Integrated Device Technology, Inc
9
Revision A March 18, 2016
83947I-147 Data Sheet
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Tray
Temperature
-40°C to 85°C
-40°C to 85°C
83947AYI-147LF
ICS947AI147L
ICS947AI147L
Lead-Free, 32 Lead LQFP
Lead-Free, 32 Lead LQFP
83947AYI-147LFT
Tape & Reel
©2016 Integrated Device Technology, Inc
10
Revision A March 18, 2016
83947I-147 Data Sheet
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
Updated datasheet’s header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
A
T8
10
12
8/12/10
Ordering Information Table - added lead-free ordering information.
Deleted non lead-free ordering information. Deleted tape & reel count.
A
A
T8
10
2/27/13
3/18/16
Removed ICS from part numbers where needed.
Updated header and footer.
©2016 Integrated Device Technology, Inc
11
Revision A March 18, 2016
83947I-147 Data Sheet
Tech Support
www.idt.com/go/support
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
Sales
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and
operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided
without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe-
ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect-
ed to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or
their respective third party owners.
For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.
Copyright ©2016 Integrated Device Technology, Inc. All rights reserved.
相关型号：
83947AYI-147T
Clock Driver, 83947 Series, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
IDT
83947AYIT
Low Skew Clock Driver, 83947 Series, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32
IDT
83948AYI-01
Clock Driver, 83948 Series, 12 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32
IDT
83948AYI-147
Low Skew Clock Driver, 83948 Series, 12 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026ABC-HD, LQFP-32
IDT
83948AYI-147T
Low Skew Clock Driver, 83948 Series, 12 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026ABC-HD, LQFP-32
IDT
©2020 ICPDF网 联系我们和版权申明