83940AY-02T [IDT]
Low Skew Clock Driver, 83940 Series, 18 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32;
| 型号： | 83940AY-02T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 83940 Series, 18 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总15页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
GENERAL DESCRIPTION
FEATURES
The ICS83940-02 is a low skew, 1-to-18 Fanout Buffer .The
83940-02 has two selectable clock inputs. The CLK0,
nCLK0 pair can accept most standard differential input
levels. The single ended clock input accepts LVCMOS or
LVTTL input levels. The low impedance LVCMOS/LVTTL
outputs are designed to drive 50Ω series or parallel
terminated transmission lines. The effective fanout can be
increased from 18 to 36 by utilizing the ability of the
outputs to drive two series terminated lines.
• 18 LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable LVCMOS_Clock or CLK0, nCLK0 input pair
• LVCMOS_CLK supports the following input types:
LVCMOS or LVTTL
• CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 200MHz
• Output skew: 120ps (maximum)
• Part-to-part skew: 850ps (maximum)
The ICS83940-02 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS83940 ideal for those clock distribution
applications demanding well defined performance and
repeatability.
• Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• NOT RECOMMENDED FOR NEW DESIGNS
For New Designs Use: ICS83940D
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
CLK0
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q6
Q7
Q8
GND
GND
0
nCLK0
Q0:Q17
LVCMOS_CLK
CLK_SEL
CLK
1
LVCMOS_CLK
V
DDO
Q9
Q10
Q11
GND
nCLK
V
DD
VDDO
9
10 11 12 13 14 15 16
32-Lead LQFP
Y Pacakge
7mm x 7mm x 1.4mm package body
TopView
83940AY-02
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REV. A MAY 21, 2013
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ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
TABLE 1. PIN DESCRIPTIONS
Number
1, 2, 12, 17, 25
3
Name
GND
Type
Description
Power
Output supply ground.
LVCMOS_CLK
Input Pulldown Clock input. LVCMOS/LVTTL interface levels.
Clock select input. Selects LVCMOS clock input
Input Pulldown when HIGH. Selects CLK0, nCLK0 inputs when
LOW. LVCMOS/LVTTL itnerface levels.
4
CLK_SEL
5
CLK0
nCLK0
VDD
Input Pulldown Non-inverting differential clock input.
6
Input
Power
Power
Pullup Inverting differential clock input
Core supply pin.
7
8, 16, 21, 29
VDDO
Output supply pins.
9, 10, 11, 13, 14, Q17, Q16, Q15, Q14, Q13,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Clock outputs. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
Output
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
pF
pF
KΩ
KΩ
Ω
VDD, VDDO = 3.465V
VDD = 3.465V, VDDO = 2.625V
VDD, VDDO = 2.625V
12
18
18
51
51
7
Power Dissipation Capacitance
(per output)
CPD
RPULLUP
RPULLDOWN
ROUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
5
12
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
CLK0, nCLK0
LVCMOS_CLK
De-selected
Selected
0
1
Selected
De-selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Q0:Q17
LOW
Input to Output Mode
Polarity
CLK_SEL LVCMOS_CLK
CLK0
nCLK0
0
0
0
0
0
0
1
1
—
—
—
—
—
—
0
0
1
Differential to Single Ended
Differential to Single Ended
Non Inverting
Non Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
Biased; NOTE 1
HIGH
HIGH
LOW
Biased; NOTE 1
0
1
Single Ended to Single Ended
Single Ended to Single Ended
Inverting
Inverting
Biased; NOTE 1
—
—
—
—
LOW
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
HIGH
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
83940AY-02
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ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ OR 2.5V 5ꢀ, VDDO = 3V 5ꢀ OR 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter Test Conditions Minimum Typical Maximum Units
3.135
2.375
3.135
2.375
3.3
2.5
3.3
2.5
3.465
2.625
3.465
2.625
25
V
V
VDD
Core Supply Voltage
V
VDDO
Output Supply Voltage
V
IDD
Power Supply Current
Output Supply Current
mA
mA
IDDO
25
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = 3.3V 5ꢀ OR 2.5V 5ꢀ, VDDO = 3V 5ꢀ OR 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
LVCMOS_CLK
CLK_SEL
VIH
VIL
Input High Voltage
2
VDD + 0.3
V
Input Low Voltage
LVCMOS_CLK
CLK_SEL
-0.3
-0.3
1.3
0.8
V
V
V
DD = VIN = 3.465V or
2.625V
LVCMOS_CLK,
CLK_SEL
IIH
IIL
Input High Current
Input Low Current
150
µA
µA
LVCMOS_CLK,
CLK_SEL
VDD = 3.465V or 2.625V,
VIN = 0V
-5
V
DDO = 3.465V
2.4
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDDO = 2.625V
VDDO = 3.465V or 2.625V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See 3.3V Output Load Test Circuit Diagram.
83940AY-02
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REV. A MAY 21, 2013
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ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ OR 2.5V 5ꢀ, VDDO = 3V 5ꢀ OR 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum Typical Maximum Units
CLK0
V
DD = VIN = 3.465V or 2.625V
150
5
µA
µA
nCLK0
VDD = VIN = 3.465V or 2.625V
V
DD = 3.465V or 2.625V,
IN = 0V
CLK0
-5
µA
µA
V
IIL
Input Low Current
VDD = 3.465V or 2.625V,
VIN = 0V
nCLK0
-150
VPP
Peak-to-Peak Input Voltage
0.15
1.3
V
V
Input Common Mode Voltage;
NOTE 1, 2
VCMR
GND + 0.5
V
DD - 0.85
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
tpHL
tsk(o)
tsk(pp)
tR
Output Frequency
200
3.5
MHz
ns
ns
ps
ps
ns
ns
ꢀ
Propagation Delay; NOTE 1
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
2
2
3.5
120
850
1050
1050
55
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
f ≤ 133MHz
350
350
45
tF
Output Fall Time
odc
Output Duty Cycle
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages,
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83940AY-02
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REV. A MAY 21, 2013
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ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ; VDDO = 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
tpHL
tsk(o)
tsk(pp)
tR
Output Frequency
200
3.5
MHz
ns
ns
ps
ps
ns
ns
ꢀ
Propagation Delay; NOTE 1
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
2
2
3.5
120
850
1050
1050
55
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
f ≤ 133MHz
350
350
45
tF
Output Fall Time
odc
Output Duty Cycle
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages,
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
tpHL
tsk(o)
tsk(pp)
tR
Output Frequency
200
3.5
MHz
ns
ns
ps
ps
ns
ns
ꢀ
Propagation Delay; NOTE 1
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
2
2
3.5
120
850
1050
1050
60
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
f ≤ 133MHz
350
350
40
tF
Output Fall Time
odc
Output Duty Cycle
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages,
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83940AY-02
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REV. A MAY 21, 2013
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ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
VDD
VDDO
,
VDD
VDDO
,
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.05V 5ꢀ 1.25V 5ꢀ
VDD
SCOPE
nCLK0
VDD
VPP
VCMR
Cross Points
VDDO
Qx
CLK0
GND
LVCMOS
GND
-1.25V 5ꢀ
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
VDDx
VDDx
Qx
2
Qx
2
PART 2
VDDx
VDDx
Qy
Qy
2
2
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
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ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
VDD
2
LVCMOS_CLK
nCLK0
CLK0
80ꢀ
tF
80ꢀ
tR
20ꢀ
20ꢀ
Clock
Outputs
VDDO
2
Q0:Q17
➤
tPD
➤
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
VDDO
2
Q0:Q17
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
83940AY-02
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REV. A MAY 21, 2013
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ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
83940AY-02
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ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL examples only. Please consult with the vendor of the driver
and other differential signals. Both VSWING and VOH must meet
the VPP and VCMR input requirements. Figures 2A to 2E show
component to confirm the driver termination requirements. For
example in Figure 2A, the input termination applies for LVHSTL
interface examples for the CLK/nCLK input driven by the most drivers. If you are using an LVHSTL driver from another
common driver types. The input interfaces suggested here are vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 2A. CLK/nCLK INPUT DRIVEN BY
LVHSTL DRIVER
FIGURE 2B. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
LVPECL
R1
84
R2
84
FIGURE 2C. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
R4
125
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
R6
100 - 200
R1
84
R2
84
100 - 200
R5,R6 locate near the driver pin.
FIGURE 2E. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
83940AY-02
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REV. A MAY 21, 2013
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ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
APPLICATION SCHEMATIC EXAMPLE
input signals. In this example, this input is driven by a 3.3V
LVPECL driver.For the LVCMOS output, a termination example
is shown in this schematic. For more termination approaches,
please refer to the LVCMOS Termination Application Note.
Figure 3 shows an example of ICS83940-02 application sche-
matic. In this example, the device is operated at VCC=3.3V.The
decoupling capacitor should be located as close as possible to
the power pin.The differential input can accept different type of
VDDO
R1
43
Zo = 50
VCC
Q3
R3
43
Zo = 50 Ohm
LVCMOS
U1
VCC
1
24
23
22
21
20
19
18
17
GND
Q6
Q7
2
3
4
5
6
7
8
GND
LVCMOS_CLK
CLK_SEL
CLK
Q8
Zo = 50 Ohm
Zo = 50 Ohm
VDDO
Q9
nCLK
Q10
Q11
GND
VDD
VDDO
3.3V LVPECL
VDD
R4
50
R5
50
ICS83940-02
C5
0.1u
R6
50
C8 (Option)
0.1u
VDDO
R2
43
Zo = 50
(U1-16)
(U1-21)
(U1-29)
VDD=3.3V
(U1-8)
VDDO=3.3V
C1
C2
C3
C4
0.1u
0.1u
0.1u
0.1u
FIGURE 3. APPLICATION SCHEMATIC EXAMPLE
83940AY-02
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REV. A MAY 21, 2013
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ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83940-02 is: 4270
83940AY-02
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REV. A MAY 21, 2013
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ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
REFERENCE DOCUMENT:JEDEC PUBLICATION 95, MS-026
83940AY-02
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REV. A MAY 21, 2013
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ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
TABLE 8. ORDERING INFORMATION
Part/Order Number
83940AY-02
Marking
Package
Shipping Packaging
tray
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS83940AY-02
ICS83940AY-02
ICS3940AY02L
ICS3940AY02L
32 Lead LQFP
83940AY-02T
32 Lead LQFP
1000 Tape and Reel
tray
83940AY-02LF
83940AY-02LFT
32 Lead LQFP Lead Free
32 Lead LQFP Lead Free
1000 Tape and Reel
NOTE: Parts that are ordered with an ""LF"" suffix to the part number are the Pb-Free configuration and are RoHS
compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated DeviceTechnology, Inc.(IDT) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications.Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
83940AY-02
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REV. A MAY 21, 2013
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ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
A
T8
13
Ordering Information Table - Added Lead Free Marking and Note
7/30/07
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NRND - Not Recommended For New Designs
Use Replacement Part 83940D
A
A
T8
13
15
8/4/10
1
5/21/13
83940AY-02
www.idt.com
REV. A MAY 21, 2013
14
ICS83940-02
NRND
Low Skew, 1-to-18 Differential-to-
LVCMOS/LVTTL Fanout Buffer
NOT RECOMMENDED FOR NEW DESIGNS
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information
in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express
or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document
is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
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their respective third party owners.
Copyright 2013. All rights reserved.
83940AY-02
www.idt.com
REV. A MAY 21, 2013
15
相关型号：
83940BY
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83940BYT
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