83940BY [IDT]
Low Skew Clock Driver, 83940 Series, 18 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32;
| 型号： | 83940BY |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 83940 Series, 18 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总13页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83940
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
GENERAL DESCRIPTION
FEATURES
The ICS83940 is a low skew, 1-to-18 LVPECL-to-LVCMOS/
LVTTL Fanout Buffer. The ICS83940 has twoselectable
clock inputs. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The LVCMOS_CLK can accept
LVCMOS or LVTTL input levels. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50Ω series
or parallel terminated transmission lines.
• Eighteen LVCMOS/LVTTL outputs, 16Ω typical output
impedance
• Selectable LVCMOS_CLK or LVPECL clock inputs
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
The ICS83940 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS83940 ideal for those clock distribution
applications demanding well defined performance and
repeatability.
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Part to part skew: 750ps (maximum)
• Full 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Lead-Free package fully RoHS compliant
• For New Designs Use: 83940DYLF or 83940DYILF
BLOCK DIAGRAM
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
CLK_SEL
Q6
Q7
Q8
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
GND
PCLK
0
nPCLK
18
Q0:Q17
LVCMOS_CLK
CLK_SEL
PCLK
1
LVCMOS_CLK
V
DD
Q9
Q10
Q11
GND
nPCLK
VDD
V
DDO
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Pacakge
Top View
83940BY
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REV. B JANUARY 31, 2014
1
ICS83940
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
TABLE 1. PIN DESCRIPTIONS
Number
1, 2, 12, 17, 25
3
Name
GND
Type
Description
Power
Power supply ground.
LVCMOS_CLK
Input Pulldown Clock input. LVCMOS / LVTTL interface levels.
Clock select input. Selects LVCMOS / LVTTL clock
Input Pulldown input when HIGH. Selects PCLK, nPCLK inputs
when LOW. LVCMOS / LVTTL interface levels.
4
CLK_SEL
5
6
PCLK
nPCLK
VDD
Input Pulldown Non-inverting differential LVPECL clock input.
Input
Power
Power
Pullup Inverting differential LVPECL clock input.
Core supply pins.
7, 21
8, 16, 29
VDDO
Output supply pins.
9, 10, 11, 13, 14, Q17, Q16, Q15, Q14, Q13,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Clock outputs. 16Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
pF
KΩ
KΩ
Ω
V
DD, VDDO = 3.47
13
11
51
51
16
Power Dissipation Capacitance
(per output)
CPD
V
DD, VDDO = 2.625
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
11
21
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
PCLK, nPCLK
LVCMOS_CLK
De-selected
Selected
0
1
Selected
De-selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Q0:Q17
LOW
Input to Output Mode
Polarity
CLK_SEL LVCMOS_CLK
PCLK
nPCLK
0
0
—
—
0
1
1
0
Differential to Single Ended
Differential to Single Ended
Non Inverting
Non Inverting
HIGH
Biased;
NOTE 1
Biased;
NOTE 1
0
0
—
—
0
1
LOW
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
HIGH
0
0
1
1
—
—
0
Biased; NOTE 1
0
1
HIGH
LOW
LOW
HIGH
Single Ended to Single Ended
Single Ended to Single Ended
Inverting
Inverting
Biased; NOTE 1
—
—
—
—
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
NOTE 1: Please refer to the Application Information section. "Wiring the Differential Input to Accept Single Ended Levels".
83940BY
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REV. B JANUARY 31, 2014
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ICS83940
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0° TO 70°
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
25
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
mA
mA
IDDO
25
TABLE 4B. DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
2.4
VDD
0.8
V
V
Input Low Voltage
Peak-to-Peak
Input Voltage
Input Common Mode
Voltage; NOTE 1, 2
VPP
PCLK, nPCLK
PCLK, nPCLK
300
mV
V
VCMR
GND + 1.5
VDD
IIN
Input Current
200
µA
V
VOH
VOL
Output High Voltage
Output Low Voltage
IOH = -20mA
IOL = 20mA
2.4
0.5
V
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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ICS83940
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
250
MHz
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
2
3.4
ns
Propagation Delay;
tpLH
2.6
2
3.8
3.7
4
ns
ns
ns
Propagation Delay;
tpLH
2.6
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
150
150
1.4
1.2
1.7
1.4
850
750
1.2
1.2
55
ps
ps
ns
ns
ns
ns
ps
ps
ns
ns
ꢀ
Output Skew;
NOTE 3, 5
Measured on rising edge
@VDDO/2
tsk(o)
f < 150MHz
f < 150MHz
f > 150MHz
f > 150MHz
Part-to-Part Skew;
NOTE 6
tsk(pp)
tsk(pp)
tsk(pp)
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 4, 5
Measured on rising edge
@VDDO/2
tR
Output Rise Time
Output Fall Time
Output Duty Cycle
0.5 to 2.4V
0.5 to 2.4V
f < 134MHz
0.3
0.3
45
tF
odc
50
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages,
same temperature, and with equal load conditions. Using the same type of inputs on each device, the
outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDDO/2.
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
2.375
2.375
2.5
2.5
2.625
2.625
25
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
mA
mA
IDDO
25
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ICS83940
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
TABLE 4D. DC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
2
VDD
0.8
V
V
Input Low Voltage
Peak-to-Peak
Input Voltage
Input Common Mode
Voltage; NOTE 1, 2
VPP
PCLK, nPCLK
PCLK, nPCLK
300
mV
V
VCMR
GND + 1.5
VDD
IIN
Input Current
200
µA
V
VOH
VOL
Output High Voltage
Output Low Voltage
IOH = -12mA
IOL = 12mA
1.8
0.5
V
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
200
MHz
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
2
4.6
ns
Propagation Delay;
tpLH
2.7
2.2
2.7
4.4
4.4
4.4
ns
ns
ns
Propagation Delay;
tpLH
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
200
200
2.6
1.7
2.2
1.7
1.2
1.0
1.2
1.2
55
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ
Output Skew;
NOTE 3, 5
Measured on rising edge
@VDDO/2
tsk(o)
f < 150MHz
f < 150MHz
f > 150MHz
f > 150MHz
Part-to-Part Skew;
NOTE 6
tsk(pp)
tsk(pp)
tsk(pp)
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 4, 5
Measured on rising edge
@VDDO/2
tR
Output Rise Time
Output Fall Time
Output Duty Cycle
0.5 to 1.8V
0.5 to 1.8V
f < 134MHz
0.3
0.3
45
tF
odc
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages,
same temperature, and with equal load conditions. Using the same type of inputs on each device, the
outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDDO/2.
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ICS83940
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
PARAMETER MEASUREMENT INFORMATION
1.25V 5ꢀ
1.65V 5ꢀ
SCOPE
SCOPE
VDD
VDDx
,
VDD,
VDDx
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD
VDDx
Qx
2
nPCLK
VPP
VCMR
Cross Points
VDDx
PCLK
Qy
2
tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
PART 1
VDDx
2.4V
2.4V
Qx
2
0.5V
0.5V
Clock
Outputs
PART 2
Qy
VDDx
2
tR
tF
tsk(pp)
PART-TO-PART SKEW
3.3V OUTPUT RISE/FALL TIME
VDD
2
LVCMOS_CLK
nPCLK
PCLK
1.8V
tF
1.8V
0.5V
0.5V
Clock
tR
Outputs
VDDx
2
Q0:Q17
➤
tPD
➤
2.5V OUTPUT RISE/FALL TIME
PROPAGATION DELAY
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ICS83940
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
VDD
R1
1K
Single Ended Clock Input
V_REF
PCLK
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS83940
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other are examples only. If the driver is from another vendor, use
differential signals. Both VSWING and VOH must meet the VPP their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver
termination requirements.
and VCMR input requirements. Figures 2A to 2E show interface
examples for the PCLK/nPCLK input driven by the most
common driver types. The input interfaces suggested here
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
R1
120
R2
120
PCLK/nPCLK
FIGURE 2A. PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 2B. PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
R4
Zo = 50 Ohm
R3
1K
R4
1K
125
125
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
LVDS
PCLK
PCLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 2C. PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2D. PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 2E. PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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ICS83940
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83940 is: 820
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ICS83940
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
REFERENCE DOCUMENT:JEDEC PUBLICATION 95, MS-026
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ICS83940
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
TABLE 8. ORDERING INFORMATION
Part/Order Number
83940BY
Marking
Package
Shipping Packaging
Tray
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS83940BY
ICS83940BY
ICS83940BYLF
ICS83940BYLF
32 Lead LQFP
83940BYT
32 Lead LQFP
1000 Tape & Reel
Tray
83940BYLF
83940BYLFT
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP
1000 Tape & Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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ICS83940
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
A
T2
2
1
2
CPD Value changed from 10pF to 13pF for 3.47V and added 11pF for 2.625V
In Features section, first bullet changed Output Impedance from 23Ω to 16Ω.
T1 Pin Description, changed Q outputs description from 23Ω to 16Ω output
impedanace.
Updated format.
4/25/02
5/23/02
12/12/02
A
A
T5A
4
7
3V AC Characteristics - corrected Part-to-Part Skew (f<150MHz) unit from
ps to ns.
Updated Single Ended Signal Driving Differential Input diagram.
A
3/17/04
8
1
11
Added LVPECL Input Interface section.
Features Section - added Lead-Free bullet.
Ordering Information Table - added Lead-Free part number.
Updated datasheet's header/footer with IDT from ICS.
Removed "ICS" prefix from Part/Order Number column.
Added Contact Page.
A
A
12/14/04
11/17/10
T8
T8
11
13
1
Not Recommended For New Designs
For new designs use 83940D
A
B
5/21/13
1/31/14
Product Discontinuation Notice - Last time buy expires January 27, 2015,
PDN# CQ-14-02
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12
ICS83940
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
We’ve Got Your Timing Solution.
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information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described
products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation
or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement
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Copyright 2013. All rights reserved.
83940BY
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REV. B JANUARY 31, 2014
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