83904AGI-02 [IDT]
Clock Generator, PDSO16;
| 型号： | 83904AGI-02 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO16 光电二极管 外围集成电路 |
| 文件： | 总15页 (文件大小：748K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW, 1-TO-4, CRYSTAL-TO-
LVCMOS/LVTTL FANOUT BUFFER
ICS83904I-02
GENERAL DESCRIPTION
FEATURES
The ICS83904I-02 is a low skew, high perfor-
• Four LVCMOS/LVTTL outputs,
ICS
mance 1-to-4 Crystal Oscillator/Crystal-to-LVCMOS
Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from IDT.
The ICS83904I-02 has selectable single-ended clock
19Ω typical output impedance @ VDD = VDDO = 3.3V
HiPerClockS™
• Two Crystal oscillator input pairs
One LVCMOS/LVTTL clock input
or two crystal-oscillator inputs. There is an output enable to
disable the outputs by placing them into a high-impedance state.
• Crystal input frequencry range: 12MHz – 38.88MHz
• Output frequency: 200MHz (maximum)
Guaranteed output and part-to-part skew characteristics
make the ICS83904I-02 ideal for those applications demand-
ing well defined performance and repeatability.
• Output Skew: 40ps (maximum) @ VDD = VDDO = 3.3V
• RMS phase jitter @ 25MHz output, using a 25MHz crystal
(100Hz – 1MHz): 0.16ps (typical) @ VDD = VDDO = 3.3V
• RMS phase noise at 25MHz:
Offset
Noise Power
100Hz ............. -118.4 dBc/Hz
1kHz ............. -141.5 dBc/Hz
10kHz ............. -157.2 dBc/Hz
100kHz ............. -157.2 dBc/Hz
• Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pullup
OE
Pulldown
CLK_SEL0
Pulldown
CLK_SEL1
PIN ASSIGNMENT
XTAL_IN0
OSC
Q0
Q1
Q2
Q3
1
0 0
CLK_SEL0
XTAL_OUT0
XTAL_IN0
VDD
XTAL_IN1
XTAL_OUT1
CLK_SEL1
CLK
16
15
14
13
12
11
10
9
VDDO
Q0
Q1
GND
Q2
Q3
2
3
4
5
6
7
8
XTAL_OUT0
VDDO
OE
XTAL_IN1
OSC
0 1
ICS83904I-02
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
XTAL_OUT1
Pulldown
1 0
1 1
CLK
G Package
Top View
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
CLK_SEL0,
CLK_SEL1
XTAL_OUT0,
XTAL_IN0
Clock select inputs. See Table 3, Input Reference Function Table.
LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN0 is the input.
XTAL_OUT0 is the output.
1, 7
Input Pulldown
2, 3
4
Input
Power
Input
VDD
Core supply pin.
XTAL_IN1,
XTAL_OUT1
Crystal oscillator interface. XTAL_IN1 is the input.
XTAL_OUT1 is the output.
5, 6
8
CLK
Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. When LOW, outputs are in HIGH impedance state.
9
OE
Input
Pullup
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
10, 16
VDDO
Power
Output supply pins.
11, 12, 14, 15 Q3, Q2, Q1, Q0 Output
13 GND Power
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
51
51
8
pF
kΩ
kΩ
pF
pF
pF
Ω
RPULLUP
RPULLDOWN Input Pulldown Resistor
VDDO = 3.465V
VDDO = 2.625V
VDDO = 2.0V
Power Dissipation Capacitance
(per output)
CPD
7
7
V
DDO = 3.3V
19
21
32
ROUT
Output Impedance
VDDO = 2.5V
VDDO = 1.8V
Ω
Ω
TABLE 3. INPUT REFERENCE FUNCTION TABLE
Control Inputs
Reference
CLK_SEL1
CLK_SEL0
0
0
1
1
0
1
0
1
XTAL0 (default)
XTAL1
CLK
CLK
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Supply Voltage, VDD
4.6V
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
100.3°C/W (0 mps)
-65°C to 150°C
I
Outputs, VO
Package Thermal Impedance, θ
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
Core Supply Voltage
3.135
3.135
3.3
3.3
3.465
V
VDDO
Output Supply Voltage
Power Supply Current
Output Supply Current
3.465
V
No Load & XTALx selected @ 12MHz
No Load & CLK selected
7
1
1
mA
mA
mA
IDD
IDDO
No Load & CLK selected
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
Core Supply Voltage
3.135
2.375
3.3
2.5
3.465
V
VDDO
Output Supply Voltage
Power Supply Current
Output Supply Current
2.625
V
No Load & XTALx selected @ 12MHz
No Load & CLK selected
7
1
1
mA
mA
mA
IDD
IDDO
No Load & CLK selected
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
Core Supply Voltage
3.135
1.6
3.3
1.8
3.465
V
VDDO
Output Supply Voltage
Power Supply Current
Output Supply Current
2.0
7
V
No Load & XTALx selected @ 12MHz
No Load & CLK selected
mA
mA
mA
IDD
1
IDDO
No Load & CLK selected
1
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
Core Supply Voltage
2.375
2.375
2.5
2.5
2.625
V
VDDO
Output Supply Voltage
Power Supply Current
Output Supply Current
2.625
V
No Load & XTALx selected @ 12MHz
No Load & CLK selected
3
1
1
mA
mA
mA
IDD
IDDO
No Load & CLK selected
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
Core Supply Voltage
2.375
1.6
2.5
1.8
2.625
V
VDDO
Output Supply Voltage
Power Supply Current
Output Supply Current
2.0
3
V
No Load & XTALx selected @ 12MHz
No Load & CLK selected
mA
mA
mA
IDD
1
IDDO
No Load & CLK selected
1
TABLE 4F. DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD = 3.3V 5ꢀ
VDD = 2.5V 5ꢀ
VDD = 3.3V 5ꢀ
VDD = 2.5V 5ꢀ
2.2
1.6
VDD + 0.3
VDD + 0.3
1.3
V
V
V
V
VIH
VIL
Input High Voltage
Input Low Voltage
-0.3
-0.3
0.9
CLK,
CLK_SEL0:1
V
DD = 3.3V or 2.5V 5ꢀ
VDD = 3.3V or 2.5V 5ꢀ
DD = 3.3V or 2.5V 5ꢀ
150
5
µA
µA
µA
IIH
Input High Current
Input Low Current
OE
CLK,
CLK_SEL0:1
V
-5
IIL
OE
VDD = 3.3V or 2.5V 5ꢀ
VDDO = 3.3V 5ꢀ; NOTE 1
-150
2.6
µA
V
VOH
Output HighVoltage
Output Low Voltage
V
DDO = 2.5V 5ꢀ; NOTE 1
DDO = 1.8V 0.2V; NOTE 1
VDDO = 3.3V 5ꢀ; NOTE 1
DDO = 2.5V 5ꢀ; NOTE 1
DDO = 1.8V 0.2V; NOTE 1
1.8
V
V
1.2
V
0.6
0.5
0.4
V
VOL
V
V
V
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
12
38.88
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
w/external XTAL
w/external CLK
12
38.88
200
MHz
MHz
fMAX
tpLH
Output Frequency
Propagation Delay, Low-to-High;
1.4
1.9
2.4
ns
NOTE 1
tsk(o)
Output Skew; NOTE 2
40
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
700
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz – 1MHz
tjit(Ø)
0.16
ps
tR / tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
100
45
800
55
ps
ꢀ
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
ƒ< 150MHz
46
54
10
10
ꢀ
tEN
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
ns
ns
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
TABLE 6B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
w/external XTAL
w/external CLK
12
38.88
200
MHz
MHz
fMAX
tpLH
Output Frequency
Propagation Delay, Low-to-High;
1.5
2.0
2.5
ns
NOTE 1
tsk(o)
Output Skew; NOTE 2
40
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
700
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
tjit(Ø)
0.16
ps
tR / tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
100
45
800
55
ps
ꢀ
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
ƒ< 150MHz
46
54
10
10
ꢀ
tEN
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
ns
ns
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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TABLE 6C. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
w/external XTAL
w/external CLK
12
38.88
200
MHz
MHz
fMAX
tpLH
Output Frequency
Propagation Delay, Low-to-High;
1.7
2.2
2.7
ns
NOTE 1
tsk(o)
Output Skew; NOTE 2
40
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
700
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
tjit(Ø)
0.16
ps
tR / tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
100
45
1000
55
ps
ꢀ
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
ƒ< 150MHz
46
54
ꢀ
tEN
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
10
ns
ns
tDIS
10
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
TABLE 6D. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
w/external XTAL
w/external CLK
12
38.88
200
MHz
MHz
fMAX
tpLH
Output Frequency
Propagation Delay, Low-to-High;
1.5
2.2
3.0
ns
NOTE 1
tsk(o)
Output Skew; NOTE 2
40
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
700
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
tjit(Ø)
0.20
ps
tR / tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
100
45
800
55
ps
ꢀ
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
ƒ< 150MHz
48
52
ꢀ
tEN
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
10
10
ns
ns
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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TABLE 6E. AC CHARACTERISTICS, VDD = 2.5V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
w/external XTAL
w/external CLK
12
38.88
200
MHz
MHz
fMAX
tpLH
Output Frequency
Propagation Delay, Low-to-High;
1.7
2.5
3.3
ns
NOTE 1
tsk(o)
Output Skew; NOTE 2
40
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
700
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
tjit(Ø)
0.19
ps
tR / tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
100
45
1000
55
ps
ꢀ
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
ƒ< 150MHz
46
54
ꢀ
tEN
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
10
ns
ns
tDIS
10
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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TYPICAL PHASE NOISE AT 25MHZ
0
-10
-20
25MHz
RMS Phase Jitter (Random)
100Hz to 1MHz = 0.16ps (typical)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
Raw Phase Noise Data
-170
-180
-190
100
1k
10k
100k
1M
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
VDD,
VDDO
VDD,
VDDO
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.4V 0.065V
0.9V 0.1V
2.05V 5ꢀ
1.25V 5ꢀ
SCOPE
VDD
SCOPE
VDD
VDDO
VDDO
GND
Qx
Qx
GND
LVCMOS
LVCMOS
-1.25V 5ꢀ
-0.9V 0.1V
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
1.6V 0.025V
0.9V 0.1V
Part 1
Qx
VDDO
2
SCOPE
VDD
VDDO
Qx
Part 2
Qy
VDDO
GND
2
LVCMOS
tsk(pp)
-0.9V 0.1V
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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VDDO
Qx
2
VDD
2
VDD
2
CLK
VDDO
2
VDDO
2
VDDO
2
Qy
Q0:Q3
tpLH
tpHL
tsk(o)
PROPAGATION DELAY
OUTPUT SKEW
VDDO
2
Q0:Q3
tPW
80ꢀ
tF
80ꢀ
tR
tPERIOD
20ꢀ
20ꢀ
tPW
Clock
Outputs
x 100ꢀ
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
Figure 1 shows an example of ICS83904I-02 crystal interface
with a parallel resonant crystal. The frequency accuracy can be
fine tuned by adjusting the C1 and C2 values. For a parallel crystal
with loading capacitance CL = 18pF, we suggest C1 = 15pF and
C2 = 15pF to start with. These values may be slightly fine tuned
further to optimize the frequency accuracy for different board
layouts.Slightly increasing the C1 and C2 values will slightly reduce
the frequency.Slightly decreasing the C1 and C2 values will slightly
increase the frequency. For the oscillator circuit below, R1 can be
used, but is not required. For new designs, it is recommended
that R1 not be used.
XTAL_IN
C1
15p
X1
18pF Parallel Crystal
0
XTAL_OUT
C2
R1 (optional)
15p
FIGURE 1. Crystal Input Interface
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω.This can also be accomplished by removing
R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 2. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise.This configuration requires that the output
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 2. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUTS
OUTPUTS:
LVCMOS OUTPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
All unused LVCMOS output can be left floating. There should be
no trace attached.
CLK INPUT
For applications not requiring the use of the clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
SELECT PINS
All select pins have internal pull-ups and pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
12
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RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
100.3°C/W
96.0°C/W
93.9°C/W
TRANSISTOR COUNT
The transistor count for ICS83904I-02 is: 205
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS83904AGI-02
Marking
3904AI02
3904AI02
904AI02L
904AI02L
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
16 Lead TSSOP
ICS83904AGI-02T
ICS83904AGI-02LF
ICS83904AGI-02LFT
16 Lead TSSOP
2500 tape & reel
tube
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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ICS83904AGI-02 REV. A AUGUST 21, 2007
ICS83904I-02
LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
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