83905AG [IDT]
Low Skew, 1:6 Crystal-to- LVCMOS/LVTTL Fanout Buffer; 低偏移， 1 ： 6晶体用于─ LVCMOS / LVTTL扇出缓冲器
| 型号： | 83905AG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew, 1:6 Crystal-to- LVCMOS/LVTTL Fanout Buffer |
| 文件： | 总21页 (文件大小：961K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1:6 Crystal-to- LVCMOS/LVTTL
Fanout Buffer
ICS83905
DATA SHEET
General Description
Features
The ICS83905 is a low skew, 1-to-6 LVCMOS /
LVTTL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The low impedance
• Six LVCMOS / LVTTL outputs
S
IC
• Outputs able to drive 12 series terminated lines
• Crystal Oscillator Interface
HiPerClockS™
• Crystal input frequency range: 10MHz to 40MHz
• Output skew: 80ps (maximum)
LVCMOS/LVTTL outputs are designed to drive 50Ω
series or parallel terminated transmission lines. The effective
fanout can be increased from 6 to 12 by utilizing the ability of the
outputs to drive two series terminated lines.
• RMS phase jitter @ 25MHz, (100Hz – 1MHz): 0.26ps (typical),
VDD = VDDO = 2.5V
The ICS83905 is characterized at full 3.3V, 2.5V, and 1.8V, mixed
3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply
mode. Guaranteed output and part-to-part skew characteristics
along with the 1.8V output capabilities makes the ICS83905 ideal
for high performance, single ended applications that also require a
limited output voltage.
Offset
Noise Power
100Hz.................-129.7 dBc/Hz
1kHz...................-144.4 dBc/Hz
10kHz.................-147.3 dBc/Hz
100kHz...............-157.3 dBc/Hz
• 5V tolerant enable inputs
• Synchronous output enables
• Operating power supply modes:
Full 3.3V, 2.5V, 1.8V
Mixed 3.3V core/2.5V output operating supply
Mixed 3.3V core/1.8V output operating supply
Mixed 2.5V core/1.8V output operating supply
Pin Assignments
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
20
18 17 16
19
ICS83905
packages
GND
1
2
3
4
5
BCLK5
VDDO
15
14
13
12
11
20-Lead VFQFN
4mm x 4mm x 0.925mm
package body
K Package
GND
BCLK0
VDDO
BCLK4
GND
GND
BCLK1
Top View
6
7
8
9 10
Block Diagram
XTAL_IN
XTAL_OUT
ENABLE2
GND
1
2
3
4
5
6
7
8
16
15
14
BCLK0
ENABLE1
BCLK5
BCLK0
VDDO
BCLK1
GND
13 VDDO
12
BCLK1
BCLK2
BCLK3
BCLK4
BCLK5
BCLK4
XTAL_IN
11
10 BCLK3
VDD
GND
9
XTAL_OUT
BCLK2
ICS83905
16-Lead SOIC, 150 Mil
3.9mm x 9.9mm x 1.38mm package body
M Package
Top View
ENABLE 1
ENABLE 2
SYNCHRONIZE
SYNCHRONIZE
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
ICS83905AM REVISION B JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 1. Pin Descriptions
Name
XTAL_OUT
Type
Output
Input
Description
Crystal oscillator interface. XTAL_OUT is the output.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_IN
ENABLE1, ENABLE2
Input
Clock enable. LVCMOS/LVTTL interface levels. See Table 3.
BCLK0, BCLK1, BCLK2,
BCLK3, BCLK4, BCLK5
Output
Clock outputs. LVCMOS/LVTTL interface levels.
GND
VDD
VDDO
nc
Power
Power
Power
Unused
Power supply ground.
Power supply pin.
Output supply pin.
No connect.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
pF
pF
pF
Ω
CIN
Input Capacitance
4
VDDO = 3.465V
VDDO = 2.625V
19
18
16
Power Dissipation Capacitance
(per output)
CPD
VDDO = 2.0V
VDDO = 3.3V 5ꢀ
VDDO = 2.5V 5ꢀ
VDDO = 1.8V 0.2V
7
7
ROUT
Output Impedance
Ω
10
Ω
Function Table
Table 3. Clock Enable Function Table
Control Inputs
Outputs
ENABLE 1
ENABLE2
BCLK[0:4]
BCLK5
0
0
1
1
0
1
0
1
LOW
LOW
LOW
Toggling
LOW
Toggling
Toggling
Toggling
BCLK5
BCLK0:4
ENABLE2
ENABLE1
Figure 1. Enable Timing Diagram
ICS83905AM REVISION B JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO+ 0.5V
Outputs, VO
Package Thermal Impedance, θJA
16 Lead SOIC package
16 Lead TSSOP package
20 Lead VFQFN package
78.8°C/W (0 mps)
100.3°C/W (0 mps)
57.5°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
3.465
10
Units
V
VDD
VDDO
IDD
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
3.135
3.3
V
ENABLE [1:2] = 00
ENABLE [1:2] = 00
mA
mA
IDDO
5
Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V 5ꢀ, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
Units
V
VDD
VDDO
IDD
Power Supply Voltage
2.625
2.625
8
Output Supply Voltage
Power Supply Current
Output Supply Current
2.375
2.5
V
ENABLE [1:2] = 00
ENABLE [1:2] = 00
mA
mA
IDDO
4
Table 4C. Power Supply DC Characteristics, VDD = VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
1.6
Typical
1.8
Maximum
Units
V
VDD
VDDO
IDD
Power Supply Voltage
2.0
2.0
5
Output Supply Voltage
Power Supply Current
Output Supply Current
1.6
1.8
V
ENABLE [1:2] = 00
ENABLE [1:2] = 00
mA
mA
IDDO
3
ICS83905AM REVISION B JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 4D. Power Supply DC Characteristics, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
2.625
10
Units
V
VDD
VDDO
IDD
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
2.375
2.5
V
ENABLE [1:2] = 00
ENABLE [1:2] = 00
mA
mA
IDDO
4
Table 4E. Power Supply DC Characteristics, 3.3V 5ꢀ, VDDO = 1.8V 0.2Vꢀ, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
Units
V
VDD
VDDO
IDD
Power Supply Voltage
3.465
2.0
10
Output Supply Voltage
Power Supply Current
Output Supply Current
1.6
1.8
V
ENABLE [1:2] = 00
ENABLE [1:2] = 00
mA
mA
IDDO
3
Table 4F. Power Supply DC Characteristics, VDD = 2.5V 5ꢀ, VDDO = 1.8V 0.2Vꢀ, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
Units
V
VDD
VDDO
IDD
Power Supply Voltage
2.625
2.0
8
Output Supply Voltage
Power Supply Current
Output Supply Current
1.6
1.8
V
ENABLE [1:2] = 00
ENABLE [1:2] = 00
mA
mA
IDDO
3
ICS83905AM REVISION B JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 4G. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
DD = 3.3V 5ꢀ
VDD = 2.5V 5ꢀ
Minimum
2
Typical
Maximum
VDD + 0.3
VDD + 0.3
VDD + 0.3
0.8
Units
V
V
ENABLE1,
ENABLE2
VIH
Input High Voltage
1.7
V
V
DD = 1.8V 0.2V
VDD = 3.3V 5ꢀ
0.65 * VDD
-0.3
V
V
ENABLE1,
ENABLE2
VIL
Input Low Voltage
VDD = 2.5V 5ꢀ
-0.3
0.7
V
VDD = 1.8V 0.2V
-0.3
0.35 * VDD
V
VDDO = 3.3V 5ꢀ% NOTE 1
DDO = 2.5V 5ꢀ% IOH = -1mA
2.6
V
V
2.0
V
VOH
Output High Voltage
VDDO = 2.5V 5ꢀ% NOTE 1
VDDO = 1.8V 0.2V% NOTE 1
VDDO = 3.3V 5ꢀ% NOTE 1
VDDO = 2.5V 5ꢀ% IOL = 1mA
VDDO = 2.5V 5ꢀ% NOTE 1
1.8
V
VDDO - 0.3
0.5
0.4
V
V
V
VOL
Output Low Voltage% NOTE 1
0.45
0.35
V
DDO = 1.8V 0.2V% NOTE 1
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Frequency
Fundamental
10
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
ICS83905AM REVISION B JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
AC Electrical Characteristics
Table 6A. AC Characteristics, VDD = VDDO = 3.3V 5ꢀ,TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum
Units
Using External Crystal
10
40
MHz
fMAX
Output Frequency
Using External Clock
Source NOTE 1
DC
100
MHz
ps
tsk(o)
Output Skew% NOTE 2, 3
80
25MHz, Integration Range:
100Hz – 1MHz
tjit(Ø)
RMS Phase Jitter (Random)% NOTE 4
0.13
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
200
48
800
52
4
ps
ꢀ
ENABLE1
ENABLE2
ENABLE1
ENABLE2
cycles
cycles
cycles
cycles
Output Enable
Time% NOTE 5
tEN
4
4
Output Disable
Time% NOTE 5
tDIS
4
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: See phase noise plot.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
Table 6B. AC Characteristics, VDD = VDDO = 2.5V 5ꢀ,TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Using External Crystal
10
40
MHz
fMAX
Output Frequency
Using External Clock
Source NOTE 1
DC
100
80
MHz
ps
tsk(o)
Output Skew% NOTE 2, 3
25MHz, Integration Range:
100Hz – 1MHz
tjit
RMS Phase Jitter (Random)% NOTE 4
0.26
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
200
47
800
53
4
ps
ꢀ
ENABLE1
ENABLE2
ENABLE1
ENABLE2
cycles
cycles
cycles
cycles
Output Enable
Time% NOTE 5
tEN
4
4
Output Disable
Time% NOTE 5
tDIS
4
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: See phase noise plot.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
ICS83905AM REVISION B JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 6C. AC Characteristics, VDD = VDDO = 1.8V 0.2V,TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Using External Crystal
10
40
MHz
fMAX
Output Frequency
Using External Clock
Source NOTE 1
DC
100
80
MHz
ps
tsk(o)
Output Skew% NOTE 2, 3
25MHz, Integration Range:
100Hz – 1MHz
tjit(Ø)
RMS Phase Jitter (Random)
0.27
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
200
47
900
53
4
ps
ꢀ
ENABLE1
cycles
cycles
cycles
cycles
Output Enable
Time% NOTE 4
tEN
ENABLE2
ENABLE1
ENABLE2
4
4
Output Disable
Time% NOTE 4
tDIS
4
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65..
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
Table 6D. AC Characteristics, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ,TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Using External Crystal
10
40
MHz
fMAX
Output Frequency
Using External Clock
Source NOTE 1
DC
100
80
MHz
ps
tsk(o)
Output Skew% NOTE 2, 3
25MHz, Integration Range:
100Hz – 1MHz
tjit
RMS Phase Jitter (Random)
0.14
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
48
52
800
4
ps
200
ꢀ
ENABLE1
cycles
cycles
cycles
cycles
Output Enable
Time% NOTE 4
tEN
ENABLE2
ENABLE1
ENABLE2
4
4
Output Disable
Time% NOTE 4
tDIS
4
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
ICS83905AM REVISION B JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 6E. AC Characteristics, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V,TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Using External Crystal
10
40
MHz
fMAX
Output Frequency
Using External Clock
Source NOTE 1
DC
100
80
MHz
ps
tsk(o)
Output Skew% NOTE 2, 3
25MHz, Integration Range:
100Hz – 1MHz
tjit
RMS Phase Jitter (Random)
0.18
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
200
48
900
52
4
ps
ꢀ
ENABLE1
cycles
cycles
cycles
cycles
Output Enable
Time% NOTE 4
tEN
ENABLE2
ENABLE1
ENABLE2
4
Output Disable
Time% NOTE 4
tDIS
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65..
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
Table 6F. AC Characteristics, VDD = 2.5V 5ꢀ, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Using External Crystal
10
40
MHz
fMAX
Output Frequency
Using External Clock
Source NOTE 1
DC
100
80
MHz
ps
tsk(o)
Output Skew% NOTE 2, 3
25MHz, Integration Range:
100Hz – 1MHz
tjit
RMS Phase Jitter (Random)
0.19
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
200
47
900
53
4
ps
ꢀ
ENABLE1
cycles
cycles
cycles
cycles
Output Enable
Time% NOTE 4
tEN
ENABLE2
ENABLE1
ENABLE2
4
4
Output Disable
Time% NOTE 4
tDIS
4
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
ICS83905AM REVISION B JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Typical Phase Noise at 25MHz (2.5V Core/2.5V Output)
25MHz
RMS Phase Jitter (Random)
100Hz to 1MHz = 0.26ps (typical)
Raw Phase Noise Data
Offset Frequency (Hz)
Typical Phase Noise at 25MHz (3.3VCore/3.3V Output)
.25MHz
RMS Phase Jitter (Random)
100Hz to 1MHz = 0.13ps (typical)
Raw Phase Noise Data
Offset Frequency (Hz)
ICS83905AM REVISION B JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Parameter Measurement Information
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
V
V
V
V
DD,
DD,
DDO
DDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25 5ꢀ
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
2.05V 5ꢀ
1.25V 5ꢀ
0.9V 0.1V
SCOPE
SCOPE
V
DD
V
V
DD,
DDO
V
DDO
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-0.9V 0.1V
-1.25 5ꢀ
1.8V Core/1.8V LVCMOS Output Load AC Test Circuit
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
2.4V 0.9V
0.9V 0.1V
1.6V 0.025ꢀ
0.9V 0.1V
SCOPE
SCOPE
V
V
DD
DD
V
V
DDO
DDO
Qx
Qx
GND
GND
LVCMOS
LVCMOS
-0.9V 0.1V
-0.9V 0.1V
3.31.8V Core/1.8V LVCMOS Output Load AC Test Circuit
2.5V Core/1.8V LVCMOS Output Load AC Test Circuit
ICS83905AM REVISION B JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Parameter Measurement Information, continued
Phase Noise Plot
VCCO
2
Qx
Phase Noise Mask
VCCO
2
Qy
tsk(b)
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
Output Skew
RMS Phase Jitter
VDD
2
BCLK[0:5]
80ꢀ
tF
tPW
80ꢀ
tR
tPERIOD
20ꢀ
20ꢀ
BCLK[0:5]
tPW
x 100ꢀ
odc =
tPERIOD
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
ICS83905AM REVISION B JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Application Information
Crystal Input Interface
Figure 2 shows an example of ICS83905 crystal interface with a
parallel resonant crystal. The frequency accuracy can be fine tuned
by adjusting the C1 and C2 values. For a parallel crystal with loading
capacitance CL = 18pF, to start with, we suggest C1 = 15pF and C2
= 15pF. These values may be slightly fine tuned further to optimize
the frequency accuracy for different board layouts. Slightly increasing
the C1 and C2 values will slightly reduce the frequency. Slightly
decreasing the C1 and C2 values will slightly increase the frequency.
For the oscillator circuit below, R1 can be used, but is not required.
For new designs, it is recommended that R1 not be used.
XTAL_IN
C1
15p
X1
18pF Parallel Crystal
0
XTAL_OUT
C2
R1 (optional)
15p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and R2
can be 100Ω. This can also be accomplished by removing R1 and
making R2 50Ω. By overdriving the crystal oscillator, the device will
be functional, but note, the device performance is guaranteed by
using a quartz crystal.
VCC
VCC
R1
0.1µf
50Ω
Ro
Rs
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
ICS83905AM REVISION B JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
Thermally/Electrically Enhance Leadframe Base Package, Amkor
Technology.
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVCMOS Outputs
All control pins have internal pull-ups or pull-downs% additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
All unused LVCMOS output can be left floating. There should be no
trace attached.
ICS83905AM REVISION B JULY 20, 2009
13
©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Layout Guideline
Figure 5 shows an example of ICS83905 applications schematic. In
this example, the device is operated at VDD = 3.3V and VDDO = 3.3V.
The decoupling capacitors should be loacted as close as possible to
the power pins. The input is driven by an 18pF load resonant quartz
crystal. The tuning capacitors (C1, C2) are fairly accurate, but minor
adjustments might be required. For the LVCMOS output drivers, two
termination examples are shown in the schematic. For additonal
termination, examples are shown in the LVCMOS Termination
Applications Note.
VDDO = 3.3V
R2
VDD = 3.3V
31
Zo = 50 Ohm
CL = 18 pf
C2
C1
15pf
15pF
LVCMOS
U1
1
16
15
14
13
12
11
10
9
XTAL_OUT
ENABLE 2
GND
XTAL_I N
ENABLE 2
VDDO
ENABLE 1
2
3
4
5
6
7
8
ENABLE 1
BCLK5
VDDO
BCLK4
GND
VDD
BCLK0
VDDO
R3
BCLK1
GND
100
BCLK3
VDD
Zo = 50 Ohm
BCLK2
R4
ICS83905I
100
LVCMOS
VDD
VDDO
C5
Optional Termination
C3
C4
C6
.1uF
10uF
.1uF
.1uF
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
Figure 5. Schmatic of Recommended Layout
ICS83905AM REVISION B JULY 20, 2009
14
©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS83905.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS83905 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The
following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
•
•
Power (core)MAX = VDD_MAX * (IDD + IDDO) = 3.465V *(10mA + 5mA) = 51.9mW
Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 7Ω)] = 30.4mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 7Ω * (30.4mA)2 = 6.5mW per output
•
Total Power Dissipation on the ROUT
Total Power (ROUT) = 6.5mW * 6 = 39mW
Dynamic Power Dissipation at 25MHz
Power (25MHz) = CPD * Frequency * (VDD)2 = 19pF * 25MHz * (3.465V)2 = 5.70mW per output
Total Power (25MHz) = 5.70mW * 6 = 34.2mW
Total Power Dissipation
•
Total Power
= Power (core)MAX + Total Power (ROUT) + Total Power (25MHz)
= 51.98mW + 39mW + 34.2mW
= 125.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 100.3°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.125W *100.3°C/W = 82.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
100.3°C/W
96.0°C/W
93.9°C/W
ICS83905AM REVISION B JULY 20, 2009
15
©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Reliability Information
Table 8A. θJA vs. Air Flow Table for a 16 Lead TSSOP
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
100.3°C/W
96.0°C/W
93.9°C/W
Table 8B. θJA vs. Air Flow Table for a 16 Lead SOIC
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
78.8°C/W
71.1°C/W
66.2°C/W
Table 8C. θJA vs. Air Flow Table for a 20 Lead VFQFN
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
57.5°C/W
50.3°C/W
45.1°C/W
Transistor Count
The transistor count for ICS83905: 339
Pin compatible to MPC905
ICS83905AM REVISION B JULY 20, 2009
16
©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Package Outline and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP
Package Outline - M Suffix for 16 Lead SOIC
Table 9B. Package Dimensions for 16 Lead SOIC
All Dimensions in Millimeters
Table 9A. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
Symbol
Minimum
Maximum
N
A
A1
B
C
D
E
16
N
A
16
1.35
0.10
0.33
0.19
9.80
3.80
1.75
0.25
0.51
0.25
10.00
4.00
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.5
0.80
0.19
0.09
4.90
c
D
e
1.27 Basic
E
6.40 Basic
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
E1
e
4.30
4.50
0.65 Basic
L
L
0.45
0°
0.75
8°
α
α
aaa
0.10
Reference Document: JEDEC Publication 95, MS-012
Reference Document: JEDEC Publication 95, MO-153
ICS83905AM REVISION B JULY 20, 2009
17
©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
Seating Plane
N & N
(N -1)x e
(Ref.)
Even
A1
IndexArea
L
A3
E2
e
2
N
N
(Ty p.)
If N & N
are Even
Anvil
Singulation
1
2
(N -1)x e
OR
(Ref.)
E2
2
TopView
D
b
(Ref.)e
N &N
Odd
Thermal
Base
A
D2
2
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9C below.
Table 9C. Package Dimensions
JEDEC Variation: VGGD-1/-5
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
20
A
0.80
0
1.00
0.05
A1
A3
0.25 Ref.
b
ND & NE
D & E
D2 & E2
e
0.18
0.30
5
4.00 Basic
1.95
0.35
2.25
0.75
0.50 Basic
L
Reference Document: JEDEC Publication 95, MO-220
ICS83905AM REVISION B JULY 20, 2009
18
©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Ordering Information
Table 10. Ordering Information
Part/Order Number
83905AM
83905AMT
83905AMLF
83905AMLFT
83905AG
Marking
Package
16 Lead SOIC
16 Lead SOIC
Shipping Packaging
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Tray
2500 Tape & Reel
Tray
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
83905AM
83905AM
83905AML
83905AML
83905AG
83905AG
83905AGL
83905AGL
83905A
“Lead-Free” 16 Lead SOIC
“Lead-Free” 16 Lead SOIC
16 Lead TSSOP
83905AGT
16 Lead TSSOP
83905AGLF
83905AGLFT
83905AK
83905AKT
83905AKLF
83905AKLFT
“Lead-Free” 16 Lead TSSOP
“Lead-Free” 16 Lead TSSOP
20 Lead VFQFN
20 Lead VFQFN
“Lead-Free” 20 Lead VFQFN
“Lead-Free” 20 Lead VFQFN
83905A
3905AL
3905AL
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
ICS83905AM REVISION B JULY 20, 2009
19
©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
A
2
Added Enable Timing Diagram.
3/28/05
1
5 - 7
8
Features Section - added RMS Phase Jitter bullet.
B
T6A - T6F
T9
AC Characteristics Tables - added RMS Phase Jitter specs.
Added Phase Noise Plot.
4/8/05
B
B
14
Ordering Information Table - added TSSOP, non-LF part number.
4/25/05
5/16/05
11
12
Added Crystal Input Interface in Application Section.
Added Schematic layout.
3
Absolute Maximum Ratings - corrected 20 lead VFQFN package Thermal Impedance.
Added Recommendations for Unused Input and Output Pins.
B
B
11
13
10/2/06
7/9/07
Corrected Theta JA Air Flow Table for 20 lead VFQFN.
11
12
17
Added LVCMOS to XTAL Interface section.
Added Thermal Release Path section.
T9
AC Characteristics Table - added lead-free marking for 20 lead VFQFN package.
3
Absolute Maximum Ratings - updated TSSOP and VFQFN Thermal Impedance.
Updated Thermal Release Path section.
12
14
16
B
B
1/24/08
7/20/09
T7B - T7C
Updated TSSOP and VFQFN Thermal Impedance.
Added note to VFQFN Package Outline.
15
Added Power Considerations section.
Converted datasheet format.
ICS83905AM REVISION B JULY 20, 2009
20
©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
San Jose, California 95138
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
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party owners.
Copyright 2009. All rights reserved.
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