83904AGI-02LFT [IDT]
Low Skew, 1-to-4, Crystal-to-LVCMOS/LVTTL Fanout Buffer;
| 型号： | 83904AGI-02LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew, 1-to-4, Crystal-to-LVCMOS/LVTTL Fanout Buffer 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-4, Crystal-to-LVCMOS/LVTTL
Fanout Buffer
83904I-02
Datasheet
General Description
Features
The 83904I-02 is a low skew, high performance 1-to-4 Crystal-
to-LVCMOS Fanout Buffer. The 83904I-02 has selectable
single-ended clock or two crystal-oscillator inputs. There is an output
enable to disable the outputs by placing them into a high-impedance
state.
• Four LVCMOS / LVTTL outputs, 19 output impedance at
DD = VDDO = 3.3V
V
• Two crystal oscillator input pairs
LVCMOS / LVTTL clock input
• Crystal input frequency range: 12MHz – 38.88MHz
• Output frequency: 200MHz (maximum)
Guaranteed output and part-to-part skew characteristics make the
83904I-02 ideal for those applications demanding well defined
performance and repeatability.
• Output skew: 40ps (maximum) at VDD = VDDO = 3.3V
• RMS phase jitter @ 25MHz output, using a 25MHz crystal,
(100Hz – 1MHz): 0.16ps (typical) at VDD = VDDO = 3.3V
• RMS phase noise at 25MHz
Offset
Noise Power
100Hz .............. -118.4 dBc/Hz
1kHz................. -141.5 dBc/Hz
10kHz............... -157.2 dBc/Hz
100kHz............. -157.2 dBc/Hz
•Power Supply Voltage Modes:
Core / Output
3.3V / 3.3V
3.3V / 2.5V
3.3V / 1.8V
2.5V / 2.5V
2.5V / 1.8V
Block Diagram
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packaging
Pullup
OE
Pulldown
CLK_SEL0
Pulldown
CLK_SEL1
Pin Assignment
XTAL_IN0
V
Q0
Q1
GND
Q2
Q3
V
OE
DDO
1
2
3
4
5
6
16
15
14
13
12
11
10
9
OSC
CLK_SEL0
XTAL_OUT0
XTAL_IN0
Q0
0 0
XTAL_OUT0
V
DD
Q1
Q2
Q3
XTAL_IN1
XTAL_OUT1
CLK_SEL1
CLK
DDO
XTAL_IN1
7
8
OSC
0 1
XTAL_OUT1
83904I-02
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
1 0
1 1
Pulldown
CLK
Top View
©2016 Integrated Device Technology, Inc.
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Revision B, April 8, 2016
83904I-02 Datasheet
Pin Descriptions and Pin Characteristics
Table 1. Pin Descriptions
Number
Name
Type
Pulldown
Description
1,
7
CLK_SEL0,
CLK_SEL1
Clock select inputs. See Table 3, Input Reference Function Table.
LVCMOS/LVTTL interface levels.
Input
2.
3
XTAL_OUT0,
XTAL_IN0
Crystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT0 is the
output.
Input
Power
Input
Input
Input
4
VDD
Power supply pin.
5,
6
XTAL_IN1,
XTAL_OUT1
Crystal oscillator interface. XTAL_IN1 is the input. XTAL_OUT1 is the
output.
8
CLK
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable pin. When LOW, outputs are in high-impedance state.
Pullup
9
OE
When HIGH, outputs are active. LVCMOS/LVTTL interface levels.
10, 16
11, 12, 14, 15
13
VDDO
Q3, Q2, Q1, Q0
GND
Power
Output
Power
Output supply pins.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
k
k
pF
pF
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
51
51
8
RPULLUP
RPULLDOWN
VDDO = 3.465V
Power Dissipation
Capacitance
(per output)
CPD
VDDO = 2.625V
7
VDDO = 2.0V
VDDO = 3.3V
VDDO = 2.5V
VDDO = 1.8V
7
19
21
32
ROUT
Output Impedance
Function Table
Table 3. Input Reference Function Table
Control Inputs
CLK_SEL1
CLK_SEL0
Reference
XTAL0 (default)
XTAL1
0
0
1
1
0
1
0
1
CLK
CLK
©2016 Integrated Device Technology, Inc.
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83904I-02 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
100.3C/W (0 mps)
-65C to 150C
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V = V
= 3.3V 5ꢀ, T = -40°C to 85°C
A
DD
DDO
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
Units
V
VDD
Power Supply Voltage
3.465
VDDO
Output Supply Voltage
Power Supply Current
Output Supply Current
3.135
3.3
3.465
V
No Load & XTALx selected @ 12MHz
No Load & CLK selected
7
1
1
mA
mA
mA
IDD
IDDO
No Load & CLK selected
Table 4B. Power Supply DC Characteristics, V = 3.3V 5ꢀ, V
= 2.5V 5ꢀ, T = -40°C to 85°C
A
DD
DDO
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
Units
V
VDD
Power Supply Voltage
3.465
VDDO
Output Supply Voltage
Power Supply Current
Output Supply Current
2.375
2.5
2.625
V
No Load & XTALx selected @ 12MHz
No Load & CLK selected
7
1
1
mA
mA
mA
IDD
IDDO
No Load & CLK selected
Table 4C. Power Supply DC Characteristics, V = 3.3V 5ꢀ, V
= 1.8V 0.2V, T = -40°C to 85°C
A
DD
DDO
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
Units
V
VDD
Power Supply Voltage
3.465
VDDO
Output Supply Voltage
Power Supply Current
Output Supply Current
1.6
1.8
2.0
7
V
No Load & XTALx selected @ 12MHz
No Load & CLK selected
mA
mA
mA
IDD
1
IDDO
No Load & CLK selected
1
©2016 Integrated Device Technology, Inc.
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83904I-02 Datasheet
Table 4D. Power Supply DC Characteristics, V = V
= 2.5V 5ꢀ, T = -40°C to 85°C
A
DD
DDO
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
Units
V
VDD
Power Supply Voltage
2.625
VDDO
Output Supply Voltage
Power Supply Current
Output Supply Current
2.375
2.5
2.625
V
No Load & XTALx selected @ 12MHz
No Load & CLK selected
3
1
1
mA
mA
mA
IDD
IDDO
No Load & CLK selected
Table 4E. Power Supply DC Characteristics, V = 2.5V 5ꢀ, V
= 1.8V 0.2V, T = -40°C to 85°C
A
DD
DDO
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
Units
V
VDD
Power Supply Voltage
2.625
VDDO
Output Supply Voltage
Power Supply Current
Output Supply Current
1.6
1.8
2.0
3
V
No Load & XTALx selected @ 12MHz
No Load & CLK selected
mA
mA
mA
IDD
1
IDDO
No Load & CLK selected
1
Table 4F. LVCMOS/LVTTL DC Characteristics, T = -40°C to 85°C
A
Symbol Parameter
Test Conditions
DD = 3.3V 5ꢀ
Minimum
2.2
Typical
Maximum
VDD + 0.3
VDD + 0.3
1.3
Units
V
V
V
V
V
VIH
VIL
Input High Voltage
VDD = 2.5V 5ꢀ
VDD = 3.3V 5ꢀ
VDD = 2.5V 5ꢀ
1.6
-0.3
Input Low Voltage
-0.3
0.9
CLK,
CLK_SEL[0:1]
VDD = VIN = 3.3V or 2.5V 5ꢀ
VDD = VIN = 3.3V or 2.5V 5ꢀ
150
5
µA
µA
µA
Input
High Current
IIH
OE
CLK,
CLK_SEL[0:1]
VDD = 33.3V or 2.5V 5ꢀ,
VIN = 0V
-5
Input
IIL
Low Current
VDD = 3.3V or 2.5V 5ꢀ,
VIN = 0V
OE
-150
µA
V
DDO = 3.3V 5ꢀ
2.6
1.8
1.2
V
V
V
V
V
V
VOH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDDO = 2.5V 5ꢀ
VDDO = 1.8V 0.2V
V
DDO = 3.3V 5ꢀ
VDDO = 2.5V 5ꢀ
DDO = 1.8V 0.2V
0.6
0.5
0.4
VOL
V
NOTE: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, Load Test Circuit diagram.
©2016 Integrated Device Technology, Inc.
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Revision B, April 8, 2016
83904I-02 Datasheet
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Frequency
Fundamental
12
38.88
MHz
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
AC Electrical Characteristics
Table 6A. AC Characteristics, V = V
= 3.3V 5ꢀ, T = -40°C to 85°C
DD
DDO
A
Parameter Symbol
Test Conditions
Minimum
Typical
Maximum
38.88
Units
MHz
MHz
w/external XTAL
w/external CLK
12
Output
fOUT
tpLH
Frequency
200
Propagation Delay, Low to High;
NOTE 1
1.4
1.9
2.4
ns
tsk(o)
Output Skew; NOTE 2, 5
40
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
700
25MHz, Integration Range:
100MHz – 1MHz
tjit()
RMS Phase Jitter, Random; 4, 5
Output Rise/Fall Time
0.16
ps
tR / tF
20ꢀ to 80ꢀ
100
45
800
55
ps
ꢀ
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
<150MHz
46
54
ꢀ
tEN
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
10
ns
ns
tDIS
10
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc.
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Revision B, April 8, 2016
83904I-02 Datasheet
Table 6B. AC Characteristics, V = 3.3V 5ꢀ, V
= 2.5V 5ꢀ, T = -40°C to 85°C
A
DD
DDO
Parameter Symbol
Test Conditions
Minimum
Typical
Maximum
Units
MHz
MHz
w/external XTAL
w/external CLK
12
38.88
200
Output
fOUT
tpLH
Frequency
Propagation Delay, Low to High;
NOTE 1
1.5
2.0
2.5
ns
tsk(o)
Output Skew; NOTE 2, 5
40
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
700
25MHz, Integration Range:
100MHz – 1MHz
tjit()
RMS Phase Jitter, Random; 4, 5
Output Rise/Fall Time
0.16
ps
tR / tF
20ꢀ to 80ꢀ
100
45
800
55
ps
ꢀ
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
<150MHz
46
54
ꢀ
tEN
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
10
ns
ns
tDIS
10
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
Table 6C. AC Characteristics, V = 3.3V 5ꢀ, V
= 1.8V 0.2V, T = -40°C to 85°C
A
DD
DDO
Parameter Symbol
Test Conditions
Minimum
Typical
Maximum
38.88
Units
MHz
MHz
w/external XTAL
w/external CLK
12
Output
fOUT
tpLH
Frequency
200
Propagation Delay, Low to High;
NOTE 1
1.7
2.2
2.7
ns
tsk(o)
Output Skew; NOTE 2, 5
40
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
700
25MHz, Integration Range:
100MHz – 1MHz
tjit()
RMS Phase Jitter, Random; 4, 5
Output Rise/Fall Time
0.16
ps
tR / tF
20ꢀ to 80ꢀ
100
45
1000
55
ps
ꢀ
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
<150MHz
46
54
ꢀ
tEN
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
10
ns
ns
tDIS
10
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc.
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Revision B, April 8, 2016
83904I-02 Datasheet
Table 6D. AC Characteristics, V = V
= 2.5V 5ꢀ, T = -40°C to 85°C
DD
DDO
A
Parameter Symbol
Test Conditions
Minimum
Typical
Maximum
Units
MHz
MHz
w/external XTAL
w/external CLK
12
38.88
200
Output
fOUT
tpLH
Frequency
Propagation Delay, Low to High;
NOTE 1
1.5
2.2
3.0
ns
tsk(o)
Output Skew; NOTE 2, 5
40
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
700
25MHz, Integration Range:
100MHz – 1MHz
tjit()
RMS Phase Jitter, Random; 4, 5
Output Rise/Fall Time
0.20
ps
tR / tF
20ꢀ to 80ꢀ
100
45
800
55
ps
ꢀ
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
<150MHz
46
54
ꢀ
tEN
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
10
ns
ns
tDIS
10
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
Table 6E. AC Characteristics, V = 2.5V 5ꢀ, V
= 1.8V 0.2V, T = -40°C to 85°C
A
DD
DDO
Parameter Symbol
Test Conditions
Minimum
Typical
Maximum
38.88
Units
MHz
MHz
w/external XTAL
w/external CLK
12
Output
fOUT
tpLH
Frequency
200
Propagation Delay, Low to High;
NOTE 1
1.7
2.5
3.3
ns
tsk(o)
Output Skew; NOTE 2, 5
40
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
700
25MHz, Integration Range:
100MHz – 1MHz
tjit()
RMS Phase Jitter, Random; 4, 5
Output Rise/Fall Time
0.19
ps
tR / tF
20ꢀ to 80ꢀ
100
45
1000
55
ps
ꢀ
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
<150MHz
46
54
ꢀ
tEN
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
10
ns
ns
tDIS
10
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc.
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Revision B, April 8, 2016
83904I-02 Datasheet
Typical Phase Noise at 25MHz, 100Hz - 1MHz
25MHz
RMS Phase Jitter
100Hz to 1MHz = 0.16ps (typical)
Raw Phase Noise Data
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
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83904I-02 Datasheet
Parameter Measurement Information
2.05V 5ꢀ
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
V
SCOPE
DD
V
DD,
V
DDO
V
DDO
Qx
Qx
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V Core/3.3V LVCMOS Output Load Test Circuit
3.3V Core/2.5V LVCMOS Output Load Test Circuit
2.4V 0.065V
0.9V 0.1V
1.25V 5ꢀ
SCOPE
V
SCOPE
DD
V
DD,
V
DDO
V
DDO
Qx
Qx
GND
GND
-1.25V 5ꢀ
-1.25V 5ꢀ
3.3V Core/1.8V LVCMOS Output Load Test Circuit
2.5V Core/2.5V LVCMOS Output Load Test Circuit
1.6V 0.025V
0.9V 0.1V
V
SCOPE
DD
V
DDO
Qx
GND
2.5V Core/1.8V LVCMOS Output Load Test Circuit
RMS Phase Jitter
©2016 Integrated Device Technology, Inc.
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83904I-02 Datasheet
Parameter Measurement Information, continued
Part 1
Part 2
VDDO
VDDO
2
Qx
Qy
2
Qx
Qy
VDDO
2
VDDO
2
tsk(o)
tsk(pp)
Output Skew
Part-to-Part Skew
VDD
OE
(High-level
enabling)
VDD/2
VDD/2
VDD
0V
2
CLK
VDDO
2
tEN
tDIS
Q[0:3]
VOH
t
PD
VDD/2
VDD/2
Output Qx
Propagation Delay
Output Enable/Disable Time
Q[0:3]
Q[0:3]
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
©2016 Integrated Device Technology, Inc.
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83904I-02 Datasheet
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Outputs
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
All unused LVCMOS outputs can be left floating. There should be no
trace attached.
CLK Input
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pullup and pulldown resistors; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Crystal Input Interface
Figure 1 shows an example of 83904I-02 crystal interface with a
parallel resonant crystal. The frequency accuracy can be fine tuned
by adjusting the C1 and C2 values. For a parallel crystal with loading
capacitance CL = 18pF, we suggest C1 = 15pF and C2 = 15pF to
start with. These values may be slightly fine tuned further to optimize
the frequency accuracy for different board layouts. Slightly increasing
the C1 and C2 values will slightly reduce the frequency. Slightly
decreasing the C1 and C2 values will slightly increase the frequency.
For the oscillator circuit below, R1 can be used, but is not required.
For new designs, it is recommended that R1 not be used.
XTAL_IN
C1
15pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
15pF
Figure 1. Crystal Input Interface
©2016 Integrated Device Technology, Inc.
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83904I-02 Datasheet
Overdriving the XTAL Interface
TheXTAL_INinputcanbe overdriven byan LVCMOSdriver orby one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 2A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 2B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
VCC
XTAL_OUT
R1
100
C1
Rs
Zo = 50 ohms
Ro
XTAL_IN
.1uf
R2
100
Zo = Ro + Rs
LVCMOS Driver
Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OU T
C2
Zo = 50 ohms
XTAL_I N
.1uf
Zo = 50 ohms
R1
50
R2
50
LVPECL Driver
R3
50
Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface
©2016 Integrated Device Technology, Inc.
12
Revision B, April 8, 2016
83904I-02 Datasheet
Reliability Information
Table 7. JA vs. Air Flow Table for a 16 Lead TSSOP
JA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
100.3°C/W
96.0°C/W
93.9°C/W
Transistor Count
The transistor count for 83904I-02: 205
Package Outline and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP
Table 8. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
16
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 Basic
0.65 Basic
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
©2016 Integrated Device Technology, Inc.
13
Revision B, April 8, 2016
83904I-02 Datasheet
Ordering Information
Table 9. Ordering Information
Part/Order Number
83904AGI-02LF
Marking
Package
Shipping Packaging
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
904AI02L
904AI02L
“Lead-Free” 16 Lead TSSOP
“Lead-Free” 16 Lead TSSOP
83904AGI-02LFT
Tape & Reel
©2016 Integrated Device Technology, Inc.
14
Revision B, April 8, 2016
83904I-02 Datasheet
Revision History Sheet
Rev
Table
Page
Description of Change
Date
Deleted “ICS” prefix from part number throughout the datasheet.
Updated datasheet header/footer.
B
4/8/16
©2016 Integrated Device Technology, Inc.
15
Revision B, April 8, 2016
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