74ALVCH16903PF8 [IDT]
TVSOP-56, Reel;
| 型号： | 74ALVCH16903PF8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TVSOP-56, Reel 电视 |
| 文件： | 总13页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 12-BIT UNIVERSAL
IDT74ALVCH16903
BUS DRIVER WITH PARITY
CHECKER, DUAL 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
FEATURES:
This 12-bit universal bus driver is built using advanced dual metal CMOS
technology. This device has dual outputs and can operate as a buffer or an
edge-triggered register. In both modes, parity is checked on APAR, which
arrivesonecycleafterthedatatowhichitapplies.TheYERRoutput,whichis
produced one cycle after APAR, is open drain.
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
MODE selects one of the two data paths. When MODE is low, the device
operatesasanedge-triggeredregister.Onthepositivetransitionoftheclock
(CLK)inputandwhentheclock-enable(CLKEN)inputislow,datasetupatthe
Ainputsisstoredintheinternalregisters.OnthepositivetransitionofCLKand
when CLKEN is high, only data setup at the 9A-12A inputs is stored in their
internalregisters.WhenMODEishigh,thedeviceoperatesasabufferanddata
attheAinputspassesdirectlytotheoutputs.The11A/YERREN servesadual
purpose;itactsasanormaldatabitandalsoenablesYERRdatatobeclocked
intotheYERRoutputregister.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
Whenusedasasingledevice,parityoutputenable(PAROE)mustbetied
high;whenparityinput/output(PARI/O)islow,evenparityisselectedandwhen
PARI/Oishigh,oddparityisselected.WhenusedinpairsandPAROEislow,
theparitysumisoutputonPARI/OforcascadingtothesecondALVCH16903.
WhenusedinpairsandPAROEishigh,PARI/Oacceptsapartialparitysum
fromthefirstALVCH16903.
Abufferedoutput-enable(OE)inputcanbeusedtoplacethe24outputsand
YERRineitheranormallogicstate(highorlowlogiclevels)orahigh-impedance
state.Inthehigh-impedancestate,theoutputsneitherloadnordrivethebuslines
significantly. The high-impedance state and increased drive provide the
capabilitytodrivebuslineswithoutneedforinterfaceorpullupcomponents.
The ALVCH16903 has been designed with a ±24mA output driver. This
driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed
performance.
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +4.6
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
(Outputs Only)
V
TSTG
IOUT
IIK
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
° C
mA
mA
Continuous Clamp Current,
VI < 0 or VI > VCC
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
ICC
ISS
Continuous Current through each
VCC or GND
±100
The ALVCH16903 has “bus-hold” which retains the inputs’ last state
whenevertheinputbusgoestoahigh-impedance.Thispreventsfloatinginputs
andeliminatestheneedforpull-up/downresistors.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. This value is limited to 4.6V maximum.
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
COUT
COUT
NOTE:
1. As applicable to the device type.
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JUNE 2006
1
© 2006 Integrated Device Technology, Inc.
DSC-4911/4
IDT74ALVCH16903
3.3VCMOS12-BITUNIVERSALBUSDRIVERWITHPARITYCHECKER
INDUSTRIALTEMPERATURERANGE
FUNCTIONALBLOCKDIAGRAM
1
OE
33
MODE
1Y1-12Y1
56
CLK
12
(1A-11A/YERREN, APAR)
(1A-12A)
12
13
13
1A-12A,
APAR
1Y2-12Y2
13
5
12
(1A-8A)
8
13
(11A/YERREN)
D
D
Q
Q
29
Flip
Flop
CLKEN
APAR
12
11
10
APAR
5
(9A-12A, APAR)
Flip
Flop
(1A-10A)
36
YERR
D
Q
Parity
Check
D
Q
XOR
30
PARI/O
28
PAROE
FUNCTIONTABLE(1)
PARITYFUNCTIONTABLE(1)
Inputs
Output
Inputs
Outputs
OE PAROE(2)
11A/
YERREN(3)
PARI/O Σ OF INPUTS APAR YERR
OE
L
MODE CLKEN
CLK
↑
A
1Yx-8Yx 9Yx-12Yx
1A-10A=H
L
L
L
L
H
L
H
L
H
L
H
L
H
L
Z
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
X
L
L
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
X
L
L
H
L
L
↑
(2)
L
L
H
H
X
X
X
↑
H
L
Y
L
H
H
L
L
(2)
L
L
↑
Y
L
H
L
L
H
H
X
X
H
L
H
H
H
H
H
X
L
X
L
Z
L
H
H
L
H
H
X
H
X
X
NOTES:
H
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
L
X
H
X
X
X
H
NOTES:
↑ = LOW-to-HIGH Transition
2. Output level before the indicated steady-state conditions were established.
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2. When used as a single device, PAROE must be tied HIGH.
3. Valid after appropriate number of clock pulses have set internal register.
2
IDT74ALVCH16903
3.3VCMOS12-BITUNIVERSALBUSDRIVERWITHPARITYCHECKER
INDUSTRIALTEMPERATURERANGE
PARI/OFUNCTION TABLE(1)
PINCONFIGURATION
Inputs
Output
PAROE
Σ OF INPUTS
1A-10A = H
APAR
PARI/O
OE
1
2
56
55
CLK
1A
1Y1
L
L
L
L
H
0, 2, 4, 6, 8,10
1, 3, 5, 7, 9
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
X
L
L
L
H
H
L
1Y2
3
4
54
53
11A/YERREN
GND
H
H
X
GND
5
6
7
8
9
52
51
50
49
48
11Y1
11Y2
VCC
2A
2Y1
2Y2
VCC
3Y1
3Y2
Z
NOTE:
1. This table applies to the first device of a cascaded pair of ALVCH16903 devices.
3A
4Y1
10
11
12
13
47
46
45
44
4A
GND
12A
12Y1
GND
4Y2
5Y1
14
15
16
17
18
19
20
21
22
23
24
25
5Y2
6Y1
6Y2
7Y1
GND
7Y2
8Y1
8Y2
VCC
43
42
12Y2
5A
PINDESCRIPTION
6A
41
40
Pin Names
1A-12A
1Y1-12Y2
CLK
I/O
Description
7A
I
Data Inputs(1)
GND
APAR
8A
39
38
37
O
I
3-StateDataOutputs
ClockInput
CLKEN
MODE
YERREN
PAROE
PARI/O
YERR
I
Clock Enable Input (Active LOW)
SelectPin
I
YERR
VCC
36
35
34
33
32
I
ErrorSignalOutputEnable (Active LOW)
Parity Output Enable (Active LOW)
ParityInput/Output
I
I/O
O
I
9Y1
9Y2
9A
ErrorSignal(OpenDrain)
OutputEnableInput(ActiveLOW)
ParityInput
MODE
GND
10A
OE
GND
10Y1
10Y2
APAR
I
26
27
28
31
30
29
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
PARI/O
PAROE
CLKEN
TSSOP
TOP VIEW
3
IDT74ALVCH16903
3.3VCMOS12-BITUNIVERSALBUSDRIVERWITHPARITYCHECKER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
OperatingCondition:TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
InputLOWVoltageLevel
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V
—
—
—
—
—
—
—
—
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
InputLOWCurrent
VI = VCC
—
± 5
µA
VCC = 3.6V
VI = GND
—
± 5
IOZH
IOZL
IOH
HighImpedanceOutputCurrent
(3-StateOutputpins)
YERROutput
VCC = 3.6V
VO = VCC
—
± 10
± 10
± 10
± 10
–1.2
—
µA
µ A
µA
µ A
V
VO = GND
VO = VCC
—
VCC = 0V to 3.6V
VCC = 3.6V
—
(2)
IOZ
HighImpedanceOutputCurrent
ClampDiodeVoltage
InputHysteresis
VO = VCC or GND
—
VIK
VCC = 2.3V, IIN = – 18mA
VCC = 3.3V
–0.7
100
VH
mV
ICCL
ICCH
ICCZ
ΔICC
Quiescent Power Supply Current
VCC = 3.6V, VIN = GND or VCC
—
—
0.1
—
40
µ A
µ A
pF
Quiescent Power Supply
CurrentVariation
ControlInputs
DataInputs
One input at VCC − 0.6V, other inputs at VCC or GND
750
Ci
Co
Cio
VCC = 3.3V
VCC = 3.3V
VCC = 3.3V
VI = VCC or GND
VO = VCC or GND
VO = VCC or GND
—
—
—
—
—
5.5
5.5
5
—
—
—
—
—
YERROutput
DataOutputs
pF
pF
6
PARI/O
7
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. For I/O ports, the parameter IOZ includes the input leakage current.
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
VI = 2V
µ A
IBHL
VI = 0.8V
VI = 1.7V
VI = 0.7V
VI = 0 to 3.6V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-HoldInputOverdrive Current
VCC = 2.3V
VCC = 3.6V
–45
45
—
—
µ A
µ A
IBHL
—
—
IBHHO
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
4
IDT74ALVCH16903
3.3VCMOS12-BITUNIVERSALBUSDRIVERWITHPARITYCHECKER
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS,xYxPORTS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VCC = 2.3V to 3.6V
VCC = 2.3V
IOH = – 0.1mA
VCC–0.2
IOH = – 6mA, VIH = 1.7V
IOH = – 12mA, VIH = 1.7V
IOH = – 12mA, VIH = 2V
2
—
VOH
Output HIGH Voltage
VCC = 2.3V
1.7
2.2
2.4
2
—
V
VCC = 2.7V
—
VCC = 3V
—
VCC = 3V
IOH = – 24mA, VIH = 2V
IOL = 0.1mA
—
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
IOL = 6mA, VIL = 0.7V
IOL = 12mA, VIL = 0.7V
IOL = 12mA, VIL = 0.8V
—
—
—
0.4
0.7
0.4
VOL
IOH
OutputLOWVoltage
V
VCC = 2.7V
VCC = 3V
IOL = 24mA, VIL = 0.8V
Y Port
—
—
—
0.55
−12
−12
VCC = 2.3V
VCC = 2.7V
VCC = 3V
High-LevelOutputCurrent
mA
PARI/O
Y Port
—
—
—
−12
−24
12
VCC = 2.3V
VCC = 2.7V
Y Port
—
—
—
12
12
24
IOL
Low-LevelOutputCurrent
PARI/O
mA
VCC = 3V
Y Port
YERROutput
—
24
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS FOR YERR AND PARI/O
Symbol
Parameter
TestConditions(1)
Min.
2
Max.
—
Unit
V
VOH
PARI/O
VCC = 3V
VCC = 3V
IOH = – 12mA, VIH = 2V
VOL
PARI/O
IOL = 12mA, VIL = 0.8V
IOL = 24mA
—
0.55
V
VOL
YERR Output only
VCC = 3V
—
0.5
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
5
IDT74ALVCH16903
3.3VCMOS12-BITUNIVERSALBUSDRIVERWITHPARITYCHECKER
INDUSTRIALTEMPERATURERANGE
OPERATING CHARACTERISTICS FOR BUFFER MODE, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
CPD
Parameter
Test Conditions
Typical
57.5
Typical
65
Unit
PowerDissipationCapacitanceOutputsenabled
PowerDissipationCapacitanceOutputsdisabled
CL = 0pF, f = 10Mhz
pF
CPD
15
17.5
OPERATING CHARACTERISTICS FOR REGISTER MODE, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
CPD
Parameter
Test Conditions
Typical
57
Typical
87.5
Unit
PowerDissipationCapacitanceOutputsenabled
PowerDissipationCapacitanceOutputsdisabled
CL = 0pF, f = 10Mhz
pF
CPD
16.5
34
SIMULTANEOUSSWITCHINGCHARACTERISTICS(1)
Parameter
From
(Input)
CLK
To
(Output)
Y
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Min.
1.8
Max.
6.5
Min. Max.
Min.
1.8
Max.
5
Unit
tPLH
tPHL
Registermode
6.1
5.1
ns
1.4
5.9
1.7
4.5
NOTE:
1. All outputs switching.
6
IDT74ALVCH16903
3.3VCMOS12-BITUNIVERSALBUSDRIVERWITHPARITYCHECKER
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol Parameter
Min.
125
1
Max.
—
Min.
125
—
Max.
—
Min.
125
1.1
Max.
—
Unit
MHz
ns
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
PropagationDelay,BufferMode
4.4
4.2
3.8
xAx to xYx
PropagationDelay,BothModes
CLK to YERR
PropagationDelay,BothModes
1
1.2
1
5.7
8.6
6.8
5.9
—
—
—
—
4.9
7.9
5.2
5.8
1.4
1.7
1.3
1.3
4.4
6.6
4.5
4.9
ns
ns
ns
ns
ns
ns
ns
ns
CLK to PARI/O
PropagationDelay,BothModes
CLK to PARI/O
PropagationDelay,BothModes
Mode to xYx
1
PropagationDelay,RegisterMode
CLK to xYx
1
1
1
6.1
5.9
3.6
—
—
—
5.5
4.9
4.2
1.2
1.2
1.9
4.8
4.6
4
PropagationDelay,BothModes
OE to YERR
tPHL
PropagationDelay,BothModes
OE to YERR
1.2
1.1
1
5.1
6.5
5.6
—
—
—
4.9
6.4
6
1.5
1.4
1
4.2
5.4
4.8
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
tSU
tSU
tSU
tSU
tSU
tSU
tSU
tH
OutputEnableTime,BothModes
OE to xYx
OutputEnableTime,BothModes
PAROE to PARI/O
ns
ns
ns
OutputDisableTime,BothModes
OE to xYx
1
1
6.4
3.2
—
—
5.2
3.8
1.7
1.2
5
OutputDisableTime,BothModes
PAROE to PARI/O
3.8
Set-upTime,RegisterMode,1A-12AbeforeCLK↑
Set-upTime, BufferMode, 1Ato10Abefore CLK↑
Set-up Time, Register Mode, APAR before CLK↑
Set-up Time, Buffer Mode, APAR before CLK↑
Set-up Time, Both Modes, PARI/O before CLK↑
Set-up Time, Buffer Mode, 11A/YERREN before CLK↑
Set-up Time, Register Mode, CLKEN before CLK↑
Hold Time, Register Mode, 1A-12A after CLK↑
Hold Time, Buffer Mode, 1A-10A after CLK↑
Hold Time, Register Mode, APAR after CLK↑
Hold Time, Buffer Mode, APAR after CLK↑
Hold Time, Register Mode, PARI/O after CLK↑
Hold Time, Buffer Mode, PARI/O after CLK↑
Hold Time, Buffer Mode, 11A/YERREN after CLK↑
Hold Time, Register Mode, CLKEN after CLK↑
Pulse Width, CLK↑
1.7
5.9
1.2
4.6
2.4
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.9
5.2
1.5
3.6
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.45
4.4
1.3
3.1
1.7
1.6
2.2
0.55
0.25
0.7
0.25
0.4
0.5
0.4
0.4
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
1.9
2.6
0.25
0.25
0.4
0.25
0.25
0.25
0.25
0.5
3
2.5
0.4
0.25
0.7
0.25
0.25
0.25
0.25
0.25
3
tH
tH
tH
tH
tH
tH
tH
tW
(2)
tSK(O)
OutputSkew
—
—
—
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
Skew between any two outputs of the same package and switching in the same direction.
2
7
IDT74ALVCH16903
3.3VCMOS12-BITUNIVERSALBUSDRIVERWITHPARITYCHECKER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
TESTCONDITIONS
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V Unit
tPHL
tPLH
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
V
V
2.7
1.5
300
300
50
2.7
1.5
300
300
50
tPHL
tPLH
VT
Vcc / 2
150
V
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
150
ALVC Link
30
Propagation Delay
VLOAD
Open
GND
DISABLE
VCC
ENABLE
VIH
VT
0V
CONTROL
INPUT
500Ω
tPZL
tPLZ
VIN
VOUT
(1, 2)
Pulse
VLOAD/2
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
VT
Generator
VLZ
VOL
CLOSED
500Ω
tPHZ
tPZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
ALVC Link
0V
Test Circuit for All Outputs
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
VIH
VT
DATA
INPUT
0V
tSU
tH
VIH
TIMING
INPUT
SWITCHPOSITION
VT
Test
Switch
VLOAD
GND
Open
0V
tREM
VIH
Open Drain
Disable Low
Enable Low
ASYNCHRONOUS
CONTROL
VT
0V
VIH
VT
0V
SYNCHRONOUS
CONTROL
Disable High
Enable High
tSU
tH
All Other Tests
ALVC Link
VIH
Set-up, Hold, and Release Times
VT
INPUT
0V
tPLH1
tPHL1
VOH
VT
LOW-HIGH-LOW
VT
PULSE
OUTPUT 1
VOL
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
OUTPUT 2
ALVC Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
Pulse Width
ALVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
8
IDT74ALVCH16903
3.3VCMOS12-BITUNIVERSALBUSDRIVERWITHPARITYCHECKER
INDUSTRIALTEMPERATURERANGE
PARAMETERMEASUREMENTINFORMATION
VCC = 2.7V AND 3.3V ± 0.3V
6V
500Ω
S1
TEST
S1
Open
From Output
Under Test
t
pd
/t
Open
6V
GND
GND
t
PLZ PZL
CL = 30 pF
(see Note 1)
500Ω
t
/t
PHZ PZH
S1
YERR
t
PHL (see Note 8)
PLH (see Note 9)
6V
6V
Load Circuit
t
2.7V
TIMING
INPUT
1.5V
0V
tW
th
tsu
2.7V
0V
2.7V
0V
DATA
INPUT
1.5V
1.5V
1.5V
INPUT
1.5V
Voltage Waveforms
Setup and Hold Times
Voltage Waveforms
Pulse Duration
OUTPUT
CONTROL
(low-level enabling)
1.5V
2.7V
0V
1.5V
tPZL
tPLZ
2.7V
0V
OUTPUT
WAVEFORM 1
S1 at 6V (see Note 2)
3V
1.5V
Input
1.5V
1.5V
tPZH
VOL+0.3V
VOL
t
t
PHL
PLH
tPHZ
V
OH
VOH
VOH-0.3V
Output
OUTPUT
WAVEFORM 2
S1 at GND (see Note 2)
1.5V
V
1.5V
1.5V
0V
OL
Voltage Waveforms
Voltage Waveforms
Propagation Delay Times
Enable and DisableTimes
NOTES:
1. CL includes probe and jig capacitance.
2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
3. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤ 2 ns, tf ≤ 2 ns.
4. The outputs are measured one at a time with one transition per measurement.
5. tPLZ and tPHZ are the same as tdis.
6. tPZL and tPZH are the same as ten.
7. tPLH and tPHL are the same as tpd.
8. tPHL is measured at 1.5V.
9. tPLH is measured at VOL +0.3V.
9
IDT74ALVCH16903
3.3VCMOS12-BITUNIVERSALBUSDRIVERWITHPARITYCHECKER
INDUSTRIALTEMPERATURERANGE
LOAD CIRCUIT AND VOLTAGE WAVEFORMS
VCC = 2.7V AND 3.3V ± 0.3V
2.7V
1.5V
1.5V
INPUT
0V
tPHL
1.5V
tPLH
V
OH
1.5V
OUTPUT
V
OL
PARI/O Load Circuit
PARI/O of
second
ALVCH16903
From Output
Under Test
PARI/O
Test
Point
Z
T
= 52 Ω
= 63 ps
O
d
CL = 0.6 pF
(see Note 1)
CL = 0.6 pF
(see Note 1)
NOTE:
1. CL includes probe and jig capacitance.
10
IDT74ALVCH16903
3.3VCMOS12-BITUNIVERSALBUSDRIVERWITHPARITYCHECKER
INDUSTRIALTEMPERATURERANGE
PARAMETERMEASUREMENTINFORMATION
VCC = 2.5V ±0.2V
2 x VCC
S1
TEST
500Ω
S1
Open
t
pd
Open
From Output
Under Test
t
/t
2 x VCC
PLZ PZL
GND
GND
S1
t
/t
PHZ PZH
CL = 30 pF
(see Note 1)
500Ω
YERR
t
t
PHL (see Note 8)
PLH (see Note 9)
2 x VCC
2 x VCC
Load Circuit
VCC
TIMING
INPUT
VCC/2
0V
tW
th
tsu
VCC
0V
VCC
0V
DATA
INPUT
VCC/2
VCC/2
VCC/2
INPUT
VCC/2
Voltage Waveforms
Setup and Hold Times
Voltage Waveforms
Pulse Duration
INPUT
CONTROL
(low-level
enabling)
VCC/2
VCC
VCC/2
0V
tPZL
tPLZ
OUTPUT
WAVEFORM 1
S1 at 2xVcc
V
cc
VCC
V
/2
Input
V
/2
cc
cc
Vcc/2
tPZH
VOL+0.15V
0V
(see Note 2)
VOL
t
t
PHL
PLH
tPHZ
V
OH
VOH
VOH-0.15V
OUTPUT
WAVEFORM 2
S1 at GND
Output
V
/2
/2
V
Vcc/2
cc
cc
0V
V
OL
(see Note 2)
Voltage Waveforms
Propagation Delay Times
Voltage Waveforms
Enable and DisableTimes
NOTES:
1. CL includes probe and jig capacitance.
2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
3. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤ 2 ns, tf ≤ 2 ns.
4. The outputs are measured one at a time with one transition per measurement.
5. tPLZ and tPHZ are the same as tdis.
6. tPZL and tPZH are the same as ten.
7. tPLH and tPHL are the same as tpd.
8. tPHL is measured at VCC /2.
9. tPLH is measured at VOL + 0.15V.
11
IDT74ALVCH16903
3.3VCMOS12-BITUNIVERSALBUSDRIVERWITHPARITYCHECKER
INDUSTRIALTEMPERATURERANGE
PARAMETERMEASUREMENTINFORMATION
VCC = 2.5V ±0.2V
PARI/O of
second
ALVCH16903
From Output
Under Test
PARI/O
Test
Point
Z
T
= 52 Ω
= 63 ps
O
d
CL = 0.6 pF
(see Note 1)
CL = 0.6 pF
(see Note 1)
Load Circuit
V
cc
V
/2
Input
t
V
/2
cc
cc
0V
t
PHL
PLH
V
OH
Output
V
/2
V
/2
cc
cc
V
OL
Voltage Waveforms
Propagation Delay Times
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50Ω, tr ≤ 2 ns, tf ≤2ns.
3. tPLH and tPHL are the same as tpd.
V
cc
RL = 10Ω
V
/2
Input
V
/2
cc
From Output
cc
0V
Under Test
Test
Point
t
t
PHL
PLH
V
OH
Output
V
/2
V
/2
cc
cc
CL = 30 pF
(see Note 1)
V
OL
Load Circuit
Voltage Waveforms
Propagation Delay Times
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50Ω, tr ≤ 2 ns, tf ≤2ns.
12
IDT74ALVCH16903
3.3VCMOS12-BITUNIVERSALBUSDRIVERWITHPARITYCHECKER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
Temp. Range
XXX
XX
ALVC
X
XXX
XX
Device Type Package
Bus-Hold Family
PA
Thin Shrink Small Outline Package
PAG TSSOP - Green
903
16
12-Bit Universal Bus Driver with Parity Checker
Double-Density, 24mA
Bus-Hold
H
74
-40°C to +85°C
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
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San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
logichelp@idt.com
www.idt.com
13
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