74ALVCH16240PA [IDT]
TSSOP-48, Tube;
| 型号： | 74ALVCH16240PA |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TSSOP-48, Tube 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 16-BIT
IDT74ALVCH16240
BUFFER/DRIVER WITH
3-STATE OUTPUTS AND
BUS-HOLD
DESCRIPTION:
FEATURES:
–
–
–
0.5 MICRON CMOS Technology
TypicaltSK(0) (Output Skew) < 250ps
This 16-bit buffer/driver is built using advanced dual metal CMOS
technology. The ALVCH16240 is deigned specifically to improve the
performance and density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and transmitters. The device can be
used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It
provides inverting outputs and symmetrical active-low output-enable
(OE) inputs.
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
Extended commercial range of – 40°C to + 85°C
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4µW typ. static)
Rail-to-Rail output swing for increased noise margin
–
–
–
–
–
–
–
The ALVCH16240 has been designed with a ±24mA output driver.
This driver is capable of driving a moderate to heavy load while
maintaining speed performance.
Drive Features for ALVCH16240:
–
–
The ALVCH16240 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
High Output Drivers: ±24mA
Suitable for heavy loads
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
Functional Block Diagram
25
1
1OE
3OE
36
13
47
2
1Y1
1Y2
1Y3
1Y4
3Y1
3Y2
3Y3
3Y4
1A1
3A1
3
5
35
33
14
16
17
46
44
1A2
3A2
1A3
3A3
32
43
6
1A4
3A4
24
48
2OE
2A1
4OE
8
30
29
27
26
19
41
40
38
37
2Y1
4Y1
4A1
4A2
4A3
9
11
12
20
22
23
2A2
2Y2
2Y3
2Y4
4Y2
4Y3
4Y4
2A3
2A4
4A4
EXTENDED COMMERCIAL TEMPERATURE RANGE
MARCH1999
1
c
1999 Integrated Device Technology, Inc.
DSC-4485/1
IDT74ALVCH16240
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATING (1)
Symbol
Description
Terminal Voltage
Max.
Unit
(2)
VTERM
– 0.5 to + 4.6
V
with Respect to GND
Terminal Voltage
1OE
1Y1
1
48
47
46
45
2OE
1A1
(3)
VTERM
– 0.5 to
VCC + 0.5
V
2
with Respect to GND
Storage Temperature
TSTG
IOUT
IIK
1Y2
– 65 to + 150
°C
3
1A2
GND
1A3
DC Output Current
– 50 to + 50
± 50
mA
mA
4
GND
1Y3
Continuous Clamp Current,
VI < 0 or VI > VCC
Continuous Clamp Current, VO < 0
5
44
43
42
41
40
IOK
– 50
mA
mA
6
1Y4
VCC
2Y1
1A4
ICC
ISS
Continuous Current through
each VCC or GND
±100
7
VCC
2A1
NEW16link
8
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VCC terminals.
9
2Y2
2A2
10
11
12
13
14
15
16
17
GND
2Y3
GND
2A3
39
38
37
36
35
34
33
32
31
30
SO48-1
SO48-2
SO48-3
2A4
2Y4
3. All terminals except VCC.
3Y1
3A1
3Y2
3A2
CAPACITANCE (TA = +25oC, f = 1.0MHz)
GND
3Y3
GND
3A3
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
3Y4
VCC
4Y1
3A4
COUT
CI/O
Output
Capacitance
I/O Port
VOUT = 0V
VIN = 0V
7
7
9
9
pF
pF
18
19
20
21
22
23
24
VCC
4A1
4A2
Capacitance
NEW16link
4Y2
29
28
27
26
25
NOTE:
1. As applicable to the device type.
GND
4Y3
GND
4A3
4Y4
4A4
FUNCTION TABLE (each 4-bit buffer)(1)
4OE
3OE
Inputs
Outputs
xYx
xOE
L
xAx
L
SSOP/
TSSOP/TVSOP
TOP VIEW
H
L
Z
L
H
H
X
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
PIN DESCRIPTION
Pin Names
Description
xOE
xAx
3–State Output Enable Inputs (Active LOW)
Data Inputs(1)
Z = High-Impedance
xYx
3-State Outputs
NOTE:
1. These pins have “Bus-Hold.” All other pins are standard inputs,
outputs, or I/Os.
2
IDT74ALVCH16240
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max.
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V
1.7
—
—
V
2
—
—
—
0.7
VIL
Input LOW Voltage Level
—
—
—
—
—
—
—
—
—
V
—
0.8
IIH
Input HIGH Current
VI = VCC
—
± 5
± 5
± 10
± 10
– 1.2
—
µA
IIL
Input LOW Current
VCC = 3.6V
VI = GND
VO = VCC
VO = GND
—
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
VCC = 3.6V
—
µA
µA
V
—
VCC = 2.3V, IIN = – 18mA
VCC = 3.3V
– 0.7
100
0.1
mV
µA
ICCL
ICCH
ICCZ
∆ICC
VCC = 3.6V
VIN = GND or VCC
40
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
One input at VCC − 0.6V,
other inputs at VCC or GND
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
Parameter(1)
Test Conditions
Min.
Typ.(2)
Max.
Unit
IBHH
Bus-Hold Input Sustain Current
VCC = 3.0V
VCC = 2.3V
VCC = 3.6V
VI = 2.0V
VI = 0.8V
VI = 1.7V
VI = 0.7V
VI = 0 to 3.6V
– 75
—
—
µA
IBHL
75
– 45
45
—
—
—
—
—
—
IBHH
IBHL
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
µA
—
IBHHO
IBHLO
—
± 500
µA
NEW16link
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCH16240
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Output HIGH Voltage
Test Conditions(1)
IOH = – 0.1mA
Min.
Max.
Unit
VOH
VCC = 2.3V to 3.6V
VCC = 2.3V
VCC – 0.2
—
V
IOH = – 6mA
IOH = – 12mA
2
—
—
VCC = 2.3V
1.7
2.2
2.4
2
VCC = 2.7V
—
VCC = 3.0V
—
VCC = 3.0V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3.0V
NEW16link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to + 85°C.
o
OPERATING CHARACTERISTICS, T = 25 C
A
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Unit
Symbol
Parameter
Power Dissipation Capacitance
Outputs enabled
Test Conditions
Typical
Typical
CPD
CL = 0pF, f = 10Mhz
16
19
pF
pF
CPD
Power Dissipation Capacitance
Outputs disabled
4
5
(1)
SWITCHING CHARACTERISTICS
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLH
tPHL
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Propagation Delay
xAx to xYx
1
5.3
—
5.3
1
3.9
ns
tPZH
Output Enable Time
xOE to xYx
1
1
6.4
5.4
—
—
—
—
6.1
4.8
—
1
1
5
ns
tPZL
tPHZ
Output Disable Time
xOE to xYx
4.4
500
ns
ps
tPLZ
tSK(o)
Output skew between any two outputs of the same package and
switching in the same direction.
—
—
tSK(b)
Output skew for outputs in the same bank.
—
—
—
—
—
350
ps
NOTE:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
4
IDT74ALVCH16240
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS:
PROPAGATION DELAY
TEST CONDITIONS
Symbol
(1)
(1)
(2)
VCC = 3.3V±0.3V VCC = 2.7V VCC = 2.5V±0.2V
Unit
V
IH
VLOAD
6
6
2 x Vcc
Vcc
V
SAME PHASE
INPUT TRANSITION
VT
0V
VIH
VT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
V
tPHL
tPLH
VOH
VT
Vcc / 2
150
OUTPUT
VLZ
VHZ
CL
mV
mV
VOL
tPHL
tPLH
150
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
30
pF
NEW16link
ALVC Link
TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES
VLOAD
DISABLE
VCC
ENABLE
VIH
VT
Open
GND
CONTROL
INPUT
500Ω
0V
tPZL
tPLZ
VIN
VOUT
Pulse(1, 2)
Generator
VLOAD/2
VT
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
VLZ
VOL
500Ω
tPHZ
t
PZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
ALVC Link
DEFINITIONS:
0V
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
ALVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SET-UP, HOLD, AND RELEASE TIMES
VIH
DATA
INPUT
SWITCH POSITION
VT
0V
tSU
tH
Test
Switch
VIH
VT
0V
TIMING
INPUT
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
VLOAD
tREM
VIH
VT
0V
ASYNCHRONOUS
CONTROL
GND
Open
VIH
VT
0V
SYNCHRONOUS
CONTROL
tSU
tH
NEW16link
ALVC Link
OUTPUT SKEW - TSK (x)
VIH
VT
0V
INPUT
PULSE WIDTH
tPLH1
tPHL1
VOH
VT
LOW-HIGH-LOW
PULSE
VT
OUTPUT 1
tSK (x)
VOL
tSK (x)
tW
VOH
VT
HIGH-LOW-HIGH
PULSE
VT
OUTPUT 2
VOL
ALVC Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVCH16240
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
ORDERINGINFORMATION
XX
Device Type Package
XX
ALVC
X
XX
XXX
IDT
Bus-Hold
Family
Temp. Range
Shrink Small Outline Package (SO48-1)
Thin Shrink Small Outline Package (SO48-2)
Thin Very Small Outline Package (SO48-3)
PV
PA
PF
240
16
16-Bit Buffer/Driver with 3-State Outputs
Double-Density with Resistors, ±24mA
H
Bus-Hold
74
-40°C to +85°C
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6
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