74ALVCH16244/D [ETC]
Low-Voltage 16-Bit Buffer with Bus Hold 1.8/2.5/3.3 V ; 低电压16位缓冲器与总线保持1.8 / 2.5 / 3.3 V\n
| 型号： | 74ALVCH16244/D |
| 厂家： | 
ETC |
| 描述： | Low-Voltage 16-Bit Buffer with Bus Hold 1.8/2.5/3.3 V
|
| 文件： | 总12页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ALVCH16244
Low-Voltage 16-Bit Buffer
with Bus Hold 1.8/2.5/3.3 V
(3–State, Non–Inverting)
The 74ALVCH16244 is an advanced performance, non–inverting
16–bit buffer. It is designed for very high–speed, very low–power
operation in 1.8 V, 2.5 V or 3.3 V systems.
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The 74ALVCH16244 is nibble controlled with each nibble
functioning identically, but independently. The control pins may be
tied together to obtain full 16–bit operation. The 3–state outputs are
controlled by an Output Enable (OEn) input for each nibble. When
OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are
in the high impedance state. The data inputs include active bushold
circuitry, eliminating the need for external pull–up resistors to hold
unused or floating inputs at a valid logic state.
MARKING DIAGRAM
48
48
74ALVCH16244DT
AWLYYWW
1
TSSOP–48
DT SUFFIX
CASE 1201
• Designed for Low Voltage Operation: V = 1.65 – 3.6 V
CC
1
= Assembly Location
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 3.0 ns max for 3.0 to 3.6 V
3.7 ns max for 2.3 to 2.7 V
A
WL = Wafer Lot
6.0 ns max for 1.65 to 1.95 V
YY = Year
WW = Work Week
• Static Drive:
±24 mA Drive at 3.0 V
±12 mA Drive at 2.3 V
±4 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
ORDERING INFORMATION
• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
Device
Package
Shipping
†
• I
Specification Guarantees High Impedance When V = 0 V
CC
OFF
74ALVCH16244DTR TSSOP 2500/Tape & Reel
• Near Zero Static Supply Current in All Three Logic States (40 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance: Human Body Model >2000V; Machine Model >200V
• Second Source to Industry Standard 74ALVCH16244
†To ensure the outputs activate in the 3–state condition, the output enable pins
should be connected to V through a pull–up resistor. The value of the resistor is
CC
determined by the current sinking capability of the output connected to the OE pin.
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
September, 2002 – Rev. 1
74ALVCH16244/D
74ALVCH16244
1
25
24
OE1
O0
1
2
3
4
5
6
7
8
9
48 OE2
47 D0
46 D1
45 GND
44 D2
43 D3
OE1
OE3
OE4
48
OE2
O1
GND
O2
D0:3
D4:7
O0:3
O4:7
D8:11
O8:11
O3
V
CC
42
V
CC
D12:15
O12:15
O4
O5
41 D4
40 D5
39 GND
38 D6
37 D7
36 D8
35 D9
34 GND
33 D10
32 D11
One of Four
GND 10
O6 11
Figure 2. Logic Diagram
O7 12
O8 13
O9 14
1
GND 15
O10 16
O11 17
EN1
EN2
EN3
EN4
OE1
OE2
OE3
OE4
48
25
24
V
18
31
V
CC
2
3
CC
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1
1
1
2
O0
D0
D1
O12 19
O13 20
GND 21
O14 22
O15 23
OE4 24
30 D12
29 D13
28 GND
27 D14
26 D15
25 OE3
O1
5
O2
D2
6
O3
O4
D3
D4
8
9
O5
D5
11
12
13
14
16
17
19
20
22
23
O6
D6
1
1
3
4
O7
O8
D7
D8
O9
D9
O10
O11
O12
O13
O14
O15
D10
D11
D12
D13
D14
D15
Figure 1. 48–Lead Pinout
(Top View)
PIN NAMES
Pins
Function
Figure 3. IEC Logic Diagram
OEn
D0–D15
O0–O15
Output Enable Inputs
Inputs
Outputs
OE1
D0:3
L
O0:3
OE2
D4:7
L
O4:7
OE3
L
D8:11
O8:11
OE4
L
D12:15
O12:15
L
L
L
H
Z
L
L
L
H
Z
L
H
X
L
H
Z
L
H
X
L
H
Z
H
H
L
L
H
X
H
X
H
H
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level and Transitions Are Acceptable, for
reasons, DO NOT FLOAT Inputs
I
CC
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2
74ALVCH16244
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
*0.5 to )4.6
*0.5 to )4.6
*0.5 to )4.6
*50
Unit
V
V
V
V
DC Supply Voltage
CC
I
DC Input Voltage
V
DC Output Voltage
V
O
I
I
I
I
I
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
V < GND
mA
mA
mA
mA
mA
°C
IK
I
V
< GND
O
*50
OK
O
$50
$100
CC
GND
$100
T
T
T
*65 to )150
260
STG
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 2)
Moisture Sensitivity
°C
L
)150
°C
J
q
90
°C/W
JA
MSL
Level 1
F
R
Flammability Rating
Oxygen Index: 30 to 35
UL 94 V–O @ 0.125 in
V
ESD
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
u2000
u200
N/A
V
I
Latch–Up Performance
Above V and Below GND at 125°C (Note 6)
$
2
5
0
mA
LATCH–UP
CC
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
1. I absolute maximum rating must be observed.
O
2. Measured with minimum pad spacing on an FR4 board, using 10 mm–by–1 inch, 2–ounce copper trace with no air flow.
3. Tested to EIA/JESD22–A114–A.
4. Tested to EIA/JESD22–A115–A.
5. Tested to JESD22–C101–A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
Supply Voltage
Operating
Data Retention Only
2.3
1.5
3.6
3.6
V
V
V
Input Voltage
(Note 7)
–0.5
3.6
V
V
I
Output Voltage
(Active State)
(3–State)
0
0
3.6
3.6
O
T
Operating Free–Air Temperature
Input Transition Rise or Fall Rate
*
4
0
)
8
5
°C
A
Dt/DV
V
CC
V
CC
= 2.5 V
= 3.0 V
$
0.2 V
0.3 V
0
0
20
10
ns/V
$
7. Unused inputs may not be left open. All inputs must be tied to a high–logic voltage level or a low–logic input voltage level.
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3
74ALVCH16244
DC ELECTRICAL CHARACTERISTICS
T
= *405C to )855C
A
Min
Max
Symbol
Parameter
Condition
Unit
V
V
V
HIGH Level Input Voltage
(Note 8)
1.65 V v V t 2.3 V
0.65 ꢀ V
1.7
V
IH
CC
CC
2.3 V v V v 2.7 V
CC
2.7 V t V v 3.6 V
2.0
CC
LOW Level Input Voltage
(Note 8)
1.65 V v V t 2.3 V
0.35 ꢀ V
0.7
V
V
IL
CC
CC
2.3 V v V v 2.7 V
CC
2.7 V t V v 3.6 V
0.8
CC
HIGH Level Output Voltage
1.65 V v V v 3.6 V; I
=
*
1
0
0
m
A
V
CC
*
0
.
2
OH
CC
OH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V; I
=
*
4
m
A
1.20
OH
= 2.3 V; I
= 2.3 V; I
= 2.7 V; I
= 3.0 V; I
= 3.0 V; I
=
*
6
m
A
2.0
1.7
2.2
2.4
2.0
OH
OH
OH
OH
OH
=
=
=
=
*12 mA
*12 mA
*12 mA
*24 mA
V
LOW Level Output Voltage
1.65 V v V v 3.6 V; I = 100 mA
0.2
0.45
0.4
V
OL
CC
OL
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V; I = 4 mA
OL
= 2.3 V; I = 6 mA
OL
= 2.3 V; I = 12 mA
0.7
OL
= 2.7 V; I = 12 mA
0.4
OL
= 3.0 V; I = 24 mA
0.55
$5.0
$500
OL
I
I
Input Leakage Current
1.65 V v V v 3.6 V; 0 V v V v 3.6 V
mA
mA
I
CC
I
Minimum Bus–hold Input
Current
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.6 V; V = 0 to 3.6 V
IN
I(HOLD)
= 3.0 V, V = 0.8 V
75
*75
45
IN
= 3.0 V, V = 2.0 V
IN
= 2.3 V, V = 0.7 V
IN
= 2.3 V, V = 1.7 V
*45
25
IN
= 1.65 V, V = 0.58 V
IN
= 1.65 V, V = 1.07 V
*25
IN
I
I
I
3–State Output Current
1.65 V v V v 3.6 V; 0 V v V v 3.6 V; V = V or V
IL
$10
10
mA
mA
mA
OZ
CC
O
I
IH
Power–Off Leakage Current
V = 0 V; V or V = 3.6 V
CC I O
OFF
CC
Quiescent Supply Current
(Note 9)
1.65 V v V v 3.6 V; V = GND or V
CC
40
CC
I
1.65 V v V v 3.6 V; 3.6 V v V, V v 3.6 V
$40
750
CC
I
O
DI
Increase in I per Input
2.7 V t V ≤ 3.6 V; V = V * 0.6 V
mA
CC
CC
CC
IH
CC
8. These values of V are used to test DC electrical characteristics only.
I
9. Outputs disabled or 3–state only.
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4
74ALVCH16244
AC CHARACTERISTICS (Note 10; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 W)
Limits
= –40°C to +85°C
T
A
V
CC
= 3.0 V to 3.6 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 1.65 V – 1.95 V
Min
1.0
Max
Min
1.0
Max
Min
1.0
Max
Symbol
Parameter
Waveform
Unit
t
t
Propagation Delay
Input to Output
1
3.0
3.0
3.7
3.7
6.0
6.0
ns
PLH
1.0
1.0
1.0
PHL
t
t
Output Enable Time to
High and Low Level
2
2
1.0
1.0
4.4
4.4
1.0
1.0
5.7
5.7
1.0
1.0
8.2
8.2
ns
ns
ns
PZH
PZL
t
t
Output Disable Time From
High and Low Level
1.0
1.0
4.1
4.1
1.0
1.0
5.2
5.2
1.0
1.0
6.8
6.8
PHZ
PLZ
t
t
Output–to–Output Skew
(Note 11)
0.5
0.5
0.5
0.5
0.75
0.75
OSHL
OSLH
10.For C = 50 pF, add approximately 300 ps to the AC maximum specification.
L
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t
guaranteed by design.
) or LOW–to–HIGH (t
); parameter
OSHL
OSLH
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Input Capacitance
Condition
Note 12
Typical
Unit
pF
C
C
C
6
7
IN
Output Capacitance
Note 12
pF
OUT
PD
Power Dissipation Capacitance
Note 12, 10 MHz
20
pF
12.V = 1.8, 2.5 or 3.3 V; V = 0 4 V or V .
CC
CC
I
V
IH
V
V
m
Dn
On
m
0 V
t
t
PHL
PLH
V
OH
OL
V
m
V
m
V
WAVEFORM 1 - PROPAGATION DELAYS
= t = 2.0 ns, 10% to 90%; f = 1 MHz; t = 500 ns
t
R
F
W
V
IH
V
m
OEn
0 V
t
t
PHZ
PZH
V
OH
V
y
V
V
On
m
≈ 0 V
t
t
PLZ
PZL
≈ V
CC
On
m
V
x
V
OL
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES
t
R
= t = 2.0 ns, 10% to 90%; f = 1 MHz; t = 500 ns
F W
Figure 4. AC Waveforms
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5
74ALVCH16244
V
CC
3.3 V ±0.3 V
2.5 V ±0.2 V
1.8 V ±0.15 V
Symbol
V
IH
2.7 V
V
CC
V
CC
V
m
1.5 V
V
CC
/2
V
CC
/2
V
V
+ 0.3 V
– 0.3 V
V
+ 0.15 V
– 0.15 V
V
+ 0.15 V
– 0.15 V
x
OL
OL
OL
V
y
V
OH
V
OH
V
OH
V
CC
6V or V × 2
CC
OPEN
GND
R
L
PULSE
GENERATOR
DUT
R
T
C
L
R
L
TEST
SWITCH
t
t
, t
Open
PLH PHL
, t
6 V at V = 3.3 ±0.3 V;
CC
× 2 at V = 2.5 ±0.2 V; 1.8 ±0.15 V
PZL PLZ
V
CC
CC
t
, t
GND
PZH PHZ
C = 50 pF for V = 3.0 ± 0.3 V
L
CC
R = 500 W or equivalent
L
R = Z
of pulse generator (typically 50 W)
T
OUT
Figure 5. Test Circuit
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74ALVCH16244
10 PITCHES
CUMULATIVE
TOLERANCE ON
TAPE
±0.2 mm
(±0.008")
P
0
K
t
P
2
D
TOP
COVER
TAPE
E
A
B
SEE NOTE 2
+
0
F
W
+
+
K
0
B
1
0
SEE
NOTE 2
D
1
P
FOR COMPONENTS
2.0 mm × 1.2 mm
AND LARGER
EMBOSSMENT
USER DIRECTION OF FEED
CENTER LINES
OF CAVITY
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B
0
*TOP COVER
TAPE THICKNESS (t )
1
0.10 mm
(0.004") MAX
R MIN
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS R"
WITHOUT DAMAGE
EMBOSSED
CARRIER
BENDING RADIUS
EMBOSSMENT
100 mm
(3.937")
MAXIMUM COMPONENT ROTATION
10°
1 mm MAX
TYPICAL
COMPONENT CAVITY
CENTER LINE
TAPE
1 mm
(0.039") MAX
250 mm
(9.843")
TYPICAL
COMPONENT
CENTER LINE
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 6. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS (See Notes 13 and 14)
Tape
Size
B
1
Max
D
D
E
F
K
P
P
0
P
2
R
T
W
1
24mm
20.1mm 1.5 + 0.1mm
(0.791")
1.5mm
Min
(0.060")
1.75
11.5
11.9 mm
Max
(0.468")
16.0
±0.1 mm
(0.63
4.0
±0.1 mm
(0.157
2.0
±0.1 mm
(0.079
30 mm
(1.18")
0.6 mm
(0.024")
24.3 mm
(0.957")
-0.0
(0.059
+0.004" -0.0)
±0.1 mm ±0.10 mm
(0.069
±0.004")
(0.453
±0.004")
±0.004")
±0.004")
±0.004")
13.Metric Dimensions Govern–English are in parentheses for reference only.
14.A , B , and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0
0
0
0.50 mm max. The component cannot rotate more than 10° within the determined cavity.
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7
74ALVCH16244
t MAX
13.0 mm ±0.2 mm
(0.512" ±0.008")
1.5 mm MIN
(0.06")
20.2 mm MIN
(0.795")
50 mm MIN
(1.969")
A
FULL RADIUS
G
Figure 7. Reel Dimensions
REEL DIMENSIONS
Tape Size
A Max
G
t Max
24 mm
360 mm
(14.173")
24.4 mm + 2.0 mm, -0.0
(0.961" + 0.078", -0.00)
30.4 mm
(1.197")
DIRECTION OF FEED
BARCODE LABEL
POCKET
HOLE
Figure 8. Reel Winding Direction
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8
74ALVCH16244
TAPE TRAILER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
TAPE LEADER
NO COMPONENTS
400 mm MIN
COMPONENTS
CAVITY TOP TAPE
TAPE
DIRECTION OF FEED
Figure 9. Tape Ends for Finished Goods
User Direction of Feed
Figure 10. Reel Configuration
F
K
G
L
48 Leads
Figure 11. Package Footprint
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9
74ALVCH16244
PACKAGE DIMENSIONS
TSSOP
DT SUFFIX
CASE 1201–01
ISSUE A
48X K REF
K
K1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.12 (0.005)
T
U
J
J1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
48
25
SECTION N–N
B
–U–
L
N
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
24
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
MILLIMETERS
INCHES
MIN
0.488
A
–V–
PIN 1
IDENT.
DIM MIN
MAX
MAX
0.496
0.244
0.043
0.006
0.030
A
B
12.40
6.00
---
12.60
6.20 0.236
1.10 ---
N
C
M
F
D
0.05
0.50
0.15 0.002
0.75 0.020
F
0.25 (0.010)
DETAIL E
G
H
0.50 BSC
0.0197 BSC
0.37
0.09
0.09
0.17
0.17
7.95
0
--- 0.015
0.20 0.004
0.16 0.004
0.27 0.007
0.23 0.007
8.25 0.313
---
0.008
0.006
0.011
0.009
0.325
8
J
J1
K
D
C
K1
L
–W–
0.076 (0.003)
M
8
0
_
_
_
_
DETAIL E
–T–
SEATING
PLANE
H
G
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10
74ALVCH16244
Notes
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11
74ALVCH16244
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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74ALVCH16244/D
相关型号：
74ALVCH16244DGG,11
74ALVC(H)16244 - 2.5 V / 3.3 V 16-bit buffer/line driver (3-State) TSSOP 48-Pin
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74ALVCH16244DGG,118
IC ALVC/VCX/A SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, ROHS COMPLIANT, PLASTIC, MO-153, SOT362-1, TSSOP-48, Bus Driver/Transceiver
NXP
74ALVCH16244DGG-T
IC ALVC/VCX/A SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48, Bus Driver/Transceiver
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74ALVCH16244DGG:11
74ALVC(H)16244 - 2.5 V / 3.3 V 16-bit buffer/line driver (3-State) TSSOP 48-Pin
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74ALVCH16244DGG:51
74ALVC(H)16244 - 2.5 V / 3.3 V 16-bit buffer/line driver (3-State) TSSOP 48-Pin
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74ALVCH16244DGGRG4
ALVC/VCX/A SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48
TI
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