74ALVCH16240T [FAIRCHILD]
Low Voltage 16-Bit Inverting Buffer/Line Driver with Bushold; 低电压16位反相缓冲器/线路驱动器与Bushold
| 型号： | 74ALVCH16240T |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit Inverting Buffer/Line Driver with Bushold |
| 文件： | 总6页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2001
Revised February 2002
74ALVCH16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with Bushold
General Description
The ALVCH16240 contains sixteen inverting buffers with
Features
3-STATE outputs to be employed as
a memory and
■ 1.65V to 3.6V VCC supply operation
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
■ 3.6V tolerant control inputs and outputs
■ Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
The ALVCH16240 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating inputs at a valid logic level.
■ tPD
3.9 ns max for 3.0V to 3.6V VCC
5.3 ns max for 2.3V to 2.7V VCC
6.0 ns max for 1.65V to 1.95V VCC
The 74ALVCH16240 is designed for low voltage (1.65V to
3.6V) VCC applications with output capability up to 3.6V.
The 74ALVCH16240 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
■ Uses patented noise/EMI reduction circuitry
■ Latch-up conforms to JEDEC JED78
■ ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Package
Order Number
Package Descriptions
Number
74ALVCH16240T
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
Bushold Inputs
I0–I15
O0–O15
Outputs
© 2002 Fairchild Semiconductor Corporation
DS500629
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Connection Diagram
Truth Tables
Inputs
Outputs
OE1
L
I0–I3
L
O0–O3
H
L
L
H
H
X
Z
Inputs
Outputs
OE2
I4–I7
O4–O7
L
L
L
H
X
H
L
H
Z
Inputs
OE3
Outputs
O8–O11
I8–I11
L
L
H
L
H
L
H
X
Z
Inputs
OE4
Outputs
O12–O15
I12–I15
L
L
H
L
H
L
H
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Functional Description
The 74ALVCH16240 contains sixteen inverting buffers with
3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble functioning identically, but independent of
each other. The control pins may be shorted together to
obtain full 16-bit operation.The 3-STATE outputs are con-
trolled by an Output Enable (OEn) input. When OEn is
LOW, the outputs are in the 2-state mode. When OEn is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the inputs.
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to 4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO) (Note 2)
−0.5V to VCC +0.5V
Operating
1.65V to 3.6V
0V to VCC
DC Input Diode Current (IIK
)
Input Voltage (VI)
VI < 0V
−50 mA
−50 mA
±50 mA
Output Voltage (VO)
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (∆t/∆V)
0V to VCC
DC Output Diode Current (IOK
O < 0V
DC Output Source/Sink Current
(IOH/IOL
)
−40°C to +85°C
V
V
IN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
)
DC VCC or GND Current per
Supply Pin (ICC or GND)
±100 mA
Storage Temperature Range (TSTG
)
−65°C to +150°C
Note 2: IO Absolute Maximum Rating must be observed, limited to 4.6V.
Note 3: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Conditions
Min
Max
Units
(V)
HIGH Level Input Voltage
1.65 - 1.95 0.65 x VCC
2.3 - 2.7
2.7 - 3.6
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
1.65 - 3.6
1.65
1.7
2.0
V
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.35 x VCC
0.7
V
V
0.8
VOH
IOH = −100 µA
IOH = −4 mA
IOH = −6 mA
IOH = −12 mA
VCC - 0.2
1.2
2.3
2.0
2.3
1.7
2.7
2.2
3.0
2.4
I
I
I
I
I
OH = −24 mA
OL = 100 µA
OL = 4 mA
3.0
2
VOL
LOW Level Output Voltage
1.65 - 3.6
1.65
0.2
0.45
0.4
OL = 6 mA
2.3
V
OL = 12 mA
2.3
0.7
2.7
0.4
I
OL = 24 mA
3.0
0.55
±5.0
II
Input Leakage Current
Bushold Input Minimum
Drive Hold Current
0 ≤ VI ≤ 3.6V
3.6
µA
II(HOLD)
VIN = 0.58V
VIN = 1.07V
VIN = 0.7V
VIN = 1.7V
VIN = 0.8V
VIN = 2.0V
1.65
25
−25
45
1.65
2.3
2.3
−45
75
µA
3.0
3.0
−75
0 < VO ≤ 3.6V
0 ≤ VO ≤ 3.6V
3.6
±500
±10
40
IOZ
3-STATE Output Leakage
Quiescent Supply Current
Increase in ICC per Input
3.6
µA
µA
µA
ICC
VI = VCC or GND, IO = 0
IH = VCC − 0.6V
3.6
∆ICC
V
3 - 3.6
750
3
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AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500Ω
C
L = 50 pF
C
L = 30 pF
CC = 1.8V ± 0.15V
Symbol
Parameter
Units
V
CC = 3.3V ± 0.3V
VCC = 2.7V
V
CC = 2.5V ± 0.2V
V
Min
1.0
1.0
1.0
Max
3.9
5
Min
Max
5.3
6.1
4.8
Min
1.0
1.0
1.0
Max
5.3
6.4
5.4
Min
1.5
1.5
1.5
Max
6.0
8.2
6.8
t
t
PHL, tPLH
PZL, tPZH
Propagation Delay
ns
ns
ns
Output Enable Time
Output Disable Time
tPLZ, tPHZ
4.4
Capacitance
T
A = +25°C
Symbol
Parameter
Conditions
Units
VCC
Typical
CIN
Input Capacitance
Control
Data
VI = 0V or VCC
VI = 0V or VCC
VI = 0V or VCC
3.3
3.3
3.3
3.3
2.5
3.3
2.5
3
6
pF
pF
COUT
CPD
Output Capacitance
Power Dissipation Capacitance
7
Outputs Enabled f = 10 MHz, CL = 50 pF
19
16
5
pF
Outputs Disabled f = 10 MHz, CL = 50 pF
4
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4
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
SWITCH
Open
VL
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω)
VCC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
2.5V ± 0.2V
VCC/2
1.8V ± 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
1.5V
VCC/2
VCC/2
V
OL + 0.3V
V
OL + 0.3V
V
OL + 0.15V
VOL + 0.15V
VY
V
OH − 0.3V
V
OH − 0.3V
V
OH − 0.15V
V
OH − 0.15V
VL
6V
6V
VCC*2
VCC*2
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
5
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Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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