MK9173-01_技术文档

Integrated

Circuit

Systems, Inc.

MK9173-01

MK9173-15

Video Genlock PLL

General Description

Features

•

Designed to replace the AV9173 in most applications

Phase-detector/VCO circuit block

Ideal for genlock system

The MK9173-01 and MK9173-15 provide the analog PLL

circuit blocks to implement a frequency multiplier. Because

the device is configured to use an external divider in the PLL

clock feedback path, a large divider can be used to result in a

large frequency multiplication ratio. This is useful when using

a low frequency input clock to generate a high frequency

output clock. The MK9173-01/15 contains a phase detector,

charge pump, loop filter, and voltage-controlled oscillator

(VCO). The ICS674-01 can be used as the external feedback

divider.

Reference clock range 12 kHz to 1MHz for full

output clock range

•

Output clock range 1.25 to 75 MHz (-01), 0.625 to

37.5 MHz (-15), see Table 1 for conditions

On-chip loop filter

•

Single 5 volt power supply

Low power CMOS technology

Small 8-pin SOIC package

A common application of the MK9173-01/-15 is the

implementation of a video genlock circuit. Because of this,

the MK9173-01/-15 inputs operate on the negative-going

clock edge.

The MK9173-01/15 is pin and function compatible to the

AV9173-01/15. Please refer to page 4 regarding performance

differences. For new video genlock designs, please refer to the

ICS673-01, ICS1522 or ICS1523.

Block Diagram

Integrated Circuit Systems, Incorporated • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800tel • www.icst.com

MDS 9173-01/15 B

121400

MK9173-01

MK9173-15

Pin Configuration

PinDescriptions

NUMBER

PIN NAME

TYPE

DESCRIPTION

1

2

3

4

5

6

7

8

FBIN

IN

GND

FS0

Input

—

Input

Output

—

Feedback Input

Input for reference sync pulse

Ground

Frequency Select 0 input

Output Enable

Clock Output 1

OE

CLK1

VDD

CLK2

Power Supply (+5V)

Clock Output 2 (Divided-by-2 from Clock 1)

Output

Table 1: Allowable Input Frequency to Output Frequency (Outputs in MHz)MK9173-01

(MK9173-15 outputs run at exactly 1/2 the MK9173-01 frequencies)

fIN (kHz)

fOUT for FS = 0 (MHz)

fOUT for FS = 1 (MHz)

CLK1 Output

CLK2 Output

22.0 to 37.5

15.0 to 37.5

12.5 to 37.5

7.5 to 37.5

5.0 to 37.5

CLK1 Output

CLK2 Output

5.5 to 9.375

3.75 to 9.375

3.125 to 9.375

1.875 to 9.375

1.25 to 9.375

12 ≤ fIN ≤ 14 kHz

14 < fIN ≤ 17 kHz

17 < fIN ≤ 30 kHz

30 < fIN ≤ 35 kHz

35 < fIN ≤ 1000 kHz

44.0 to 75

30.0 to 75

25.0 to 75

15.0 to 75

10.0 to 75

11.0 to 18.75

7.5 to 18.75

6.25 to 18.75

3.75 to 18.75

2.5 to 18.75

Integrated Circuit Systems, Incorporated • 525 Race Street •San Jose • CA• 95126 • (408) 295-9800 tel • www.icst.com

2

MK9173-01

MK9173-15

Using the MK9173-01/15 in

GenlockApplications

Most video sources, such as video cameras, are asynchronous, AC specifications (VCO frequency), an input as low as 12kHz

free-running devices. To digitize video or synchronize one

video source to another free-running reference video source, a

video “genlock” (generator lock) circuit is required. The

MK9173-01 and MK9173-15 integrate the analog blocks

which make the task much easier.

(such as NTSC or PAL H-SYNC) can be used.

The output hook-ups of the MK9173-01 and MK9173-15 are

dictated by the desired dot clock frequency. The primary

consideration is the internal VCO which operates over a

frequency range of 10 MHz to 75 MHz. Because of the

In the complete video genlock circuit, the primary function of selectable VCO output divider and the additional divider on

the MK9173-01 and MK9173-15 is to provide the analog output CLK2, four distinct output frequency ranges can be

circuitry required to generate the video dot clock within a achieved. The following Table lists these ranges and the

PLL. This application is illustrated in Figure 1. The input

reference signal for this circuit is the horizontal

synchronization (H-SYNC) signal. If a composite video

reference source is being used, the h-sync pulses must be

separated from the composite signal. A video sync separator

circuit, such as the National Semiconductor LM1881, can be

used for this purpose.

corresponding device configuration.

Frequency Range

MK9173-01

Frequency Range

MK9173-15

FS0 State

Output Used

CLK1

CLK2

CLK1

CLK2

10 - 75 MHz

5 - 37.5 MHz

2.5 - 18.75 MHz

1.25 - 9.375 MHz

0.625-4.6875 MHz

0

1

5 - 37.5 MHz

2.5 - 18.75 MHz

1.25 - 9.375 MHz

The clock feedback divider shown in Figure 1 is a digital

divider used within the PLL to multiply the reference

frequency. Its divide ratio establishes how many video dot

Note that both outputs, CLK1 and CLK2, are available during

operation even though only one is fed back via the external

clock cycles occur per h-sync pulse. For example, if 880 pixel clock divider.

clocks are desired per h-sync pulse, then the divider ratio is set

Pin 5, OE, tristates both CLK1 and CLK2 upon logic low

to 880. Hence, together the h-sync frequency and external

divider ratio establish the dot clock frequency:

input. This feature can be used to revert dot clock control to

the system clock when not in genlock mode (hence, when in

genlock mode the system dot clock must be tristated).

f

_OUT= f_{I N}• N where N is external divide ratio

Both input pins IN and FBIN respond only to negative-going

clock edges of the input signal. The H-SYNC signal must be

constant frequency in the 12 kHz to 1MHz range and stable

(low clock jitter) for creation of a stable output clock.

When unused, inputs FS0 and OE must be tied to either GND

(logic low) or VDD (logic high).

For further discussion of VCO/PLL operation as it applies to

the MK9173-01 and MK9173-15, please refer to the AV9170

application note. The AV9170 is a similar device with fixed

feedback dividers for skew control applications.

Refer to Application Brief (AB01) for additional details on

use of input frequencies below 25kHz. By following the

guidelines in this brief and meeting the test conditions in the

Figure 1: Typical Application of MK9173-01/-15 in a Video Genlock System

Integrated Circuit Systems, Incorporated• 525 Race Street • San Jose •CA • 95126 • (408) 295-9800tel • www.icst.com

3

MK9173-01

MK9173-15

Using the MK9173-01/15 to

replacetheAV9173-01/15

Increasing leadtimes from our wafer fab on the AV917x family

of products led us to introduce the MK917x family. The

MK917x have been designed for a 0.6 micron CMOS process,

whereas the AV917x devices are on a 1.2 micron process.

There are characteristic differences between the old and new

products which may lead to problems in the application. The

most commonly reported problem is increased jitter.

2. Due to differences in behavior between the AV and MK

parts, the MK parts may not be a viable substitute in some

applications. Accordingly, ICS is working to establish a new

source of supply for the AV part.

3. Keep in mind the following advice for PLLs, which might

help you troubleshoot problems in migrating to the MK917x

family:

Design Considerations

a) Don't open the external clock feedback path. In doing so,

the MK917x will start to run as its maximum frequency, which

might be faster than the logic in your feedback path is able to

handle.

The primary difference between old (AV) and new (MK)

products is that the MK series is built on a faster process. To

compensate for this process difference, we recommend the

following design considerations.

b) Fast transitions on the input pins reduce jitter. Remove any

filters or unneeded loads on the inputs.

1. Because the MK series is faster, good power supply

decoupling is more important. A board layout which works

well with the AV parts may require better decoupling to work

with the MK parts. The recommended decoupling is 0.01 uF

mounted as close as possible (within 0.2") to the VDD pin (if a

larger value device is in place, such as a 0.1 uF, try replacing

this with a 0.01 uF device). To determine if improved

decoupling would help performance, connect a disc capacitor

directly across the VDD and ground pins. Trim the leads as

short as possible.

c) Terminate the clock output lines properly. Try adding a 33

ohm series termination resistor.

For new video genlock applications, please consider the

ICS673-01, ICS1522, or ICS1523.

Integrated Circuit Systems, Incorporated • 525 Race Street •San Jose • CA• 95126 • (408) 295-9800 tel • www.icst.com

4

MK9173-01

MK9173-15

Absolute Maximum Ratings

V_DD(referenced to GND) . . . . . . . . . . . . . . 7.0V

Operating Temperature under Bias . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . – 65°C to +150°C

Voltage on I/O pins referenced to GND. . . . . GND – 0.5V to V_DD+ 0.5V

Power Dissipation . . . . . . . . . . . . . . . . . . . . 0.5 watts

Stresses above those listed underAbsolute Maximum Ratingsabove may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other conditions above those listed in the operational sections

of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product

reliability.

Electrical Characteristic

V_DD= +5V ±5%, T_A= 0°C to 70°C, unless otherwise stated

DC CHARACTERISTICS

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Input Low Voltage

Input High Voltage

Input Low Current

Input High Current

Output Low Voltage¹

Output High Voltage¹

VIL

VIH

IIL

IIH

VOL

VOH1

VDD = 5V

VIN = 0V

VIN = VDD

IOL = 8mA

IOH = -1mA,

VDD = 5.0V

IOH = -4mA,

VDD = 5.0V

—

2.0

-5

—

0.8

—

5

0.4

—

V

µA

V

VDD -0.4V

V

Output High Voltage¹

VOH2

VDD -0.8V

—

V

Output High Voltage¹

Supply Current

VOH3

IDD

IOH = -8mA

Unloaded, 50 MHZ

2.4

—

20

—

50

V

mA

Notes:

1. Duty cycle measured at 1.4V.

2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical pixels.

3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4.

Integrated Circuit Systems, Incorporated• 525 Race Street • San Jose •CA • 95126 • (408) 295-9800tel • www.icst.com

5

MK9173-01

MK9173-15

Electrical Characteristics

V_DD= +5V ±5%, T_A= 0°C to 70°C, unless otherwise stated

AC CHARACTERISTICS

PARAMETER

S Y M B O L

TEST CONDITIONS

MIN

T Y P

MAX

UNITS

Input Clock Rise Time¹

Input Clock Fall Time¹

Output Rise Time¹

ICLK r

I C L K f

tr1

—

0.6

10

1.5

ns

15pF load; 0.8 to 2.0V

15pF load;

Output Rise time¹

Output Fall time¹

Output Duty Cycle¹

t r2

tf1

t f2

—

1.4

0.8

3.0

2.0

ns

20% to 80% VDD

15pF load; 2.0 to 0.8V

15pF load;

80% to 20% VDD

d t

15pF load

40

—

-400

—

47

120

±250

—

± 4

—

55

250

400

1

2

—

%

ps

%

ns

1 ,5

Jitter, one sigma

T1s1

Ta b s 1

T1s2

Ta b s 2

T L abs

fi n

CLK1 frequency ³ 2 5 M H z

CLK1 frequency < 25 MHz

5

Jitter, absolute^1,

1, 5

Jitter, one sigma

5

Jitter, absolute^1,

Line-to-line jitter,¹absolute²

Input Frequency,¹IN or FBIN

See allowable fi b e l o w :

12 ≤ fin ≤ 14 kHz

14 < fin ≤ 17 kHz

17 < fin ≤ 30 kHz

30 < fi n ≤ 35 kHz

35 < fi n ≤ 1000 kHz

12 ≤ fin ≤ 14 kHz

14 < fin ≤ 17 kHz

17 < fin ≤ 30 kHz

30 < fin ≤ 35 kHz

35 < fin ≤ 1000 kHz

12

1000

75

k H z

MHz

44.0

30.0

25.0

15.0

10.0

22.0

15.0

12.5

7.5

CLK1 Frequency^{1, 3, 4}

MK9173-01

fC L K 1

—

75

37.5

CLK1 Frequency^{1, 3, 4}

MK9173-15

fC L K 1

5.0

Notes:

1. Parameter is guaranteed by design and characterization. Not 100% tested in production.

2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical pixels.

3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4.

4. An Application Brief (AB01) documents the operation of the AV9173 for low input frequencies. This provides

guidelines for usable output frequencies and feedback ratios required to use inputs below 25 kHz. By following these

guidelines, the MK9173 will operate down to 12 kHz inputs across temperature, voltage and lot-to-lot variation.

5. Jitter values are measured at frequencies ≥25 MHz for MK9173-01, for MK9173-15, jitter is measured at frequency

≥12.5 MHz.

Integrated Circuit Systems, Incorporated • 525 Race Street •San Jose • CA• 95126 • (408) 295-9800 tel • www.icst.com

6

MK9173-01

MK9173-15

8-Pin SOIC PACKAGE

Millimeters

Inches

Symbol

Min

1.35

Max

Min

0.0532

0.0040

0.013

Max

0.0688

0.0098

0.020

A

A1

B

C

D

E

1.75

0.25

0.51

0.25

5.00

4.00

1.10

E H

0.33

0.19

0.0075

.1890

0.0098

.1968

4.80

3.80

0.1497

0.050 Basic

0.2284

0.010

0.1574

D

h x 45⁰

e

1.27 Basic

5.80

H

h

6.20

0.50

1.27

8°

0.2440

0.020

0.050

8°

0.25

A

L

0.40

0.016

Q

c

a

0°

e

b

Ordering Information

Order Number

Part Marking Package

Shipping

Packaging

MK9173-01CS08 MK73-1

MK9173-01CS08T MK73-1

MK9173-15CS08 MK73-15

MK9173-15CS08T MK73-15

8 pin SOIC Tubes

8 pin SOIC Tape and Reel

8 pin SOIC Tubes

8 pin SOIC Tape and Reel

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no

responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No

other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications

such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS

does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

Integrated Circuit Systems, Incorporated• 525 Race Street • San Jose •CA • 95126 • (408) 295-9800tel • www.icst.com

7


型号：	MK9173-01
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	Video Genlock PLL 视频同步锁相PLL
文件：	总7页 (文件大小：163K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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