MK9173-01CS08LF [IDT]
PLL Based Clock Driver, 9173 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, SOIC-8;
| 型号： | MK9173-01CS08LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 9173 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, SOIC-8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
VIDEO GENLOCK PLL
MK9173-01/-15
Description
Features
The MK9173-01/-15 provide the analog PLL circuit blocks
to implement a frequency multiplier. Because the device is
configured to use an external divider in the PLL clock
feedback path, a large divider can be used to result in a
large frequency multiplication ratio. This is useful when
using a low frequency input clock to generate a high
frequency output clock. The MK9173-01/-15 contains a
phase detector, charge pump, loop filter, and
• Phase-detector/VCO circuit block
• Ideal for genlock system
• Reference clock range 12 kHz to 1 MHz for full output
clock range
• Output clock range of 1.25 to 75 MHz (-01), and 0.625 to
37.5 MHz (-15). See “Allowable Input Frequency to
Output Frequency” table for conditions
voltage-controlled oscillator (VCO). The ICS674-01 can be
used as the external feedback divider.
• On-chip loop filter
• Single 5 V power supply
• Low power CMOS technology
• 8-pin SOIC package
A common application of the MK9173-01/-15 is the
implementation of a video genlock circuit. Because of this,
the MK9173-01/-15 inputs operate on the negative-going
clock edge.
• For new video genlock applications, please refer to the
ICS673-01, ICS1522 or ICS1523.
The MK9173-01/-15 is pin and function compatible to the
AV9173-01/15.
Block Diagram
IDT™ VIDEO GENLOCK PLL
1
MK9173-01/-15
REV C 12/21/06
MK9173-01/-15
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
Pin Assignment
FBIN
IN
8
7
6
5
1
2
3
4
CLK2
VDD
CLK1
OE
GND
FS0
8 pin SOIC
Pin Descriptions
Pin Number Pin Name
Pin Type
Input
Pin Description
1
2
3
4
5
6
7
8
FBIN
IN
Feedback input.
Input
Input for reference sync pulse.
Ground.
GND
FS0
OE
Power
Input
Frequency select 0 input.
Output enable.
Input
CLK1
VDD
CLK2
Output
Power
Output
Clock output 1.
Power supply (+5 V).
Clock output 2.
Allowable Input Frequency to Output Frequency for MK9173-01 (in MHz)
(MK9173-15 outputs run at exactly half of the MK9173-01 frequencies)
fOUTfor FS = 0
fOUTfor FS = 1
CLK1 Output
CLK2 Output
22.0 to 37.5
15.0 to 37.5
12.5 to 37.5
7.5 to 37.5
CLK1 Output
CLK2 Output
5.5 to 9.375
f
IN (kHz)
12 < f < 14 kHz
44.0 to 75
30.0 to 75
25.0 to 75
15.0 to 75
10.0 to 75
11.0 to 18.75
7.5 to 18.75
6.25 to 18.75
3.75 to 18.75
2.5 to 18.75
IN
14 < f < 17 kHz
3.75 to 9.375
3.125 to 9.375
1.875 to 9.375
1.25 to 9.375
IN
17 < f < 30 kHz
IN
30 < f < 35 kHz
IN
35 < f < 1000 kHz
5.0 to 37.5
IN
IDT™ VIDEO GENLOCK PLL
2
MK9173-01/-15
REV C 12/21/06
MK9173-01/-15
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
Using the MK9173-01/-15 in Genlock Applications
Most video sources, such as video cameras, are
asynchronous, free-running devices. To digitize video or
synchronize one video source to another free-running
reference video source, a video “genlock” (generator lock)
circuit is required. The MK9173-01/-15 integrate the analog
blocks which make the task much easier.
The output hook-ups of the MK9173-01/-15 are dictated by
the desired dot clock frequency. The primary consideration
is the internal VCO which operates over a frequency range
of 10 MHz to 75 MHz. Because of the selectable VCO
output divider and the additional divider on output CLK2,
four distinct output frequency ranges can be achieved. The
following Table lists these ranges and the corresponding
device configuration.
In the complete video genlock circuit, the primary function of
the MK9173-01/-15 is to provide the analog circuitry
required to generate the video dot clock within a PLL. This
application is illustrated in Figure 1. The input reference
signal for this circuit is the horizontal synchronization
(H-SYNC) signal. If a composite video reference source is
being used, the h-sync pulses must be separated from the
composite signal. A video sync separator circuit, such as the
National Semiconductor LM1881, can be used for this
purpose.
FS0
Output Frequency /Range Frequency /Range
State
Used
CLK1
CLK2
CLK1
CLK2
MK9173-01
MK9173-15
0
0
1
1
10 to 75 MHz
5 to 37.5 MHz
5 to 37.5 MHz
2.5 to 18.75 MHz
2.5 to 18.75 MHz
1.25 to 9.375 MHz
1.25 to 9.375 MHz 0.625 to 4.6875 MHz
Note that both outputs, CLK1 and CLK2, are available
during operation even though only one is fed back via the
external clock divider.
The clock feedback divider shown in Figure 1 is a digital
divider used within the PLL to multiply the reference
frequency. Its divide ratio establishes how many video dot
clock cycles occur per h-sync pulse. For example, if 880
pixel clocks are desired per h-sync pulse, then the divider
ratio is set to 880. Hence, together the h-sync frequency and
external divider ratio establish the dot clock frequency:
Pin 5, OE, tristates both CLK1 and CLK2 upon logic low
input. This feature can be used to revert dot clock control to
the system clock when not in genlock mode (hence, when in
genlock mode the system dot clock must be tristated).
f
= f x N where N is external divide ratio
IN
OUT
When unused, inputs FS0 and OE must be tied to either
GND (logic low) or VDD (logic high).
Both input pins IN and FBIN respond only to negative-going
clock edges of the input signal. The H-SYNC signal must be
constant frequency in the 12 kHz to 1 MHz range and stable
(low clock jitter) for creation of a stable output clock.
Figure 1: Typical Application of MK9173-01/-15 in a Video Genlock System
IDT™ VIDEO GENLOCK PLL
3
MK9173-01/-15
REV C 12/21/06
MK9173-01/-15
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK9173-01/-15. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
Storage Temperature
7 V
-65 to +150°C
Voltage on I/O Pins referenced to GND
Junction Temperature
GND - 0.5 V to VDD + 0.5 V
125°C
Soldering Temperature
260°C
Power Dissipation
0.5 Watts
Recommended Operation Conditions
Parameter
Min.
-0
Typ.
Max.
+70
Units
°C
Operating Temperature under Bias
Power Supply Voltage (measured with respect to
GND)
+4.75
+5 V
+5.25
V
IDT™ VIDEO GENLOCK PLL
4
MK9173-01/-15
REV C 12/21/06
MK9173-01/-15
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
DC Electrical Characteristics
Unless stated otherwise, VDD = 5 V 5ꢀ, Ambient Temperature 0 to +70°C
Parameter
Operating Supply Current
Input Low Voltage
Symbol
Conditions
No load,50 MHz
VDD = 5 V
Min.
Typ.
Max.
50
Units
mA
V
IDD
20
V
0.8
IH
Input High Voltage
Input Low Current
V
VDD = 5 V
2.0
-5
V
IL
I
VIN = 0V
µA
µA
V
IL
Input High Current
Output Low Voltage
I
VIN = VDD
-5
5
IH
V
I
I
I
I
= 8 mA
= -1 mA
= -4 mA
= -8 mA
0.4
OL
OL
OH
OH
OH
1
Output High Voltage
V
V
V
VDD-0.4
VDD-0.8
2.4
V
OH1
OH2
OH3
1
Output High Voltage
V
1
Output High Voltage
V
Notes:
1. Duty cycle measured at 1.4 V.
2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical
pixels.
3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4.
AC Electrical Characteristics
Unless stated otherwise, VDD = 5 V 5ꢀ, Ambient Temperature 0 to +70° C
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
1
Output Clock Rise Time
ICLK
10
10
ns
ns
ns
ns
ns
ns
%
r
1
Output Clock Fall Time
ICLK
f
1
Output Rise Time
t
t
15 pF load, 20% to 80%
15 pF load, 20% to 80%
15 pF load, 80% to 20%
15 pF load, 80% to 20%
15 pF load
0.6
1.4
0.8
0.8
47
1.5
3.0
2.0
2.0
55
r1
r2
1
Output Rise Time
1
Output Fall Time
t
t
f1
1
Output Fall Time
f2
1
Output Duty Cycle
40
1, 5
3
One-Sigma Jitter
T1 1
CLK1 frequency , 25 MHz
120
250
ps
ps
%
S
1, 5
3
Jitter, Absolute
T
1
CLK1 frequency , 25 MHz
-400
250 400
ABS
1, 5
One-Sigma Jitter
T1 2
CLK1 frequency < 25 MHz
CLK1 frequency < 25 MHz
1
S
1, 5
Jitter, Absolute
T
2
2
%
ABS
1
2
Line-to-Line Jitter , Absolute
T
4
ns
kHz
LABS
1
Input Frequency , IN or FBIN
f
see allowable fi below
12
1000
IN
IDT™ VIDEO GENLOCK PLL
5
MK9173-01/-15
REV C 12/21/06
MK9173-01/-15
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
Parameter
Symbol
Conditions
Min.
44
Typ. Max. Units
1, 3, 4
CLK1 Frequency, -01
CLK1 Frequency, -15
f
12 < f < 14 kHz
75
75
MHz
CLK1
IN
14 < f < 17 kHz
30
IN
17 < f < 30 kHz
25
75
IN
30 < f < 35 kHz
15
75
IN
35 < f < 1000 kHz
10
75
IN
1, 3, 4
f
12 < f < 14 kHz
22
37.5
37.5
37.5
37.5
37.5
MHz
CLK1
IN
14 < f < 17 kHz
15
IN
17 < f < 30 kHz
12.5
7.5
5
IN
30 < f < 35 kHz
IN
35 < f < 1000 kHz
IN
Notes:
1. Parameter is guaranteed by design and characterization. Not 100% tested in production.
2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical
pixels.
3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4.
4. An Application Brief (AB01) documents the operation of the AV9173 for low input frequencies. This provides
guidelines for usable output frequencies and feedback ratios required to use inputs below 25 kHz. By following
these guidelines, the MK9173 will operate down to 12 kHz inputs across temperature, voltage and lot-to-lot
variation.
5. Jitter values are measured at frequencies > 25 MHz for MK9173-01, for MK9173-15, jitter is measured at
frequency > 12.5 MHz.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
Still air
150
140
120
40
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
θ
IDT™ VIDEO GENLOCK PLL
6
MK9173-01/-15
REV C 12/21/06
MK9173-01/-15
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
8
Millimeters
Inches
Symbol
Min
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
A
A1
B
C
D
E
e
1.35
0.10
0.33
0.19
4.80
3.80
.0532
.0040
.013
.0688
.0098
.020
E
H
INDEX
AREA
.0075
.1890
.1497
.0098
.1968
.1574
1.27 BASIC
0.050 BASIC
1
2
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
.2284
.010
.016
0°
.2440
.020
.050
8°
D
L
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
MK9173-01CS08
Marking
MK73-1
MK73-1
MK73-15
MK73-15
AV73-15
AV73-15
Shipping Packaging
Tubes
Package
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
Temperature
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
MK9173-01CS08T
Tape and Reel
Tubes
Tape and Reel
Tubes
MK9173-15CS08 (see note below)
MK9173-15CS08T (see note below)
AV9173-15CS08 (see note below)
AV9173-15CS08T (see note below)
Tape and Reel
Note: the AV9173-15CS08 and the MK9173-15CS08 use the same die. Both part numbers are active and
orderable.
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ VIDEO GENLOCK PLL
7
MK9173-01/-15
REV C 12/21/06
MK9173-01/-15
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
Revision History
Rev. Originator
Date
Description of Change
C
12/21/06 Eliminated "Using the MK9173 to replace the AV9173" section; updated template.
IDT™ VIDEO GENLOCK PLL
8
MK9173-01/-15
REV C 12/21/06
MK9173-01/-15
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
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Printed in USA
相关型号：
MK9173-15CS08LFT
PLL Based Clock Driver, 9173 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, SOIC-8
IDT
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