IS61C64AH-25U [ICSI]
8K x 8 HIGH-SPEED CMOS STATIC RAM; 8K ×8高速CMOS静态RAM
| 型号： | IS61C64AH-25U |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 8K x 8 HIGH-SPEED CMOS STATIC RAM |
| 文件： | 总8页 (文件大小：435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61C64AH
8K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
DESCRIPTION
The ICSI IS61C64AH is a very high-speed, low power,
8192-word by 8-bit static RAM. It is fabricated using ICSI's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 15 ns with low power consumption.
• High-speed access time: 15, 20, 25 ns
• Automatic power-down when chip is
deselected
• CMOS low power operation
— 450 mW (typical) operating
— 250 µW (typical) standby
• TTL compatible interface levels
• Single 5V power supply
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down to 250 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
• Fully static operation: no clock or refresh
required
• Three state outputs
The IS61C64AH is packaged in the JEDEC standard 28-pin,
300mil SOJ and 330mil SOP.
• Two Chip Enables (CE1 and CE2) for
simple memory expansion
FUNCTIONAL BLOCK DIAGRAM
256 X 256
MEMORY ARRAY
A0-A12
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE2
CE1
OE
CONTROL
CIRCUIT
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
1
SR001-B
IS61C64AH
PIN CONFIGURATION
28-Pin SOJ and SOP
PIN DESCRIPTIONS
A0-A12
Address Inputs
NC
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE2
A8
CE1
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
2
3
CE2
A6
4
OE
A5
5
A9
WE
A4
6
A11
OE
I/O0-I/O7
Vcc
A3
7
Power
A2
8
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A1
9
GND
Ground
A0
10
11
12
13
14
I/O0
I/O1
I/O2
GND
TRUTH TABLE
Mode
WE
CE1
CE2
OE
I/O Operation
Vcc Current
Not Selected
(Power-down)
X
X
H
X
X
L
X
X
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
Output Disabled
Read
Write
H
H
L
L
L
L
H
H
H
H
L
X
High-Z
DOUT
DIN
ICC
ICC
ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5 to +7.0
–55 to +125
–65 to +150
1.0
Unit
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND
V
°C
°C
W
Temperature Under Bias
Storage Temperature
Power Dissipation
IOUT
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial(1)
Ambient Temperature
VCC
5V ± 10%
5V ± 10%
0°C to +70°C
–40°C to +85°C
Notes:
1. Industrial supplement specification available upon request.
2
Integrated Circuit Solution Inc.
SR001-B
IS61C64AH
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
VCC = Min., IOH = –4.0 mA
Min.
2.4
—
Max.
—
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
1
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
VCC = Min., IOL = 8.0 mA
0.4
V
2.2
–0.5
–2
VCC + 0.5
V
0.8
2
V
2
GND ≤ VIN ≤ VCC
µA
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
–2
2
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
3
4
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
5
-15 ns
-20 ns
Min. Max.
-25 ns
Min. Max.
Symbol Parameter
Test Conditions
VCC = Max.,
IOUT = 0 mA, f = fMAX
Min. Max.
Unit
mA
ICC
Vcc Dynamic Operating
Supply Current
—
135
—
120
—
110
6
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
—
20
—
20
—
20
mA
mA
CE1
CE2
≥
≥
VIH or
VIL, f = 0
7
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
—
6
—
6
—
6
CE1
≥
≤
VCC – 0.2V,
0.2V,
CE2
8
VIN
VIN
≥
≤
VCC – 0.2V, or
0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
9
10
11
12
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Input Capacitance
Conditions
VIN = 0V
Max.
5
Unit
pF
COUT
Output Capacitance
VOUT = 0V
7
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Circuit Solution Inc.
3
SR001-B
IS61C64AH
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-15 ns
Min.
15
—
3
-20 ns
Min.
20
—
3
-25 ns
Min.
25
—
3
Symbol Parameter
Max.
—
15
—
15
15
7
Max.
—
20
—
20
20
7
Max.
—
25
—
25
25
9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
tAA
Address Access Time
Output Hold Time
CE1 Access Time
CE2 Access Time
OE Access Time
tOHA
tACE1
tACE2
tDOE
—
—
—
0
—
—
—
0
—
—
—
0
(2)
tLZOE
OE to Low-Z Output
OE to High-Z Output
—
6
—
7
—
9
(2)
tHZOE
—
3
—
3
—
3
tLZCE1(2) CE1 to Low-Z Output
—
—
8
—
—
10
—
20
—
—
12
—
20
tLZCE2(2) CE2 to Low-Z Output
3
3
3
(2)
tHZCE
CE1 or CE2 to High-Z Output
—
0
—
0
—
0
(3)
tPU
CE1 or CE2 to Power-Up
—
15
(3)
tPD
CE1 or CE2 to Power-Down
—
—
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 3.0V
3 ns
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
255 Ω
255 Ω
30 pF
5 pF
Including
jig and
scope
Including
jig and
scope
Figure 1.
Figure 2.
4
Integrated Circuit Solution Inc.
SR001-B
IS61C64AH
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
1
t
RC
ADDRESS
2
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
3
4
READ CYCLE NO. 2(1,3)
t
RC
5
ADDRESS
OE
t
AA
t
OHA
6
t
HZOE
t
DOE
t
LZOE
CE1
7
CE2
8
t
t
ACE1
ACE2
t
t
HZCE1
HZCE2
t
t
LZCE1
LZCE2
HIGH-Z
DOUT
DATA VALID
9
Notes:
1. WE is HIGH for a Read Cycle.
10
11
12
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
Integrated Circuit Solution Inc.
5
SR001-B
IS61C64AH
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-12 ns
Min.
-15 ns
Min.
-20 ns
Max.
-25 ns
Symbol Parameter
Max.
—
—
—
—
—
—
—
—
—
6
Max.
—
—
—
—
—
—
—
—
—
8
Min.
20
17
17
15
0
Min.
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
12
10
10
10
0
15
12
12
12
0
—
—
—
—
—
—
—
—
—
10
—
25
22
22
20
0
tSCE1
tSCE2
tAW
CE1 to Write End
—
CE2 to Write End
—
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
—
tHA
—
tSA
0
0
0
0
—
(4)
tPWE
tSD
WE Pulse Width
8
10
9
12
10
0
15
12
0
—
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
8
—
tHD
0
0
—
(2)
tHZWE
—
0
—
0
—
0
—
0
12
—
(2)
tLZWE
—
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
AC WAVEFORMS
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW) (1 )
t
WC
VALID ADDRESS
ADDRESS
CE1
t
t
SCE1
SCE2
t
SA
t
HA
CE2
t
AW
t
t
PWE1
PWE2
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
6
Integrated Circuit Solution Inc.
SR001-B
IS61C64AH
AC WAVEFORMS
WRITE CYCLE NO. 2(OE is HIGH During Write Cycle) (1,2)
1
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
2
LOW
HIGH
CE1
CE2
3
t
AW
t
PWE1
4
WE
t
HZWE
t
LZWE
t
SA
HIGH-Z
DATA UNDEFINED
DOUT
5
t
SD
t
HD
DATAIN VALID
DIN
6
WRITE CYCLE NO. 3(OE is LOW During Write Cycle) (1)
tWC
7
ADDRESS
VALID ADDRESS
tHA
8
LOW
OE
CE1
LOW
HIGH
9
CE2
WE
tAW
tPWE2
10
11
12
tSA
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
D
OUT
tSD
tHD
DATAIN VALID
DIN
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE = VIH.
Integrated Circuit Solution Inc.
7
SR001-B
IS61C64AH
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
15
20
25
IS61C64AH-15J
IS61C64AH-15U
300mil SOJ
330mil SOP
IS61C64AH-20J
IS61C64AH-20U
300mil SOJ
330mil SOP
IS61C64AH-25J
IS61C64AH-25U
300mil SOJ
330mil SOP
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
8
Integrated Circuit Solution Inc.
SR001-B
相关型号：
IS61C64AL-10JLI-TR
Standard SRAM, 8KX8, 10ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, PLASTIC, SOJ-28
ISSI
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