ICS843051 [ICSI]
FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR; FEMTOCLOCKS CRYSTAL - TO- 3.3V LVPECL时钟发生器
| 型号： | ICS843051 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR |
| 文件： | 总15页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS843051 is a Gb Ethernet Generator and a • 1 differential 3.3V LVPECL output
ICS
member of the HiPerClocksTM family of high
• Crystal oscillator interface designed for
performance devices from ICS.The ICS843051 can
18pF parallel resonant crystals
HiPerClockS™
synthesize 10 Gigabit Ethernet, SONET, or Serial
ATA reference clock frequencies with the
• RMS phase jitter at:
155.52MHz (12KHz - 20MHz): 0.74ps (typical)
156.25MHz (1.875MHz - 20MHz): 0.43ps (typical)
161.13MHz (1.933MHz - 20MHz): 0.43ps (typical)
appropriate choice of crystal and output divider.The ICS843051
has excellent phase jitter performance and is packaged in a
small 8-pin TSSOP, making it ideal for use in systems with
limited board space.
• RMS phase noise at 156.25MHz
Offset
Noise Power
100Hz .................. -95 dBc/Hz
1KHz ................ -110 dBc/Hz
10KHz ................ -125 dBc/Hz
100KHz ................ -125 dBc/Hz
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Lead-Free package fully RoHS compliant
FREQUENCY TABLE
PIN ASSIGNMENT
Inputs
Output Frequency
(MHz)
Crystal Frequency (MHz)
20.141601
20.141601
19.53125
19.53125
19.44
FREQ_SEL
VCCA
VEE
VCC
1
2
3
4
8
7
6
5
Q0
0
1
0
1
0
1
0
1
161.132812
80.566406
156.25
78.125
155.52
77.76
XTAL_OUT
XTAL_IN
nQ0
FREQ_SEL
ICS843051
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
19.44
G Package
TopView
18.75
150
18.75
75
BLOCK DIAGRAM
FREQ_SEL
XTAL_IN
0 ÷4 (default)
1 ÷8
nQ0
Q0
Phase
Detector
OSC
VCO
XTAL_OUT
÷32
(fixed)
843051AG
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REV. A DECEMBER 14, 2004
1
ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
VCCA
VEE
Type
Description
1
2
Power
Power
Analog supply pin.
Negative supply pin.
3,
4
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Input
5
6, 7
8
FREQ_SEL
nQ0, Q0
VCC
Input
Output
Power
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Differential clock outputs. LVPECL interface levels.
Core supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characterristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pulldown Resistor
4
pF
RPULLDOWN
51
KΩ
843051AG
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REV. A DECEMBER 14, 2004
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ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
101.7°C/W (0 mps)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
ICC
Core Supply Voltage
3.465
3.465
70
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Power Supply Current
3.135
3.3
V
mA
mA
mA
ICCA
IEE
15
85
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage FREQ_SEL
2
VCC + 0.3
0.8
V
V
Input Low Voltage FREQ_SEL
Input High Current FREQ_SEL
Input Low Current FREQ_SEL
-0.3
VCC = VIN = 3.465V
150
µA
µA
IIL
VCC = 3.465V, VIN = 0V
-5
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol Parameter Test Conditions Minimum
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 1.4
VCC - 2.0
0.6
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
12
Typical Maximum Units
Fundamental
Mode of Oscillation
Frequency
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
843051AG
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REV. A DECEMBER 14, 2004
3
ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
155.52
156.25
161.13
MHz
MHz
MHz
fOUT
Output Frequency
155.52MHz @ Integration Range:
12KHz - 20MHz
156.25MHz @ Integration Range:
1.875MHz - 20MHz
156.25MHz @ Integration Range:
12KHz - 20MHz
161.13MHz @ Integration Range:
1.933MHz - 20MHz
0.74
0.43
0.75
0.43
0.72
ps
ps
ps
ps
ps
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
161.13MHz @ Integration Range:
12KHz - 20MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
325
49
600
51
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plots following this section.
843051AG
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REV. A DECEMBER 14, 2004
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ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
TYPICAL PHASE NOISE AT 155.52MHZ
0
-10
-20
Filter
-30
-40
-50
155.52MHz
RMS Phase Noise Jitter
12KHz to 20MHz = 0.74ps (typical)
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Raw Phase Noise Data
Phase Noise Result by adding
a Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 156.25MHZ
0
-10
-20
-30
Gb Ethernet Filter
-40
-50
-60
156.25MHz
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.43ps (typical)
-70
-80
-90
-100
-110
-120
-130
Raw Phase Noise Data
-140
-150
-160
-170
-180
Phase Noise Result by adding
Gb Ethernet Filter to raw data
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843051AG
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REV. A DECEMBER 14, 2004
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ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
TYPICAL PHASE NOISE AT 161.13MHZ
0
-10
-20
-30
-40
Filter
161.13MHz
-50
-60
RMS Phase Noise Jitter
1.933M to 20MHz = 0.43ps (typical)
-70
-80
-90
-100
-110
-120
-130
-140
-150
Raw Phase Noise Data
-160
-170
-180
Phase Noise Result by adding
a Filter to raw data
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843051AG
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REV. A DECEMBER 14, 2004
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ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
SCOPE
VCC
Qx
LVPECL
VEE
Phase Noise Mask
nQx
Offset Frequency
f1
f2
-1.3V 0.165V
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ0
80ꢀ
tF
80ꢀ
tR
Q0
VSWING
20ꢀ
Pulse Width
tPERIOD
Clock
Outputs
20ꢀ
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
843051AG
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REV. A DECEMBER 14, 2004
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ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
CLOCKS™ CRYSTAL- -
TO
3.3V LVPECL CLOCK
GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS843051 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, and VCCA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10µF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843051 has been characterized with 18pF parallel parallel resonant crystal and were chosen to minimize the ppm
resonant crystals. The capacitor values, C1 and C2, shown in error.The optimum C1 and C2 values can be slightly adjusted
Figure 2 below were determined using a 26.04167MHz, 18pF for different board layouts.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
Figure 2. CRYSTAL INPUt INTERFACE
843051AG
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REV. A DECEMBER 14, 2004
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ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
LAYOUT GUIDELINE
parallel resonant crystal is used.The C1 = 27pF and C2 = 33pF
are recommended for frequency accuracy.The C1 and C2 val-
ues may be slightly adjusted for optimizing frequency accuracy.
Figure 3A shows a schematic example of the ICS843051. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECLTermination Application Note.In this example, an 18 pF
VCC
VCCA
VCC
VCC
R2
10
C3
10uF
C4
0.1u
R1
R3
R5
1K
133
133
U1
Zo = 50 Ohm
Zo = 50 Ohm
Q
VCC
1
8
7
6
5
VCCA
VEE
VCC
Q0
nQ0
+
-
2
3
4
XTAL2
XTAL_OUT
XTAL2
XTAL_IN
FREQ_SEL
nQ
C2
33pF
19.44MHz
18pF
X1
ICS843051
XTAL1
R4
82.5
R6
82.5
C5
0.1u
C1
27pF
F
IGURE 3A. ICS843051 SCHEMATIC
E
XAMPLE
PC BOARD
L
AYOUT
E
XAMPLE
Figure 3B shows an example of ICS843051 P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age.The footprints of other components in this example are listed
in the Table 6. There should be at least one decoupling capacitor
per power pin.The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
C1, C2
C3
Size
0402
0805
0603
0603
C4, C5
R2
NOTE: Table 6, lists component
sizes shown in this layout example.
F
IGURE 3B. ICS843051 PC BOARD
L
AYOUT
E
XAMPLE
843051AG
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REV. A DECEMBER 14, 2004
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ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843051.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843051 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_TYP = 3.465V * 85mA = 294.5mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 294.5mW + 30mW = 324.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W perTable 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.324W * 90.5°C/W = 99.3°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7.THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
843051AG
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REV. A DECEMBER 14, 2004
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ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
CLOCKS™ CRYSTAL- -
TO
3.3V LVPECL CLOCK
GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW L
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843051AG
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REV. A DECEMBER 14, 2004
11
ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA by Velocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TRANSISTOR COUNT
The transistor count for ICS843051 is: 1892
843051AG
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REV. A DECEMBER 14, 2004
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ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843051AG
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REV. A DECEMBER 14, 2004
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ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
CLOCKS™ CRYSTAL- -
TO
3.3V LVPECL CLOCK
GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS843051AG
Marking
3051A
3051A
051AL
Package
Count
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
8 Lead TSSOP
100 per tube
ICS843051AGT
ICS843051AGLF
8 Lead TSSOP on Tape and Reel
8 Lead "Lead-Free" TSSOP
2500
100 per tube
8 Lead "Lead-Free" TSSOP
on Tape and Reel
ICS843051AGLFT
051AL
2500
0°C to 70°C
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
843051AG
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REV. A DECEMBER 14, 2004
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ICS843051
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
T10
14
Ordering Information Table - corrected count from 154 per tube to 100 per
tube.
A
11/16/04
1
14
Added Lead-Free bullet in Features section.
Ordering Information Table - added "Lead-Free" part.
A
12/14/04
T10
843051AG
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REV. A DECEMBER 14, 2004
15
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