ICS843081AGI-01LF [ICSI]
FEMTOCLOCKS? CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK MULTIPLIER; FEMTOCLOCKS⑩ CRYSTAL - TO- 3.3V ， 2.5V LVPECL时钟乘法器
| 型号： | ICS843081AGI-01LF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK MULTIPLIER |
| 文件： | 总15页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS843081I-01 is an Ethernet Clock • One differential LVPECL output
ICS
HiPerClockS™
Multiplier and a member of the HiPerClocksTM
family of high performance devices from ICS. The
ICS843081I-01 accepts a crystal reference of
19.6MHz - 28MHz. The ICS843081I-01 has
• One crystal oscillator interface: 19.6MHz - 28MHz
• Output frequency range: 490MHz - 700MHz
• VCO range: 490MHz - 700MHz
excellent 1ps or lower phase jitter performance, over the
1.875MHz - 20MHz integration range. The ICS843081I-01 is
packaged in a small 8-pin TSSOP, making it ideal for use in
systems with limited board space.
• RMS phase jitter @ 625MHz using a 25MHz reference
(1.875MHz - 20MHz): 0.32ps (typical)
• 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
FREQUENCY EXAMPLE FUNCTION TABLE
Input
M/N (Multiplier) Output Frequencies (MHz)
XTAL (MHz)
20
25
28
25
25
25
500
625
700
BLOCK DIAGRAM
PIN ASSIGNMENT
OE
VCCA
XTAL_OUT
XTAL_IN
VEE
VCC
Q
1
2
3
4
8
7
6
5
nQ
OE
XTAL_IN
Q
ICS843081I-01
8-LeadTSSOP
4.40mm x 3.0mm x 0.925mm
package body
Phase
Detector
VCO
490 - 700 MHz
nQ
XTAL_OUT
G Package
TopView
M = ÷25 (fixed)
843081AGI-01
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REV.B JANUARY 23, 2006
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ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VCCA
Power
Input
Analog supply pin.
2,
3
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
4
VEE
Power
Input
Negative supply pin.
Output enable pin. When HIGH, Q output is enabled.
When LOW, forces Q to HiZ state. LVCMOS/LVTTL interface levels.
5
OE
Pullup
6, 7
8
nQ, Q
VCC
Output
Power
Differential clock outputs. LVPECL interface levels.
Core supply pin.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
RPULLUP
51
kΩ
843081AGI-01
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ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
101.7°C/W (0 mps)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
ICC
Core Supply Voltage
3.465
3.465
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Power Supply Current
3.135
3.3
V
72
mA
mA
mA
ICCA
IEE
12
78
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum Units
VCC
VCCA
ICC
Core Supply Voltage
2.625
2.625
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Power Supply Current
2.375
2.5
V
60
mA
mA
mA
ICCA
IEE
12
73
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CC = 3.3V
VCC = 2.5V
CC = 3.3V
V
2
VCC + 0.3
VCC + 0.3
0.8
V
V
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
V
V
Input Low Voltage
VCC = 2.5V
0.7
V
IIH
IIL
Input High Current
Input Low Current
VCC = VIN = 3.465V or 2.625V
VCC = 3.465V or 2.625V, VIN = 0V
5
µA
µA
-150
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ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
19.6
Typical Maximum Units
Fundamental
Mode of Oscillation
Frequency
28
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 5A. AC CHARACTERISTICS, VCC =VCCA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
490
700
MHz
RMS Phase Jitter (Random);
NOTE 1
625MHz @ Integration Range:
1.875MHz - 20MHz
tjit(Ø)
0.32
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
125
45
600
55
ps
ꢀ
XTAL = 25MHz
NOTE 1: Please refer to the Phase Noise Plot following this section.
TABLE 5B. AC CHARACTERISTICS, VCC =VCCA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
490
700
MHz
RMS Phase Jitter (Random);
NOTE 1
625MHz @ Integration Range:
1.875MHz - 20MHz
tjit(Ø)
0.39
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
125
45
650
55
ps
ꢀ
XTAL = 25MHz
NOTE 1: Please refer to the Phase Noise Plot following this section.
843081AGI-01
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ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
TYPICAL PHASE NOISE AT 625MHZ @ 3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
Gb Ethernet Filter
625MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.32ps (typical)
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
200
Phase Noise Result by adding
a Gb Ethernet Filter to raw data
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 625MHZ @ 2.5V
0
-10
-20
-30
Gb Ethernet Filter
-40
-50
625MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.39ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
200
Phase Noise Result by adding
a Gb Ethernet Filter to raw data
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843081AGI-01
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REV.B JANUARY 23, 2006
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ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
2V
SCOPE
SCOPE
VCC,
VCCA
VCC,
VCCA
Qx
Qx
LVPECL
VEE
LVPECL
VEE
nQx
nQx
-0.5V 0.125V
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
80ꢀ
80ꢀ
VSWING
20ꢀ
Clock
20ꢀ
Phase Noise Mask
Outputs
tF
tR
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
OUTPUT RISE/FALL TIME
RMS PHASE JITTER
nQ
Q
tPW
tPERIOD
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS843081I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC and VCCA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V or 2.5V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843081I-01 has been characterized with 18pF parallel nant crystal and were chosen to minimize the ppm error. The
resonant crystals. The capacitor values, C1 and C2, shown in optimum C1 and C2 values can be slightly adjusted for different
Figure 2 below were determined using an 18pF parallel reso- board layouts.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
ICS843081I-01
Figure 2. CRYSTAL INPUt INTERFACE
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ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
to drive 50Ω transmission lines. Matched impedance tech-
niques should be used to maximize operating frequency and
minimize signal distortion. Figures 3A and 3B show two dif-
ferent layouts which are recommended only as guidelines.
Other suitable clock layouts may exist and it would be rec-
ommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component
process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V ground level. The R3 in Figure 4B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 4C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
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ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843081I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843081I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_TYP = 3.465V * 78mA = 270.27mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 270.27mW + 30mW = 300.27mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.300W * 90.5°C/W = 112°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6.THERMAL RESISTANCE θJA FOR 8-PINTSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
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ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT ANDT ERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW L
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOWT ABLE FOR 8 LEADTSSOP
θJA by Velocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TRANSISTOR COUNT
The transistor count for ICS843081I-01 is: 1697
843081AGI-01
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ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS843081AGI-01
Marking
1AI01
1AI01
AI01L
AI01L
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
8 lead TSSOP
ICS843081AGI-01T
ICS843081AGI-01LF
ICS843081AGI-01LFT
8 lead TSSOP
2500 tape & reel
tube
8 lead "Lead-Free" TSSOP
8 lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
843081AGI-01
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ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
1
4
Features Section - corrected RMS Phase Jitter value.
3.3V AC Characteristics Table - changed RMS Phase Jitter from 0.26ps typical
to 0.32ps typical.
2.5V AC Characteristics Table - changed RMS Phase Jitter from 0.27ps typical
to 0.39ps typical.
T5A
T5B
B
4
1/23/06
5
Updated Typical Phase Noise Plots.
T9
14
Ordering Information Table - added lead-free marking.
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REV.B JANUARY 23, 2006
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