ICS843002AGILF [ICSI]
FEMTOCLOCKS-TM CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER; FEMTOCLOCKS -TM CRYSTAL - TO- 3.3V ， 2.5V LVPECL频率合成器
| 型号： | ICS843002AGILF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS-TM CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总16页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS843002I is a 2 output LVPECL synthesizer
• Two 3.3V or 2.5V LVPECL outputs
ICS
HiPerClockS™
optimized to generate Fibre Channel reference
clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. Using a 26.5625MHz, 18pF
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz, and
53.125MHz. The ICS843002I uses ICS’ FemtoClockTM low
phase noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS843002I is packaged in a small 20-pin
TSSOP package.
• VCO range: 560MHz - 680MHz
• RMS phase jitter @212.5MHz (2.55MHz - 20MHz):
0.50ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
FREQUENCY SELECT FUNCTION TABLE
PIN ASSIGNMENT
Inputs
Output
Frequency
(MHz)
1
20
19
18
17
16
15
14
13
12
11
nc
VCCO
VCCO
2
3
4
5
6
7
8
9
Q1
nQ1
VEE
VCC
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
Input
Frequency
M Divider N Divider
M/N
Divider Value
F_SEL1 F_SEL0
Q0
nQ0
MR
nPLL_SEL
nc
VCCA
F_SEL0
VCC
Value
24
Value
3
26.5625
26.5625
26.5625
26.5625
23.4375
0
0
1
1
0
0
1
0
1
0
8
6
4
2
8
212.5
159.375
106.25
53.125
187.5
24
24
24
24
4
6
12
3
10
ICS843002I
20-LeadTSSOP
6.5mm x 4.4mm x 0.92mm
BLOCK DIAGRAM
package body
G Package
Top View
Pulldown
2
F_SEL[1:0]
Pulldown
nPLL_SEL
Q0
F_SEL[1:0]
nQ0
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
Pulldown
REF_CLK
1
0
1
0
26.5625MHz
XTAL_IN
OSC
Q1
VCO
637.5MHz
(w/26.5625MHz
Reference)
Phase
Detector
nQ1
XTAL_OUT
Pulldown
nXTAL_SEL
M = 24 (fixed)
Pulldown
MR
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 7
Name
nc
Type
Unused
Description
No connect.
2, 20
3, 4
VCCO
Power
Ouput
Output supply pins.
Q0, nQ0
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
5
MR
Input
Pulldown
Pulldown
6
nPLL_SEL
VCCA
Input
Power
Input
8
Analog supply pin.
F_SEL0,
F_SEL1
9, 11
10, 16
12, 13
14
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
VCC
Power
Input
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
REF_CLK
Input
Pulldown LVCMOS/LVTTL reference clock input.
Selects between crystal or REF_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
15
nXTAL_SEL
Input
17
VEE
Power
Output
Negative supply pins.
18, 19
nQ1, Q1
Differential output pair. LVPECL interface levels.
NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
RPULLDOWN Input Pulldown Resistor
51
kΩ
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
73.2°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC =VCCA =VCCO = 3.3V 10ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
2.97
2.97
2.97
3.3
3.3
3.3
3.63
3.63
3.63
130
13
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
ICCA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC =VCCA =VCCO = 2.5V 5ꢀ,TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
2.375
2.375
2.375
2.5
2.5
2.5
2.625
2.625
2.625
115
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
ICCA
12
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 10ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VCC = 3.3V
Minimum Typical Maximum Units
2
VCC + 0.3
VCC + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
Input Low Voltage
VCC = 2.5V
1.7
-0.3
-0.3
VCC = 3.3V
VCC = 2.5V
0.7
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
Input
High Current
IIH
VCC = VIN = 3.63V or 2.625V
150
µA
µA
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
V
CC = 3.63V or 2.625V,
VIN = 0V
Input
Low Current
IIL
-150
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REV.A JANUARY 4, 2006
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 10ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
26.5625
Mode of Oscillation
Frequency
23.33
28.33
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 5A. AC CHARACTERISTICS, VCC =VCCA =VCCO = 3.3V 10ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] =11
Minimum Typical Maximum Units
186.67
140
226.67
170
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency
93.33
46.67
113.33
56.67
30
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
212.5MHz, (2.55MHz - 20MHz)
159.375MHz, (1.875MHz - 20MHz)
106.25MHz, (637kHz - 5MHz)
53.125MHz, (637kHz - 5MHz)
20ꢀ to 80ꢀ
0.50
0.54
0.68
0.70
ps
ps
RMS Phase Jitter (Random);
NOTE 3
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
350
49
650
51
ps
F_SEL[1:0] ≠ 00
F_SEL[1:0] = 00
ꢀ
43
57
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Measured using crystal input.
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 5B. AC CHARACTERISTICS, VCC =VCCA =VCCO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] =11
Minimum Typical Maximum Units
186.67
140
226.67
170
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency
93.33
46.67
113.33
56.67
30
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
212.5MHz, (2.55MHz - 20MHz)
159.375MHz, (1.875MHz - 20MHz)
106.25MHz, (637kHz - 5MHz)
53.125MHz, (637kHz - 5MHz)
20ꢀ to 80ꢀ
0.50
0.55
0.75
0.76
ps
ps
RMS Phase Jitter (Random);
NOTE 3
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
350
49
650
51
ps
F_SEL[1:0] ≠ 00
F_SEL[1:0] = 00
ꢀ
43
57
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Measured using crystal input.
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TYPICAL PHASE NOISE AT 212.5MHZ @ 3.3V
0
-10
-20
-30
-40
-50
-60
212.5MHz
RMS Phase Jitter (Random)
2.55MHz to 20MHz = 0.50ps (typical)
-70
-80
Fibre Channel Jitter Filter
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
Fibre Channel Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
2V
SCOPE
SCOPE
Qx
Qx
VCC
,
VCC,
VCCA, VCCO
VCCA, VCCO
LVPECL
LVPECL
nQx
nQx
VEE
VEE
-1.3V 0.33V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD ACTEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx
Qx
REF_CLK
nQ0, nQ1
nQy
Q0, Q1
Qy
tPD
tsk(o)
OUTPUT SKEW
PROPAGATION DELAY
Phase Noise Plot
nQ0, nQ1
Q0, Q1
tPW
tPERIOD
Phase Noise Mask
tPW
odc =
x 100%
tPERIOD
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
tF
80%
tR
VSWING
20%
Clock
Outputs
20%
OUTPUT RISE/FALL TIME
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843002I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VCCA. The 10Ω resis-
tor can also be replaced by a ferrite bead.
3.3V or 2.5V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
LVPECL OUTPUT
For applications not requiring the use of the crystal oscillator All unused LVPECL outputs can be left floating. We
input, both XTAL_IN and XTAL_OUT can be left floating. recommend that there is no trace attached. Both sides of the
Though not required, but for additional protection, a 1kΩ differential output pair should either be left floating or
resistor can be tied from XTAL_IN to ground.
terminated.
REF_CLK INPUT:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
CRYSTAL INPUT INTERFACE
The ICS843002I has been characterized with 18pF parallel below were determined using a 26.5625MHz, 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
ICS843002I
Figure 2. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
outputs are designed to drive 50Ω transmission lines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUTT ERMINATION
FIGURE 3B. LVPECL OUTPUTTERMINATION
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for close to ground level. The R3 in Figure 4B can be eliminated
2.5V LVPECL driver.These terminations are equivalent to ter- and the termination is shown in Figure 4C.
minating 50Ω to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVERT ERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVERT ERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 4C. 2.5V LVPECLTERMINATION EXAMPLE
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
LAYOUT GUIDELINE
18pF parallel resonant 26.5625MHz crystal is used. The
C1=27pF and C2=33pF are recommended for frequency ac-
curacy. For different board layout, the C1 and C2 may be
slightly adjusted for optimizing frequency accuracy.
Figure 5A shows a schematic example of the ICS843002I. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an
3.3V
VCC
VCCA
R3
R5
133
133
R2
10
Zo = 50 Ohm
Zo = 50 Ohm
C3
10uF
C4
0.01u
+
-
VCC
VCCO
U1
C6
0.1u
C7
0.1u
Logic Control Input Examples
R4
R6
82.5
82.5
Set Logic
Input to
'1'
Set Logic
Input to
'0'
ICS843002i
VCC
VCC
VCC=3.3V
RU1
1K
RU2
Not Install
VCCO=3.3V
Zo = 50 Ohm
Zo = 50 Ohm
To Logic
Input
pins
To Logic
Input
pins
+
-
RD1
RD2
1K
VCCO
Not Install
C8
0.1u
R7
50
R8
50
ICS843002I
X1
C2
33pF
26.5625MHz
18pF
R9
50
C9
0.1u
C1
27pF
Optional Termination
FIGURE 5A. ICS843002I SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 5B shows an example of ICS843002I P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age.The footprints of other components in this example are listed
in the Table 6. There should be at least one decoupling capacitor
per power pin.The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
Size
0402
0805
0603
0603
C1, C2
C3
C4, C5, C6, C7, C8
R2
NOTE: Table 6, lists component sizes
shown in this layout example.
FIGURE 5B. ICS843002I PC BOARD LAYOUT EXAMPLE
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 10ꢀ = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 130mA = 471.9mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.63V, with all outputs switching) = 471.9mW + 60mW = 531.9mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W perTable 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.532W * 66.6°C/W = 120.4°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 20-PINTSSOP, FORCED CONVECTION
θ
JA by Velocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
843002AGI
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT ANDT ERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
CCO_MAX
OL_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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REV.A JANUARY 4, 2006
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOWT ABLE FOR 20 LEADTSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC StandardTest Boards
Multi-Layer PCB, JEDEC StandardTest Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843002I is: 2578
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REV.A JANUARY 4, 2006
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
MAX
SYMBOL
MIN
N
A
20
--
1.20
A1
A2
b
0.05
0.80
0.19
0.09
6.40
0.15
1.05
0.30
c
0.20
D
6.60
E
6.40 BASIC
4.50
E1
e
4.30
0.65 BASIC
0.75
L
0.45
0°
α
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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REV.A JANUARY 4, 2006
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ICS843002I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS843002AGI
ICS843002AGIT
ICS843002AGILF
ICS843002AGILFT
ICS843002AGI
ICS843002AGI
20 Lead TSSOP
20 Lead TSSOP
2500 tape & reel
tube
ICS843002AGILF
ICS843002AGILF
20 Lead "Lead-Free" TSSOP
20 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV.A JANUARY 4, 2006
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