HT48CA6(20SOP) [HOLTEK]
Microcontroller, 8-Bit, MROM, 4MHz, CMOS, PDSO20;
| 型号： | HT48CA6(20SOP) |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | Microcontroller, 8-Bit, MROM, 4MHz, CMOS, PDSO20 微控制器 光电二极管 |
| 文件： | 总31页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT48CA6
8-Bit Remote Type Low Voltage Mask MCU
Features
·
·
·
·
·
Operating voltage: 1.8V~3.6V
Ten bidirectional I/O lines
HALT function and wake-up feature reduce power
consumption
·
·
·
·
·
·
·
62 powerful instructions
Six Schmitt trigger input lines
Up to 1ms instruction cycle with 4MHz system clock
All instructions in 1 or 2 machine cycles
14-bit table read instructions
One carrier output, 1/2 or 1/3 duty with high sink cur-
rent capability
·
·
·
·
On-chip crystal and RC oscillator
Watchdog Timer
One-level subroutine nesting
1K´14 program ROM
32´8 data RAM
Bit manipulation instructions
20/24-pin SOP package
General Description
The HT48CA6 is an 8-bit high performance RISC-like
microcontroller specifically designed for multiple I/O
product applications. The device is particularly suitable
for use in products such as remote controllers, toys and
various subsystem controllers. A HALT feature is in-
cluded to reduce power consumption.
Block Diagram
S
T
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1
7
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2
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V
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Rev. 1.10
1
July 26, 2002
HT48CA6
Pin Assignment
P
P
P
P
A
A
B
B
1
0
1
0
1
2
3
4
5
6
7
8
9
1
1
1
2
2
2
2
2
1
1
1
1
1
1
1
4
3
2
1
0
9
8
7
6
5
4
3
P
A
2
P
A
3
P
P
P
P
A
A
B
B
1
0
1
0
1
2
3
4
5
6
7
8
9
1
2
1
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
2
1
P
P
P
P
P
P
P
P
P
P
A
A
A
A
A
A
B
B
B
B
2
3
4
5
6
7
2
3
4
5
P
A
4
P
A
5
V
D
D
P
A
6
O
S
C
1
2
P
A
7
V
D
D
O
S
C
P
B
2
O
S
C
1
P
C
0
/
R
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M
P
B
3
O
S
C
2
V
S
S
P
B
4
P
C
0
/
R
E
M
R
E
S
0
1
2
P
B
5
V
S
S
N
N
C
P
P
B
B
6
7
R
E
S
0
C
H
T
4
8
C
A
6
H
T
4
8
C
A
6
2
0
S
O
P
-
A
2
4
S
O
P
-
A
Pad Assignment
2
2
1
2
3
2
1
2
0
1
9
1
8
P
B
0
2
1
7
P
A
6
3
4
V
D
D
P
A
7
1
6
O
S
C
1
1
5
P
B
2
(
0
ꢀ
0
)
1
4
P
B
3
O
S
C
2
5
6
7
P
C
0
8
9
1
0
1
1
1
2
1
3
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.10
2
July 26, 2002
HT48CA6
Pad Description
Pad No. Pad Name I/O Mask Option
Description
2-bit bidirectional input/output lines with pull-high resistors. Each bit
can be determined as NMOS output or Schmitt trigger input by soft-
ware instructions. Each bit can also be configured as wake-up input
by mask option.
Wake-up
2, 1
3
PB0, PB1
VDD
I/O
or None
Positive power supply
¾
¾
OSC1, OSC2 are connected to an RC network or a crystal (deter-
mined by mask option) for the internal system clock. In the case of RC
operation, OSC2 is the output terminal for 1/4 system clock (NMOS
open drain output).
4
5
OSC1
OSC2
I
Crystal or RC
O
Level or carrier output pin
Level or
Carrier
6
PC0/REM
O
PC0 can be set as CMOS level output pin or carrier output pin by
mask option.
7, 8
9
VSS
RES
Negative power supply, ground
¾
¾
¾
I
Schmitt trigger reset input. Active low.
Wake-up
or None
6-bit Schmitt trigger input lines with pull-high resistors. Each bit can
be configured as a wake-up input by mask option.
15~10
23~16
PB2~PB7
PA0~PA7
I
Bidirectional 8-bit input/output port with pull-high resistors. Each bit
can be determined as NMOS output or Schmitt trigger input by soft-
ware instructions.
I/O
¾
Absolute Maximum Ratings
Supply Voltage ............................................-0.3V to 4V
Input Voltage..............................VSS-0.3V to VDD+0.3V
Storage Temperature............................-50°C to 125°C
Operating Temperature...........................-25°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max. Unit
VDD
¾
VDD
IDD
fSYS=4MHz
Operating Voltage
1.8
¾
3.6
1.5
1
V
mA
mA
V
¾
0.7
¾
No load, fSYS=4MHz
Operating Current
3V
ISTB
VIL1
VIH1
VIL2
VIH2
IOL1
IOL2
IOH1
IOL3
Standby Current
3V No load, system HALT
¾
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
Input Low Voltage (RES)
Input High Voltage (RES)
PC0/REM Sink Current
PC0/REM Sink Current
PC0/REM Source Current
Sink Current of I/O Line
3V
3V
3V
3V
3V
3V
3V
3V
0
1.05
3
¾
¾
¾
¾
¾
1.95
¾
V
¾
1.5
2.4
150
300
-2
V
¾
V
¾
¾
VOL=0.3V
VOL=0.6V
VOH=2.7V
VOL=0.3V
100
200
-1
mA
mA
mA
mA
¾
¾
¾
1.5
2.5
¾
Pull-high Resistance of PA Port,
PB0~PB7 and RES
RPH
3V
20
40
¾
¾
kW
Rev. 1.10
3
July 26, 2002
HT48CA6
A.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VDD
3V
¾
fSYS
tRES
System Clock
400
1
4000
kHz
¾
¾
¾
¾
External Reset Low Pulse Width
¾
ms
Power-up or wake-up
from HALT
tSYS
tSST
System Start-up timer Period
1024
¾
¾
¾
Note: tSYS=1/fSYS
Functional Description
Execution flow
ecuted and its contents specify a maximum of 1024 ad-
dresses.
The HT48CA6 system clock can be derived from a crys-
tal/ceramic resonator oscillator. It is internally divided
into four non-overlapping clocks. One instruction cycle
consists of four system clock cycles.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by 1. The program counter then points to
the memory word containing the next instruction code.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute within 1 cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set or return from subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
proceed with the next instruction.
Program counter - PC
The 10-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
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P
C
P
C
+
1
P
C
+
2
P
C
,
e
t
c
h
I
N
S
T
(
P
C
)
E
x
e
c
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t
e
I
N
S
T
(
P
C
-
1
)
,
e
t
c
h
I
N
S
T
(
P
C
+
1
)
E
x
e
c
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e
I
N
S
T
(
P
C
)
,
e
t
c
h
I
N
S
T
(
P
C
+
2
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
+
1
)
Execution flow
Program Counter
Mode
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
Skip
0
0
0
0
0
0
0
0
0
0
PC+2
Loading PCL
*9
#9
S9
*8
#8
S8
@7
#7
@6
#6
@5
#5
@4
#4
@3
#3
@2
#2
@1
#1
@0
#0
Jump, call branch
Return from subroutine
S7
S6
S5
S4
S3
S2
S1
S0
Program counter
Note: *9~*0: Program counter bits
#9~#0: Instruction code bits
S9~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.10
4
July 26, 2002
HT48CA6
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
bits of the table word are transferred to the lower por-
tion of TBLH, the remaining 2 bits are read as ²0². The
Table Higher-order byte register (TBLH) is read only.
The table pointer (TBLP) is a read/write register
(07H), where P indicates the table location. Before ac-
cessing the table, the location must be placed in
TBLP. The TBLH is read only and cannot be restored.
All table related instructions need 2 cycles to complete
the operation. These areas may function as normal
program memory depending upon the requirements.
When a control transfer takes place, an additional
dummy cycle is required.
Program memory - ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data and table and is organized into 1024´14 bits, ad-
dressed by the program counter and table pointer.
Stack register - STACK
This is a special part of the memory used to save the
contents of the program counter (PC) only. The stack is
organized into one level and is neither part of the data
nor part of the program space, and is neither readable
nor writeable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call the contents of the program counter are
pushed onto the stack. At the end of a subroutine sig-
naled by a return instruction (RET), the program counter
is restored to its previous value from the stack. After a
chip reset, the SP will point to the top of the stack.
Certain locations in the program memory are reserved
for special usage:
·
Location 000H
This area is reserved for the initialization program. Af-
ter chip reset, the program always begins execution at
location 000H.
·
Table location
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m] (the cur-
rent page, 1 page=256 words) and TABRDL [m] (the
last page) transfer the contents of the lower-order byte
to the specified data memory, and the higher-order
byte to TBLH (08H). Only the destination of the
lower-order byte in the table is well-defined, the other
If the stack is full and a ²CALL² is subsequently exe-
cuted, stack overflow occurs and the first entry will be
lost (only the most recent return address is stored).
Data memory - RAM
0
0
0
H
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a
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p
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The data memory is designed with 42´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(32´8). Most of them are read/write, but some are read
only.
n
0
0
H
The special function registers include the indirect address-
ing register (00H), the memory pointer register (MP;01H),
the accumulator (ACC;05H) the program counter
lower-order byte register (PCL;06H), the table pointer
(TBLP;07H), the table higher-order byte register
(TBLH;08H), the status register (STATUS;0AH) and the
I/O registers (PA;12H, PB;14H, PC;16H). The remaining
space before the 20H is reserved for future expanded us-
age and reading these locations will return the result 00H.
The general purpose data memory, addressed from 20H
to 3FH, is used for data and control information under in-
struction command.
L
o
o
k
-
u
p
t
a
b
l
e
(
2
5
6
w
o
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d
s
)
P
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R
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M
n
,
,
H
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-
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p
t
a
b
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e
(
2
5
6
w
o
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s
)
3
,
,
H
1
4
b
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s
N
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:
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3
Program memory
Table Location
Instruction(s)
*9
P9
1
*8
P8
1
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TABRDL [m]
@7
@7
@6
@6
@5
@5
@4
@4
@3
@3
@2
@2
@1
@1
@0
@0
Table location
P9~P8: Current program counter bits
Note: *9~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.10
5
July 26, 2002
HT48CA6
accessible through memory pointer register (MP;01H).
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
I
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i
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e
c
t
A
d
d
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e
s
s
i
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g
R
e
g
i
s
t
e
r
M
P
H
Indirect addressing register
H
H
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses data memory pointed to by MP (01H).
Reading location 00H itself indirectly will return the re-
sult 00H. Writing indirectly results in no operation.
H
A
C
C
H
P
C
L
H
T
B
L
P
H
T
B
L
H
H
H
S
T
A
T
U
S
0
0
A
B
H
H
The memory pointer register MP (01H) is a 6-bit regis-
ter. The bit 7~6 of MP is undefined and reading will re-
turn the result ²1². Any writing operation to MP will only
transfer the lower 6-bit data to MP.
S
p
e
c
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P
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p
o
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D
A
T
A
M
E
M
O
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Y
0
0
C
D
H
H
0
E
H
0
,
H
H
H
H
H
H
H
H
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
Accumulator
The accumulator closely relates to ALU operations. It is
also mapped to location 05H of the data memory and is
capable of carrying out immediate data operations.
Data movement between two data memory locations
has to pass through the accumulator.
P
P
A
B
P
C
H
H
H
Arithmetic and logic unit - ALU
:
U
n
u
s
e
d
1
1
A
B
H
H
R
e
a
d
a
s
"
0
0
"
This circuit performs 8-bit arithmetic and logic opera-
tion. The ALU provides the following functions.
1
1
C
D
H
·
H
Arithmetic operations (ADD, ADC, SUB,
1
E
H
SBC, DAA)
1
,
H
H
·
·
·
·
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
2
0
G
e
n
e
r
a
l
P
E
u
r
p
o
s
e
D
A
T
A
M
M
O
R
Y
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
(
3
2
B
y
t
e
s
)
3
,
H
The ALU not only saves the results of a data operation but
also changes the contents of the status register.
RAM mapping
All data memory areas can handle arithmetic, logic, in-
crement, decrement and rotate operations directly. Ex-
cept for some dedicated bits, each bit in the data
memory can be set and reset by the SET [m].i and CLR
[m].i instructions, respectively. They are also indirectly
Status register - STATUS
This 8-bit status register (0AH) contains the 0 flag (Z),
carry flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PD) and watchdog time-out flag (TO). It
Labels
Bits
Function
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
C
0
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
AC
Z
1
2
3
Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
OV
PD is cleared when either a system power-up or executing the CLR WDT instruction. PD is set
by executing the HALT instruction.
PD
TO
4
5
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set
by a WDT time-out.
6
7
¾
¾
Unused bit, read as ²0²
Unused bit, read as ²0²
Status register
Rev. 1.10
6
July 26, 2002
HT48CA6
also records the status information and controls the opera-
tion sequence.
cost effective solution. However, the frequency of the
oscillation may vary with VDD, temperature and the chip
itself due to process variations. It is, therefore, not suit-
able for timing sensitive operations where accurate os-
cillator frequency is desired.
With the exception of the TO and PD flags, bits in the
status register can be altered by instructions like most
other register. Any data written into the status register
will not change the TO or PD flags. In addition it should
be noted that operations related to the status register
may give different results from those intended. The TO
and PD flags can only be changed by the Watchdog
Timer overflow, chip power-up, clearing the Watchdog
Timer and executing the HALT instruction.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift for the oscillator. No other external components are
needed. Instead of a crystal, the resonator can also be
connected between OSC1 and OSC2 to get a frequency
reference, but two external capacitors in OSC1 and
OSC2 are required.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Watchdog Timer - WDT
In addition, on executing the subroutine call, the status
register will not be automatically pushed onto the stack.
If the contents of the status are important and if the sub-
routine can corrupt the status register, precautions must
be taken to save it properly.
The clock source of the WDT is implemented by instruc-
tion clock (system clock divided by 4). The clock source
is processed by a frequency divider and a prescaller to
yield various time out periods.
Clock Source
WDT time out period =
2n
Oscillator configuration
There are two oscillator circuits in the HT48CA6.
Where n= 8~11 selected by mask option.
This timer is designed to prevent a software malfunction
or sequence jumping to an unknown location with un-
predictable results. The Watchdog Timer can be dis-
abled by mask option. If the Watchdog Timer is disabled,
all the executions related to the WDT result in no opera-
tion and the WDT will lose its protection purpose. In this
situation the logic can only be restarted by an external
logic.
O
S
C
1
O
S
C
1
O
S
C
2
O
S
C
2
S
Y
S
(
N
M
O
S
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R
C
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s
c
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l
l
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t
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r
System oscillator
A WDT overflow under normal operation will initialize chip
reset and set the status bit ²TO². To clear the contents of
the WDT prescaler, three methods are adopted; external
reset (a low level to RES), software instructions, or a HALT
instruction. There are two types of software instructions.
One type is the single instruction ²CLR WDT², the other
type comprises two instructions, ²CLR WDT1² and ²CLR
WDT2². Of these two types of instructions, only one can
be active depending on the mask option ¾ ²CLR WDT
times selection option². If the ²CLR WDT² is selected (i.e..
CLRWDT times equal one), any execution of the CLR
WDT instruction will clear the WDT. In case ²CLR WDT1²
Both are designed for system clocks; the RC oscillator
and the Crystal oscillator, which are determined by
mask options. No matter what oscillator type is selected,
the signal provides the system clock. The HALT mode
stops the system oscillator and ignores the external sig-
nal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VSS in needed and the resistance must
range from 51kW to 1MW. The system clock, divided by
4, is available on OSC2, which can be used to synchro-
nize external logic. The RC oscillator provides the most
C
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(
8
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M
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a
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t
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(
n
=
8
~
1
1
)
n
T
i
m
e
-
o
u
t
2
Watchdog Timer
7
Rev. 1.10
July 26, 2002
HT48CA6
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem powers up or when the system awakes from a HALT
state.
and ²CLR WDT2² are chosen (i.e.. CLRWDT times equal
two), these two instructions must be executed to clear the
WDT; otherwise, the WDT may reset the chip due to a
time-out.
Power down operation - HALT
When a system power up occurs, an SST delay is added
during the reset period. But when the reset comes from
the RES pin, the SST delay is disabled. Any wake-up
from HALT will enable the SST delay.
The HALT mode is initialized by the HALT instruction
and results in the following...
·
·
The system oscillator turns off and the WDT stops.
The contents of the on-chip RAM and registers remain
unchanged.
The functional unit chip reset status is shown below.
PC
000H
·
·
·
WDT prescaler are cleared.
WDT Prescaler
Input/output Ports
SP
Clear
All I/O ports maintain their original status.
The PD flag is set and the TO flag is cleared.
Input mode
The system can quit the HALT mode by means of an ex-
ternal reset or an external falling edge signal on port B.
An external reset causes a device initialization. Exam-
ining the TO and PD flags, the reason for chip reset can
be determined. The PD flag is cleared when the system
powers up or execute the CLR WDT instruction and is set
when the HALT instruction is executed. The TO flag is set
if the WDT time-out occurs, and causes a wake-up that
only resets the PC (Program Counter) and SP, the others
keep their original status.
Points to the top of the stack
High level
Carrier Output
R
E
S
Reset circuit
The port B wake-up can be considered as a continuation
of normal execution. Each bit in port B can be independ-
ently selected to wake up the device by the mask option.
Awakening from an I/O port stimulus, the program will
resume execution of the next instruction.
H
A
L
T
W
T
D
T
e
W
D
T
Once a wake-up event(s) occurs, it takes 1024 tSYS
(system clock period) to resume normal operation. In
other words, a dummy cycle period will be inserted after
the wake-up.
i
m
-
o
u
t
R
e
s
e
t
R
E
S
R
e
s
e
t
S
S
T
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
1
0
-
s
t
a
g
e
O
S
C
1
R
i
p
p
l
e
C
o
u
n
t
e
r
Reset
Reset configuration
There are three ways in which a reset can occur:
·
·
·
RES reset during normal operation
RES reset during HALT
V
D
D
WDT time-out reset during normal operation
R
E
S
t
S S T
Some registers remain unchanged during reset condi-
tions. Most registers are reset to the ²initial condition²
when the reset conditions are met. By examining the PD
and TO flags, the program can distinguish between dif-
ferent ²chip resets².
S
S
T
T
i
m
e
-
o
u
t
C
h
i
p
R
e
s
e
t
Reset timing chart
TO
0
PD
0
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
u
u
0
1
1
u
WDT time-out during normal operation
Note: ²u² means ²unchanged².
Rev. 1.10
8
July 26, 2002
HT48CA6
The chip reset status of the registers is summarized in the following table:
WDT Time-out
(Norma Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
Register
PC (Program Counter)
000H
000H
000H
MP
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--1u uuuu
1111 1111
1111 1111
---- ---1
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
1111 1111
1111 1111
---- ---1
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--01 uuuu
1111 1111
1111 1111
---- ---1
ACC
TBLP
TBLH
STATUS
PA
PB
PC
Note:
²u² means ²unchanged²
²x² means ²unknown²
Carrier
where m=2 or 3 and n=0~3, both are selected by mask
option. If m=2, the duty cycle of the carrier output is 1/2
duty. If m=3, the duty cycle (active low) of the carrier out-
put can be 1/2 duty or 1/3 duty also determined by mask
option (with the exception of n=0).
The HT48CA6 provides a carrier output which shares
the pin with PC0. It can be selected to be a carrier output
(REM) or level output pin (PC0) by mask option. If the
carrier output option is selected, setting PC0=²0² to en-
able carrier output and setting PC0=²1² to disable it at
high level output.
Detailed selection of the carrier duty is shown below:
m´2n
Duty Cycle (Active Low)
The clock source of the carrier is implemented by in-
struction clock (system clock divided by 4) and pro-
cessed by a frequency divider to yield various carry
frequency.
2, 4, 8, 16
3
1/2
1/3
6, 12, 24
1/2 or 1/3
Clock Source
Carry Frequency=
m ´ 2n
,
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M
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3
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(
S
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m
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/
4
)
1
/
2
o
r
1
/
3
d
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y
1
/
2
R
E
M
/
P
C
0
C
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D
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1
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3
R
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h
f
o
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d
-
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-
w
r
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P
C
0
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g
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r
Carrier/Level output
V
D
D
P
u
l
l
-
u
p
R
e
a
d
D
a
t
a
P
B
2
~
P
B
7
D
A
T
A
B
U
S
S
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e
m
W
a
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-
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p
M
a
s
k
O
p
t
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o
n
PB input lines
Rev. 1.10
9
July 26, 2002
HT48CA6
The following table shows examples of carrier fre-
quency selection.
data are latched and remain unchanged until the output
latch is rewritten.
m´2n
When the PA and PB0~PB1 is used for input operation,
it should be noted that before reading data from pads, a
²1² should be written to the related bits to disable the
NMOS device.
fSYS
fCARRIER
37.92kHz
56.9kHz
Duty (Active Low)
1/3 only
3
2
455kHz
1/2 only
After chip reset, PA and PB remain at a high level input
line and PC remain at high level output.
Input/output ports
There are an 8-bit bidirectional input/output port, a 6-bit
input with 2-bit I/O port and 1-bit output port in the
HT48CA6, labeled PA, PB and PC which are mapped to
[12H], [14H], [16H] of the RAM, respectively. Each bit of
PA can be selected as NMOS output or Schmitt trigger
with pull-high resistor by software instruction. PB0~PB1
have the same structure with PA, while PB2~PB7 can
only be used for input operation (Schmitt trigger with
pull-high resistors). PC is only 1-bit output port shares
the pin with carrier output. If the level option is selected,
the PC is CMOS output.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR [m]²,
²CPL [m]², ²CPLA [m]² read the entire port states into
the CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or to the
accumulator.
It is recommended to apply ²MOV² instructions to the
I/O lines since a read-modify-write instruction may
change the original state of I/O lines.
Each line of PB has a wake-up capability to the device
by mask option. The highest seven bits of PC are not
physically implemented, on reading them a ²0² is re-
turned and writing results in a no-operation.
Both PA and PB for the input operation, these ports are
non-latched, that is, the inputs should be ready at the T2
rising edge of the instruction ²MOV A, [m]² (m=12H or
14H). For PA, PB0~PB1 and PC output operation, all
V
D
D
W
e
a
k
P
u
l
l
-
u
p
D
A
T
A
B
U
S
D
C
Q
P
A
0
~
P
A
7
P
B
0
~
P
B
1
K
Q
W
r
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e
S
C
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p
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d
D
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S
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m
W
a
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-
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M
a
s
k
O
p
t
i
o
n
P
B
0
~
P
B
1
o
n
l
y
PA, PB input/output lines
Mask option
The following table shows eight kinds of mask option in the HT48CA6. All the mask options must be defined to ensure
proper system functioning.
No.
Mask Option
WDT time-out period selection
Clock Source
1
Time-out period=
2n
where n=8~11.
2
WDT enable or disable selection. This option is to decide whether the WDT timer is enabled or disabled.
CLRWDT times selection. This option defines how to clear the WDT by instruction. ²One time² means that
the CLR WDT instruction can clear the WDT. ²Two times² means only if both of the CLR WDT1 and CLR
WDT2 instructions have been executed, the WDT can be cleared.
3
Wake-up selection. This option defines the wake-up activity function. External input pins (PB only) all have
the capability to wake-up the chip from a HALT.
4
5
Carrier or level output selection. This option defines the activity of PC0 to be carrier output or level output.
Rev. 1.10
10
July 26, 2002
HT48CA6
No.
Mask Option
Carry frequency selection.
Clock Source
6
Carry frequency=
where n=0~3.
(2 or 3) ´2n
Carrier duty selection. There are two types of selection: 1/2 duty or 1/3 duty.
If carrier frequency= Clock Source / (2, 4, 8 or 16), the duty cycle will be 1/2 duty.
If carrier frequency= Clock Source / 3, the duty cycle will be 1/3 duty.
7
8
If carrier frequency= Clock Source / (6, 12 or 24), the duty cycle can be 1/2 duty or 1/3 duty.
OSC type selection. This option is to decide if an RC or Crystal oscillator is chosen as system clock. If the
Crystal oscillator is selected, the SST (System Start-up Timer) default is activated, otherwise the SST is
disabled.
Application Circuits
P
P
B
B
1
0
P
P
P
B
B
B
2
3
4
P
P
A
A
3
2
P
P
P
B
B
B
5
6
7
P
P
A
A
1
0
H
T
4
8
C
A
6
V
D
D
1
W
P
O
C
0
/
R
E
M
3
0
0
p
,
P
P
A
A
7
6
2
m
2 ,
S
C
1
X
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t
a
l
(
s
e
e
N
o
t
e
2
)
O
S
C
2
P
A
5
3
0
0
p
,
P
A
4
R
E
S
m
0 . 1 ,
Note:
It is recommended that a 22mF decoupling capacitor is placed between VSS and VDD.
If the crystal has a value above 1MHz the capacitors are not required.
Rev. 1.10
11
July 26, 2002
HT48CA6
Instruction Set Summary
Mnemonic
Instruction
Cycle
Flag
Affected
Description
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
Add data memory to ACC
1
1(1)
1
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
Add ACC to data memory
Add immediate data to ACC
ADC A,[m]
ADCM A,[m]
SUB A,x
Add data memory to ACC with carry
1
1(1)
Add ACC to data memory with carry
Subtract immediate data from ACC
1
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Subtract data memory from ACC
1
1(1)
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1(1)
Logic Operation
AND A,[m]
OR A,[m]
AND data memory to ACC
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
OR data memory to ACC
XOR A,[m]
ANDM A,[m]
ORM A,[m]
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
1
1(1)
1(1)
1(1)
1
XORM A,[m] Exclusive-OR ACC to data memory
AND A,x
OR A,x
AND immediate data to ACC
OR immediate data to ACC
1
XOR A,x
CPL [m]
CPLA [m]
Exclusive-OR immediate data to ACC
Complement data memory
1
1(1)
Complement data memory with result in ACC
1
Increment & Decrement
INCA [m]
INC [m]
Increment data memory with result in ACC
1
Z
Z
Z
Z
Increment data memory
1(1)
DECA [m]
DEC [m]
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
Rotate
RRA [m]
RR [m]
Rotate data memory right with result in ACC
Rotate data memory right
1
1(1)
1
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
1(1)
C
1
None
None
C
1(1)
1
RLCA [m]
RLC [m]
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1(1)
C
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Rev. 1.10
12
July 26, 2002
HT48CA6
Instruction
Cycle
Flag
Affected
Mnemonic
Branch
Description
JMP addr
SZ [m]
Jump unconditionally
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Skip if data memory is zero
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
Return from subroutine
2
RET A,x
RETI
Return from subroutine and load immediate data to ACC
Return from interrupt
2
2
Table Read
TABRDC [m] Read ROM code (current page) to data memory and TBLH
TABRDL [m] Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
Miscellaneous
NOP
No operation
1
1(1)
1(1)
1
None
None
CLR [m]
Clear data memory
SET [m]
Set data memory
None
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Clear Watchdog Timer
TO,PD
TO(4),PD(4)
TO(4),PD(4)
None
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1
1(1)
1
None
1
TO,PD
Note: x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1): If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2): If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(1) and (2)
(3)
:
(4): The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared.
Otherwise the TO and PD flags remain unchanged.
Rev. 1.10
13
July 26, 2002
HT48CA6
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
Rev. 1.10
14
July 26, 2002
HT48CA6
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND op-
eration. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND op-
eration. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
Operation
The contents of the specified data memory are cleared to 0.
[m] ¬ 00H
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Rev. 1.10
15
July 26, 2002
HT48CA6
CLR [m].i
Clear bit of data memory
Description
Operation
The bit i of the specified data memory is cleared to 0.
[m].i ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PD and TO ¬ 0
Affected flag(s)
TC2
TC1
TO
0
PD
0
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of
this instruction without the other preclear instruction just sets the indicated flag which im-
plies this instruction has been executed and the TO and PD flags remain unchanged.
Operation
WDT ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
0*
PD
0*
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of
this instruction without the other preclear instruction, sets the indicated flag which implies
this instruction has been executed and the TO and PD flags remain unchanged.
Operation
WDT ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
0*
PD
0*
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
Rev. 1.10
16
July 26, 2002
HT48CA6
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-
lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-
justment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Operation
Data in the specified data memory is decremented by 1.
[m] ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
Rev. 1.10
17
July 26, 2002
HT48CA6
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PD) is set and the WDT time-out bit (TO) is cleared.
Operation
PC ¬ PC+1
PD ¬ 1
TO ¬ 0
Affected flag(s)
TC2
TC1
TO
0
PD
1
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Operation
Data in the specified data memory is incremented by 1
[m] ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
PC ¬addr
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV A,[m]
Description
Operation
Move data memory to the accumulator
The contents of the specified data memory are copied to the accumulator.
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Rev. 1.10
18
July 26, 2002
HT48CA6
MOV A,x
Move immediate data to the accumulator
Description
Operation
The 8-bit data specified by the code is loaded into the accumulator.
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
Operation
Affected flag(s)
No operation is performed. Execution continues with the next instruction.
PC ¬ PC+1
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) per-
form a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
Rev. 1.10
19
July 26, 2002
HT48CA6
RET
Return from subroutine
Description
Operation
Affected flag(s)
The program counter is restored from the stack. This is a 2-cycle instruction.
PC ¬ Stack
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the speci-
fied 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
Operation
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-
places the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
Rev. 1.10
20
July 26, 2002
HT48CA6
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
Operation
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
Rev. 1.10
21
July 26, 2002
HT48CA6
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-
cles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Rev. 1.10
22
July 26, 2002
HT48CA6
SET [m]
Set data memory
Description
Operation
Each bit of the specified data memory is set to 1.
[m] ¬ FFH
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Operation
Bit i of the specified data memory is set to 1.
[m].i ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the fol-
lowing instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory re-
mains unchanged. If the result is 0, the following instruction, fetched during the current in-
struction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-
wise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Rev. 1.10
23
July 26, 2002
HT48CA6
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumula-
tor, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memo-
ries) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writ-
ing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Rev. 1.10
24
July 26, 2002
HT48CA6
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Rev. 1.10
25
July 26, 2002
HT48CA6
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-
sive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-
sive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-
eration. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
Rev. 1.10
26
July 26, 2002
HT48CA6
Package Information
20-pin SOP (300mil) outline dimensions
2
0
1
1
A
B
1
1
0
C
C
'
G
H
D
a
E
,
Dimensions in mil
Nom.
Symbol
Min.
394
290
14
490
92
¾
Max.
A
B
C
C¢
D
E
F
419
300
20
¾
¾
¾
¾
¾
50
¾
¾
¾
¾
510
104
¾
4
¾
G
H
a
32
4
38
12
0°
10°
Rev. 1.10
27
July 26, 2002
HT48CA6
24-pin SOP (300mil) outline dimensions
2
4
1
3
A
B
1
1
2
C
C
'
G
H
D
a
E
,
Dimensions in mil
Nom.
Symbol
Min.
394
290
14
590
92
¾
Max.
A
B
C
C¢
D
E
F
419
300
20
¾
¾
¾
¾
¾
50
¾
¾
¾
¾
614
104
¾
4
¾
G
H
a
32
4
38
12
0°
10°
Rev. 1.10
28
July 26, 2002
HT48CA6
Product Tape and Reel Specifications
Reel dimensions
D
T
2
C
A
B
T
1
SOP 20W
Symbol
Description
Dimensions in mm
330±1.0
A
B
Reel Outer Diameter
Reel Inner Diameter
62±1.5
13.0+0.5
-0.2
C
D
Spindle Hole Diameter
Key Slit Width
2.0±0.5
24.8+0.3
-0.2
T1
T2
Space Between Flange
Reel Thickness
30.2±0.2
SOP 24W
Symbol
Description
Dimensions in mm
330±1.0
A
B
Reel Outer Diameter
Reel Inner Diameter
62±1.5
13.0+0.5
-0.2
C
D
Spindle Hole Diameter
Key Slit Width
2.0±0.5
24.8+0.3
-0.2
T1
T2
Space Between Flange
Reel Thickness
30.2±0.2
Rev. 1.10
29
July 26, 2002
HT48CA6
Carrier tape dimensions
P
0
P
1
t
D
E
,
W
B
0
C
D
1
P
K
0
A
0
SOP 20W
Symbol
Description
Dimensions in mm
24.0+0.3
-0.1
W
Carrier Tape Width
P
E
Cavity Pitch
12.0±0.1
1.75±0.1
11.5±0.1
1.5+0.1
1.5+0.25
4.0±0.1
2.0±0.1
10.8±0.1
13.3±0.1
3.2±0.1
0.3±0.05
21.3
Perforation Position
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
D
D1
P0
P1
A0
B0
K0
t
Cavity to Perforation (Length Direction)
Cavity Length
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
SOP 24W
Symbol
Description
Carrier Tape Width
Dimensions in mm
24.0±0.3
12.0±0.1
1.75±0.1
11.5±0.1
1.55+0.1
1.5+0.25
4.0±0.1
W
P
Cavity Pitch
E
Perforation Position
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
F
D
D1
P0
P1
A0
B0
K0
t
Cavity to Perforation (Length Direction)
Cavity Length
2.0±0.1
10.9±0.1
15.9±0.1
3.1±0.1
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
0.35±0.05
21.3
C
Rev. 1.10
30
July 26, 2002
HT48CA6
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Sales Office)
11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Shanghai) Inc.
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Holmate Semiconductor, Inc.
48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2002 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most
up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
31
July 26, 2002
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