HT48CXX_技术文档

HT48CXX/HT48RXX

8-Bit Microcontroller Series

Features

•

Operating voltage: 2.4V~5.2V

Bidirectional I/O lines with a selection of 18,

Data RAM with size selection of 64×8, 96×8,

160×8 and 224×8 bits

•

22, 32 and 56 lines

One interrupt input

Halt function and wake-up feature to reduce

power consumption

•

Programmable timer/event counters with

overflow interrupts and a selection of one

8-bit counter, one 8-bit and one 16-bit count-

ers, or two 16-bit counters

On-chip crystal and RC oscillator

Watchdog timer

63 powerful instructions

Up to 0.5µs instruction cycle with 8MHz

system clock at V_DD=5V

All instructions in 1 or 2 machine cycles

14-bit/15-bit/16-bit table read instructions

2-level/4-level/8-level subroutine nesting

Bit manipulation instructions

•

Program ROM with size selection of

1K×14, 2K×14, 4K×15 and 8K×16 bits

General Description

The HT48C10/48C30/48C50/48C70 are 8-bit

high performance RISC-like microcontrollers,

specifically designed for multiple I/O product

applications. These devices are suitable for use

in products such as remote controllers, fan/light

con t r oller s, wa sh in g m a ch in e con t r oller s,

scales, toys, and various subsystem controllers.

They all contain a halt feature to reduce power

consumption. The major differences between

these microcontrollers are attributed to vari-

ations in sizes of the ROM and RAM, as well as

bit number, counter number, I/O line number,

and different level subroutine nesting. Roughly

speaking, the HT48C10 is a microcontroller

with most economic features and the HT48C70

is one with the most features of the four micro-

controllers.

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25th May ’99

HT48CXX/HT48RXX

Selection Table

Mask version

P a r t No.

HT48C10

HT48C30

HT48C50

HT48C70

Operating Voltage

External Interrupt

Internal Interrupt

8-bit Timer/Event Counter

16-bit Timer/Event Counter

System Oscillator

Watchdog Timer

ROM

2.4V~5.2V

1

2

1

0

Crystal/RC

1

0

Crystal/RC

1

Crystal/RC

1

2

Crystal/RC

1

1K×14

2K×14

4K×15

8K×16

64×8

(40H~7FH)

96×8

(20H~7FH)

160×8

(60H~FFH)

224×8

(20H~FFH)

RAM

I/O Lines

18

63

2

22

63

2

32

63

4

56

63

8

Instructions

Stack Levels

Operating Frequency

Power Down Mode

Table Read Instructions

400kHz~8MHz 400kHz~8MHz 400kHz~8MHz 400kHz~8MHz

√

OTP version

P a r t No.

HT48R11

V_DD

f_SYS

I/O P u ll-h igh

Ma sk ver sion

HT48C10

HT48C30

HT48C50

3.0V~5.2V

400k~4MHz

No

Yes

No

HT48R12

HT48R31

HT48R32

HT48R50

HT48R51*

Yes

No

* Under development

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HT48CXX/HT48RXX

Block Diagram of HT48C70

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HT48CXX/HT48RXX

Pin Assignment

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25th May ’99

HT48CXX/HT48RXX

Note: For the dice form, the TMR0 and TMR1 pads have to be bonded to VDD or VSS if the TMR0

and/or TMR1 pad are not used.

The (TMR0) INT indicates that the TMR0 pad should be bonded to the INT pin.

The PC5 (TMR1) indicates that the TMR1 pad should be bonded to the PC5 pin.

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25th May ’99

HT48CXX/HT48RXX

Pin Description of HT48C10

Ma sk

Op tion

P in Na m e

I/O

F u n ction

Bidirectional 8-bit input/output ports

Wake-up

Pull-high

or None

Each bit can be configured as a wake-up input by mask option.

Software instructions determine the CMOS output or schmitt

trigger input with or without pull high resistor (by mask option).

PA0~PA7

I/O

Bidirectional 8-bit input/output ports

Pull-high

or None

Software instructions determine the CMOS output or schmitt

trigger input with or without pull high resistor (by mask

option).

PB0~PB7

I/O

VSS

INT

TMR

—

I

—

Negative power supply, GND

External interrupt schmitt trigger input with pull high resistor

Edge trigger is activated during high to low transition.

I

Schmitt trigger input for timer/event counter

Bidirectional 2-bit input/output ports

Software instructions determine the CMOS output or schmitt

trigger input with or without pull high resistor (by mask option).

Pull-high

or None

PC0~PC1

I/O

RES

I

—

Schmitt trigger reset input, active low

Positive power supply

VDD

—

OSC1 and OSC2 are connected to an RC network or a crystal

(by mask option) for the internal system clock. In the case of RC

operation, OSC2 is the output terminal for 1/4 system clock.

OSC1

OSC2

I

O

Crystal or

RC

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HT48CXX/HT48RXX

Pin Description of HT48C30

Ma sk

Op tion

P in Na m e

I/O

F u n ction

Bidirectional 8-bit input/output ports

Wake-up

Pull-high

or None

Each bit can be configured as a wake-up input by mask option.

Software instructions determine the CMOS output or schmitt

trigger input with or without a pull high resistor (by mask option).

PA0~PA7

I/O

Bidirectional 8-bit input/output ports

Pull-high

or None

Software instructions determine the CMOS output or schmitt

trigger input with or without a pull high resistor (by mask

option).

PB0~PB7

I/O

VSS

INT

TMR

—

I

—

Negative power supply, GND

External interrupt schmitt trigger input with a pull high

resistor. Edge triggered is activated on a high to low transition.

I

Schmitt trigger input for timer/event counter

Bidirectional 6-bit input/output ports

Pull-high

or None

Software instructions determine the CMOS output or schmitt

trigger input with or without a pull high resistor (by mask

option).

PC0~PC5

I/O

RES

I

—

Schmitt trigger reset input, active low

Positive power supply

VDD

—

OSC1 and OSC2 are connected to an RC network or a crystal

(by mask option) for the internal system clock. In the case of RC

operation, OSC2 is the output terminal for 1/4 system clock.

OSC1

OSC2

I

O

Crystal or

RC

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HT48CXX/HT48RXX

Pin Description of HT48C50

Ma sk

Op tion

P in Na m e

I/O

F u n ction

Bidirectional 8-bit input/output ports

Wake-up

Pull-high

or None

Each bit can be configured as a wake-up input by mask option.

Software instructions determine the CMOS output or schmitt

trigger input with or without a pull high resistor (by mask option).

PA0~PA7

I/O

Bidirectional 8-bit input/output ports

Pull-high

or None

Software instructions determine the CMOS output or schmitt

trigger input with or without a pull high resistor (by mask

option).

PB0~PB7

I/O

VSS

INT

—

I

—

Negative power supply, GND

External interrupt schmitt trigger input with a pull high

resistor. Edge triggered is activated on a high to low transition.

TMR0

TMR1

I

—

Schmitt trigger input for timer/event counter 0

Schmitt trigger input for timer/event counter 1

Bidirectional 8-bit input/output ports

Pull-high

or None

Software instructions determine the CMOS output or schmitt

trigger input with or without a pull high resistor (by mask

option).

PC0~PC7

I/O

RES

I

—

Schmitt trigger reset input, active low

Positive power supply

VDD

—

OSC1 and OSC2 are connected to an RC network or a crystal

(by mask option) for the internal system clock. In the case of RC

operation, OSC2 is the output terminal for 1/4 system clock.

OSC1

OSC2

I

O

Crystal or

RC

Bidirectional 8-bit Input/Output port. Software instructions

determine the CMOS output or schmitt trigger input with or

without a pull high resistor (by mask option).

Pull-high

or None

PD0~PD7

I/O

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HT48CXX/HT48RXX

Pin Description of HT48C70

Ma sk

Op tion

P in Na m e

I/O

F u n ction

Bidirectional 8-bit input/output ports

Wake-up

Pull-high

or None

Each bit can be configured as a wake-up input by mask option.

Software instructions determine the CMOS output or schmitt

trigger input with or without pull high resistor (by mask option).

PA0~PA7

I/O

Bidirectional 8-bit input/output ports

Software instructions determine the CMOS output or schmitt

trigger input (pull-high depends on mask option).

Pull-high

or None

PB0~PB7

I/O

VSS

INT

—

I

—

Negative power supply, GND

External interrupt schmitt trigger with pull high resistor

Edge trigger is activated during high to low transition.

TMR0

TMR1

I

—

Schmitt trigger input for timer/event counter 0

Schmitt trigger input for timer/event counter 1

Bidirectional 8-bit input/output ports

Software instructions determine the CMOS output or schmitt

trigger input (pull-high depends on mask option).

Pull-high

or None

PC0~PC7

I/O

RES

I

—

Schmitt trigger reset input, active low

Positive power supply

VDD

—

OSC1 and OSC2 are connected to an RC network or a crystal

(by mask option) for the internal system clock. In the case of RC

operation, OSC2 is the output terminal for 1/4 system clock.

OSC1

OSC2

I

O

Crystal or

RC

Bidirectional 8-bit input/output ports

Software instructions determine the CMOS output or schmitt

trigger input (pull-high depends on mask option).

Pull-high

or None

PD0~PD7

PE0~PE7

PF0~PF7

PG0~PG7

I/O

Bidirectional 8-bit input/output ports

Software instructions determine the CMOS output or schmitt

trigger input (pull-high depends on mask option).

Pull-high

or None

Bidirectional 8-bit input/output ports

Software instructions determine the CMOS output or schmitt

trigger input (pull-high depends on mask option).

Pull-high

or None

Bidirectional 8-bit input/output ports

Software instructions determine the CMOS output or schmitt

trigger input (pull-high depends on mask option).

Pull-high

or None

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HT48CXX/HT48RXX

Absolute Maximum Ratings

Supply Voltage ....................... V_DD–0.3V to 5.5V

Input Voltage .................V_SS–0.3V to V_DD+0.3V

Storage Temperature................. –50°C to 125°C

Operating Temperature .............. –25°C to 70°C

Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maxi-

mum Ratings” may cause substantial damage to the device. Functional operation of this device

at other conditions beyond those listed in the specification is not implied and prolonged

exposure to extreme conditions may affect device reliability.

D.C. Characteristics

Ta=25°C

Test Con d ition s

Sym bol

V_DD

P a r a m eter

Min . Typ . Ma x. Un it

V_DD

Con d ition s

Operating Voltage

—

2.4

—

0.7

2

5.2

1.5

3

V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

Operating Current

(HT48C10 Crystal OSC)

No load

f_SYS=4MHz

I_DD1

mA

0.5

1

Operating Current

(HT48C10 RC OSC)

No load

_SYS=2MHz

I_DD2

I_DD3

I_DD4

I_DD5

I_DD6

I_DD7

I_DD8

I_STB1

I_STB2

mA

µA

f

2

0.7

2

1.5

3

Operating Current

(HT48C30 Crystal OSC)

No load

f_SYS=4MHz

0.5

1

Operating Current

(HT48C30 RC OSC)

No load

_SYS=2MHz

f

2

1

2

Operating Current

(HT48C50 Crystal OSC)

No load

f_SYS=4MHz

2.5

0.75

1.5

3.4

1

5

1.5

3

Operating Current

(HT48C50 RC OSC)

No load

_SYS=2MHz

f

3

Operating Current

(HT48C70 Crystal OSC)

No load

f_SYS=4MHz

6

2

Operating Current

(HT48C70 RC OSC)

No load

_SYS=2MHz

f

2.1

—

4

5

Standby Current

(WDT Enabled)

No load

system halt

10

1

Standby Current

(WDT Disabled)

No load

system halt

µA

2

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HT48CXX/HT48RXX

Test Con d ition s

Sym bol

V_IL

P a r a m eter

Min . Typ . Ma x. Un it

V_DD

Con d ition s

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

—

0

—

0.9

1.5

3

Input Low Voltage for I/O

ports

V

—

2.1

3.5

0

—

Input High Voltage for I/O

Ports

V_IH

—

5

—

0.7

1.3

3

Input Low Voltage

(TMR, TMR0, TMR1, INT)

V_IL1

V_IH1

V_IL2

V_IH2

I_OL

V

—

0

—

2.3

3.8

—

1.5

4

—

Input High Voltage

(TMR, TMR0, TMR1, INT)

V

—

5

—

1.5

2.5

2.4

4.0

4

—

80

50

Input Low Voltage (RES)

Input High Voltage (RES)

I/O Ports Sink Current

I/O Ports Source Current

V

—

V

—

V

_OL=0.3V

mA

kΩ

5V V_OL=0.5V

3V _OH=2.7V

5V V_OH=4.5V

10

–2

–4.5

60

30

V

–1

–2

40

10

I_OH

3V

5V

—

Pull-high Resistance of I/O

Ports and INT

R_PH

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HT48CXX/HT48RXX

A.C. Characteristics

Ta=25°C

Test Con d ition s

Sym bol

f_SYS1

P a r a m eter

Min . Typ . Ma x. Un it

V_DD

Con d ition s

3V

5V

3V

5V

3V

5V

—

400

0

—

90

65

23

17

4000

8000

2000

3000

4000

180

kHz

System Clock (Crystal OSC)

System Clock (RC OSC)

f_SYS2

Timer I/P Frequency

(TMR, TMR0, TMR1)

f_TIMER

0

45

35

12

9

t_WDTOSCWatchdog Oscillator

—

µs

130

45

Watchdog Time-out

Period (RC)

Without WDT

prescaler

t_WDT1

ms

35

Watchdog Time-out Period

(System Clock)

Without WDT

prescaler

t_WDT2

—

1

1024

—

t_SYS

External Reset Low Pulse

Width

t_RES

—

µs

Power-up or

Wake-up from

halt

System Start-up Timer

Period

t_SST

—

1

1024

—

t_SYS

t_INT

Interrupt Pulse Width

—

µs

Note: t_SYS=1/f_SYS

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25th May ’99

HT48CXX/HT48RXX

Functional Description

The four m icrocontrollers of the HT48C10/

HT48C30/HT48C50/HT48C70 are constructed

using basically the same principles. Their dif-

ferences lie in variations in sizes such as ROM

and RAM as well as bit number, counter num-

ber, I/O line number, and different level subrou-

tine nesting bit number. The following is a more

detailed description of the system architectures

of the four microcontrollers. Unless specified,

the architecture stated below exists in these

four microcontrollers.

trols a sequence in which the instructions

stored in the program ROM are executed. The

contents of the PC can specify 1024, 2048, 4096,

or 8192 addresses at maximum, according to

t h e m icr ocon t r oller (H T48C10/H T48C30/

HT48C50/HT48C70) chosen.

After accessing a program memory word in or-

der to fetch an instruction code, the contents of

the PC is incremented by one. The PC then

points to the memory word consisting of the

next instruction code.

When executing a jump instruction, conditional

skip execution, loading a PCL register, a sub-

routine call, an initial reset, an internal inter-

rupt, an external interrupt, or returning from a

subroutine, the PC manipulates a program

transfer by loading the address corresponding

to each instruction.

Execution flow

The system clock is derived from either a crystal

or an RC oscillator. It is internally divided into

four non-overlapping clocks. Each instruction

cycle consists of four system clock cycles.

Instruction fetching and execution are pipe-

lined in such a way that a fetch takes one in-

struction cycle while decoding and execution

takes the next instruction cycle. The pipelining

scheme causes each instruction to effectively

execute in a cycle. If an instruction changes the

program counter, two cycles are required to

complete the instruction.

The conditional skip is activated by instructions.

Once the condition is met, the next instruction,

fetched during the current instruction execution,

is discarded and a dummy cycle replaces it to get

a proper instruction; otherwise it proceeds to the

next instruction.

The lower byte of the PC (PCL) is a readable

and writeable register (06H). Moving data into

the PCL performs a short jump. The destination

is within 256 locations.

Program counter – PC

The program counter (PC) is of different sizes

ranging from 10 bits to 13 bits according to the

m icr ocon t r oller s elect ed (10 bit s for t h e

HT48C10; 11 bits for the HT48C30; 12 bits for

the HT48C50; 13 bits for the HT48C70). It con-

For a control transfer to take place, an addi-

tional dummy cycle is required.

Execution flow

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25th May ’99

HT48CXX/HT48RXX

Program memory – ROM

The program memory (ROM) is used to store the

program instructions that are to be executed. It

contains data, table, and interrupt entries, and

is organized into 1024×14 bits, 2048×14 bits,

4096×15 bits, or 8192×16 bits according to the mi-

crocontroller (HT48C10/ HT48C30/HT48C50/

HT48C70) selected. These bits are all addressed by the

PC and table pointer.

Certain locations in the ROM stated below are

reserved for special usage in the four microcon-

trollers except location 00CH which is used for

the HT48C50/HT48C70 exclusively.

•

Location 000H

Location 000H is reserved for program in-

itialization. After chip reset, the program al-

ways begins execution at this area.

•

Location 004H

Location 004H is reserved for external inter-

rupt service program. If the INT input pin is

activated, the interrupt is enabled, and the

stack is not full, the program begins execution

at location 004H.

Program memory

HT48C50/HT48C70. If the timer interrupt re-

sults from a timer/event counter overflow of

t h e H T48C10/H T48C30 or a t im er /even t

counter 0 overflow of the HT48C50/HT48C70,

and the interrupt is enabled, and the stack is

not full, the program begins execution at loca-

tion 008H.

•

Location 008H

Location 008H is reserved for the timer/event

count er int errupt service program of the

HT48C10/HT48C30 and for the timer/event

counter 0 interrupt service program of the

Mod e

Con ten ts of P r ogr a m Cou n ter (m bit s)

Initial reset

0000H

0004H

0008H

000CH

PC+2

External interrupt

Timer/event counter 0 overflow

Timer/event counter 1 overflow

Skip

Loading PCL

Low byte replaced by instruction code

Instruction code

J ump, call branch

Return from subroutine

Stack register

Notes: m=10 for the HT48C10

m=11 for the HT48C30

m=12 for the HT48C50

m=13 for the HT48C70

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25th May ’99

HT48CXX/HT48RXX

•

Location 00CH

to both the main routine and the ISR cannot

be avoided, interrupts should be disabled

prior to the table read instruction, and they

should not be enabled until the TBLH is

backed-up. All the table related instructions

require 2 cycles to complete an operation.

These areas may function as a normal pro-

gram memory depending upon the user ’s re-

quirements.

Location 00CH is reserved for the timer/ event

counter 1 interrupt service program of the

HT48C50/HT48C70 only. If the timer inter-

rupt results from a timer/event counter 1

overflow, the interrupt is enabled, and the

stack is not full, the program begins execution

at location 00CH.

•

Table location

Any location in the ROM can be used as a

look–up table. The instructions TABRDC [m]

(the current page, 1 page=256 words) and

TABRDL [m] (the last page) transfer the con-

tents of the lower-order byte to the specified

data memory, and the higher-order byte to

TBLH (08H). Only the destination of the

lower-order byte in the table is well-defined,

and the higher-order byte of the table word is

transferred to the Table Higher-order byte

register (TBLH). The TBLH is read only. The

Table Pointer (TBLP), on the other hand, is a

read/write register (07H) used to indicate the

table location. Before accessing the table, the

location should be placed in the TBLP. The

TBLH is read only and cannot be restored. If

the main routine and the ISR (Interrupt Serv-

ice Routine) both employ the table read in-

struction, the contents of the TBLH in the

main routine is likely to be changed by the

table read instruction used in the ISR. Errors

will then occur. Hence, simultaneously using

the table read instruction in the main routine

and the ISR should be avoided. Nonetheless,

if the application of the table read instruction

Stack register – STACK

The stack register is a special memory port used

to save the contents of the PC. The stack can be

organized into 2, 4, or 8 levels according to the

m icr ocon t r oller select ed (2 levels for t h e

HT48C10/HT48C30, 4 levels for the HT48C50,

8 levels for the HT48C70). The register is nei-

ther part of the data nor part of the program,

and is neither readable nor writeable. Any acti-

vated level is indexed by a stack pointer (SP)

and is neither readable nor writeable. At a sub-

routine call or interrupt acknowledgment, the

contents of the PC is pushed onto the stack. At

the end of a subroutine or an interrupt routine,

signaled by a return instruction (RET or RETI),

the contents of the PC is restored to its previous

value from the stack. After chip reset, the SP

will point to the top of the stack.

If the stack is full and a non-masked interrupt

takes place, the interrupt request flag is recorded

but the acknowledgment is still inhibited. After

the stack pointer is decremented (by RET or

RETI), the interrupt will be serviced. This feature

prevents the occurrence of stack overflow, allow-

Ta ble Loca t ion

In str u ction (s)

*m ~*8

Pm~P8

1~1

7

@7

6

@6

5

@5

4

@4

3

@3

2

@2

1

@1

0

@0

TABRDC [m]

TABRDL [m]

Table location

Notes: m~ 0: Bits of table location

@7~@0: Bits of table pointer

Pm~P8: Bits of current

m=9 for the HT48C10

m=10 for the HT48C30

m=11 for the HT48C50

m=12 for the HT48C70

Program Counter

15

25th May ’99

HT48CXX/HT48RXX

ing the programmer to use the structure easily.

Likewise, if the stack is full and a CALL is

subsequently executed, a stack overflow will

occur and the first entry will be lost (only the

m ost r ecent four r etur n addresses will be

stored).

Data memory – RAM

The data memory (RAM) is composed of bits

ranging from 81×8, 113×8, 184×8, or 255×8, de-

p en d in g on t h e m icr ocon t r oller ch os en

(HT48C10/ HT48C30/HT48C50/HT48C70). It is

divided into two functional groups, i.e., special

function registers and general purpose data

memory (of 64×8, 96×8, 160×8, or 224×8 bits,

depen ding on t h e m icr ocon t r oller select ed

(H T48C10/ H T48C30/H T48C50/H T48C70).

Most components of the two functional groups

are readable/writable, but some are read-only.

Of the two functional groups, the special func-

tion registers of the four microcontrollers con-

sist of a program counter lower-order byte

register (PCL;06H ), an accum ulator (ACC;

05H), a ta ble pointer (TBLP;07H), a table

h igh er-or der byt e r egist er (TBLH ;08H ), a

status register (STATUS;0AH), an interrupt

control register (INTC;0BH), a watchdog timer

option setting register (WDTS;09H), an indirect

addressing register (00H), a memory pointer

r egist er (MP ;01H ), a t im er /even t cou n t er

(TMR;0DH), a timer/event counter control reg-

is t er

(TMRC;0E H ),

I /O

r e gis t er s

(PA;12H,PB;14H, PC;16H), and I/O control reg-

isters (PAC;13H,PBC;15H,PCC;17H). But of

the HT48C50/HT48C70, the following compo-

nents are further divided into two or several

sub-components. First, the indirect addressing

register is divided into two registers involving

indirect addressing register 0 (00H) and indi-

rect addressing register 1 (02H). Second, the

memory pointer register is also comprised by

two registers involving memory pointer register

0 (MP0;01H) and memory pointer register 1

(MP1;03H). Third, the timer/event counter reg-

ister is organized by two registers according to

different orders of byte, namely timer/event

h igher-or der byt e register a nd timer/event

lower-order byte register, both of which are fur-

ther divided into timer/event counter 0 higher-

RAM mapping

order byte register (TMR0H; 0CH), timer/ event

cou n t er h igh er -or der byt e r egis t er

1

(TMR1H;0FH), timer/event counter 0 lower-or-

d er byt e r e gis t er (TMR0L;0DH ), a n d

timer/event counter 1 lower-order byte register

(TMR1L;10H). Fourth, the timer/event counter

control register is divided into two registers

involving timer/event counter 0 control register

16

25th May ’99

HT48CXX/HT48RXX

(TMR0C;0EH) and timer/event counter 1 con-

trol register (TMR1C;11H). Fifth, the entire

number of I/O registers is expanded from 3 to 6

(PA;12H ,P B;14H ,P C;16H ,P D;18H ,P E ;1AH ,

PF;1CH,PG; 1EH). Finally, the number of I/O

control registers is also doubled (PAC;13H,

P B C ;1 5 H ,P C C ;1 7 H ,P D C ;1 9 H ,P E C ;1 B H ,

PFC;1DH,PGC;1FH). The remaining space be-

fore the 20H of the four microcontrollers are all

reserved for future expansion usage. Reading

these remaining locations will return the result

to 00H. The general purpose data memory, ad-

dr essed fr om 40H ~7F H of t h e H T48C10,

20H~7FH of the HT48C30, 60H~FFH of the

HT48C50, or 20H~FFH of the HT48C70 accord-

ing to the microcontroller selected, is used for

data and control information under instruction

commands.

by combining the corresponding indirect ad-

d r es s in g r egis t er s . Th e bit

7

of MP

(HT48C10/HT48C30) is undefined and reading

will return the result “1”. Any writing operation to

MP will only transfer the lower 7-bit data to MP.

Accumulator ACC

The accumulator (ACC) relates to the ALU op-

erations. It is also mapped to location 05H of the

RAM and is capable of operating with immedi-

ate data. The data movement between two data

memories will pass through the ACC.

Arithmetic and logic unit – ALU

This circuit performs 8-bit arithmetic and logic

operations. It provides the following functions:

•

Arithmetic operations (ADD, ADC, SUB,

SBC, DAA)

All the RAM areas can directly execute arithme-

tic, logic, increment, decrement, and rotate op-

erations. Except some dedicated bits, each bit in

the RAM can be set and reset by the SET [m].i

and CLR [m].i instructions, respectively. These

RAM areas are indirectly accessible through the

memory pointer register(s) MP (01H) of the

HT48C10/HT48C30 or MP0 (01H) and MP1

(03H) of the HT48C50/HT48C70.

•

Logic operations (AND, OR, XOR, CPL)

•

Rotation (RL, RR, RLC, RRC)

•

Increment and Decrement (INC, DEC)

•

Branch decision (SZ, SNZ, SIZ, SDZ, etc.)

The ALU saves the results of the data operation

and change the status register as well.

Status register – STATUS

Indirect addressing register

The status register (0AH) is of 8 bits wide and

consists of a zero flag (Z), a carry flag (C), an

auxiliary carry flag (AC), an overflow flag (OV),

a power down flag (PD), and a watchdog time-

out flag (TO). The register also records the status

information and controls the operation sequence.

Of the four microcontrollers, the HT48C10/

HT48C30 make use of location 00H whereas the

HT48C50/HT48C70 of locations 00H and 02H

as indirect addressing registers that are not

physically implemented. Any read/write opera-

tion of [00H] or of [00H] and [02H] accesses the

RAM pointed to by MP (01H) or by MP0 (01H)

and MP1 (03H) respectively according to the

microcontroller chosen. Reading location 00H or

02H indirectly will return the result 00H. Writ-

ing it indirectly will, result to no operation.

Except the TO and PD flags, bits in the status

register can all be altered by instructions, simi-

lar to the case with other registers. Any data

written into the status register will not change

the TO or PD flags. But the operations related

to the status register may lead to different re-

sults from those intended. The TO and PD flags

can be changed by system power up, Watchdog

Timer overflow, executing the HALT instruc-

tion, or clearing the Watchdog Timer. The Z, OV,

AC, and C flags all reflect the status of the

latest operations.

The function of data movement between two

indirect addressing registers is not supported.

Th e m em or y p oin t er r egist er MP of t h e

HT48C10/HT48C30 or MP0 and MP1 of the

HT48C50/HT48C70 are of 7 bits or 8 bits wide

respectively, and can be used to access the RAM

17

25th May ’99

HT48CXX/HT48RXX

On entering the interrupt sequence or execut-

ing the subroutine call, the status register will

not be automatically pushed onto the stack . If

the contents of the status is important and the

subroutine can corrupt the status register, the

programmer should take precautions to save it

properly.

if the related interrupt is enabled, until the SP

is decremented. If immediate servicing is de-

sired, the stack should be prevented from be-

coming full.

All these interrupts have a wake-up capability.

As an interrupt is serviced, a control transfer

occurs by pushing the PC onto the stack and

then by branching it to subroutines at the speci-

fied location(s) in the ROM. Only the contents of

the PC can be pushed onto the stack. If the

contents of the register and of the status regis-

ter (STATUS) are altered by the interrupt serv-

ice program which corrupts the desired control

sequence, the programmer should save these

contents first.

Interrupt

The four microcontrollers all provide an exter-

nal interrupt and internal timer/event counter

in t er r u pt s. Th e in t er r u pt con t r ol r egist er

(INTC;0BH) contains interrupt control bits for

setting the enable/disable mode and the interrupt

request flags.

Once an interrupt subroutine is serviced, the

remaining interrupts will all be blocked (by

clearing the EMI bit). This scheme may prevent

any further interrupt nesting. Other interrupt

requests may happen during this interval but

only the interrupt request flag will be recorded.

If a certain interrupt requires servicing within

the service routine, the programmer may set the

EMI bit and the corresponding bit of INTC so as

to allow interrupt nesting. If the stack is full, the

interrupt request will not be acknowledged, even

The external interrupt is triggered by a high to

low transition of the INT, and the related inter-

rupt request flag (EIF; bit 4 of INTC) is then set.

When the interrupt is enabled, the stack is not

full, and the external interrupt is active, a sub-

routine call to location 04H will occur. The inter-

rupt request flag (EIF) and EMI bits will also be

cleared to disable other interrupts.

Of t h e fou r m icr ocon t r oller s, t h e in t er n a l

timer/event counter interrupt of the HT48C10/

HT48C30 is initialized by setting the timer/

La bels

Bits

F u n ction

C is set if the operation results in a carry during an addition operation or if a

borrow does not take place during a subtraction operation; otherwise C is

cleared. Also it is affected by a rotate through carry instruction.

C

0

AC is set if the operation results in a carry out of the low nibbles in addition or

no borrow from the high nibble into the low nibble in subtraction; otherwise AC

is cleared.

AC

1

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is

cleared.

Z

2

3

4

5

OV is set if the operation results in a carry into the highest-order bit but not a

carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

OV

PD

TO

PD is cleared by either a system power-up or executing the CLR WDT

instruction. PD is set by executing the HALT instruction.

TO is cleared by a system power-up or executing the CLR WDT or HALT

instruction. TO is set by a WDT time-out.

—

6

7

Undefined, read as 0

Status register

18

25th May ’99

HT48CXX/HT48RXX

event counter interrupt request flag (TF; bit 5 of

INTC), that is caused by a timer overflow. When

the interrupt is enabled, and the stack is not

full, and the TF bit is set, a subroutine call to

location 08H will occur. The related interrupt

request flag (TF) will be reset and the EMI bit

will be cleared to disable further interrupts.

knowledgments are all held until the RETI in-

struction is executed or the EMI bit and the

related interrupt control bit are both set to 1

(when the stack is not full). To return from the

interrupt subroutine, the RET or RETI instruc-

tion may be invoked. The RETI will set the EMI

bit in order to enable an interrupt service

whereas the RET will not.

Th e in t er n a l t im er /even t cou n t er of t h e

HT48C50/HT48C70, is composed of two inter-

rupts, namely internal timer/event counter 0

interrupt and timer/event counter 1 interrupt.

The internal timer/event counter 0 interrupt is

initialized by setting the timer/event counter 0

interrupt request flag (T0F; bit 5 of INTC)

which is caused by a timer/event counter 0 over-

flow. After the interrupt is enabled, the stack is

not full, and the T0F bit is set, a subroutine call

to location 08H will occur. The related interrupt

request flag (T0F) will be reset and the EMI bit

be cleared to disable further interrupts. On the

other hand, the timer/event counter 1 interrupt

is operated in the same manner as the timer/

event counter 0. The related interrupt control

bits ET1I and T1F of the timer/event counter 1

are bit 3 and bit 6 of the INTC, respectively.

Interrupts that occur in an interval between the

rising edges of two consecutive T2 pulses are

serviced on the latter of the two T2 pulses if the

corresponding interrupts are enabled. In case of

sim ulta neous r equests, the following ta ble

shows the priority that is applied. These can be

masked by resetting the EMI bit.

No. In ter r u p t Sou r ce P r ior ity Vector

a

External interrupt

1

2

04H

08H

Timer/event

counter 0 overflow

b

Timer/event

counter 1 overflow

*c

3

0CH

* Note: c applies only to the HT48C50/ HT48C70

During the execution of an interrupt subroutine

of the four microcontrollers, other interrupt ac-

Register

Bit No.

La bel

F u n ction

Control the master (global) interrupt

(1= enabled; 0= disabled)

0

EMI

Control the external interrupt

(1= enabled; 0= disabled)

1

2

3

4

5

EEI

ET0I

ET1I

EIF

Control the timer/event counter 0 interrupt

(1= enabled; 0= disabled)

Con t r ol t h e t im er /even t cou n t er 1 in t er r u pt (for t h e

HT48C50/HT48C70 only) (1= enabled; 0= disabled)

INTC

(0BH)

External interrupt request flag

(1= active; 0= inactive)

Internal timer/event counter 0 request flag

(1= active; 0= inactive)

T0F

I n t er n a l t im er /even t cou n t er 1 r equ es t fla g (for t h e

HT48C50/HT48C70 only) (1= active; 0= inactive)

6

7

T1F

—

Unused bit, read as “0”

INTC register

19

25th May ’99

HT48CXX/HT48RXX

The timer/event counter interrupt request flag

(TF), external interrupt request flag (EIF), en-

able timer/event counter bit (ETI), enable exter-

nal interrupt bit (EEI), and enable master

interrupt bit (EMI) constitute an interrupt con-

trol register (INTC) of the HT48C10/HT48C30

which is located at 0BH in the RAM. On the

other hand, the timer/event counter 0/1 inter-

rupt request flag (T0F/T1F), external interrupt

request flag (EIF), enable timer/event counter

0/1 bit (ET0I/ET1I), enable external interrupt

bit (EEI), and enable master interrupt bit (EMI)

make up the interrupt control register (INTC) of

the HT48C50/HT48C70 which is located at 0BH

in t h e RAM. E MI, E E I, a n d E TI, of t h e

HT48C10/HT48C30 or EMI, EEI, ET0I, and

ET1I of the HT48C50/HT48C70 are all used to

control the enable/disable status of interrupts.

These bits prevent the requested interrupt from

being serviced. Once the interrupt request flags

(TF, EIF of the HT48C10/HT48C30 or T0F, T1F,

EIF of the HT48C50/HT48C70) are set, they

will remain in the INTC register until the inter-

rupts are all serviced or cleared by a software

instruction.

System oscillator

VDD is required and its resistance ranges from

51kΩ to 1MΩ. The system clock, divided by 4, is

available on OSC2 (NMOS open drain output),

which can be used to synchronize external logic.

The RC oscillator provides the most cost effec-

tive solution. However, the frequency of the os-

cillation may vary with VDD, temperature and

the chip itself due to process variations. It is,

therefore, not suitable for timing sensitive op-

erations where accurate oscillator frequency is

desired. On the other hand, if the crystal oscil-

lator is used, a crystal across OSC1 and OSC2

is needed to provide the feedback and phase

shift required for the crystal oscillator. No other

external components are required. Instead of a

crystal, the resonator can also be connected be-

tween OSC1 and OSC2 to derive a frequency

reference, but two external capacitors in OSC1

and OSC2 are required.

It is suggested that a program should not em-

ploy the “CALL subroutine” within the inter-

rupt subroutine, since its operation within the

interrupt subroutine may damage the original

control sequence, and interrupts often occur in

an unpredictable manner or it may need imme-

diate servicing for certain applications. Given

this, if only one stack is left and enabling the

interrupt is not well controlled, the original con-

trol sequence may be ruined as a result of operating

the CALL subroutine in the interrupt subroutine.

The WDT oscillator is a free running on-chip RC

oscillator, and no external components are re-

quired. Even if the system enters the power

down mode, the system clock is stopped but the

WDT oscillator still works with a period of ap-

proximately 78 µs. The WDT oscillator can be

disabled by mask option to conserve power.

Oscillator configuration

Watchdog timer – WDT

There are 2 oscillator circuits available, namely

RC oscillator and crystal oscillator, decided by

mask options. Both are designed for system

clocks. No matter what type of oscillator is cho-

sen, the signal supports the system clock. The

HALT mode stops the system oscillator and ig-

nores any external signals so as to conserve

power.

The clock source of the WDT is implemented by

a dedicated RC oscillator (WDT oscillator) or an

instruction clock (system clock divided by 4),

decided by mask options. The WDT is designed

to prevent a software malfunction or sequence

from jumping to an unknown location with un-

predictable results. The WDT can be disabled

by mask option. If the WDT is disabled, all the

executions related to the WDT may lead to no

operation.

Of the two oscillator types, if an RC oscillator is

used, an external resistor between OSC1 and

20

25th May ’99

HT48CXX/HT48RXX

Watchdog timer

If the internal WDT oscillator (RC oscillator

with a period of 78µs normally) is selected, it is

first divided by 256 (8 stages) to derive a nomi-

nal time-out period of about 20ms. This time-

out period may vary with temperature, VDD,

and process variations. By invoking the WDT

prescaler, longer time-out periods can be real-

ized. Writing data to WS2, WS1, and WS0 (bit

2,1,0 of the WDTS) can lead to different time-

out periods. If the values of WS2, WS1, and WS0

all equal to 1, the division ratio is up to 1:128,

and the maximum time-out period is 2.6 sec-

onds.

strongly recommended, since the HALT will ter-

minate the system clock.

The overflow of WDT under normal operation

can initialize “chip reset” and set the status bit

TO. But in the HALT mode, the overflow will

initialize a “warm reset”, and only the PC and

SP are reset to zero. To clear the contents of

WDT (t he WDT pr esca ler included), t hree

methods can be adopted, i.e., external reset (a

low level to RES), software instruction(s), and a

HALT instruction. The software instruction(s)

consists of CLR WDT and the other set — CLR

WDT1 and CLR WDT2. Of these two types of

instructions, only one type can be active de-

pending on mask option — “CLR WDT times

selection option”. If the “CLR WDT” is chosen

(i.e., CLRWDT times equal one), any execution

of the CLR WDT instruction will clear the WDT.

In the case that the “CLR WDT1” and “CLR

WDT2” are chosen (i.e., CLRWDT times equal

two), these two instructions should be executed

to clear the WDT; otherwise, the WDT may

reset the chip due to time-out.

But if the WDT oscillator is disabled, the WDT

clock may still come from the instruction clock

and operate in the same manner except that in

the HALT state the WDT may stop counting

and lose its protecting purpose. In this situation

the logic can be restarted by external logic. The

high nibble and bit 3 of the WDTS are reserved

for user defined flags, and the programmer may

use these flags to indicate some specified status.

WS2

WS1

WS0

Division Ra t io

Power down operation – HALT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1:1

1:2

The HALT mode is initialized by the HALT

instruction and results in the following.

1:4

•

The system oscillator turns off but the WDT

1:8

oscillator keeps running (if the WDT oscillator

is selected).

1:16

1:32

1:64

1:128

•

The contents of the on–chip RAM and regis-

ters remain unchanged.

•

The WDT and WDT prescaler are cleared and

recount (if the WDT clock comes from the

WDT oscillator).

•

All I/O ports maintain their original status.

WDTS Register

•

The PD flag is set and the TO flag is cleared.

If the device operates in a noisy environment,

using the on-chip RC oscillator (WDT OSC) is

The system can quit the HALT mode by exter-

25th May ’99

21

HT48CXX/HT48RXX

nal reset, interrupt, external falling edge signal

on port A, or a WDT overflow. An external reset

may cause device initialization, and the WDT

overflow performs a “warm reset”. Examining the

TO and PD flags, the reason for chip reset is

determined. The PD flag is cleared by system

power-up or executing the CLR WDT instruction,

and is set by executing the HALT instruction. The

TO flag is set if the WDT time-out occurs, and

causes a wake-up that resets the PC and SP only.

The others maintain their original status.

Reset timing chart

The port A wake-up and interrupt methods can

be considered as a continuation of normal exe-

cution. Each bit in port A can be independently

selected to wake up the device by mask option.

Awakening from an I/O port stimulus, the pro-

gram will resume execution of the next instruc-

tion. On the other hand, awakening from an

interrupt, two sequences may happen. If the

related interrupt(s) is disabled or the inter-

rupt(s) is enabled but the stack is full, the pro-

gr a m will r esu m e execu t ion a t t h e n ext

instruction. But if the interrupt is enabled and

the stack is not full, the regular interrupt re-

sponse takes place.

Reset circuit

When wake-up event(s) occurs, it takes 1024

t_SYS(system clock period) to resume normal

operation. That is to say, a dummy period is

inserted after the wake-up. If the wake-up re-

sults from an interrupt acknowledgment, the

actual interrupt subroutine execution will be

delayed by more than one cycle. But if the wake-

up results in the next instruction execution, the

instruction will execute immediately after the

dummy period is finished. If an interrupt re-

quest flag is set to “1” before entering the HALT

mode, the make-up function of the related inter-

rupt will be disabled.

Reset configuration

WDT time-out during the HALT is different

from other chip reset conditions, for it can per-

form a “warm reset” that resets only PC and SP

and leaves the other circuits at their original

state. Some registers remain unchanged during

any other reset conditions. Most of the registers

are reset to the “initial condition” when the

reset conditions are met. By examining the PD

flag and TO flag, the program distinguishes

between different “chip resets”.

To minimize power consumption, all the I/O

pins should be carefully managed before enter-

ing the HALT status.

TO

P D

RESET Con d ition s

Reset

0

RES reset during power-up

There are three ways in which reset may occur:

•

RES reset during normal

operation

RES is reset during normal operation

RES is reset during HALT

u

0

u

1

WDT timeout is reset during normal operation

RES wake-up HALT

22

25th May ’99

HT48CXX/HT48RXX

Timer/event counter

TO

1

P D

u

RESET Con d ition s

There a re two tim er/event counters im ple-

mented in the four microcontrollers. Of the four

microcontrollers, the timer/event counter of the

HT48C10/HT48C30 contains an 8-bit program-

mable count-up counter. On the other hand, the

timer/event counter of the HT48C50/HT48C70

composes of two counters, namely timer/event

cou nt er 0 a nd t im er /even t cou n ter 1. The

timer/event counter 0 contains a 16-bit pro-

gr a m m a ble cou n t er, a n d t h e t im er /even t

cou n t er 1 con ta in s a n 8-bit progra mm able

cou n t -u p cou n t er of t h e H T48C50. Th e

timer/event counters 0 and 1 of the HT48C70

both contain a 16-bit programmable count-up

counter. The source of the clock of the four mi-

cr ocon t r oller s m a y com e fr om a n ext erna l

source or the system clock divided by 4. If the

internal instruction clock is applied, only one

reference time-base is available. The external

clock input, on the other hand, allows the user

to count external events, measure time inter-

vals or pulse width, or generate an accurate

time base.

WDT time-out during normal

operation

1

WDT wake-up HALT

Note: “u” means “unchanged”

To gu a ra n t ee that the system oscillator is

started and stabilized, the SST (System Start-

up Timer) provides an extra-delay. The extra-

delay delays 1024 system clock pulses when the

system powers up or awakes from the HALT

state.

When the system power-up occurs, the SST de-

lay is added during the reset period. But when

the reset comes from the RES pin, the SST delay

is disabled. Any wake-up from HALT will enable

the SST delay.

The status of the chip reset of the functional

units are as shown.

PC

000H

Interrupt

Prescaler

Disabled

Cleared

Of the HT48C10/HT48C30, there are two regis-

ters related to the timer/event counter, i.e.,

TMR ([0DH]) and TMRC ([0EH]). There are two

physical registers mapped to the TMR location.

Writing TMR puts the starting value in the

tim er /even t cou n t er preloa d register while

reading TMR gets the contents of the timer/

event counter. The TMRC, on the other hand, is

a timer/event counter control register.

Cleared

After a master reset,

WDT begins counting.

WDT

Timer/event

counter (0/1)

Off

Input/output ports

SP

Input mode

Point to the top of the

stack

Timer/event counter 0/1

23

25th May ’99

HT48CXX/HT48RXX

The states of the special function registers are summarized in the following table:

WDT tim e-ou t

(n or m a l

op er a tion )

RES r eset

(n or m a l

op er a tion )

WDT

tim e-ou t*

(HALT)

Reset

(p ow er on )

RES r eset

(HALT)

Register

TMR1H

TMR1L

TMR1C

TMR0H

TMR0L

TMR0C

PC

xxxx xxxx

00-0 1---

uuuu uuuu

00-0 1---

uuuu uuuu

00-0 1---

uuuu uuuu

00-0 1---

uuuu uuuu

uu-u u---

xxxx xxxx

00-0 1---

uuuu uuuu

00-0 1---

uuuu uuuu

00-0 1---

uuuu uuuu

00-0 1---

uuuu uuuu

uu-u u---

000H

MP0

MP1

ACC

xxxx xxxx

--00 xxxx

-000 0000

0000 0111

1111 1111

uuuu uuuu

--1u uuuu

-000 0000

0000 0111

1111 1111

uuuu uuuu

--uu uuuu

-000 0000

0000 0111

1111 1111

uuuu uuuu

--01 uuuu

-000 0000

0000 0111

1111 1111

uuuu uuuu

--11 uuuu

TBLP

TBLH

STATUS

INTC

WDTS

PA

-uuu uuuu

uuuu uuuu

PAC

PB

PBC

PC

PCC

PD

PDC

PE

PEC

PF

PFC

PG

PGC

Note: “ ” means “warm reset”

“u” means “unchanged”

“x” means “unknown”

“–” means “undefined”

The bits of the special function registers are denoted as “–” if they are not defined

in the microcontrollers.

24

25th May ’99

HT48CXX/HT48RXX

Of the HT48C50/HT48C70, the timer/event

counter is com prised by two counters, i.e.,

timer/event counter 0 and timer/event counter

1. There are three registers related to the

timer/event counter 0, namely TMR0H (0CH),

TMR0L (0DH), and TMR0C (0EH). Writing

TMR0L only writes the data into a low byte

buffer, but writing TMR0H writes the data

along with the contents of the low byte buffer

into the timer/event counter 0 preload register

(16-bit). The timer/event counter 0 preload reg-

ister is changed by writing the TMR0H opera-

tions, and writing TMR0L keeps the timer/

event counter 0 preload register unaltered.

Also, reading the TMR0H latches the TMR0L

into the low byte buffer in order to avoid the

false timing problem. Then, reading the TMR0L

will return the contents of the low byte buffer.

In other words, the low byte of the timer/event

counter 0 cannot be read directly. Instead it has

to read the TMR0H first in order to make the

low byte contents of the timer/event counter 0

latched into the buffer. On the other hand, there

a r e a ls o t h r e e r egis t e r s r ela t e d t o t h e

timer/event counter 1, namely TMR1H (0FH),

TMR1L (10H), and TMR1C (11H). The timer/

event counter 1 operates in the same manner as

the timer/event counter 0.

options as the timer/event counter 0 and is de-

fined by TMR1C.

The timer/event counter control registers of the

four microcontrollers are all used to define the

operation mode, counting enable or disable, and

active edge.

The TM0 and TM1 bits define the operation

mode. The event count mode is used to count

external events, which means that the clock

source comes from an external pin TMR of the

H T48C10/H T48C30 or TMR0/TMR1 of the

HT48C50/HT48C70. The timer mode functions

as a normal timer with the clock source coming

from the instruction clock. The pulse width

measurement mode can be used to count the

high or low level duration of the external signal

TMR of the HT48C10/HT48C30 or TMR0/TMR

1 of the HT48C50/HT48C70. The counting is

based on the instruction clock.

In the event count or timer mode, once the

timer/event counter starts counting, it will count

from the current contents in the timer/event

counter to FFH of the HT48C10/HT48C30/

HT48C50 (TMR1) or to FFFFH of the HT48C50

(TMR0)/HT48C70. If an overflow occurs, the

counter is reloaded from the timer/ event counter

preload register and generates the corresponding

interrupt request flag TF (bit 5 of INTC) of the

HT48C10/HT48C30 or T0F/T1F (bit 5/6 of INTC)

of the HT48C50/ HT48C70 at the same time.

The TMR0C is a timer/event counter 0 control

register defining the timer/event counter 0 op-

tions. The timer/event counter 1 has the same

La bel

Bit s

F u n ction

—

0~2

Unused bits, read as “0”

To define TMR0/TMR1 active edge of the timer/event counter

(0= active on low to high; 1= active on high to low)

TE

3

To enable/disable timer counting

(0= disabled; 1= enabled)

TON

4

5

—

Unused bits, read as “0”

To define the operating mode

01= Event count mode (external clock)

10= Timer mode (internal clock)

11= Pulse width measurement mode

00= Unused

TM0

TM1

6

7

TMR0C/TMR1C register

25

25th May ’99

HT48CXX/HT48RXX

In the pulse width measurement mode with the

values of the TON and TE bits equal to one, if the

TMR0/ TMR1 has received a transient from low

to high (or high to low; if the TE bit is 0) it will

s t a r t cou n t in g u n t il t h e TMR of t h e

H T48C10/H T48C30 or TMR0/TMR1 of t h e

HT48C50/ HT48C70 returns to the original level

and resets the TON. The measured result re-

mains in the timer/event counter even if the

activated transient happens again. In other

words, only one cycle measurement can be done.

Until setting the TON, the cycle measurement

will re-function as long as it receives further

transient pulse. In this operation mode, the

timer/event counter starts counting according

not to the logic level but to the transient edges.

In the case of counter overflows, the counter is

reloaded from the timer/event counter preload

register and issues an interrupt request just like

the other two modes.

HT48C10/HT48C30 or to ET0I/ET1I of the

HT48C50/HT48C70 can disable the correspond-

ing interrupt service.

In the case of timer/event counter OFF condi-

tion, writing data to the timer/event counter

preload register also reloads that data to the

timer/event counter. Bu t if t h e t im er /even t

cou nt er is t u r n ed on, da ta writ ten t o the

tim er/event counter is reserved only in the

t im er /even t cou n t er pr eloa d r egist er. The

tim er/event counter will go on operating un-

til a n overflow occurs.

After the tim er/event counter (rea ding TMR

of t h e H T 4 8 C 1 0 /H T 4 8 C 3 0 or T M R 0 H /

TMR1H of the HT48C50/HT48C70) is read,

the clock is blocked to a void errors. As this

ma y results in a counting error, blocking of

the clock should be ta ken into a ccount by the

progra mm er.

To enable the counting operation, the timer ON

bit (TON; bit 4 of TMRC of the HT48C10/

HT48C30 or bit 4 of TMR0C/TMR1C of the

HT48C50/HT48C70) should be set to 1. In the

pulse width measurement mode, the TON will

be cleared automatically after the measure-

ment cycle is complete. But in the other two

modes the TON can only be reset by instruc-

tions. The overflow of the timer/event counter is

one of the wake-up sources. No matter what the

operation mode is, writing a 0 to ETI of the

Input/output ports

There are various numbers of bidirectional in-

put/output lines in the four microcontrollers.

The HT48C10 includes 18 bidirectional in-

put/output lines, labeled from PA to PC, which

are mapped to the [12H], [14H], or [16H] of the

RAM, respectively. The HT48C30 contains 22

bidirectional input/output lines, labeled from

PA to PC, which are mapped to [12H], [14H], or

[16H], respectively. The HT48C50 consists of 32

Input/output ports

26

25th May ’99

HT48CXX/HT48RXX

bidirectional input/output lines, labeled from

PA to PD, which are mapped to the [12H], [14H],

[16H ], or 18H ], r espect ively. F in a lly, t h e

HT48C70 contains 56 bidirectional input/out-

put lines, labeled from PA to PG, which are

mapped to the RAM of [12H], [14H], [16H],

[18H], [1AH], [1CH], and [1EH], respectively. Of

the four microcontrollers, all of these I/O ports

can be used for input and output operations. For

the input operation, these ports are non-latch-

ing, i.e., the inputs should be ready at the T2

r isin g edge of t h e in st r u ct ion MOV A,[m ]

(m=12H, 14H, 16H, 18H, 1AH, 1CH, or 1EH).

For the output operation, all data are latched

and remain unchanged until the output latch is

rewritten.

14H, 16H, 18H, 1AH, 1CH or 1EH (the first

three options, namely 12H, 14H, and 16H, exist

in the four microcontrollers; the HT48C50 is

provided with an extra option of 18H; these

seven options all exist in the HT48C70) instruc-

tion.

Some instructions first input data and then fol-

low the output operations. For example, the

SET [m].i, CLR [m].i, CPL [m] and CPLA [m]

instructions read the entire port states into the

CPU, execute the defined operations (bit-opera-

tion), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability to wake-up

the device.

Each I/O line has its own control register (PAC,

PBC, PCC, PDC, PEC, PFC, PGC (the fist three

registers PAC, PBC, PCC are all used by the

four microcontrollers; the register PDC is extra-

used by the HT48C50; all the seven registers

are applied in the HT48C70) to control the in-

put/ output configuration. With this control reg-

ister, CMOS output or schmitt trigger input

with or without pull-high resistor (by mask op-

tion) structures can be reconfigured dynami-

cally (i.e., on-the-fly) under software control. To

function as an input, the corresponding latch of

the control register must be written with a “1”.

The pull-high resistance shows itself automat-

ically if the pull-high option is selected. The

input source(s) also depends on the control reg-

ister. If the value of the control register bit is “1”,

the input will read the pad state. But if the

value of the control register bit is “0”, the con-

tents of the latches will be moved to the internal

bus. The latter is possible in “read-modify-

write” instruction. For the output function,

CMOS is the only configuration. These control

registers are mapped to locations 13H, 15H,

17H, 19H, 1BH, 1DH and 1FH (the first three

locations 13H, 15H, 17H exist in the four micro-

controllers; the location 19H is used for the

HT48C50; all the 7 locations are applied in the

HT48C70).

Mask option

The following table illustrates the five kinds of

mask option provided. All these options have to

be defined to ensure proper system functioning.

No.

Ma sk Op tion

OSC type selection. This option is to

decide if an RC or Crystal oscillator is

chosen as system clock. If the Crystal

oscillator is selected, the XST (Crystal

Start-up Timer) default is activated;

otherwise the XST is disabled.

1

WDT source selection. There are three

types of selection: on-chip RC oscillator,

instruction clock or disable the WDT.

2

3

CLRWDT times selection. This option

defines the way of clearing the WDT by

instruction. “Once” means that the CLR

WDT instruction can clear the WDT.

“Twice” means only if both of the CLR

WDT1 and CLR WDT2 instructions have

been executed, the WDT can be cleared.

Wake-up selection. This option defines

the activity of the wake-up function.

External I/O pins (PA only) all have the

capability to wake-up the chip from a

HALT.

4

After a chip reset, these input/output lines stay at

the high level or floating (by mask option). Each

bit of these input/output latches can be set or

cleared by the SET [m].i or CLR [m].i (m=12H,

27

25th May ’99

HT48CXX/HT48RXX

Application Circuits of HT48C70

f_SYS(k Hz)

8000

6000

4000

3580

2000

1000

640

C1

C2

Cr yst a l

OK

—

Cer a m ic r eson a tor

0

OK

—

0

300pF

OK

480

—

455

—

400

—

28

25th May ’99

HT48CXX/HT48RXX

Instruction Set Summary

In str u ction

Mn em on ic

Descr ip tion

F la g Affected

Cycle

Arithmetic

ADD A,[m]

ADDM A,[m]

ADD A,x

ADC A,[m]

ADCM A,[m]

SUB A,x

Add data memory to ACC

Add ACC to data memory

Add immediate data to ACC

Add data memory to ACC with carry

Add ACC to register with carry

Subtract immediate data from ACC

Subtract data memory from ACC

Subtract data memory from ACC with result in

data memory

Z,C,AC,OV

1

1⁽¹⁾

1

1⁽¹⁾

1

SUB A,[m]

SUBM A,[m]

1

1⁽¹⁾

SBC A,[m]

SBCM A,[m]

Subtract data memory from ACC with carry

Subtract data memory from ACC with carry with

result in data memory

Decimal adjust ACC for addition with result in

data memory

Z,C,AC,OV

1

1⁽¹⁾

DAA [m]

C

1⁽¹⁾

Logic

Operation

AND A,[m]

OR A,[m]

XOR A,[m]

ANDM A,[m]

ORM A,[m]

XORM A,[m]

AND A,x

OR A,x

XOR A,x

CPL [m]

CPLA [m]

AND data memory to ACC

OR data memory to ACC

Exclusive-OR data memory to ACC

AND ACC to data memory

OR ACC to data memory

Exclusive-OR ACC to data memory

AND immediate data to ACC

OR immediate data to ACC

Exclusive-OR immediate data to ACC

Complement data memory

Z

1

1⁽¹⁾

1

1⁽¹⁾

1

Complement data memory with result in ACC

Increment &

Decrement

INCA [m]

INC [m]

DECA [m]

DEC [m]

Increment data memory with result in ACC

Increment data memory

Decrement data memory with result in ACC

Decrement data memory

Z

1

1⁽¹⁾

1

1⁽¹⁾

29

25th May ’99

HT48CXX/HT48RXX

In str u ction

Mn em on ic

Descr ip tion

F la g Affected

Cycle

Rotate

RRA [m]

RR [m]

RRCA [m]

Rotate data memory right with result in ACC

Rotate data memory right

Rotate data memory right through carry with

result in ACC

Rotate data memory right through carry

Rotate data memory left with result in ACC

Rotate data memory left

Rotate data memory left through carry with

result in ACC

None

C

1

1⁽¹⁾

1

RRC [m]

RLA [m]

RL [m]

C

1⁽¹⁾

1

None

C

1⁽¹⁾

1

RLCA [m]

RLC [m]

Rotate data memory left through carry

C

1⁽¹⁾

Data Move

MOV A,[m]

MOV [m],A

MOV A,x

Move data memory to ACC

Move ACC to data memory

Move immediate data to ACC

None

1

1⁽¹⁾

1

Bit Operation

CLR [m].i

SET [m].i

Clear bit of data memory

Set bit of data memory

None

1⁽¹⁾

Branch

J MP addr

SZ [m]

SZA [m]

J ump unconditionally

None

2

Skip if data memory is zero

Skip if data memory is zero with data movement

to ACC

Skip if bit i of data memory is zero

Skip if bit i of data memory is not zero

Skip if increment data memory is zero

Skip if decrement data memory is zero

Skip if increment data memory is zero with result

in ACC

1⁽²⁾

SZ [m].i

SNZ [m].i

SIZ [m]

SDZ [m]

SIZA [m]

None

1⁽²⁾

1⁽³⁾

1⁽²⁾

SDZA [m]

Skip if decrement data memory is zero with re-

sult in ACC

None

1⁽²⁾

CALL addr

RET

RET A,x

Subroutine call

Return from subroutine

Return from subroutine and load immediate data

to ACC

None

2

RETI

Return from interrupt

None

2

Table Read

TABRDC [m] Read ROM code (current page) to data memory

None

2⁽¹⁾

and TBLH

TABRDL [m] Read ROM code (last page) to data memory and

TBLH

30

25th May ’99

HT48CXX/HT48RXX

In str u ction

Mn em on ic

Descr ip tion

F la g Affected

Cycle

Miscellaneous

NOP

CLR [m]

SET [m]

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

No operation

Clear data memory

Set data memory

Clear Watchdog timer

Pre-clear Watchdog timer

Swap nibbles of data memory

Swap nibbles of data memory with result in ACC

Enter power down mode

None

TO,PD

TO*,PD*

None

1

1⁽¹⁾

1

1⁽¹⁾

1

None

TO,PD

1

Notes: x: 8-bit immediate data

m: 7-bit data memory address for HT48C10/HT48C30

m: 8-bit data memory address for HT48C50/HT48C70

A: Accumulator

i: 0~7 number of bits

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

√: Flag(s) is affected

–: Flag(s) is not affected

*: Flag(s) may be affected by the execution status

⁽¹⁾: If a loading to PCL register occurs, the execution cycle of the instructions will be delayed

one more cycle (4 system clocks).

⁽²⁾: If a skip to next instruction occurs, the execution cycle of instructions will be delayed one

more cycle (4 system clocks). Otherwise the original execution cycles remain unchanged.

(3)

(2)

:

⁽¹⁾or

31

25th May ’99

HT48CXX/HT48RXX

Instruction Definition

ADC A,[m]

Add data memory and carry to the accumulator

Description

The contents of the specified data memory, accumulator and the carry flag

are added simultaneously, leaving the result in the accumulator.

Operation

ACC ← ACC+[m]+C

Affected flag(s)

TC2 TC1 TO

PD

–

OV

Z

AC

C

–

√

ADCM A,[m]

Add the accumulator and carry to data memory

Description

The contents of the specified data memory, accumulator and the carry flag

are added simultaneously, leaving the result in the specified data memory.

Operation

[m] ← ACC+[m]+C

Affected flag(s)

TC2 TC1 TO

PD

–

OV

Z

AC

C

–

√

ADD A,[m]

Add data memory to the accumulator

Description

The contents of the specified data memory and the accumulator are added.

The result is stored in the accumulator.

Operation

ACC ← ACC+[m]

Affected flag(s)

TC2 TC1 TO

PD

–

OV

Z

AC

C

–

√

ADD A,x

Add immediate data to the accumulator

Description

The contents of the accumulator and the specified data are added, leaving the

result in the accumulator.

Operation

ACC ← ACC+x

Affected flag(s)

TC2 TC1 TO

PD

–

OV

Z

AC

C

–

√

32

25th May ’99

HT48CXX/HT48RXX

ADDM A,[m]

Add the accumulator to the data memory

Description

The contents of the specified data memory and the accumulator are added.

The result is stored in the data memory.

Operation

[m] ← ACC+[m]

Affected flag(s)

TC2 TC1 TO

PD

–

OV

Z

AC

C

–

√

AND A,[m]

Logical AND accumulator with data memory

Description

Data in the accumulator and the specified data memory perform a bitwise

logical_AND operation. The result is stored in the accumulator.

Operation

ACC ← ACC “AND” [m]

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

AND A,x

Logical AND immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logi-

cal_AND operation. The result is stored in the accumulator.

Operation

ACC ← ACC “AND” x

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

ANDM A,[m]

Logical AND data memory with the accumulator

Description

Data in the specified data memory and the accumulator perform a bitwise

logical_AND operation. The result is stored in the data memory.

Operation

[m] ← ACC “AND” [m]

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

33

25th May ’99

HT48CXX/HT48RXX

CALL addr

Subroutine call

Description

The instruction unconditionally calls a subroutine located at the indicated

address. The program counter increments once to obtain the address of the

next instruction, and pushes this onto the stack. The indicated address is

then loaded. Program execution continues with the instruction at this ad-

dress.

Operation

Stack ← PC+1

PC ← addr

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

CLR [m]

Clear data memory

Description

Operation

The contents of the specified data memory are cleared to zero.

[m] ← 00H

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

CLR [m].i

Clear bit of data memory

Description

Operation

The bit i of the specified data memory is cleared to zero.

[m].i ← 0

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

CLR WDT

Clear watchdog timer

Description

The WDT and the WDT Prescaler are cleared (re-counting from zero). The

power down bit (PD) and time-out bit (TO) are cleared.

Operation

WDT and WDT Prescaler ← 00H

PD and TO ← 0

Affected flag(s)

TC2 TC1 TO

PD

0

OV

–

Z

–

AC

–

C

–

0

34

25th May ’99

HT48CXX/HT48RXX

CLR WDT1

Preclear watchdog timer

Description

The TD, PD flags, WDT and the WDT Prescaler has cleared (re-counting from

zero), if the other preclear WDT instruction has been executed. Only execu-

tion of this instruction without the other preclear instruction sets the indi-

cated flag which implies that this instruction has been executed and the TO

and PD flags remain unchanged.

Operation

WDT and WDT Prescaler ← 00H*

PD and TO ← 0*

Affected flag(s)

TC2 TC1 TO

0*

PD

0*

OV

–

Z

–

AC

–

C

–

CLR WDT2

Preclear watchdog timer

Description

The TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting from

zero), if the other preclear WDT instruction has been executed. Only execu-

tion of this instruction without the other preclear instruction sets the indi-

cated flag which implies that this instruction has been executed and the TO

and PD flags remain unchanged.

Operation

WDT and WDT Prescaler ← 00H*

PD and TO ← 0*

Affected flag(s)

TC2 TC1 TO

0*

PD

0*

OV

–

Z

–

AC

–

C

–

CPL [m]

Complement data memory

Description

Each bit of the specified data memory is logically complemented (1’s comple-

ment). Bits which previously contained a one are changed to zero and

vice-versa.

Operation

[m] ← [m]

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

35

25th May ’99

HT48CXX/HT48RXX

CPLA [m]

Complement data memory and place result in the accumulator

Description

Each bit of the specified data memory is logically complemented (1’s comple-

ment). Bits which previously contained a one are changed to zero and

vice-versa. The complemented result is stored in the accumulator and the

contents of the data memory remain unchanged.

Operation

ACC ← [m]

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

DAA [m]

Decimal-Adjust accumulator for addition

Description

The accumulator value is adjusted to the BCD (Binary Code Decimal) code.

The accumulator is divided into two nibbles. Each nibble is adjusted to the

BCD code and an internal carry (AC1) will be done if the low nibble of the

accumulator is greater than 9. The BCD adjustment is done by adding 6 to

the original value if the original value is greater than 9 or a carry (AC or C)

is set; otherwise the original value remains unchanged. The result is stored

in the data memory and only the carry flag (C) may be affected.

Operation

If ACC.3~ACC.0 >9 or AC=1

then [m].3~[m].0 ← (ACC.3~ACC.0)+6, AC1=AC

else [m].3~[m].0) ← (ACC.3~ACC.0), AC1=0

and

If ACC.7~ACC.4+AC1 >9 or C=1

then [m].7~[m].4 ← ACC.7~ACC.4+6+AC1,C=1

else [m].7~[m].4 ← ACC.7~ACC.4+AC1,C=C

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

√

DEC [m]

Decrement data memory

Description

Operation

Data in the specified data memory is decremented by one.

[m] ← [m]–1

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

36

25th May ’99

HT48CXX/HT48RXX

DECA [m]

Decrement data memory and place result in the accumulator

Description

Data in the specified data memory is decremented by one, leaving the result

in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC ← [m]–1

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

HALT

Enter power down mode

Description

This instruction stops program execution and turns off the system clock. The

contents of the RAM and registers are retained. The WDT and prescaler are

cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is

cleared.

Operation

PC ← PC+1

PD ← 1

TO ← 0

Affected flag(s)

TC2 TC1 TO

PD

1

OV

–

Z

–

AC

–

C

–

0

INC [m]

Increment data memory

Description

Operation

Data in the specified data memory is incremented by one.

[m] ← [m]+1

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

INCA [m]

Increment data memory and place result in the accumulator

Description

Data in the specified data memory is incremented by one, leaving the result

in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC ← [m]+1

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

37

25th May ’99

HT48CXX/HT48RXX

JMP addr

Directly jump

Description

The contents of the program counter are replaced with the directly-specified

address unconditionally, and control is passed to this destination.

Operation

PC ← addr

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

MOV A,[m]

Description

Operation

Move data memory to the accumulator

The contents of the specified data memory are copied to the accumulator.

ACC ← [m]

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

MOV A,x

Move immediate data to the accumulator

Description

Operation

The 8-bit data specified by the code is loaded into the accumulator.

ACC ← x

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

MOV [m],A

Move the accumulator to data memory

Description

The contents of the accumulator are copied to the specified data memory (one

of the data memories).

Operation

[m] ← ACC

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

NOP

No operation

Description

Operation

Affected flag(s)

No operation is performed. Execution continues with the next instruction.

PC ← PC+1

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

38

25th May ’99

HT48CXX/HT48RXX

OR A,[m]

Logical OR accumulator with data memory

Description

Data in the accumulator and the specified data memory (one of the data

memories) perform a bitwise logical_OR operation. The result is stored in the

accumulator.

Operation

ACC ← ACC “OR” [m]

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

OR A,x

Logical OR immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical_OR

operation. The result is stored in the accumulator.

Operation

ACC ← ACC “OR” x

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

ORM A,[m]

Logical OR data memory with the accumulator

Description

Data in the data memory (one of the data memories) and the accumulator

perform a bitwise logical_OR operation. The result is stored in the data

memory.

Operation

[m] ← ACC “OR” [m]

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

RET

Return from subroutine

Description

The program counter is restored from the stack. This is a two-cycle instruc-

tion.

Operation

PC ← Stack

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

39

25th May ’99

HT48CXX/HT48RXX

RET A,x

Return and place immediate data in the accumulator

Description

The program counter is restored from the stack and the accumulator loaded

with the specified 8-bit immediate data.

Operation

PC ← Stack

ACC ← x

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

RETI

Return from interrupt

Description

The program counter is restored from the stack, and interrupts are enabled

by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0;

register INTC).

Operation

PC ← Stack

EMI ← 1

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

RL [m]

Rotate data memory left

Description

The contents of the specified data memory are rotated one bit left with bit 7

rotated into bit 0.

Operation

[m].(i+1) ← [m].i; [m].i:bit i of the data memory (i=0-6)

[m].0 ← [m].7

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

RLA [m]

Rotate data memory left and place result in the accumulator

Description

Data in the specified data memory is rotated one bit left with bit 7 rotated

into bit 0, leaving the rotated result in the accumulator. The contents of the

data memory remain unchanged.

Operation

ACC.(i+1) ← [m].i; [m].i:bit i of the data memory (i=0-6)

ACC.0 ← [m].7

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

40

25th May ’99

HT48CXX/HT48RXX

RLC [m]

Rotate data memory left through carry

Description

The contents of the specified data memory and the carry flag are rotated one

bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the

bit 0 position.

Operation

[m].(i+1) ← [m].i; [m].i:bit i of the data memory (i=0-6)

[m].0 ← C

C ← [m].7

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

√

RLCA [m]

Rotate left through carry and place result in the accumulator

Description

Data in the specified data memory and the carry flag are rotated one bit left.

Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0

position. The rotated result is stored in the accumulator but the contents of

the data memory remain unchanged.

Operation

ACC.(i+1) ← [m].i; [m].i:bit i of the data memory (i=0-6)

ACC.0 ← C

C ← [m].7

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

√

RR [m]

Rotate data memory right

Description

The contents of the specified data memory are rotated one bit right with bit

0 rotated to bit 7.

Operation

[m].i ← [m].(i+1); [m].i:bit i of the data memory (i=0-6)

[m].7 ← [m].0

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

41

25th May ’99

HT48CXX/HT48RXX

RRA [m]

Rotate right-place result in the accumulator

Description

Data in the specified data memory is rotated one bit right with bit 0 rotated

into bit 7, leaving the rotated result in the accumulator. The contents of the

data memory remain unchanged.

Operation

ACC.(i) ← [m].(i+1); [m].i:bit i of the data memory (i=0-6)

ACC.7 ← [m].0

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

RRC [m]

Rotate data memory right through carry

Description

The contents of the specified data memory and the carry flag are together

rotated one bit right. Bit 0 replaces the carry bit; the original carry flag is

rotated into the bit 7 position.

Operation

[m].i ← [m].(i+1); [m].i:bit i of the data memory (i=0-6)

[m].7 ← C

C ← [m].0

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

√

RRCA [m]

Rotate right through carry-place result in the accumulator

Description

Data of the specified data memory and the carry flag are rotated one bit right.

Bit 0 replaces the carry bit and the original carry flag is rotated into the bit

7 position. The rotated result is stored in the accumulator. The contents of

the data memory remain unchanged.

Operation

ACC.i ← [m].(i+1); [m].i:bit i of the data memory (i=0-6)

ACC.7 ← C

C ← [m].0

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

√

42

25th May ’99

HT48CXX/HT48RXX

SBC A,[m]

Subtract data memory and carry from the accumulator

Description

The contents of the specified data memory and the complement of the carry

flag are subtracted from the accumulator, leaving the result in the accumu-

lator.

Operation

ACC ← ACC+[m]+C

Affected flag(s)

TC2 TC1 TO

PD

–

OV

Z

AC

C

–

√

SBCM A,[m]

Subtract data memory and carry from the accumulator

Description

The contents of the specified data memory and the complement of the carry

flag are subtracted from the accumulator, leaving the result in the data

memory.

Operation

[m] ← ACC+[m]+C

Affected flag(s)

TC2 TC1 TO

PD

–

OV

Z

AC

C

–

√

SDZ [m]

Skip if decrement data memory is zero

Description

The contents of the specified data memory are decremented by one. If the

result is zero, the next instruction is skipped. If the result is zero, the

following instruction, fetched during the current instruction execution, is

discarded and a dummy cycle is replaced to get the proper instruction (two

cycles). Otherwise proceed with the next instruction (one cycle).

Operation

Skip if ([m]–1)=0, [m] ← ([m]–1)

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

SDZA [m]

Decrement data memory and place result in ACC, skip if zero

Description

The contents of the specified data memory are decremented by one. If the

result is zero, the next instruction is skipped. The result is stored in the

accumulator but the data memory remains unchanged. If the result is zero,

the following instruction, fetched during the current instruction execution, is

discarded and a dummy cycle is replaced to get the proper instruction (two

cycles). Otherwise proceed with the next instruction (one cycle).

Operation

Skip if ([m]–1)=0, ACC ← ([m]–1)

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

43

25th May ’99

HT48CXX/HT48RXX

SET [m]

Set data memory

Description

Operation

Each bit of the specified data memory is set to one.

[m] ← FFH

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

SET [m].i

Set bit of data memory

Description

Operation

Bit “i” of the specified data memory is set to one.

[m].i ← 1

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

SIZ [m]

Skip if increment data memory is zero

Description

The contents of the specified data memory are incremented by one. If the

result is zero, the following instruction, fetched during the current instruc-

tion execution, is discarded and a dummy cycle is replaced to get the proper

instruction (two cycles). Otherwise proceed with the next instruction (one

cycle).

Operation

Skip if ([m]+1)=0, [m] ← ([m]+1)

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

SIZA [m]

Increment data memory and place result in ACC, skip if zero

Description

The contents of the specified data memory are incremented by one. If the

result is zero, the next instruction is skipped and the result is stored in the

accumulator. The data memory remains unchanged. If the result is zero, the

following instruction, fetched during the current instruction execution, is

discarded and a dummy cycle is replaced to get the proper instruction (two

cycles). Otherwise proceed with the next instruction (one cycle).

Operation

Skip if ([m]+1)=0, ACC ← ([m]+1)

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

44

25th May ’99

HT48CXX/HT48RXX

SNZ [m].i

Skip if bit “i” of the data memory is not zero

Description

If bit “i” of the specified data memory is not zero, the next instruction is

skipped. If bit “i” of the data memory is not zero, the following instruction,

fetched during the current instruction execution, is discarded and a dummy

cycle is replaced to get the proper instruction (two cycles). Otherwise proceed

with the next instruction (one cycle).

Operation

Skip if [m].i≠0

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

SUB A,[m]

Subtract data memory from the accumulator

Description

The specified data memory is subtracted from the contents of the accumula-

tor, leaving the result in the accumulator.

Operation

ACC ← ACC+[m]+1

Affected flag(s)

TC2 TC1 TO

PD

–

OV

Z

AC

C

–

√

SUBM A,[m]

Subtract data memory from the accumulator

Description

The specified data memory is subtracted from the contents of the accumula-

tor, leaving the result in the data memory.

Operation

[m] ← ACC+[m]+1

Affected flag(s)

TC2 TC1 TO

PD

–

OV

Z

AC

C

–

√

SUB A,x

Subtract immediate data from the accumulator

Description

The immediate data specified by the code is subtracted from the contents of

the accumulator, leaving the result in the accumulator.

Operation

ACC ← ACC+x+1

Affected flag(s)

TC2 TC1 TO

PD

–

OV

Z

AC

C

–

√

45

25th May ’99

HT48CXX/HT48RXX

SWAP [m]

Swap nibbles within the data memory

Description

The low-order and high-order nibbles of the specified data memory (one of the

data memories) are interchanged.

Operation

[m].3~[m].0 ↔ [m].7~[m].4

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

SWAPA [m]

Swap data memory-place result in the accumulator

Description

The low-order and high-order nibbles of the specified data memory are

interchanged, writing the result to the accumulator. The contents of the data

memory remain unchanged.

Operation

ACC.3~ACC.0 ← [m].7~[m].4

ACC.7~ACC.4 ← [m].3~[m].0

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

SZ [m]

Skip if data memory is zero

Description

If the contents of the specified data memory are zero, the following instruc-

tion, fetched during the current instruction execution, is discarded and a

dummy cycle is replaced to get the proper instruction (two cycles). Otherwise

proceed with the next instruction (one cycle).

Operation

Skip if [m]=0

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

SZA [m]

Move data memory to ACC, skip if zero

Description

The contents of the specified data memory are copied to the accumulator. If

the contents is zero, the following instruction, fetched during the current

instruction execution, is discarded and a dummy cycle is replaced to get the

proper instruction (two cycles). Otherwise proceed with the next instruction

(one cycle).

Operation

Skip if [m]=0, ACC ← [m]

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

46

25th May ’99

HT48CXX/HT48RXX

SZ [m].i

Skip if bit “i” of the data memory is zero

Description

If bit “i” of the specified data memory is zero, the following instruction,

fetched during the current instruction execution, is discarded and a dummy

cycle is replaced to get the proper instruction (two cycles). Otherwise proceed

with the next instruction (one cycle).

Operation

Skip if [m].i=0

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

TABRDC [m]

Move the ROM code (current page) to TBLH and data memory

Description

The low byte of ROM code (current page) addressed by the table pointer

(TBLP) is moved to the specified data memory and the high byte transferred

to TBLH directly.

Operation

[m] ← ROM code (low byte)

TBLH ← ROM code (high byte)

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

TABRDL [m]

Move the ROM code (last page) to TBLH and data memory

Description

The low byte of ROM code (last page) addressed by the table pointer (TBLP)

is moved to the data memory and the high byte transferred to TBLH directly.

Operation

[m] ← ROM code (low byte)

TBLH ← ROM code (high byte)

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

–

AC

–

C

–

XOR A,[m]

Logical XOR accumulator with data memory

Description

Data in the accumulator and the indicated data memory perform a bitwise

logical Exclusive_OR operation and the result is stored in the accumulator.

Operation

ACC ← ACC “XOR” [m]

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

47

25th May ’99

HT48CXX/HT48RXX

XORM A,[m]

Logical XOR data memory with the accumulator

Description

Data in the indicated data memory and the accumulator perform a bitwise

logical Exclusive_OR operation. The result is stored in the data memory. The

zero flag is affected.

Operation

[m] ← ACC "XOR" [m]

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

XOR A,x

Logical XOR immediate data to the accumulator

Description

Data in the the accumulator and the specified data perform a bitwise logical

Exclusive_OR operation. The result is stored in the accumulator. The zero

flag is affected.

Operation

ACC ← ACC “XOR” x

Affected flag(s)

TC2 TC1 TO

PD

–

OV

–

Z

AC

–

C

–

√

48

25th May ’99

HT48CXX/HT48RXX

Characteristic Curves

Figure A: Typical RC oscillator frequency vs. temperature

Figure B: Typical RC oscillator frequency vs. V_DD

49

25th May ’99

HT48CXX/HT48RXX

Figure C: I_OHvs. V_OH, V_DD=3V

Figure D: I_OHvs. V_OH, V_DD=5V

50

25th May ’99

HT48CXX/HT48RXX

Figure E: I_OLvs. V_OL, V_DD=3V

Figure F: I_OLvs. V_OL, V_DD=5V

51

25th May ’99

HT48CXX/HT48RXX

Figure G: V_DDvs. R_PHin Max.

Figure H: V_DDvs. R_PHin Min.

52

25th May ’99

HT48CXX/HT48RXX

Figure I: V_IH,V_ILvs. V_DDin –40°C to +85°C

53

25th May ’99

HT48CXX/HT48RXX

Figure J: Typical I_STBvs. V_DDwatchdog enabled

Figure K: Typical I_STBvs. V_DDwatchdog disabled

54

25th May ’99

HT48CXX/HT48RXX

Figure L: Maximum I_DDvs. Frequency (external clock –40°C To 85°C)

55

25th May ’99

HT48CXX/HT48RXX

56

25th May ’99

HT48CXX/HT48RXX

Figure M: Operating voltage-Operating frequency (crystal)

57

25th May ’99

HT48CXX/HT48RXX

Figure N: Operating voltage vs. T_WDT

58

25th May ’99

HT48CXX/HT48RXX

Holtek Sem icon d u ctor In c. (Hea d qu a r ter s)

No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.

Tel: 886-3-563-1999

Fax: 886-3-563-1189

Holtek Sem icon d u ctor In c. (Ta ip ei Office)

5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.

Tel: 886-2-2782-9635

Fax: 886-2-2782-9636

Fax: 886-2-2782-7128 (International sales hotline)

Holtek Micr oelectr on ics En ter p r ises Ltd .

RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong

Tel: 852-2-745-8288

Fax: 852-2-742-8657

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek

assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are

used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications

will be suitable without further modification, nor recommends the use of its products for application that may present

a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior

notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

59

25th May ’99


型号：	HT48CXX
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	8-Bit Microcontroller Series 8位微控制器系列微控制器
文件：	总59页 (文件大小：2624K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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