HT48E06(18DIP)_技术文档

HT48E06

I/O Type 8-Bit MTP MCU With EEPROM

Technical Document

·

Tools Information

·

FAQs

·

Application Note

-

HA0086E HT48E MCU Series - Using Assembly Language to Write to the 1K EEPROM Data Memory

HA0087E HT48E MCU Series - Using C Language to Write to the 1K EEPROM Data Memory

HA0088E HT48E MCU Series - Using Assembly Language to Write to the 2K EEPROM Data Memory

HA0089E HT48E MCU Series - Using C Language to Write to the 2K EEPROM Data Memory

-

Features

·

Operating voltage:

HALT function and wake-up feature reduce power

consumption

f

_SYS=4MHz: 2.2V~5.5V

_SYS=8MHz: 3.3V~5.5V

·

2-level subroutine nesting

·

Low voltage reset function

Up to 0.5ms instruction cycle with 8MHz system clock

13 bidirectional I/O lines (max.)

Interrupt input shared with an I/O line

at V_DD=5V

·

Bit manipulation instruction

8-bit programmable timer/event counter with overflow

interrupt and 8-stage prescaler

14-bit table read instruction

63 powerful instructions

·

10⁶erase/write cycles EEPROM data memory

EEPROM data retention > 10 years

All instructions in one or two machine cycles

In system programming (ISP)

On-chip crystal and RC oscillator

Watchdog Timer

1,000 erase/write cycles MTP program memory

1024´14 program memory ROM (MTP)

128´8 data memory EEPROM

64´8 data memory RAM

18-pin DIP/SOP package

20-pin SSOP package

Buzzer driving pair and PFD supported

General Description

The HT48E06 is an 8-bit high performance, RISC archi-

tecture microcontroller device specifically designed for

multiple I/O control product applications.

wake-up functions, watchdog timer, buzzer driver, as

well as low cost, enhance the versatility of these devices

to suit a wide range of application possibilities such as

industrial control, consumer products, subsystem con-

trollers, etc.

The advantages of low power consumption, I/O flexibil-

ity, timer functions, oscillator options, HALT and

Rev. 1.20

1

October 28, 2005

HT48E06

Block Diagram

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Pin Assignment

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2

1

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2

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9

8

7

6

5

4

3

2

1

P

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7

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1

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4

5

6

7

8

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2

P

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2

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Rev. 1.20

2

October 28, 2005

HT48E06

Pad Description

Pad Name I/O

Options

Description

Bidirectional 8-bit input/output port. Each bit can be configured as a

wake-up input by options. Software instructions determine the CMOS

output or Schmitt trigger input with pull-high resistor (determined by

pull-high options).

Pull-high*

Wake-up

PA0~PA7

I/O

Bidirectional 3-bit input/output port. Software instructions determine the

CMOS output or Schmitt trigger input with pull-high resistor (deter-

mined by pull-high options).

PB0/BZ

PB1/BZ

PB2

Pull-high*

PB0 or BZ

PB1 or BZ

The PB0 and PB1 are pin-shared with BZ and BZ, respectively. Once

PB0 or PB1 is selected as buzzer driving output, the output signals

come from an internal PFD generator (shared with timer/event coun-

ter).

VSS

Negative power supply, ground

¾

Bidirectional I/O lines. Software instructions determine the CMOS out-

put or Schmitt trigger input with pull-high resistor (determined by

pull-high options). The external interrupt and timer input are pin-shared

with PC0 and PC1, respectively. The external interrupt input is acti-

vated on a high to low transition.

PC0/INT

I/O

Pull-high*

PC1/TMR

RES

VDD

I

Schmitt trigger reset input. Active low.

Positive power supply

¾

OSC1and OSC2 are connected to an RC network or Crystal (deter-

mined by options) for the internal system clock. In the case of RC oper-

ation, OSC2 is the output terminal for 1/4 system clock.

OSC1

OSC2

I

Crystal or RC

O

Note:

²*² All pull-high resistors are controlled by an option bit.

Absolute Maximum Ratings

Supply Voltage...........................V_SS-0.3V to V_SS+6.0V

Input Voltage..............................V_SS-0.3V to V_DD+0.3V

Storage Temperature............................-50°C to 125°C

Operating Temperature...........................-40°C to 85°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those

listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-

ity.

Rev. 1.20

3

October 28, 2005

HT48E06

D.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

¾

f

_SYS=4MHz

_SYS=8MHz

2.2

3.3

¾

5.5

1.5

4

V

¾

V_DD

Operating Voltage

f

V

¾

3V

5V

3V

5V

0.6

2

mA

I_DD1

No load, f_SYS=4MHz

Operating Current (Crystal OSC)

Operating Current (RC OSC)

¾

0.8

2.5

1.5

4

¾

I_DD2

I_DD3

I_STB1

No load, f_SYS=4MHz

No load, f_SYS=8MHz

No load, system HALT

¾

Operating Current

5V

4

8

mA

¾

(Crystal OSC, RC OSC)

3V

5V

3V

5V

¾

5

10

¾

3.0

8

mA

V

Standby Current (WDT Enabled)

Standby Current (WDT Disabled)

1

¾

I_STB2

No load, system HALT

2

¾

V_IL1

V_IH1

V_IL2

V_IH2

V_LVR

0.3V_DD

V_DD

0.4V_DD

V_DD

3.3

¾

Input Low Voltage for I/O Ports

Input High Voltage for I/O Ports

Input Low Voltage (RES)

0

¾

0.7V_DD

0

V

¾

V

¾

0.9V_DD

2.7

4

Input High Voltage (RES)

V

¾

Low Voltage Reset Voltage

LVR enabled

V

¾

3V

5V

3V

5V

3V

5V

mA

kW

I_OL

V

_OL=0.1V_DD

_OH=0.9V_DD

I/O Port Sink Current

I/O Port Source Current

Pull-high Resistance

10

20

-4

-10

60

30

¾

-2

¾

I_OH

-5

¾

20

100

50

¾

R_PH

10

Rev. 1.20

4

October 28, 2005

HT48E06

A.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

¾

2.2V~5.5V

3.3V~5.5V

2.2V~5.5V

3.3V~5.5V

2.2V~5.5V

3.3V~5.5V

¾

400

0

4000

8000

4000

8000

4000

8000

180

kHz

¾

90

65

23

17

f_SYS1

System Clock (Crystal OSC)

System Clock (RC OSC)

Timer I/P Frequency (TMR)

Watchdog Oscillator Period

¾

f_SYS2

¾

f_TIMER

0

¾

3V

5V

3V

5V

45

32

11

8

ms

t_WDTOSC

130

¾

46

ms

Watchdog Time-out Period

(WDT OSC)

t_WDT1

Without WDT prescaler

33

Watchdog Time-out Period

(System Clock)

t_WDT2

t_SYS

1024

¾

t_RES

t_SST

t_INT

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

1

¾

1

¾

Wake-up from HALT

¾

1024

¾

ms

t_SYS

ms

Rev. 1.20

5

October 28, 2005

HT48E06

Functional Description

Execution Flow

incremented by one. The program counter then points to

the memory word containing the next instruction code.

The HT48E06 system clock is derived from either a

crystal or an RC oscillator and is internally divided into

four non-overlapping clocks. One instruction cycle con-

sists of four system clock cycles.

When executing a jump instruction, conditional skip ex-

ecution, loading into the PCL register, subroutine call or

return from subroutine, initial reset, internal interrupt,

external interrupt or return from interrupt, the PC man-

ages the program transfer by loading the address corre-

sponding to each instruction.

Instruction fetching and execution are pipelined in such

a way that a fetch takes an instruction cycle while de-

coding and execution takes the next instruction cycle.

This pipelining scheme ensures that instructions are ef-

fectively executed in one cycle. If an instruction changes

the contents of the program counter, such as subroutine

calls or jumps, in which case, two cycles are required to

complete the instruction.

The conditional skip is activated by instructions. Once

the condition is met, the next instruction, fetched during

the current instruction execution, is discarded and a

dummy cycle replaces it to get the proper instruction.

Otherwise proceed with the next instruction.

The lower byte of the program counter (PCL) is a read-

able and writeable register (06H). Moving data into the

PCL performs a short jump. The destination will be

within the 256 locations.

Program Counter - PC

The program counter (PC) controls the sequence in

which the instructions stored in the program ROM are

executed and its contents specify a full range of pro-

gram memory.

When a control transfer takes place, an additional

dummy cycle is required.

After accessing a program memory word to fetch an in-

struction code, the contents of the program counter are

T

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2

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3

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Execution Flow

Program Counter

Mode

*9

0

*8

0

*7

0

*6

0

*5

0

*4

0

*3

0

*2

0

*1

0

*0

0

Initial Reset

External Interrupt

0

1

0

Timer/Event Counter Overflow

Skip

0

1

0

Program Counter+2

Loading PCL

*9

*8

@7

#7

@6

#6

@5

#5

@4

#4

@3

#3

@2

#2

@1

#1

@0

#0

Jump, Call Branch

Return from Subroutine

#9

S9

#8

S8

S7

S6

S5

S4

S3

S2

S1

S0

Program Counter

Note: *9~*0: Program counter bits

#9~#0: Instruction code bits

S9~S0: Stack register bits

@7~@0: PCL bits

Rev. 1.20

6

October 28, 2005

HT48E06

·

Location 000H

In System Programming

This area is reserved for program initialization. After a

chip reset, the program always begins execution at lo-

cation 000H.

In system programming allows programming and repro-

gramming of HT48EXX microcontroller on application

circuit board, this will save time and money, both during

development in the lab. Using a simple 3-wire interface,

the ISP communicates serially with the HT48EXX

microcontroller, reprogramming program memory and

EEPROM data memory on the chip.

·

Location 004H

This area is reserved for the external interrupt service

program. If the INT input pin is activated, the interrupt

is enabled and the stack is not full, the program begins

execution at location 004H.

Pin Name Function

Description

Serial data input/output

Serial clock input

Device reset

·

Location 008H

PA0

PA4

RES

VDD

VSS

SDATA

SCLK

RESET

VDD

This area is reserved for the timer/event counter inter-

rupt service program. If a timer interrupt results from a

timer/event counter overflow, and if the interrupt is en-

abled and the stack is not full, the program begins exe-

cution at location 008H.

Power supply

VSS

Ground

·

Table location

ISP Pin Assignments

Any location in the program memory space can be

used as look-up tables. The instructions ²TABRDC

[m]² (the current page, one page=256 words) and

²TABRDL [m]² (the last page) transfer the contents of

the lower-order byte to the specified data memory,

and the higher-order byte to TBLH (08H). Only the

destination of the lower-order byte in the table is

well-defined, the other bits of the table word are trans-

ferred to the lower portion of TBLH, and the remaining

2-bits words are read as ²0². The Table Higher-order

byte register (TBLH) is read only. The table pointer

(TBLP) is a read/write register (07H), which indicates

the table location. Before accessing the table, the lo-

cation must be placed in the TBLP. The TBLH is read

only and cannot be restored. If the main routine and

the ISR (Interrupt Service Routine) both employ the

table read instruction, the contents of the TBLH in the

main routine are likely to be changed by the table read

instruction used in the ISR. Errors can occur. In other

words, using the table read instruction in the main rou-

tine and the ISR simultaneously should be avoided.

However, if the table read instruction has to be applied

in both the main routine and the ISR, the interrupt is

supposed to be disabled prior to the table read in-

struction. It will not be enabled until the TBLH has

been backed up. All table related instructions require

two cycles to complete the operation. These areas

may function as normal program memory depending

on the requirements.

Program Memory - ROM

The program memory is used to store the program in-

structions which are to be executed. It also contains

data, table, and interrupt entries, and is organized into

1024´14 bits, addressed by the program counter and ta-

ble pointer.

Certain locations in the program memory are reserved

for special usage:

0

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Program Memory

Table Location

Instruction

*9

P9

1

*8

P8

1

*7

*6

*5

*4

*3

*2

*1

*0

TABRDC [m]

TABRDL [m]

@7

@6

@5

@4

@3

@2

@1

@0

Table Location

P9~P8: Current program counter bits

Note: *9~*0: Table location bits

@7~@0: Table pointer bits

Rev. 1.20

7

October 28, 2005

HT48E06

Stack Register - STACK

I

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A

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0

1

2

3

4

5

6

7

8

9

H

P

0

1

This is a special part of the memory which is used to

save the contents of the Program Counter only. The

stack is organized into 2 levels and is neither part of the

data nor part of the program space, and is neither read-

able nor writeable. The activated level is indexed by the

stack pointer (SP) and is neither readable nor writeable.

At a subroutine call or interrupt acknowledge signal, the

contents of the program counter are pushed onto the

stack. At the end of a subroutine or an interrupt routine,

signaled by a return instruction (RET or RETI), the pro-

gram counter is restored to its previous value from the

stack. After a chip reset, the SP will point to the top of the

stack.

B

P

A

C

P

C

L

T

B

L

P

T

B

L

H

W

D

T

S

0

A

B

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A

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0

E

H

T

M

R

C

0

F

H

1

0

1

2

3

4

5

6

7

H

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledge signal will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a ²CALL² is sub-

sequently executed, stack overflow occurs and the first

entry will be lost (only the most recent 2 return ad-

dresses are stored).

P

A

B

P

A

B

C

:

U

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0

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8

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3

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)

Data Memory - RAM

7

F

H

The data memory has a capacity of 81´8 bits and is di-

vided into two functional groups: special function regis-

ters and general purpose data memory (64´8). Most

are read/write, but some are read only.

B

a

n

k

0

B

a

n

k

1

RAM Mapping

Indirect Addressing Register

The special function registers include the indirect ad-

dressing registers (R0;00H), timer/event counter

(TMR;0DH), timer/event counter control register

(TMRC;0EH), program counter lower-order byte regis-

ter (PCL;06H), memory pointer registers (MP;01H), ac-

cumulator (ACC;05H), table pointer (TBLP;07H), table

higher-order byte register (TBLH;08H), status register

(STATUS;0AH), interrupt control register (INTC;0BH),

Watchdog Timer option setting register (WDTS;09H),

I/O registers (PA;12H, PB;14H, PC;16H) and I/O con-

trol registers (PAC;13H, PBC;15H, PCC;17H). The re-

maining space before the 40H is reserved for future

expanded usage and reading these locations will re-

turn the result ²00H². The general purpose data

memory, addressed from 40H to 7FH, is used for data

and control information under instruction commands.

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration on [00H] and [02H] access the RAM pointed to

by MP0 (01H) and MP1 (03H) respectively. Reading lo-

cation 00H or 02H indirectly returns the result 00H. Writ-

ing indirectly results in no operation. The function of

data movement between two indirect addressing regis-

ters is not supported.

The memory pointer registers, MP0 and MP1, are both

7-bit registers used to access the RAM by combining

corresponding indirect addressing registers. MP0.7 and

MP1.7 are always ²1². MP0 can only be applied to data

memory in Bank 0, while MP1 can be applied to data

memory in Bank 0 and Bank 1.

Accumulator

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by ²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer registers (MP). The control register of

the EEPROM data memory is located at [40H] in Bank 1.

The accumulator is closely related to ALU operations. It

is also mapped to location 05H of the data memory and

can carry out immediate data operations. The data

movement between two data memory locations must

pass through the accumulator.

Rev. 1.20

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October 28, 2005

HT48E06

Interrupt

Arithmetic and logic unit - ALU

The device provides an external interrupt and internal

timer/event counter interrupts. The Interrupt Control

Register (INTC;0BH) contains the interrupt control bits

to set the enable or disable and the interrupt request

flags.

This circuit performs 8-bit arithmetic and logic opera-

tions. The ALU provides the following functions:

·

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

·

Logic operations (AND, OR, XOR, CPL)

·

Rotation (RL, RR, RLC, RRC)

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may occur during this interval but only

the interrupt request flag is recorded. If a certain inter-

rupt requires servicing within the service routine, the

EMI bit and the corresponding bit of the INTC may be set

to allow interrupt nesting. If the stack is full, the interrupt

request will not be acknowledged, even if the related in-

terrupt is enabled, until the Stack Pointer is decremented.

If immediate service is desired, the stack must be pre-

vented from becoming full.

·

Increment and Decrement (INC, DEC)

·

Branch decision (SZ, SNZ, SIZ, SDZ...)

The ALU not only saves the results of a data operation

but also changes the status register.

Status Register - STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry

flag (C), auxiliary carry flag (AC), overflow flag (OV),

power down flag (PDF), and watchdog time-out flag

(TO). It also records the status information and controls

the operation sequence.

With the exception of the TO and PDF flags, bits in

the status register can be altered by instructions like

most other registers. Any data written into the status

register will not change the TO or PDF flag. In addi-

tion, operations related to the status register may

give different results from those intended. The TO

flag can be affected only by a system power-up, a

WDT time-out or executing the ²CLR WDT² or

²HALT² instruction. The PDF flag can be affected

only by executing the ²HALT² or ²CLR WDT² instruc-

tion or during a system power-up.

All these kinds of interrupts have a wake-up capability.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack, followed by

a branch to a subroutine at specified location in the pro-

gram memory. Only the program counter is pushed onto

the stack. If the contents of the register or status register

(STATUS) are altered by the interrupt service program

which corrupts the desired control sequence, the con-

tents should be saved in advance.

External interrupts are triggered by a high to low transi-

tion of the INT and the related interrupt request flag (EIF;

bit 4 of the INTC) will be set. When the interrupt is en-

abled, the stack is not full and the external interrupt is

active, a subroutine call to location 04H will occur. The

interrupt request flag (EIF) and EMI bits will be cleared

to disable other interrupts.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

In addition, on entering the interrupt sequence or exe-

cuting the subroutine call, the status register will not be

automatically pushed onto the stack. If the contents of

the status are important and if the subroutine may cor-

rupt the status register, precautions must be taken to

save it properly.

The internal timer/event counter interrupt is initialized by

setting the timer/event counter interrupt request flag

(TF; bit 5 of the INTC), caused by a timer overflow.

Bit No.

Label

Function

C is set if an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate

through carry instruction.

0

C

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

1

2

3

AC

Z

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

OV

PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by

executing the ²HALT² instruction.

4

PDF

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is

5

TO

set by a WDT time-out.

6, 7

¾

Unused bit, read as ²0²

Status (0AH) Register

Rev. 1.20

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October 28, 2005

HT48E06

Bit No.

Label

EMI

EEI

ETI

¾

Function

Controls the master (global) interrupt (1= enable; 0= disable)

Controls the external interrupt (1= enable; 0= disable)

Controls the Timer/Event Counter 0 interrupt (1= enable; 0= disable)

Unused bit, read as ²0²

0

1

2

3, 6, 7

4

5

EIF

TF

External interrupt request flag (1= active; 0= inactive)

Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)

INTC (0BH)Register

Oscillator Configuration

There are 2 oscillator circuits in the microcontroller.

When the interrupt is enabled, the stack is not full and

the TF bit is set, a subroutine call to location 08H will oc-

cur. The related interrupt request flag (TF) will be reset

and the EMI bit cleared to disable further interrupts.

V

D

During the execution of an interrupt subroutine, other in-

terrupt acknowledge signals are held until the ²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (if the stack is not full). To

return from the interrupt subroutine, ²RET² or ²RETI²

may be invoked. RETI will set the EMI bit to enable an in-

terrupt service, but RET will not.

O

S

C

1

O

S

C

1

4

7

0

p

F

S

Y

S

O

S

C

2

O

S

C

2

N

M

O

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r

System Oscillator

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

All of them are designed for system clocks, namely, ex-

ternal RC oscillator and external Crystal oscillator,

which are determined by options. No matter what oscil-

lator type is selected, the signal provides the system

clock. The HALT mode stops the system oscillator and

ignores an external signal to conserve power.

Interrupt Source

External Interrupt

Timer/Event Counter Overflow

Priority Vector

If an RC oscillator is used, an external resistor between

OSC1 and VDD is required and the resistance must

range from 24kW to 1MW. The system clock, divided by

4, is available on OSC2, which can be used to synchro-

nize external logic. The RC oscillator provides the most

cost effective solution. However, the frequency of oscil-

lation may vary with VDD, temperatures and the chip it-

self due to process variations. It is, therefore, not

suitable for timing sensitive operations where an accu-

rate oscillator frequency is desired.

1

2

04H

08H

The timer/event counter interrupt request flag (TF), ex-

ternal interrupt request flag (EIF), enable timer/event

counter interrupt bit (ETI), enable external interrupt bit

(EEI) and enable master interrupt bit (EMI) constitute an

interrupt control register (INTC) which is located at 0BH

in the data memory. EMI, EEI, ETI are used to control

the enabling/disabling of interrupts. These bits prevent

the requested interrupt from being serviced. Once the

interrupt request flags (TF, EIF) are set, they will remain

in the INTC register until the interrupts are serviced or

cleared by a software instruction.

If a Crystal oscillator is used, a crystal across OSC1 and

OSC2 is needed to provide the feedback and phase

shift required for the oscillator. No other external compo-

nents are required. In stead of a crystal, a resonator can

also be connected between OSC1 and OSC2 to obtain

a frequency reference, but two external capacitors in

OSC1 and OSC2 are required.

It is recommended that a program does not use the

²CALL subroutine² within the interrupt subroutine. Inter-

rupts often occur in an unpredictable manner or need to

be serviced immediately in some applications. If only one

stack is left and enabling the interrupt is not well con-

trolled, the original control sequence will be damaged

once the ²CALL² operates in the interrupt subroutine.

The WDToscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Even if

the system enters the power down mode and the sys-

tem clock is stopped, the oscillator still works within a

period of 65ms at 5V. The WDT oscillator can be dis-

abled by options to conserve power.

Rev. 1.20

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October 28, 2005

HT48E06

Watchdog Timer - WDT

The WDT overflow under normal operation will initialize

a ²chip reset² and set the status bit ²TO². But in the

HALT mode, the overflow will initialize a ²warm reset²

and only the Program Counter and SP are reset to zero.

To clear the contents of WDT (including the WDT

prescaler), three methods are adopted; external reset (a

low level to RES), software instruction and a ²HALT² in-

struction. The software instruction includes ²CLR WDT²

and the other set - ²CLR WDT1² and ²CLR WDT2². Of

these two types of instruction, only one can be active de-

pending on the option - ²CLR WDT times selection op-

tion². If the ²CLR WDT² is selected (i.e. CLRWDT times

is equal to one), any execution of the ²CLR WDT² in-

struction will clear the WDT. In the case that ²CLR

WDT1² and ²CLR WDT2² are chosen (i.e. CLRWDT

times is equal to two), these two instructions must be ex-

ecuted to clear the WDT; otherwise, the WDT may reset

the chip as a result of time-out.

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator), instruction clock (system

clock divided by 4), determines the options. This timer is

designed to prevent a software malfunction or sequence

from jumping to an unknown location with unpredictable

results. The Watchdog Timer can be disabled by op-

tions. If the Watchdog Timer is disabled, all the execu-

tions related to the WDT result in no operation.

Once the internal WDT oscillator (RC oscillator with a

period of 65ms at 5V normally) is selected, it is first di-

vided by 256 (8-stage) to get the nominal time-out pe-

riod of 16.6ms at 5V. This time-out period may vary with

temperatures, VDD and process variations. By invoking

the WDT prescaler, longer time-out periods can be real-

ized. Writing data to WS2, WS1, WS0 (bit 2, 1, 0 of the

WDTS) can give different time-out periods. If WS2, WS1,

and WS0 are all equal to 1, the division ratio is up to 1:128,

and the maximum time-out period is 2.2s at 5V. If the WDT

oscillator is disabled, the WDT clock may still come from

the instruction clock and operates in the same manner ex-

cept that in the HALT state the WDT may stop counting

and lose its protecting purpose. In this situation the logic

can only be restarted by an external logic. The high nibble

and bit 3 of the WDTS are reserved for user¢s defined

flags, which can be used to indicate some specified status.

Power Down Operation - HALT

The HALT mode is initialized by the ²HALT² instruction

and results in the following:

·

The system oscillator will be turned off but the WDT

oscillator remains running (if the WDT oscillator is se-

lected).

·

The contents of the on chip RAM and registers remain

If the device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT will stop the system clock.

unchanged.

·

WDT and WDT prescaler will be cleared and re-

counted again (if the WDT clock is from the WDT os-

cillator).

WS2

WS1

WS0

Division Ratio

·

All of the I/O ports maintain their original status.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1:1

1:2

·

The PDF flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a ²warm reset². After the TO and PDF flags are

examined, the cause for chip reset can be determined.

The PDF flag is cleared by a system power-up or exe-

cuting the ²CLR WDT² instruction and is set when exe-

cuting the ²HALT² instruction. The TO flag is set if a

WDT time-out occurs, and causes a wake-up that only

resets the Program Counter and SP; the others remain

in their original status.

1:4

1:8

1:16

1:32

1:64

1:128

WDTS (09H) Register

S

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1

M

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X

W

S

0

~

W

S

2

W

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Watchdog Timer

Rev. 1.20

11

October 28, 2005

HT48E06

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake up the

device by options. Awakening from an I/O port stimulus,

the program will resume execution of the next instruc-

tion. If it awakens from an interrupt, two sequence may

occur. If the related interrupt is disabled or the interrupt

is enabled but the stack is full, the program will resume

execution at the next instruction. If the interrupt is en-

abled and the stack is not full, a regular interrupt re-

sponse takes place. If an interrupt request flag is set to

²1² before entering the HALT mode, the wake-up func-

tion of the related interrupt will be disabled. Once a

wake-up event occurs, it takes 1024 (system clock pe-

riod) to resume to normal operation. In other words, a

dummy period will be inserted after a wake-up. If the

wake-up results from an interrupt acknowledge signal,

the actual interrupt subroutine execution will be delayed

by one or more cycles. If the wake-up results in the next

instruction execution, this will be executed immediately

after the dummy period is finished.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able an SST delay.

An extra option load time delay is added during system

reset (power-up, WDT time-out at normal mode or RES

reset).

The functional unit chip reset status are shown below.

Program Counter

Interrupt

000H

Disable

Clear

Prescaler

Clear. After master reset,

WDT begins counting

WDT

Timer/Event Counter Off

Input/Output Ports

Stack Pointer

Input mode

Points to the top of the stack

V

D

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

R

E

S

t

S S T

S

T

i

m

e

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o

u

t

Reset

Therearethreewaysinwhicharesetcanoccur:

C

h

i

p

R

e

s

e

t

·

RES reset during normal operation

Reset Timing Chart

·

RES reset during HALT

·

WDT time-out reset during normal operation

V

D

The time-out during HALT is different from other chip re-

set conditions, since it can perform a ²warm reset² that

resets only the Program Counter and SP, leaving the

other circuits in their original state. Some registers re-

main unchanged during other reset conditions. Most

registers are reset to the ²initial condition² when the re-

set conditions are met. By examining the PDF and TO

flags, the program can distinguish between different

²chip resets².

m

0 . 0 1 F *

1

0

k

R

E

S

1

0

k

m

0 . 1 F *

Reset Circuit

TO PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

0

u

0

1

0

u

1

u

1

WDT time-out during normal operation

WDT wake-up HALT

H

A

L

T

W

a

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W

D

T

Note: ²u² stands for unchanged”

R

E

S

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra delay of 1024 system clock pulses when the sys-

tem reset (power-up, WDT time-out or RES reset) or the

system awakes from the HALT state.

C

o

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T

1

0

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1

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Reset Configuration

Rev. 1.20

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October 28, 2005

HT48E06

The registers status is summarized in the following table.

Reset WDT Time-out

RES Reset

(Power On) (Normal Operation) (Normal Operation)

RES Reset

(HALT)

WDT Time-out

(HALT)*

Register

MP0

-xxx xxxx

0000 0000

xxxx xxxx

-uuu uuuu

0000 0000

uuuu uuuu

-uuu uuuu

0000 0000

uuuu uuuu

-uuu uuuu

0000 0000

uuuu uuuu

-uuu uuuu

uuuu uuuu

MP1

BP

ACC

Program

Counter

000H

TBLP

TBLH

WDTS

STATUS

INTC

TMR

TMRC

PA

xxxx xxxx

--xx xxxx

0000 0111

--00 xxxx

--00 -000

xxxx xxxx

00-0 1000

1111 1111

---- -111

uuuu uuuu

--uu uuuu

0000 0111

--1u uuuu

--00 -000

xxxx xxxx

00-0 1000

1111 1111

---- -111

uuuu uuuu

--uu uuuu

0000 0111

--uu uuuu

--00 -000

xxxx xxxx

00-0 1000

1111 1111

---- -111

uuuu uuuu

--uu uuuu

0000 0111

--01 uuuu

--00 -000

xxxx xxxx

00-0 1000

1111 1111

---- -111

uuuu uuuu

--uu uuuu

uuuu uuuu

--11 uuuu

--uu -uuu

uuuu uuuu

uu-u uuuu

uuuu uuuu

---- -uuu

PAC

PB

PBC

---- -111

---- -uuu

PC

---- --11

---- --uu

PCC

EECR

---- --11

---- --uu

1000 ----

uuuu ----

Note:

²*² stands for ²warm reset²

²u² stands for ²unchanged²

²x² stands for ²unknown²

Timer/Event Counter

nal (TMR) pin. The timer mode functions as a normal

timer with the clock source coming from the f_INTclock.

The pulse width measurement mode can be used to count

the high or low level duration of the external signal (TMR).

The counting is based on the f_INTclock.

A timer/event counter (TMR) is implemented in the

microcontroller. The timer/event counter contains an

8-bit programmable count-up counter and the clock may

come from an external source or from the system clock.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current

contents in the timer/event counter to FFH. Once over-

flow occurs, the counter is reloaded from the timer/event

counter preload register and generates the interrupt re-

quest flag (TF; bit 5 of the INTC) at the same time.

Using an external clock input allows the user to count

external events, measure time internals or pulse widths,

or generate an accurate time base. Using the internal

clock allows the user to generate an accurate time base.

The timer/event counter can generate PFD signals by

using external or internal clock and the PFD frequency

is determine by the equation f_INT/[2´(256-N)].

In the pulse width measurement mode with the TON and

TE bits equal to one, once the TMR has received a tran-

sient from low to high (or high to low if the TE bit is ²0²) it

will start counting until the TMR returns to the original

level and resets the TON. The measured result will re-

main in the timer/event counter even if the activated

transient occurs again. In other words, only one cycle

measurement can be done. Until setting the TON, the

cycle measurement will function again as long as it re-

ceives further transient pulse. Note that, in this operat-

ing mode, the timer/event counter starts counting not

according to the logic level but according to the transient

There are two registers related to the timer/event coun-

ter; TMR ([0DH]), TMRC ([0EH]). Two physical registers

are mapped to TMR location; writing to TMR makes the

starting value be placed in the timer/event counter

preload register and reading TMR retrieves the contents

of the timer/event counter. The TMRC is a timer/event

counter control register, which defines some options.

The TM0, TM1 bits define the operating mode. The

event count mode is used to count external events,

which means that the clock source comes from an exter-

Rev. 1.20

13

October 28, 2005

HT48E06

edges. In the case of counter overflows, the counter is

reloaded from the timer/event counter preload register

and issues the interrupt request just like the other two

modes. To enable the counting operation, the timer ON

bit (TON; bit 4 of the TMRC) should be set to ²1². In the

pulse width measurement mode, the TON will be

cleared automatically after the measurement cycle is

completed. But in the other two modes the TON can only

be reset by instructions. The overflow of the timer/event

counter is one of the wake-up sources. No matter what

the operation mode is, writing a ²0² to ETI can disable

the corresponding interrupt services.

reload that data to the timer/event counter. But if the

timer/event counter is turned on, data written to it will

only be kept in the timer/event counter preload register.

The timer/event counter will still operate until overflow

occurs. When the timer/event counter (reading TMR) is

read, the clock will be blocked to avoid errors. As clock

blocking may result in a counting error, this must be

taken into consideration by the programmer.

Bit0~bit2 of the TMRC can be used to define the

pre-scaling stages of the internal clock sources of the

timer/event counter. The definitions are as shown. The

overflow signal of the timer/event counter can be used

to generate PFD signals for buzzer driving.

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register will also

Bit No.

Label

Function

Defines the prescaler stages, PSC2, PSC1, PSC0=

000: f_INT=f_SYS/2

001: f_INT=f_SYS/4

010: f_INT=f_SYS/8

0~2

PSC0~PSC2 011: f_INT=f_SYS/16

100: f_INT=f_SYS/32

101: f_INT=f_SYS/64

110: f_INT=f_SYS/128

111: f_INT=f_SYS/256

Defines the TMR active edge of the timer/event counter:

In Event Counter Mode (TM1,TM0)=(0,1):

1:count on falling edge;

3

TE

0:count on rising edge

In Pulse Width measurement mode (TM1,TM0)=(1,1):

1: start counting on the rising edge, stop on the falling edge;

0: start counting on the falling edge, stop on the rising edge

Enable or disable timer 0 counting

(0=disable; 1=enable)

4

5

TON

¾

Unused bit, read as ²0²

Defines the operating mode

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

6

7

TM0

TM1

TMRC (0EH) Register

(

1

/

2

~

1

P

/

2

5

6

)

f

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s

u

r

e

m

e

n

t

C

o

u

n

t

e

r

t

o

I

n

t

e

r

u

p

t

T

M

0

M

o

d

e

C

o

n

t

r

o

l

T

O

N

1

/

2

B

Z

Timer/Event Counter

Rev. 1.20

14

October 28, 2005

HT48E06

Input/Output Ports

set or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H,

14H or 16H) instructions.

There are 13 bidirectional input/output lines in the

microcontroller, labeled from PA to PC, which are

mapped to the data memory of [12H], [14H], [16H] re-

spectively. All of these I/O ports can be used for input

and output operations. For input operation, these ports

are non-latching, that is, the inputs must be ready at the

T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H

or 16H). For output operation, all the data is latched and

remains unchanged until the output latch is rewritten.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i², ²CLR

[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the de-

vice. The highest 6-bit of port C and 5-bit of port B are not

physically implemented; on reading them a ²0² is returned

whereas writing then results in no operation. See Applica-

tion note.

Each I/O line has its own control register (PAC, PBC,

PCC) to control the input/output configuration. With this

control register, CMOS output or Schmitt trigger input

with or without pull-high resistor structures can be re-

configured dynamically under software control. To func-

tion as an input, the corresponding latch of the control

register must write a ²1². The input source also depends

on the control register. If the control register bit is ²1²,

the input will read the pad state. If the control register bit

is ²0², the contents of the latches will move to the inter-

nal bus. The latter is possible in the ²read-modify-write²

instruction.

There is a pull-high option available for all I/O lines (bit

option). Once the pull-high option of an I/O line is se-

lected, the I/O line has a pull-high resistor. Otherwise,

the pull-high resistor is absent. It should be noted that a

non-pull-high I/O line operating in input mode will cause

a floating state.

The PB0 and PB1 are pin-shared with BZ and BZ, re-

spectively. If the BZ/BZ option is selected, the output

signal in output mode of PB0/PB1 will be the PFD signal

generated by the Timer/Event Counter 0 overflow sig-

nal. The input mode always remain in its original func-

tions. Once the BZ/BZ option is selected, the buzzer

output signals are controlled by the PB0 data register

only.

For output function, CMOS is the only configuration.

These control registers are mapped to locations 13H,

15H and 17H.

After a chip reset, these input/output lines remain at high

levels or in a floating state (depending on the pull-high

options). Each bit of these input/output latches can be

The I/O functions of PB0/PB1 are shown below.

PB0 I/O

I

O

B

0

x

I

O

B

1

x

O

I

O

I

O

I

O

B

0

O

B

1

PB1 I/O

O

C

x

PB0/PB1 Mode

PB0 Data

x

I

C

D

x

B

0

x

0

I

B

1

x

B

I

C

D₀

D₁

D₀

D₁

PB1 Data

D

I

x

PB0 Pad Status

PB1 Pad Status

I

D

I

0

B

I

D

0

B

0

Note:

²I² input, ²O² output, ²D, D₀, D₁² data,

²B² buzzer option, BZ or BZ, ²x² don¢t care

²C² CMOS output

Rev. 1.20

15

October 28, 2005

HT48E06

V

D

C

o

n

t

r

o

l

B

i

t

P

U

D

a

t

a

B

u

s

D

C

Q

K

W

r

i

t

e

C

o

n

t

r

o

l

R

e

g

i

s

t

e

r

S

C

h

i

p

R

e

s

e

t

P

A

0

~

P

A

7

P

B

C

0

~

P

B

2

0

~

P

C

1

R

e

a

d

C

o

n

t

r

o

l

R

e

g

i

s

t

e

r

D

a

t

a

B

i

t

D

C

Q

K

W

r

i

t

e

D

a

t

a

R

e

g

i

s

t

e

r

S

M

U

P

B

0

(

P

B

0

,

P

B

1

O

n

l

y

)

X

E

X

T

B

Z

E

N

M

(

P

B

0

,

P

B

1

O

n

l

y

)

U

X

R

e

a

d

D

a

t

a

R

e

g

i

s

t

e

r

S

y

s

t

e

m

W

a

k

e

-

u

p

O

P

0

~

O

P

7

(

P

A

o

n

l

y

)

I

N

T

f

o

r

P

C

0

O

n

l

y

T

M

R

f

o

r

P

C

1

O

n

l

y

Input/Output Ports

The PC0 and PC1 are pin-shared with INT and TMR

pins respectively.

The relationship between V_DDand V_LVRis shown below.

V

D

V

O P R

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruction

to avoid consuming power under input floating state.

5

.

5

V

5

.

5

V

Low Voltage Reset - LVR

V

L

V

R

The HT48E06 contains a low voltage reset circuit

inorder to monitor the supply voltage of the device. If the

3

.

3

V

2

.

4

V

supply voltage drops to within a range of 0.9V~V_LVR

,

such as might occur when changing the battery, the LVR

will automatically reset the device internally.

0

.

9

V

The LVR includes the following specifications:

V

_OPRis the voltage range for proper chip opera-

Note:

·

Within the low voltage range (0.9V~V_LVR), the device

tion at 4MHz system clock.

remains in their original state until exceeding 1ms. If

the low voltage state does not exceed 1ms, the LVR

will ignore it and does not perform a reset function.

·

The LVR uses the ²OR² function with the external

RES signal to perform a chip reset.

Rev. 1.20

16

October 28, 2005

HT48E06

V

D

5

.

5

V

L

V

R

D

e

t

e

c

t

V

o

l

t

a

g

e

V

L

V

R

0

.

9

0

V

R

e

s

e

t

S

i

g

n

a

l

R

e

s

e

t

N

o

r

m

a

l

O

p

e

r

a

t

i

o

n

R

e

s

e

t

*

1

*

2

Low Voltage Reset

Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of

1024 system clock pulses before entering the normal operation.

*2: Low voltage has to be maintained for over 1ms, after that 1ms delay the device enters the reset mode.

EEPROM Data Memory

The 128´8 bits EEPROM data memory is readable and writable during normal operation. It is indirectly addressed

through the control register EECR ([40H] in Bank 1). The EECR can be read and written to only by indirect addressing

mode using MP1.

Bit No.

Label

¾

Function

0~3

4

Unused bit, read as ²0²

CS

SK

EEPROM data memory select

5

Serial clock input to EEPROM data memory

Serial data input to EEPROM data memory

Serial data output from EEPROM data memory

6

DI

7

DO

EECR (40H) Register

C

S

C

o

n

t

r

o

l

A

d

r

e

s

R

e

g

i

s

t

e

r

L

o

g

i

c

S

K

a

n

d

C

S

C

l

o

c

k

A

d

r

e

s

D

e

c

o

d

e

r

G

e

n

e

r

a

t

o

r

S

K

E

C

R

D

I

M

e

m

o

r

y

C

e

l

A

r

a

y

1

´

K : ( 1 2 8 8 )

D

O

D

I

D

a

t

a

V

D

R

e

g

i

s

t

e

r

O

u

t

p

u

t

B

u

f

e

r

D

O

S

a

m

e

a

s

H

T

9

3

L

C

4

6

EEPROM Data Memory Block Diagram

Rev. 1.20

17

October 28, 2005

HT48E06

The EEPROM data memory is accessed via a

three-wire serial communication interface by writing to

EECR. It is arranged into 128 words by 8 bits. The

EEPROM data memory contains seven instructions:

READ, ERASE, WRITE, EWEN, EWDS, ERAL and

WRAL. These instructions are all made up of 10 bits

data: 1 start bit, 2 op-code bits and 7 address bits.

memory at the rising edge of SK. During the READ cy-

cle, DO acts as the data output and during the WRITE or

ERASE cycle, DO indicates the BUSY/READY status.

When the DO is active for read data or as a BUSY/

READY indicator the CS pin must be high; otherwise DO

will be in a high state. For successful instructions, CS

must be low after the instruction is sent. After power on,

the device is by default in the EWDS state. An EWEN in-

struction must be performed before any ERASE or

WRITE instruction can be executed.

By writing CS, SK and DI, these instructions can be

given to the EEPROM. These serial instruction data pre-

sented at the DI will be written into the EEPROM data

The following are the functional descriptions and timing diagrams of all seven instructions.

t

C S S

t

C D S

C

S

t

S

K

H

t

S

K

L

t

C S H

S

K

t

D I S

t

D

I

H

V

a

l

i

d

D

a

t

a

V

a

l

i

d

D

a

t

a

D

I

t

P

D

0

t

P D 1

D

O

1

EECR A.C. Characteristics

Ta=25°C

V

_CC=5V±10%

V_CC=2.2V±10%

Symbol

Parameter

Clock Frequency

Unit

Min.

0

Max.

2

Min.

0

Max.

1

f_SK

MHz

ns

ms

t_SKH

t_SKL

t_CSS

t_CSH

t_CDS

t_DIS

t_DIH

t_PD1

t_PD0

t_SV

SK High Time

250

50

500

100

0

¾

SK Low Time

¾

CS Setup Time

CS Hold Time

CS Deselect Time

DI Setup Time

DI Hold Time

¾

0

¾

250

100

¾

250

200

¾

250

¾

500

250

¾

DO Delay to ²1²

DO Delay to ²0²

Status Valid Time

DO Disable Time

¾

t_HZ

100

¾

200

¾

t_PR

Write Cycle Time Per Word

2

5

Rev. 1.20

18

October 28, 2005

HT48E06

READ

WRITE

The READ instruction will stream out data at a specified

address on the DO. The data on DO changes during the

low-to-high edge of SK. The 8 bits data stream is pre-

ceded by a logical ²0² dummy bit. Irrespective of the

condition of the EWEN or EWDS instruction, the READ

command is always valid and independent of these two

instructions. After the data word has been read the in-

ternal address will be automatically incremented by 1 al-

lowing the next consecutive data word to be read out

without entering further address data. The address will

wrap around with CS High until CS returns to Low.

The WRITE instruction writes data into the EEPROM

data memory at the specified addresses in the program-

ming enable mode. After the WRITE op-code and the

specified address and data have been issued, the data

writing is activated by the falling edge of CS. Since the

internal auto-timing generator provides all timing signal

for the internal writing, so the SK clock is not required.

The auto-timing write cycle includes an automatic

erase-before-write capability. So, it is not necessary to

erase data before the WRITE instruction. During the in-

ternal writing, we can verify the busy/ready status if CS

is high. The DO will remain low but when the operation is

over, the DO will return to high and further instructions

can be executed.

EWEN/EWDS

The EWEN/EWDS instruction will enable or disable the

programming capabilities. At both the power on and

power off state the device automatically enters the disable

mode. Before a WRITE, ERASE, WRAL or ERAL instruc-

tion is given, the programming enable instruction EWEN

must be issued, otherwise the ERASE/WRITE instruction

is invalid. After the EWEN instruction is issued, the pro-

gramming enable condition remains until power is turned

off or an EWDS instruction is given. No data can be written

into the EEPROM data memory in the programming dis-

abled state. By so doing, the internal memory data can be

protected.

ERAL

The ERAL instruction erases the entire 128´8 memory

cells to a logical ²1² state in the programming enable

mode. After the erase-all instruction set has been is-

sued, the data erase feature is activated by the falling

edge of CS. Since the internal auto-timing generator

provides all timing signal for the erase-all operation, so

the SK clock is not required. During the internal erase-all

operation, we can verify the busy/ready status if CS is

high. The DO will remain low but when the operation is

over, the DO will return to high and further instruction

can be executed.

ERASE

The ERASE instruction erases data at the specified ad-

dresses in the programming enable mode. After the

ERASE op-code and the specified address have been

issued, the data erase is activated by the falling edge of

CS. Since the internal auto-timing generator provides all

timing signals for the internal erase, so the SK clock is

not required. During the internal erase, we can verify the

busy/ready status if CS is high. The DO will remain low

but when the operation is over, the DO will return to high

and further instructions can be executed.

WRAL

The WRAL instruction writes data into the entire 128´8

memory cells in the programming enable mode. After

the write-all instruction set has been issued, the data

writing is activated by a falling edge of CS. Since the in-

ternal auto-timing generator provides all timing signals

for the write-all operation, so the SK clock is not re-

quired. During the internal write-all operation, we can

verify the busy/ready status if CS is high. The DO will re-

main low but when the operation is over the DO will re-

turn to high and further instruction can be executed.

EECR Control Timing Diagrams

·

READ

t

C D S

C

S

K

A

N

A

0

(

1

)

1

0

D

I

S

t

a

r

t

b

i

t

1

D

X

D

0

D

X

0

D

O

*

M

o

d

e

(

X

A

8

6

)

*

A

d

r

e

s

p

o

i

n

t

e

r

a

u

t

o

m

a

t

i

c

a

l

y

c

y

c

l

e

s

t

o

t

h

e

n

e

x

t

w

o

r

d

A

N

D

X

D

7

Rev. 1.20

19

October 28, 2005

HT48E06

·

EWEN/EWDS

S

C

S

t

a

n

d

b

y

S

K

0

(

1

)

D

I

S

t

a

r

t

b

i

t

1

=

E

W

E

N

0

=

E

W

D

S

·

WRITE

t

C D S

C

S

V

e

r

i

f

y

S

t

a

n

d

b

y

S

K

A

N

-

1

A

N

-

2

A

N

A

1

A

0

D

X

D

0

1

(

1

)

t

D

I

S

t

a

r

b

i

t

S V

1

D

O

B

u

s

y

R

e

a

d

y

t

P R

·

ERASE

t

C D S

C

S

V

e

r

i

f

y

S

t

a

n

d

b

y

S

K

A

N

-

1

A

N

-

2

A

N

A

1

A

0

1

(

1

)

t

D

I

S

t

a

r

b

i

t

S V

1

D

O

B

u

s

y

R

e

a

d

y

t

P R

·

ERAL

t

C D S

V

e

r

i

f

y

C

S

t

a

n

d

b

y

S

K

1

0

(

1

)

D

I

S

t

a

r

t

b

i

t

S V

1

D

O

B

u

s

y

R

e

a

d

y

t

P R

Rev. 1.20

20

October 28, 2005

HT48E06

·

WRAL

t

C D S

V

e

r

i

f

y

C

S

t

a

n

d

b

y

S

K

0

D

X

D

0

1

(

1

)

D

I

S

t

a

r

t

b

i

t

S V

1

D

O

B

u

s

y

R

e

a

d

y

t

P R

EEPROM Data Memory Instruction Set Summary

Instruction

READ

Comments

Read data

Start bit

Op Code

Address

A6~A0

Data

D7~D0

¾

1

10

11

01

00

ERASE

WRITE

EWEN

Erase data

Write data

D7~D0

¾

Erase/Write Enable

Erase/Write Disable

Erase All

11XXXXX

00XXXXX

10XXXXX

01XXXXX

EWDS

¾

ERAL

¾

WRAL

Write All

D7~D0

Note:

²X² stands for ²don¢t care²

Options

The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure having

a properly functioning system.

Items

Options

WDT clock source: WDTOSC or f_SYS/4 or disable

1

2

3

4

5

6

7

8

WDT function: enable or disable

LVR function: enable or disable

CLRWDT instruction: one or two clear WDT instruction(s)

System oscillator: RC or crystal

Pull-high resistors (PA~PC): none or pull-high

BZ function: enable or disable

PA0~PA7 wake-up: enable or disable

Rev. 1.20

21

October 28, 2005

HT48E06

Application Circuits

V

D

m

0 . 0 1 F *

V

R

D

S

P

A

0

~

P

A

7

1

0

k

P

B

0

/

B

Z

E

m

0 . 1 F

P

B

1

/

B

Z

1

0

k

P

B

2

V

D

m

0 . 1 F *

V

S

P

C

0

/

I

N

T

R

O

S

C

R

C

S

y

s

t

e

m

O

s

c

i

l

a

t

o

r

P

C

1

/

T

M

R

2

4

k

W

O

S

C

W

O

S

C

1

2

4

7

0

p

F

S

Y

S

O

S

C

1

2

O

S

C

i

r

c

u

i

t

C

1

O

S

C

1

2

S

e

R

i

g

h

t

S

i

d

e

C

F

s

r

y

s

t

a

l

S

y

s

t

e

m

O

s

c

i

l

a

t

o

r

o

r

t

h

e

v

a

l

u

e

s

,

C

2

e

t

a

b

l

e

b

e

l

o

w

R

1

H

T

4

8

E

0

6

O

S

C

i

r

c

u

i

t

The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)

Crystal or Resonator

4MHz Crystal

C1, C2

0pF

R1

10kW

12kW

10kW

27kW

9.1kW

10kW

4MHz Resonator

10pF

0pF

3.58MHz Crystal

3.58MHz Resonator

2MHz Crystal & Resonator

1MHz Crystal

25pF

35pF

300pF

480kHz Resonator

455kHz Resonator

429kHz Resonator

The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur.

Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating volt-

age. Note however that if the LVR is enabled then R1 can be removed.

Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is

stable and remains within a valid operating voltage range before bringing RES to high.

²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise

interference.

Rev. 1.20

22

October 28, 2005

HT48E06

Instruction Set Summary

Mnemonic

Instruction

Cycle

Flag

Affected

Description

Arithmetic

ADD A,[m]

ADDM A,[m]

ADD A,x

Add data memory to ACC

1

1⁽¹⁾

1

Z,C,AC,OV

C

Add ACC to data memory

Add immediate data to ACC

ADC A,[m]

ADCM A,[m]

SUB A,x

Add data memory to ACC with carry

1

1⁽¹⁾

Add ACC to data memory with carry

Subtract immediate data from ACC

1

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

Subtract data memory from ACC

1

1⁽¹⁾

Subtract data memory from ACC with result in data memory

Subtract data memory from ACC with carry

Subtract data memory from ACC with carry and result in data memory

Decimal adjust ACC for addition with result in data memory

1

1⁽¹⁾

Logic Operation

AND A,[m]

OR A,[m]

AND data memory to ACC

1

Z

OR data memory to ACC

XOR A,[m]

ANDM A,[m]

ORM A,[m]

Exclusive-OR data memory to ACC

AND ACC to data memory

OR ACC to data memory

1

1⁽¹⁾

1

XORM A,[m] Exclusive-OR ACC to data memory

AND A,x

OR A,x

AND immediate data to ACC

OR immediate data to ACC

1

XOR A,x

CPL [m]

CPLA [m]

Exclusive-OR immediate data to ACC

Complement data memory

1

1⁽¹⁾

Complement data memory with result in ACC

1

Increment & Decrement

INCA [m]

INC [m]

Increment data memory with result in ACC

1

Z

Increment data memory

1⁽¹⁾

DECA [m]

DEC [m]

Decrement data memory with result in ACC

Decrement data memory

1

1⁽¹⁾

Rotate

RRA [m]

RR [m]

Rotate data memory right with result in ACC

Rotate data memory right

1

1⁽¹⁾

1

None

C

RRCA [m]

RRC [m]

RLA [m]

RL [m]

Rotate data memory right through carry with result in ACC

Rotate data memory right through carry

Rotate data memory left with result in ACC

Rotate data memory left

1⁽¹⁾

C

1

None

C

1⁽¹⁾

1

RLCA [m]

RLC [m]

Rotate data memory left through carry with result in ACC

Rotate data memory left through carry

1⁽¹⁾

C

Data Move

MOV A,[m]

MOV [m],A

MOV A,x

Move data memory to ACC

Move ACC to data memory

Move immediate data to ACC

1

1⁽¹⁾

1

None

Bit Operation

CLR [m].i

SET [m].i

Clear bit of data memory

Set bit of data memory

1⁽¹⁾

None

Rev. 1.20

23

October 28, 2005

HT48E06

Instruction

Cycle

Flag

Affected

Mnemonic

Branch

Description

JMP addr

SZ [m]

Jump unconditionally

2

None

Skip if data memory is zero

1⁽²⁾

1⁽³⁾

1⁽²⁾

2

SZA [m]

SZ [m].i

SNZ [m].i

SIZ [m]

Skip if data memory is zero with data movement to ACC

Skip if bit i of data memory is zero

Skip if bit i of data memory is not zero

Skip if increment data memory is zero

Skip if decrement data memory is zero

Skip if increment data memory is zero with result in ACC

Skip if decrement data memory is zero with result in ACC

Subroutine call

SDZ [m]

SIZA [m]

SDZA [m]

CALL addr

RET

Return from subroutine

2

RET A,x

RETI

Return from subroutine and load immediate data to ACC

Return from interrupt

2

Table Read

TABRDC [m] Read ROM code (current page) to data memory and TBLH

TABRDL [m] Read ROM code (last page) to data memory and TBLH

2⁽¹⁾

None

Miscellaneous

NOP

No operation

1

1⁽¹⁾

1

None

CLR [m]

Clear data memory

SET [m]

Set data memory

None

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

Clear Watchdog Timer

TO,PDF

TO⁽⁴⁾,PDF⁽⁴⁾

None

Pre-clear Watchdog Timer

Swap nibbles of data memory

Swap nibbles of data memory with result in ACC

Enter power down mode

1

1⁽¹⁾

1

None

1

TO,PDF

Note: x: Immediate data

m: Data memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Ö: Flag is affected

-: Flag is not affected

⁽¹⁾: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle

(four system clocks).

⁽²⁾: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more

cycle (four system clocks). Otherwise the original instruction cycle is unchanged.

⁽¹⁾and ⁽²⁾

(3)

:

⁽⁴⁾: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the

²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.

Otherwise the TO and PDF flags remain unchanged.

Rev. 1.20

24

October 28, 2005

HT48E06

Instruction Definition

ADC A,[m]

Add data memory and carry to the accumulator

Description

The contents of the specified data memory, accumulator and the carry flag are added si-

multaneously, leaving the result in the accumulator.

Operation

ACC ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADCM A,[m]

Add the accumulator and carry to data memory

Description

The contents of the specified data memory, accumulator and the carry flag are added si-

multaneously, leaving the result in the specified data memory.

Operation

[m] ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADD A,[m]

Add data memory to the accumulator

Description

The contents of the specified data memory and the accumulator are added. The result is

stored in the accumulator.

Operation

ACC ¬ ACC+[m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADD A,x

Add immediate data to the accumulator

Description

The contents of the accumulator and the specified data are added, leaving the result in the

accumulator.

Operation

ACC ¬ ACC+x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADDM A,[m]

Add the accumulator to the data memory

Description

The contents of the specified data memory and the accumulator are added. The result is

stored in the data memory.

Operation

[m] ¬ ACC+[m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

Rev. 1.20

25

October 28, 2005

HT48E06

AND A,[m]

Logical AND accumulator with data memory

Description

Data in the accumulator and the specified data memory perform a bitwise logical_AND op-

eration. The result is stored in the accumulator.

Operation

ACC ¬ ACC ²AND² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

AND A,x

Logical AND immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical_AND operation.

The result is stored in the accumulator.

Operation

ACC ¬ ACC ²AND² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

ANDM A,[m]

Logical AND data memory with the accumulator

Description

Data in the specified data memory and the accumulator perform a bitwise logical_AND op-

eration. The result is stored in the data memory.

Operation

[m] ¬ ACC ²AND² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

CALL addr

Subroutine call

Description

The instruction unconditionally calls a subroutine located at the indicated address. The

program counter increments once to obtain the address of the next instruction, and pushes

this onto the stack. The indicated address is then loaded. Program execution continues

with the instruction at this address.

Operation

Stack ¬ Program Counter+1

Program Counter ¬ addr

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

CLR [m]

Clear data memory

Description

Operation

The contents of the specified data memory are cleared to 0.

[m] ¬ 00H

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.20

26

October 28, 2005

HT48E06

CLR [m].i

Clear bit of data memory

Description

Operation

The bit i of the specified data memory is cleared to 0.

[m].i ¬ 0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

CLR WDT

Clear Watchdog Timer

Description

The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are

cleared.

Operation

WDT ¬ 00H

PDF and TO ¬ 0

Affected flag(s)

TO

0

PDF

0

OV

Z

AC

C

¾

CLR WDT1

Preclear Watchdog Timer

Description

Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution

of this instruction without the other preclear instruction just sets the indicated flag which im-

plies this instruction has been executed and the TO and PDF flags remain unchanged.

Operation

WDT ¬ 00H*

PDF and TO ¬ 0*

Affected flag(s)

TO

0*

PDF

0*

OV

Z

AC

C

¾

CLR WDT2

Preclear Watchdog Timer

Description

Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution

of this instruction without the other preclear instruction, sets the indicated flag which im-

plies this instruction has been executed and the TO and PDF flags remain unchanged.

Operation

WDT ¬ 00H*

PDF and TO ¬ 0*

Affected flag(s)

TO

0*

PDF

0*

OV

Z

AC

C

¾

CPL [m]

Complement data memory

Description

Each bit of the specified data memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice-versa.

Operation

[m] ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.20

27

October 28, 2005

HT48E06

CPLA [m]

Complement data memory and place result in the accumulator

Description

Each bit of the specified data memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice-versa. The complemented result

is stored in the accumulator and the contents of the data memory remain unchanged.

Operation

ACC ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

DAA [m]

Decimal-Adjust accumulator for addition

Description

The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-

lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal

carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-

justment is done by adding 6 to the original value if the original value is greater than 9 or a

carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored

in the data memory and only the carry flag (C) may be affected.

Operation

If ACC.3~ACC.0 >9 or AC=1

then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC

else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0

and

If ACC.7~ACC.4+AC1 >9 or C=1

then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1

else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

DEC [m]

Decrement data memory

Description

Operation

Data in the specified data memory is decremented by 1.

[m] ¬ [m]-1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

DECA [m]

Decrement data memory and place result in the accumulator

Description

Data in the specified data memory is decremented by 1, leaving the result in the accumula-

tor. The contents of the data memory remain unchanged.

Operation

ACC ¬ [m]-1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.20

28

October 28, 2005

HT48E06

HALT

Enter power down mode

Description

This instruction stops program execution and turns off the system clock. The contents of

the RAM and registers are retained. The WDT and prescaler are cleared. The power down

bit (PDF) is set and the WDT time-out bit (TO) is cleared.

Operation

Program Counter ¬ Program Counter+1

PDF ¬ 1

TO ¬ 0

Affected flag(s)

TO

0

PDF

1

OV

Z

AC

C

¾

INC [m]

Increment data memory

Description

Operation

Data in the specified data memory is incremented by 1

[m] ¬ [m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

INCA [m]

Increment data memory and place result in the accumulator

Description

Data in the specified data memory is incremented by 1, leaving the result in the accumula-

tor. The contents of the data memory remain unchanged.

Operation

ACC ¬ [m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

JMP addr

Directly jump

Description

The program counter are replaced with the directly-specified address unconditionally, and

control is passed to this destination.

Operation

Program Counter ¬addr

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

MOV A,[m]

Description

Operation

Move data memory to the accumulator

The contents of the specified data memory are copied to the accumulator.

ACC ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.20

29

October 28, 2005

HT48E06

MOV A,x

Move immediate data to the accumulator

Description

Operation

The 8-bit data specified by the code is loaded into the accumulator.

ACC ¬ x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

MOV [m],A

Move the accumulator to data memory

Description

The contents of the accumulator are copied to the specified data memory (one of the data

memories).

Operation

[m] ¬ACC

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

NOP

No operation

Description

Operation

Affected flag(s)

No operation is performed. Execution continues with the next instruction.

Program Counter ¬ Program Counter+1

TO

PDF

OV

Z

AC

C

¾

OR A,[m]

Logical OR accumulator with data memory

Description

Data in the accumulator and the specified data memory (one of the data memories) per-

form a bitwise logical_OR operation. The result is stored in the accumulator.

Operation

ACC ¬ ACC ²OR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

OR A,x

Logical OR immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical_OR operation.

The result is stored in the accumulator.

Operation

ACC ¬ ACC ²OR² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

ORM A,[m]

Logical OR data memory with the accumulator

Description

Data in the data memory (one of the data memories) and the accumulator perform a

bitwise logical_OR operation. The result is stored in the data memory.

Operation

[m] ¬ACC ²OR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.20

30

October 28, 2005

HT48E06

RET

Return from subroutine

Description

Operation

Affected flag(s)

The program counter is restored from the stack. This is a 2-cycle instruction.

Program Counter ¬ Stack

TO

PDF

OV

Z

AC

C

¾

RET A,x

Return and place immediate data in the accumulator

Description

The program counter is restored from the stack and the accumulator loaded with the speci-

fied 8-bit immediate data.

Operation

Program Counter ¬ Stack

ACC ¬ x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RETI

Return from interrupt

Description

The program counter is restored from the stack, and interrupts are enabled by setting the

EMI bit. EMI is the enable master (global) interrupt bit.

Operation

Program Counter ¬ Stack

EMI ¬ 1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RL [m]

Rotate data memory left

Description

Operation

The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.

[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

[m].0 ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RLA [m]

Rotate data memory left and place result in the accumulator

Description

Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the

rotated result in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

ACC.0 ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.20

31

October 28, 2005

HT48E06

RLC [m]

Rotate data memory left through carry

Description

The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-

places the carry bit; the original carry flag is rotated into the bit 0 position.

Operation

[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

[m].0 ¬ C

C ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

RLCA [m]

Rotate left through carry and place result in the accumulator

Description

Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the

carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored

in the accumulator but the contents of the data memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

ACC.0 ¬ C

C ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

RR [m]

Rotate data memory right

Description

Operation

The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

[m].7 ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RRA [m]

Rotate right and place result in the accumulator

Description

Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving

the rotated result in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

ACC.7 ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RRC [m]

Rotate data memory right through carry

Description

The contents of the specified data memory and the carry flag are together rotated 1 bit

right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.

Operation

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

[m].7 ¬ C

C ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

Rev. 1.20

32

October 28, 2005

HT48E06

RRCA [m]

Rotate right through carry and place result in the accumulator

Description

Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces

the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is

stored in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

ACC.7 ¬ C

C ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SBC A,[m]

Subtract data memory and carry from the accumulator

Description

The contents of the specified data memory and the complement of the carry flag are sub-

tracted from the accumulator, leaving the result in the accumulator.

Operation

ACC ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SBCM A,[m]

Subtract data memory and carry from the accumulator

Description

The contents of the specified data memory and the complement of the carry flag are sub-

tracted from the accumulator, leaving the result in the data memory.

Operation

[m] ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SDZ [m]

Skip if decrement data memory is 0

Description

The contents of the specified data memory are decremented by 1. If the result is 0, the next

instruction is skipped. If the result is 0, the following instruction, fetched during the current

instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-

tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]-1)=0, [m] ¬ ([m]-1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SDZA [m]

Decrement data memory and place result in ACC, skip if 0

Description

The contents of the specified data memory are decremented by 1. If the result is 0, the next

instruction is skipped. The result is stored in the accumulator but the data memory remains

unchanged. If the result is 0, the following instruction, fetched during the current instruction

execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-

cles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]-1)=0, ACC ¬ ([m]-1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.20

33

October 28, 2005

HT48E06

SET [m]

Set data memory

Description

Operation

Each bit of the specified data memory is set to 1.

[m] ¬ FFH

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SET [m]. i

Set bit of data memory

Description

Operation

Bit i of the specified data memory is set to 1.

[m].i ¬ 1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SIZ [m]

Skip if increment data memory is 0

Description

The contents of the specified data memory are incremented by 1. If the result is 0, the fol-

lowing instruction, fetched during the current instruction execution, is discarded and a

dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with

the next instruction (1 cycle).

Operation

Skip if ([m]+1)=0, [m] ¬ ([m]+1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SIZA [m]

Increment data memory and place result in ACC, skip if 0

Description

The contents of the specified data memory are incremented by 1. If the result is 0, the next

instruction is skipped and the result is stored in the accumulator. The data memory re-

mains unchanged. If the result is 0, the following instruction, fetched during the current in-

struction execution, is discarded and a dummy cycle is replaced to get the proper

instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]+1)=0, ACC ¬ ([m]+1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SNZ [m].i

Skip if bit i of the data memory is not 0

Description

If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data

memory is not 0, the following instruction, fetched during the current instruction execution,

is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-

wise proceed with the next instruction (1 cycle).

Operation

Skip if [m].i¹0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.20

34

October 28, 2005

HT48E06

SUB A,[m]

Subtract data memory from the accumulator

Description

The specified data memory is subtracted from the contents of the accumulator, leaving the

result in the accumulator.

Operation

ACC ¬ ACC+[m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SUBM A,[m]

Subtract data memory from the accumulator

Description

The specified data memory is subtracted from the contents of the accumulator, leaving the

result in the data memory.

Operation

[m] ¬ ACC+[m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SUB A,x

Subtract immediate data from the accumulator

Description

The immediate data specified by the code is subtracted from the contents of the accumula-

tor, leaving the result in the accumulator.

Operation

ACC ¬ ACC+x+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SWAP [m]

Swap nibbles within the data memory

Description

The low-order and high-order nibbles of the specified data memory (1 of the data memo-

ries) are interchanged.

Operation

[m].3~[m].0 « [m].7~[m].4

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SWAPA [m]

Swap data memory and place result in the accumulator

Description

The low-order and high-order nibbles of the specified data memory are interchanged, writ-

ing the result to the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.3~ACC.0 ¬ [m].7~[m].4

ACC.7~ACC.4 ¬ [m].3~[m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.20

35

October 28, 2005

HT48E06

SZ [m]

Skip if data memory is 0

Description

If the contents of the specified data memory are 0, the following instruction, fetched during

the current instruction execution, is discarded and a dummy cycle is replaced to get the

proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if [m]=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SZA [m]

Move data memory to ACC, skip if 0

Description

The contents of the specified data memory are copied to the accumulator. If the contents is

0, the following instruction, fetched during the current instruction execution, is discarded

and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed

with the next instruction (1 cycle).

Operation

Skip if [m]=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SZ [m].i

Skip if bit i of the data memory is 0

Description

If bit i of the specified data memory is 0, the following instruction, fetched during the current

instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-

tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if [m].i=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

TABRDC [m]

Move the ROM code (current page) to TBLH and data memory

Description

The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved

to the specified data memory and the high byte transferred to TBLH directly.

Operation

[m] ¬ ROM code (low byte)

TBLH ¬ ROM code (high byte)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

TABRDL [m]

Move the ROM code (last page) to TBLH and data memory

Description

The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to

the data memory and the high byte transferred to TBLH directly.

Operation

[m] ¬ ROM code (low byte)

TBLH ¬ ROM code (high byte)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.20

36

October 28, 2005

HT48E06

XOR A,[m]

Logical XOR accumulator with data memory

Description

Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-

sive_OR operation and the result is stored in the accumulator.

Operation

ACC ¬ ACC ²XOR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

XORM A,[m]

Logical XOR data memory with the accumulator

Description

Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-

sive_OR operation. The result is stored in the data memory. The 0 flag is affected.

Operation

[m] ¬ ACC ²XOR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

XOR A,x

Logical XOR immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-

eration. The result is stored in the accumulator. The 0 flag is affected.

Operation

ACC ¬ ACC ²XOR² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.20

37

October 28, 2005

HT48E06

Package Information

18-pin DIP (300mil) Outline Dimensions

A

1

8

1

0

B

9

1

H

C

D

a

E

G

I

F

Dimensions in mil

Nom.

Symbol

Min.

895

240

125

16

Max.

A

B

C

D

E

F

G

H

I

915

260

135

145

20

¾

50

70

¾

100

¾

295

335

0°

315

375

15°

¾

a

¾

Rev. 1.20

38

October 28, 2005

HT48E06

18-pin SOP (300mil) Outline Dimensions

1

8

1

0

A

B

1

9

C

'

G

H

D

a

E

F

Dimensions in mil

Nom.

Symbol

Min.

394

290

14

447

92

¾

Max.

A

B

C

C¢

D

E

F

419

300

20

¾

50

¾

460

104

¾

4

¾

G

H

a

32

4

38

12

0°

10°

Rev. 1.20

39

October 28, 2005

HT48E06

20-pin SSOP (150mil) Outline Dimensions

2

0

1

A

B

1

0

C

'

G

H

D

a

E

F

Dimensions in mil

Nom.

Symbol

Min.

228

150

8

Max.

A

B

C

C¢

D

E

F

244

158

12

¾

25

¾

335

49

¾

347

65

¾

4

10

G

H

a

15

7

50

10

0°

8°

Rev. 1.20

40

October 28, 2005

HT48E06

Product Tape and Reel Specifications

Reel Dimensions

D

T

2

C

A

B

T

1

SOP 18W

Symbol

Description

Dimensions in mm

330±1.0

A

B

Reel Outer Diameter

Reel Inner Diameter

62±1.5

13.0+0.5

-0.2

C

D

Spindle Hole Diameter

Key Slit Width

2.0±0.5

24.8+0.3

-0.2

T1

T2

Space Between Flange

Reel Thickness

30.2±0.2

SSOP 20S (150mil)

Symbol

Description

Reel Outer Diameter

Reel Inner Diameter

Dimensions in mm

330±1

A

B

62±1.5

13+0.5

-0.2

C

D

Spindle Hole Diameter

Key Slit Width

2±0.5

16.8+0.3

-0.2

T1

T2

Space Between Flange

Reel Thickness

22.2±0.2

Rev. 1.20

41

October 28, 2005

HT48E06

Carrier Tape Dimensions

P

0

P

1

t

D

E

F

W

B

0

C

D

1

P

K

0

A

0

SOP 18W

Symbol

Description

Dimensions in mm

24.0+0.3

-0.1

W

Carrier Tape Width

P

E

Cavity Pitch

16.0±0.1

1.75±0.1

11.5±0.1

1.5±0.1

1.5+0.25

4.0±0.1

2.0±0.1

10.9±0.1

12.0±0.1

2.8±0.1

0.3±0.05

21.3

Perforation Position

F

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

D

D1

P0

P1

A0

B0

K0

t

Cavity to Perforation (Length Direction)

Cavity Length

Cavity Width

Cavity Depth

Carrier Tape Thickness

Cover Tape Width

C

SSOP 20S (150mil)

Symbol

Description

Carrier Tape Width

Cavity Pitch

Dimensions in mm

16+0.3

-0.1

W

P

E

8±0.1

1.75±0.1

7.5±0.1

1.5+0.1

1.5+0.25

4±0.1

Perforation Position

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

F

D

D1

P0

P1

A0

B0

K0

t

Cavity to Perforation (Length Direction)

Cavity Length

2±0.1

6.5±0.1

9±0.1

Cavity Width

Cavity Depth

2.3±0.1

0.3±0.05

13.3

Carrier Tape Thickness

Cover Tape Width

C

Rev. 1.20

42

October 28, 2005

HT48E06

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan

Tel: 886-3-563-1999

Fax: 886-3-563-1189

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan

Tel: 886-2-2655-7070

Fax: 886-2-2655-7373

Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shanghai Sales Office)

7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233

Tel: 021-6485-5560

Fax: 021-6485-0313

http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)

43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031

Tel: 0755-8346-5589

Fax: 0755-8346-5590

ISDN: 0755-8346-5591

Holtek Semiconductor Inc. (Beijing Sales Office)

Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031

Tel: 010-6641-0030, 6641-7751, 6641-7752

Fax: 010-6641-0125

Holmate Semiconductor, Inc. (North America Sales Office)

46712 Fremont Blvd., Fremont, CA 94538

Tel: 510-252-9880

Fax: 510-252-9885

http://www.holmate.com

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,

please visit our web site at http://www.holtek.com.tw.

Rev. 1.20

43

October 28, 2005


型号：	HT48E06(18DIP)
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PDIP18 可编程只读存储器微控制器光电二极管
文件：	总43页 (文件大小：312K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HT48E06(18DIP) [HOLTEK]

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