HT48CA1(28SOP-A) [HOLTEK]
Microcontroller, 8-Bit, MROM, 8MHz, CMOS, PDSO28;型号: | HT48CA1(28SOP-A) |
厂家: | HOLTEK SEMICONDUCTOR INC |
描述: | Microcontroller, 8-Bit, MROM, 8MHz, CMOS, PDSO28 微控制器 光电二极管 |
文件: | 总38页 (文件大小:263K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HT48RA1/HT48CA1
Remote Type 8-Bit MCU
Technical Document
·
Tools Information
·
FAQs
·
Application Note
-
HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series
HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series
HA0041E Using the HT48CA0 to Generate the HT6221 Output Signals
HA0075E MCU Reset and Oscillator Circuits Application Note
-
-
-
-
-
HA0076E HT48RAx/HT48CAx Software Application Note
HA0082E HT48xA0-1 and HT48xA0-2 Power-on Reset Timing
Features
·
·
Operating voltage: 2.0V~5.5V
HALT function and wake-up feature reduce power
consumption
·
23 bidirectional I/O lines (max.)
·
·
8-level subroutine nesting
·
1 interrupt input shared with an I/O line
Up to 1ms instruction cycle with 4MHz system clock at
·
8-bit programmable timer/event counter with overflow
V
DD=3V
interrupt and 8-stage prescaler (TMR0)
·
·
·
·
·
·
Bit manipulation instruction
·
16-bit programmable timer/event counter and
overflow interrupts (TMR1)
16-bit table read instruction
·
On-chip crystal and RC oscillator
63 powerful instructions
·
Watchdog Timer
All instructions in one or two machine cycles
Low voltage reset function
·
8K´16 program memory
·
28-pin SOP/SSOP(209mil) package
224´8 data memory RAM
·
PFD supported
General Description
The HT48RA1/HT48CA1 are 8-bit high performance,
RISC architecture microcontroller devices specifically
designed for multiple I/O control product applications.
The data ROM can be used to store remote control
codes. The mask version HT48CA1 is fully pin and func-
tionally compatible with the OTP version HT48RA1 de-
vice.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, watchdog timer,
programmable frequency divider, HALT and wake-up
functions, as well as low cost, enhance the versatility of
these devices to suit a wide range of application possi-
bilities such as industrial control, consumer products,
subsystem controllers, and particularly suitable for use
in products such as universal remote controller (URC).
Rev. 1.40
1
May 22, 2009
HT48RA1/HT48CA1
Block Diagram
f
S
Y
S
T
M
R
1
C
M
U
P
F
0
/
I
N
T
X
1
P
C
5
/
T
M
R
1
T
M
R
I
n
t
e
r
r
u
p
t
C
i
r
c
u
i
t
M
P
r
e
s
c
a
l e
S
r
f
S
Y
U
T
M
R
0
P
C
0
/
T
M
R
0
S
T
A
C
K
X
P
r
o
g
r
a
m
I
N
T
C
P
r
o
g
r
a
m
R
O
M
T
M
R
0
C
C
o
u
n
t
e
r
E
N
/
D
I
S
I
n
s
t
r
u
c
t
i
o
n
W
D
T
S
M
f
S
Y
S
R
e
g
i
s
t
e
r
M
D
A
T
A
M
P
W
D
T
U
l e
W
D
T
P
r
e
s
c
a
r
U
M
e
m
o
r
y
X
X
W
D
T
O
S
C
P
A
C
P
O
R
T
A
P
A
0
~
P
A
7
M
U
X
I
n
s
t
r
u
c
t
i
o
n
P
A
D
e
c
o
d
e
r
P
F
D
S
T
A
T
U
S
P
B
C
P
A
L
U
O
R
T
B
P
P
B
0
/
P
F
D
T
i
m
i
n
g
S
h
i
f
t
e
r
B
1
~
P
B
7
P
B
G
e
n
e
r
a
t
o
r
P
P
P
C
C
C
0
1
5
/
~
/
T
T
M
M
R
R
0
1
P
C
C
P
O
R
T
C
P
C
4
P
C
O
S
C
O
2
S
C
1
A
C
C
R
E
S
V
D
D
P
F
C
P
O
R
T
F
V
S
S
P
F
0
/
I
N
T
P
F
Pin Assignment
P
P
P
P
P
P
P
P
P
B
B
A
A
A
A
B
B
B
5
4
3
2
1
0
3
2
1
P
P
P
P
P
P
O
O
V
R
P
P
P
P
B
B
A
A
A
A
6
7
4
5
6
7
1
2
3
4
5
6
7
8
9
1
1
1
1
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
8
7
6
5
4
3
2
1
0
9
8
7
6
5
S
S
C
C
2
1
D
D
S
5
4
3
2
P
B
0
/
P
F
D
E
0
1
2
3
4
V
S
S
C
C
C
C
/
T
M
R
1
P
F
0
/
I
N
T
P
C
0
/
T
M
R
0
P
C
1
H
T
4
8
R
A
1
/
H
T
4
8
C
A
1
2
8
S
O
P
-
A
/
S
S
O
P
-
A
Rev. 1.40
2
May 22, 2009
HT48RA1/HT48CA1
Pin Description
ROM Code
Option
Pin Name I/O
Description
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up in-
put by a option. Software instructions determine the CMOS output or Schmitt trig-
Wake-up*
PA0~PA7
I/O
I/O
Pull-high*** ger input with/without pull-high resistor. The pull-high resistor of each input/output
line is also optional.
Bidirectional 8-bit input/output port. Software instructions determine the CMOS
output or Schmitt trigger input with/without pull-high resistor. The pull-high resis-
PB0/PFD
PB1~PB7
Pull-high**
tor of each input/output line is also optional. The output mode of PB0 can be
PB0 or PFD
used as an internal PFD signal output and it can be used as a various frequency
carrier signal.
Bidirectional 6-bit input/output port. Software instructions determine the CMOS
PC0/TMR0
PC1~PC4
PC5/TMR1
output or Schmitt trigger input with/without pull-high resistor. The pull-high resis-
Pull-high*
I/O
I/O
tor of each input/output line is also optional. PC0 and PC5 are pin shared with
TMR0 and TMR1 function pins.
Bidirectional 1-bit input/output port. Software instructions determine the CMOS
output or Schmitt trigger input with/without pull-high resistor. The pull-high resis-
Pull-high*
PF0/INT
tor of this input/output line is also optional. PF0 is pin shared with the INT func-
tion pin.
OSC1, OSC2 are connected to an RC network or Crystal (determined by option)
OSC1
OSC2
I
Crystal
for the internal system clock. In the case of RC operation, OSC2 is the output
O
or RC
terminal for 1/4 system clock.
RES
VSS
VDD
I
Schmitt trigger reset input, active low.
Negative power supply, ground
Positive power supply
¾
¾
¾
¾
¾
Note: * Bit option
** Nibble option
*** Byte option
Absolute Maximum Ratings
Supply Voltage...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
Storage Temperature............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
I
OL Total ..............................................................150mA
I
OH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.40
3
May 22, 2009
HT48RA1/HT48CA1
D.C. Characteristics
Ta=25°C
Test Conditions
Conditions
¾
Symbol
VDD
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
Operating Voltage
Operating Current
2.0
¾
5.5
1.5
4
V
¾
0.6
2
3V
5V
mA
mA
IDD1
No load, fSYS=4MHz
No load, fSYS=8MHz
No load, system HALT
¾
Operating Current
IDD2
5V
4
8
mA
¾
(Crystal OSC, RC OSC)
3V
5V
3V
5V
¾
1.1
4
5
10
¾
¾
mA
mA
mA
mA
V
Standby Current (WDT Enabled and
WDT RC OSC On)
ISTB1
0.1
0.2
1
¾
ISTB2
Standby Current (WDT Disabled)
No load, system HALT
2
¾
VIL1
VIH1
VIL2
VIH2
0.3VDD
VDD
0.4VDD
VDD
2.0
3.3
¾
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
Input Low Voltage (RES)
0
¾
¾
¾
¾
¾
1.9
3.0
8
0.7VDD
V
¾
¾
¾
0
0.9VDD
1.8
V
¾
Input High Voltage (RES)
V
¾
¾
LVR=2.0V
LVR=3.0V
V
VLVR
Low Voltage Reset
¾
2.7
V
3V
5V
3V
5V
3V
5V
4
mA
mA
mA
mA
IOL
V
V
OL=0.1VDD
OH=0.9VDD
¾
I/O Port Sink Current
I/O Port Source Current
Pull-high Resistance
10
20
¾
-2
-5
20
10
-4
-10
60
¾
IOH
¾
100
50
kW
kW
RPH
30
Rev. 1.40
4
May 22, 2009
HT48RA1/HT48CA1
A.C. Characteristics
Ta=25°C
Test Conditions
Conditions
2.0V~5.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
400
400
400
400
0
4000
8000
4000
8000
4000
8000
180
130
46
kHz
kHz
kHz
kHz
kHz
kHz
¾
¾
fSYS1
System Clock (Crystal OSC)
System Clock (RC OSC)
3.3V~5.5V
¾
2.0V~5.5V
¾
¾
fSYS2
3.3V~5.5V
¾
¾
3V
5V
3V
5V
3V
5V
¾
¾
fTIMER
tWDTOSC
tWDT1
Timer I/P Frequency (TMR0/TMR1)
Watchdog Oscillator Period
50% duty
0
¾
45
32
11
8
90
65
23
17
1024
ms
ms
¾
ms
ms
tSYS
Watchdog Time-out Period
(WDT OSC)
Without WDT prescaler
33
tWDT2
tRES
Watchdog Time-out Period (fSYS/4)
External Reset Low Pulse Width
Without WDT prescaler
¾
¾
1
¾
¾
¾
¾
ms
Power-up reset or
tSST
tSYS
System Start-up Timer Period
1024
¾
¾
¾
wake-up from HALT
tLVR
tINT
Low Voltage Width to Reset
Interrupt Pulse Width
1
1
ms
¾
¾
¾
¾
¾
¾
¾
¾
ms
Note: tSYS=1/(fSYS
)
Power-on Reset Characteristics
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
VDD Start Voltage to Ensure
Power-on Reset
VPOR
RRVDD
tPOR
0
mV
V/ms
ms
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
VDD raising rate to Ensure
Power-on Reset
0.05
200
¾
¾
Minimum Time for VDD Stays at
V
POR to Ensure Power-on Reset
V
D
D
t
P
O
R
R
V
R
D
D
V
P
O
R
T
i
m
Rev. 1.40
5
May 22, 2009
HT48RA1/HT48CA1
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the MCU is derived from either a
crystal or an RC oscillator. The system clock is internally
divided into four non-overlapping clocks. One instruc-
tion cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip ex-
ecution, loading register, subroutine call or return from
subroutine, initial reset, internal interrupt, external inter-
rupt or return from interrupts, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed to the next instruction.
Program Counter - PC
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of pro-
gram memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
T
1
T
2
T
3
T
1
T
4
T
2
T
3
T
1
T
4
T
2
T
3
T
4
S
y
s
t
e
m
C
l
o
c
k
O
S
C
2
(
R
C
o
n
l
y
)
P
C
P
C
+
1
P
C
+
2
P
C
F
e
t
c
h
I
N
S
T
(
P
C
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
-
1
)
S T
F
e
t
c
h
I
N
(
P
C
+
1
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
)
N
F
e
t
c
h
I
S
T
(
P
C
+
2
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
+
1
Execution Flow
Program Counter
Mode
*12~*8
00000
00000
00000
00000
*7
0
*6
0
*5
0
*4
0
*3
0
*2
0
*1
0
*0
0
Initial Reset
External Interrupt
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
Skip
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
Program Counter + 2
Loading PCL
*12~*8
@7
#7
@6
#6
@5
#5
@4
#4
@3
#3
@2
#2
@1
#1
@0
#0
Jump, Call Branch
Return (RET, RETI)
#12~#8
S12~S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *12~*0: Program counter bits
#12~#0: Instruction code bits
S12~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.40
6
May 22, 2009
HT48RA1/HT48CA1
0
0
0
0
0
4
H
H
Program Memory - ROM
D
e
v
i
c
e
I
n
i
t
i
a
l
i
z
a
t
i
The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192´16 bits, addressed by the program counter and ta-
ble pointer.
E
x
t
e
r
n
a
l
I
n
t
e
r
r
u
p
t
0
0
8
H
T
i
m
e
r
/
E
v
e
n
t
C
o
u
n
I
n
t
e
r
r
u
p
t
S
u
b
r
o
u
t
0
0
C
H
T
i
m
e
r
/
E
v
e
n
t
C
o
u
n
I
n
t
e
r
r
u
p
t
S
u
b
r
o
u
t
Certain locations in the program memory are reserved
for special usage:
P
r
o
g
M
e
m
n
0
0
H
·
Location 000H
L
o
o
k
-
u
p
T
a
b
l
e
(
2
5
6
This area is reserved for program initialization. After
chip reset, the program always begins execution at lo-
cation 000H.
n
F
F
H
·
Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
L
o
o
k
-
u
p
T
a
b
l
e
(
2
5
6
1
F
F
F
H
1
6
b
i
t
s
N
o
t
e
:
n
r
a
n
g
e
s
f
r
o
m
0
·
Location 008H
Program Memory
This area is reserved for the Timer/Event Counter 0 in-
terrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, and if the in-
terrupt is enabled and the stack is not full, the program
begins execution at location 008H .
terrupt(s) is supposed to be disabled prior to the table
read instruction. It (They) will not be enabled until the
TBLH in the main routine has been backup. All table
related instructions require 2 cycles to complete the
operation.
·
Location 00CH
This location is reserved for the Timer/Event Counter
1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and the inter-
rupt is enabled and the stack is not full, the program
begins execution at location 00CH.
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
·
Table location
Any location in the program memory can be used as
look-up tables. The instructions ²TABRDC [m]² (page
specified by TBHP) and ²TABRDL [m]² (the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the higher-order byte to
TBLH (08H). The higher-order byte table pointer
TBHP (1FH) and lower-order byte table pointer TBLP
(07H) are read/write registers, which indicate the table
locations. Before accessing the table, the location has
to be placed in TBHP and TBLP. The TBLH is read
only and cannot be restored. If the main routine and
the ISR (interrupt service routine) both employ the ta-
ble read instruction, the contents of TBLH in the main
routine are likely to be changed by the table read in-
struction used in the ISR. Errors are thus brought
about. Given this, using the table read instruction in
the main routine and the ISR simultaneously should
be avoided. However, if the table read instruction has
to be applied in both main routine and the ISR, the in-
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is sub-
Table Location
Instruction
*12~*8
TBHP
11111
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TABRDL [m]
@7
@7
@6
@6
@5
@5
@4
@4
@3
@3
@2
@2
@1
@1
@0
@0
Table Location
Note: *12~*0: Table location bits
Rev. 1.40
@7~@0: Table pointer bits
7
May 22, 2009
HT48RA1/HT48CA1
I
I
n
n
d
d
i
i
r
r
e
e
c
c
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
i
i
n
n
g
g
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return ad-
dresses are stored).
M
M
P
P
0
1
Data Memory - RAM
A
C
C
The data memory is designed with 249´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(224´8). Most are read/write, but some are read only.
P
C
L
T
B
L
P
T
L
B
H
W
D
T
S
S
T
A
T
U
S
0
0
A
B
H
H
The special function registers include the indirect ad-
dressing registers (R0;00H, R1;02H), Timer/Event
Counter 0 (TMR0;0DH), Timer/Event Counter 0 control
register (TMR0C;0EH), Timer/Event Counter 1 higher
order byte register (TMR1H;0FH), Timer/Event Coun-
ter 1 lower order byte register (TMR1L;10H),
Timer/Event Counter 1 control register (TMR1C;11H),
program counter lower-order byte register (PCL;06H),
memory pointer registers (MP0;01H, MP1;03H), accu-
mulator (ACC;05H), table pointer (TBLP;07H, TBHP;
1FH), table higher-order byte register (TBLH;08H), sta-
tus register (STATUS;0AH), interrupt control register
(INTC;0BH), Watchdog Timer option setting register
(WDTS;09H), I/O registers (PA;12H, PB;14H, PC;16H,
PF;1CH), and I/O control registers (PAC;13H,
PBC;15H, PCC;17H, PFC;1DH). The remaining space
before the 20H is reserved for future expanded usage
and reading these locations will get ²00H². The general
purpose data memory, addressed from 20H to FFH, is
used for data and control information under instruction
commands.
I
N
T
C
0
0
C
D
H
H
S
p
e
c
i
a
l
T
M
R
0
D
A
T
A
M
T
T
M
M
R
R
0
1
C
H
0
E
H
0
F
H
H
H
H
H
H
H
H
H
H
H
T
M
R
1
L
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
T
M
R
1
C
P
P
A
B
P
P
A
B
C
C
P
C
P
C
C
:
U
n
u
1
1
A
B
H
H
R
e
a
d
a
s
1
1
C
D
H
H
P
F
P
F
C
1
E
H
1
F
H
T
B
H
P
2
0
H
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0 or MP1).
G
e
n
e
r
a
l
P
u
r
p
o
s
e
D
A
T
A
M
E
M
O
R
Y
(
2
2
4
B
y
t
e
s
)
F
F
H
Indirect Addressing Register
RAM Mapping
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] ([02H]) will access data memory pointed
to by MP0 (MP1). Reading location 00H (02H) itself indi-
rectly will return the result 00H. Writing indirectly results
in no operation.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic opera-
tions. The ALU provides the following functions:
·
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
The memory pointer registers (MP0 and MP1) are 8-bit
registers.
·
Logic operations (AND, OR, XOR, CPL)
·
Increment and decrement (INC, DEC)
Accumulator
·
Rotation (RL, RR, RLC, RRC)
·
Increment and Decrement (INC, DEC)
The accumulator is closely related to ALU operations. It
is also mapped to location of the data memory and can
carry out immediate data operations. The data move-
ment between two data memory locations must pass
through the accumulator.
·
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
Rev. 1.40
8
May 22, 2009
HT48RA1/HT48CA1
Status Register - STATUS
EMI bit and the corresponding bit of the INTC may be
set to allow interrupt nesting. If the stack is full, the inter-
rupt request will not be acknowledged, even if the re-
lated interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be pre-
vented from becoming full.
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addi-
tion operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² in-
struction. The PDF flag can be affected only by exe-
cuting the ²HALT² or ²CLR WDT² instruction or
during a system power-up.
External interrupts are triggered by a high to low transi-
tion of the INT and the related interrupt request flag (EIF;
bit 4 of INTC) will be set. When the interrupt is enabled,
the stack is not full and the external interrupt is active, a
subroutine call to location 04H will occur. The interrupt
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 5 of INTC), caused by a timer 0
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further in-
terrupts.
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
to set the enable/disable and the interrupt request flags.
The internal Timer/Even Counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (T1F;bit 6 of INTC), caused by a timer 1 overflow.
When the interrupt is enabled, the stack is not full and
the T1F is set, a subroutine call to location 0CH will oc-
cur. The related interrupt request flag (T1F) will be reset
and the EMI bit cleared to disable further interrupts.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
Bit No.
Label
Function
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
0
C
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
1
2
3
AC
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
OV
PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
4
PDF
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
5
TO
set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev. 1.40
9
May 22, 2009
HT48RA1/HT48CA1
Oscillator Configuration
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the ²RETI² in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an in-
terrupt service, but RET will not.
There are 2 oscillator circuits implemented in the
microcontroller.
O
S
C
1
O
S
C
1
f
S
Y
S
O
S
C
2
O
S
C
2
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
N
M
O
S
O
p
e
n
D
r
C
r
y
s
t
a
l
O
s
c
i
l
l
R
a
C
t
o
O
r
s
c
System Oscillator
Both of them are designed for system clocks, namely
the RC oscillator and the crystal oscillator, which are de-
termined by options. No matter what oscillator type is
selected, the signal provides the system clock. The
HALT mode stops the system oscillator and resists the
external signal to conserve power.
Interrupt Source
External Interrupt
Priority Vector
1
2
3
04H
08H
0CH
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance should
range from 100kW to 820kW. The system clock, divided
by 4, is available on OSC2, which can be used to syn-
chronize external logic. The internal RC oscillator pro-
vides the most cost effective solution. However, the
frequency of oscillation may vary with VDD, tempera-
tures and the chip itself due to process variations. It is,
therefore, not suitable for timing sensitive operations
where an accurate oscillator frequency is desired.
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), external interrupt request flag (EIF), enable
Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), en-
able external interrupt bit (EEI) and enable master inter-
rupt bit (EMI) constitute an interrupt control register
(INTC) which is located at 0BH in the data memory. EMI,
EEI, ET0I and ET1I are used to control the enabling/dis-
abling of interrupts. These bits prevent the requested in-
terrupt from being serviced. Once the interrupt request
flags (T0F, T1F, EIF) are set, they will remain in the INTC
register until the interrupts are serviced or cleared by a
software instruction.
If the crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are demanded. Instead of a crystal, the
resonator can also be connected between OSC1 and
OSC2 to get a frequency reference, but two external ca-
pacitors in OSC1 and OSC2 are required.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. In-
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the ²CALL² operates in the interrupt subrou-
tine.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 90ms. The WDT oscillator can
be disabled by ROM code option to conserve power.
Bit No.
Label
EMI
EEI
Function
0
1
2
3
4
5
6
7
Controls the master (global) interrupt (1=enabled; 0=disabled)
Controls the external interrupt (1=enabled; 0=disabled)
Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
External interrupt request flag (1=active; 0=inactive)
ET0I
ET1I
EIF
T0F
T1F
¾
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
Unused bit, read as ²0²
INTC (0BH) Register
Rev. 1.40
10
May 22, 2009
HT48RA1/HT48CA1
Watchdog Timer - WDT
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit ²TO². But in the HALT
mode, the overflow will initialize a ²warm reset² and only
the program counter and SP are reset to zero. To clear
the contents of WDT (including the WDT prescaler),
three methods are adopted; external reset (a low level to
RES), software instruction and a ²HALT² instruction.
The software instruction include ²CLR WDT² and the
other set ²CLR WDT1² and ²CLR WDT2². Of these two
types of instruction, only one can be active depending
on the ROM code option ²CLR WDT² times selection
option. If the ²CLR WDT² is selected (i.e. ²CLR WDT²
times equal one), any execution of the ²CLR WDT² in-
struction will clear the WDT. In the case that ²CLR
WDT1² and ²CLR WDT2² are chosen (i.e. ²CLR WDT²
times equal two), these two instructions must be exe-
cuted to clear the WDT; otherwise, the WDT may reset
the chip as a result of time-out.
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), instruction clock (system
clock divided by 4), determines the ROM code option.
This timer is designed to prevent a software malfunction
or sequence from jumping to an unknown location with
unpredictable results. The Watchdog Timer can be dis-
abled by ROM code option. If the Watchdog Timer is dis-
abled, all the executions related to the WDT result in no
operation.
Once the internal WDT oscillator (RC oscillator with a
period of 90ms@3V normally) is selected, it is first di-
vided by 256 (8-stage) to get the nominal time-out pe-
riod of 23ms@3V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.9s@3V
seconds. If the WDT oscillator is disabled, the WDT
clock may still come from the instruction clock and oper-
ates in the same manner except that in the HALT state
the WDT may stop counting and lose its protecting pur-
pose. In this situation the logic can only be restarted by
external logic. The high nibble and bit 3 of the WDTS are
reserved for user¢s defined flags, which can be used to
indicate some specified status.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
·
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
·
The contents of the on chip RAM and registers remain
unchanged.
·
WDT and WDT prescaler will be cleared and re-
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
counted again (if the WDT clock is from the WDT os-
cillator).
·
All of the I/O ports maintain their original status.
·
The PDF flag is set and the TO flag is cleared.
WS2
WS1
WS0
Division Ratio
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or execut-
ing the ²CLR WDT² instruction and is set when execut-
ing the ²HALT² instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the program counter and SP; the others remain in their
original status.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
WDTS Register
S
y
s
t
e
m
C
l
o
c
k
/
4
W
D
T
P
r
e
s
c
a
l
e
r
R
O
M
C
o
d
e
8
-
b
i
t
C
o
u
7
n
-
b
t
e
i
t
r
C
o
u
n
t
e
r
O
p
t
i
o
n
S
e
l
e
c
t
W
D
T
O
S
C
8
-
t
o
-
1
M
U
X
S
W
0
~
W
S
2
W
D
T
T
i
m
e
-
o
u
t
Watchdog Timer
Rev. 1.40
11
May 22, 2009
HT48RA1/HT48CA1
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by mask option. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If it awakens from an interrupt, two sequence
may occur. If the related interrupt is disabled or the inter-
rupt is enabled but the stack is full, the program will re-
sume execution at the next instruction. If the interrupt is
enabled and the stack is not full, the regular interrupt re-
sponse takes place. If an interrupt request flag is set to
²1² before entering the HALT mode, the wake-up func-
tion of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
The functional unit chip reset status are shown below.
Program Counter
Interrupt
000H
Disable
Clear
Prescaler
Clear. After master reset,
WDT begins counting
WDT
Timer/event Counter Off
Input/output Ports
Stack Pointer
Input mode
Points to the top of the stack
V
D
D
V
D
D
0
.
m
0
F
1
1
0
W
0
k
1
0
W
W
0
k
R
E
S
R
E
S
0
m
. F 1
1
0
k
B
a
s
i
c
H
i
-
n
o
i
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
R
e
s
e
t
R
e
s
e
t
0
m
. F 1
C
i
r
c
u
i
t
C
i
r
c
u
Reset Circuit
Reset
Therearethreewaysinwhicharesetcanoccur:
Note: Most applications can use the Basic Reset Cir-
cuit as shown, however for applications with ex-
tensive noise, it is recommended to use the
Hi-noise Reset Circuit.
·
RES reset during normal operation
·
RES reset during HALT
·
WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the program counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
V
D
D
R
E
S
t
S
S
T
S
S
T
T
i
m
e
-
o
u
t
C
h
i
p
R
e
s
e
t
Reset Timing Chart
TO PDF
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
0
u
0
1
1
0
u
1
u
1
H
A
L
T
W
a
r
m
WDT time-out during normal operation
WDT wake-up HALT
W
D
T
Note: ²u² stands for unchanged
R
E
S
C
o
l
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
R
e
s
S
S
T
1
1
0
-
b
i
t
R
i
p
p
l
e
O
S
C
C
o
u
n
t
e
r
S
y
s
t
e
m
R
e
s
e
t
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
Reset Configuration
Rev. 1.40
12
May 22, 2009
HT48RA1/HT48CA1
The states of the registers is summarized in the table.
Reset
WDT Time-out
RES Reset
RES Reset
WDT Time-out
(HALT)*
Register
(Power On) (Normal Operation) (Normal Operation)
(HALT)
MP0
MP1
ACC
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Program
Counter
0000H
0000H
0000H
0000H
0000H
TBLP
TBHP
TBLH
WDTS
STATUS
INTC
TMR0
TMR0C
TMR1H
TMR1L
TMR1C
PA
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0111
--00 xxxx
-000 0000
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0111
--1u uuuu
-000 0000
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0111
--uu uuuu
-000 0000
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0111
--01 uuuu
-000 0000
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--11 uuuu
-uuu uuuu
uuuu uuuu
uu-u uuuu
uuuu uuuu
uuuu uuuu
uu-u u---
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
--11 1111
---- ---1
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
--11 1111
---- ---1
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
--11 1111
---- ---1
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
--11 1111
---- ---1
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
---- ---u
PAC
PB
PBC
PC
PCC
PF
PFC
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.40
13
May 22, 2009
HT48RA1/HT48CA1
Timer/Event Counter
the counter 0 is reloaded from the Timer/Event Counter
0 preload register and issues the interrupt request just
like the other two modes.
Two timer/event counters (TMR0, TMR1) are imple-
mented in the device. The Timer/Event Counter 0 con-
tains an 8-bit programmable count-up counter and the
clock may come from an external source or the system
clock. The Timer/Event Counter 1 contains an 16-bit
programmable count-up counter and the clock may
come from an external source or the system clock di-
vided by 4.
To enable the counting operation, the timer ON
bit(T0ON; bit 4 of TMR0C) should be set to 1. In the
pulse width measurement mode, the T0ON will be
cleared automatically after the measurement cycle is
complete. But in the other two modes the T0ON can only
be reset by instructions. The overflow of the
Timer/Event Counter 0 is one of the wake-up sources.
No matter what the operation mode is, writing a 0 to
ET0I can disabled the corresponding interrupt service.
Of the two timer/event counters, using external clock in-
put allows the user to count external events, measure
time internals or pulse widths, or generate an accurate
time base. While using the internal clock allows the user
to generate an accurate time base.
In the case of Timer/Event Counter 0 OFF condition,
writing data to the Timer/Event Counter 0 preload regis-
ter will also load the data to Timer/Event Counter 0. But
if the Timer/Event Counter 0 is turned on, data written to
the Timer/Event Counter 0 will only be kept in the
Timer/Event Counter 0 preload register. The
Timer/Event Counter 0 will still operate until the overflow
occurs (a Timer/Event Counter 0 reloading will occur at
the same time).
Only the Timer/Event Counter 0 can generate PFD sig-
nal by using external or internal clock, and PFD fre-
quency is determine by the equation fINT/[2´(256-N)].
There are 2 registers related to Timer/Event Counter 0;
TMR0(0DH), TMR0C(0EH). In Timer/Event Counter 0
counting mode (T0ON=1), writing TMR0 will only put the
written data to preload register (8 bits). The Timer/Event
Counter 0 preload register is changed by each writing
TMR0 operations. Reading TMR0 will also latch the
TMR0 to the destination. The TMR0C is the Timer/Event
Counter 0 control register, which defines the operating
mode, counting enable or disable and active edge.
When the Timer/Event Counter 0 (reading TMR0) is
read, the clock will be blocked to avoid errors. As this
may results in a counting error, this must be taken into
consideration by the programmer.
The bit 0~2 of the TMR0C can be used to define the
pre-scaling stages of the internal clock sources of
Timer/Event Counter 0. The definitions are as shown.
The T0M0, T0M1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR0) pin. The timer mode functions as a normal timer
with the clock source coming from the fINT clock. The
pulse width measurement mode can be used to count
the high or low level duration of the external signal
(TMR0). The counting is based on the fINT clock.
Bit
Label
Function
No.
To define the prescaler stages,
T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS/2
001: fINT=fSYS/4
0
1
2
T0PSC0
T0PSC1
T0PSC2
010: fINT=fSYS/8
In the event count or timer mode, once the Timer/Event
Counter 0 starts counting, it will count from the current
contents in the Timer/Event Counter 0 to FFH. Once
overflow occurs, the counter is reloaded from the
Timer/Event Counter 0 preload register and generates
the corresponding interrupt request flag (T0F; bit 5 of
INTC) at the same time.
011: fINT=fSYS/16
100: fINT=fSYS/32
101: fINT=fSYS/64
110: fINT=fSYS/128
111: fINT=fSYS/256
To define the TMR0 active edge of
Timer/Event Counter 0
3
T0E
(0=active on low to high;
1=active on high to low)
In pulse width measurement mode with the T0ON and
T0E bits are equal to one, once the TMR0 has received
a transition from low to high (or high to low if the T0E bit
is 0) it will start counting until the TMR0 returns to the
original level and reset the T0ON. The measured result
will remain in the Timer/Event Counter 0 even if the acti-
vated transition occurs again. In other words, only one
cycle measurement can be done. Until setting the
T0ON, the cycle measurement will function again as
long as it receives further transition pulse. Note that, in
this operating mode, the Timer/Event Counter 0 starts
counting not according to the logic level but according to
the transition edges. In the case of counter overflows,
To enable/disable timer 0 counting
(0=disabled; 1=enabled)
4
5
T0ON
¾
Unused bit, read as ²0²
To define the operating mode
(T0M1, T0M0)
01=Event count mode
(external clock)
6
7
T0M0
T0M1
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C (0EH) Register
Rev. 1.40
14
May 22, 2009
HT48RA1/HT48CA1
There are 3 registers related to Timer/Event Counter 1;
TMR1H(0FH), TMR1L(10H), TMR1C(11H). Writing
TMR1L will only put the written data to an internal
lower-order byte buffer (8 bits) and writing TMR1H will
transfer the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L preload
registers, respectively. The Timer/Event Counter 1
preload register is changed by each writing TMR1H op-
erations. Reading TMR1H will latch the contents of
TMR1H and TMR1L counters to the destination and the
lower-order byte buffer, respectively. Reading the
TMR1L will read the contents of the lower-order byte
buffer. The TMR1C is the Timer/Event Counter 1 control
register, which defines the operating mode, counting en-
able or disable and active edge.
In pulse width measurement mode with the T1ON and
T1E bits are equal to one, once the TMR1 has received
a transition from low to high (or high to low if the T1E bit
is 0) it will start counting until the TMR1 returns to the
original level and reset the T1ON. The measured result
will remain in the Timer/Event Counter 1 even if the acti-
vated transition occurs again. In other words, only one
cycle measurement can be done. Until setting the
T1ON, the cycle measurement will function again as
long as it receives further transition pulse. Note that, in
this operating mode, the Timer/Event Counter 1 starts
counting not according to the logic level but according to
the transition edges. In the case of counter overflows,
the counter 1 is reloaded from the Timer/Event Counter
1 preload register and issues the interrupt request just
like the other two modes.
The T1M0, T1M1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR1) pin. The timer mode functions as a normal timer
with the clock source coming from the instruction clock.
The pulse width measurement mode can be used to
count the high or low level duration of the external signal
(TMR1). The counting is based on the instruction clock.
To enable the counting operation, the timer ON bit
(T1ON; bit 4 of TMR1C) should be set to 1. In the pulse
width measurement mode, the T1ON will be cleared au-
tomatically after the measurement cycle is complete.
But in the other two modes the T1ON can only be reset
by instructions. The overflow of the Timer/Event Coun-
ter 1 is one of the wake-up sources. No matter what the
operation mode is, writing a 0 to ET1I can disabled the
corresponding interrupt service.
In the event count or timer mode, once the Timer/Event
Counter 1 starts counting, it will count from the current
contents in the Timer/Event Counter 1 to FFFFH. Once
overflow occurs, the counter is reloaded from the
Timer/Event Counter 1 preload register and generates
the corresponding interrupt request flag (T1F; bit 6 of
INTC) at the same time.
In the case of Timer/Event Counter 1 OFF condition,
writing data to the Timer/Event Counter 1 preload regis-
ter will also load the data to Timer/Event Counter 1. But
if the Timer/Event Counter 1 is turned on, data written to
the Timer/Event Counter 1 will only be kept in the
(
1
/
2
~
1
/
2
5
6
)
8
-
s
t
a
g
e
P
r
e
s
c
a
l
e
r
f
S
Y
S
D
a
t
a
B
u
s
f
I
N
T
8
-
1
M
U
X
T
0
M
1
T
i
m
e
r
/
E
v
e
n
t
C
o
u
n
t
e
r
T
0
M
0
T
0
P
S
C
2
~
T
0
P
S
0
C
0
T
M
R
P
r
e
l
o
a
d
R
e
g
i
s
t e
d
r
R
e
l
o
a
T
0
E
P
u
l
s
e
W
i
d
t
h
8
-
b
i
t
T
0
M
1
M
e
a
s
u
r
e
m
e
n
t
T
i
m
e
r
/
E
v
e
n
t
C
o
u
n
t
e
r
T
0
M
0
O
v
e
r
f
l
o
w
M
N
o
d
e
C
o
n
t
r
o
l
(
T
M
R
0
)
T
0
O
¸
2
P
F
D
Timer/Event Counter 0
D
a
t
a
B
u
s
T
T
1
1
M
M
1
0
f
S
Y
/
S
4
1
6
-
b
i
t
L
o
w
B
y
t
e
T
M
R
1
T
i
m
e
r
/
E
v
e
n
t
C
o
u
n t
r
e
r
B
u
f
f
e
P
r
e
l
o
a
d
R
e
g
i
s
t
e
r
T
1
E
R
e
l
o
a
d
1
6
-
b
i
t
P
u
l
s
e
W
i
d
t
h
T
1
M
1
T
t
i
m
e
r
/
E
v
e
n
t
C
o
u
n
t
e
r
M
e
a
s
u
r
e
m
e
n
O
v
e
r
f
l
o
w
t
o
I
n
T
1
M
0
( T
l
M
R
1
H
/
T
M
R
1
L
)
M
o
d
e
C
o
n
t
r
o
T
1
O
N
Timer/Event Counter 1
Rev. 1.40
15
May 22, 2009
HT48RA1/HT48CA1
Timer/Event Counter 1 preload register. The
Timer/Event Counter 1 will still operate until the overflow
occurs (a Timer/Event Counter 1 reloading will occur at
the same time).
Input/Output Ports
There are 23 bi-directional input/output lines in the mi-
cro-controller, labeled from PA to PC and PF, which are
mapped to the data memory of [12H], [14H], [16H] and
[1CH], respectively. All of these I/O ports can be used as
input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready
at the T2 rising edge of instruction ²MOV A,[m]² (m =
12H, 14H, 16H or 1CH). For output operation, all the
data is latched and remains unchanged until the output
latch is rewritten.
When the Timer/Event Counter 1 (reading TMR1H) is
read, the clock will be blocked to avoid errors. As this
may results in a counting error, this must be taken into
consideration by the programmer.
The definitions of the TMR1C are as shown.
Bit
Label
Function
No.
Each I/O line has its own control register (PAC, PBC,
PCC, PFC) to control the input/output configuration.
With this control register, CMOS output or Schmitt trig-
ger input with or without (depends on options) pull-high
resistor structures can be reconfigured dynamically (i.e.,
on-the fly) under software control. To function as an in-
put, the corresponding latch of the control register has to
be set as ²1². The pull-high resistor (if the pull-high re-
sistor is enabled) will be exhibited automatically. The in-
put sources also depends on the control register. If the
control register bit is ²1², the input will read the pad state
(²mov² and read-modify-write instructions”). If the con-
trol register bit is 0, the contents of the latches will move
to internal data bus (²mov² and read-modify-write in-
structions). The input paths (pad state or latches) of
read-modify-write instructions are dependent on the
control register bits. For output function, CMOS is the
only configuration. These control registers are mapped
to locations 13H, 15H, 17H and 1DH.
0~2
¾
Unused bit, read as ²0²
To define the active edge of TMR1 pin
3
T1E input signal
(0/1: active on low to high/high to low)
To enable/disable timer 1 counting
(0/1: disabled/enabled)
4
5
T1ON
¾
Unused bit, read as ²0²
To define the operating mode (T1M1,
T1M0)
6
7
T1M0 01=Event count mode (external clock)
T1M1 10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C (11H) Register
V
D
D
C
o
n
t
r
o
l
B
U
i
t
P
D
t
a
a
B
u
s
D
C
Q
Q
K
W
r
i
t
e
C
o
n
t
r
e
o
l
R
e
g
i
s
t
e
r
S
t
C
h
i
p
R
s
e
P
P
P
P
P
A
B
B
C
F
0
0
1
~
/
~
P
P
A
B
7
7
P
F
D
R
e
a
d
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
0
~
P
C
5
D
a
t
a
B
i
t
0
D
C
Q
Q
K
W
r
i
t
e
D
a
t
a
R
e
g
i
s
t
e
r
S
M
U
P
B
0
(
P
B
0
o
n
l
y
)
X
E
X
T
P
F
D
E
N
M
(
P
B
0
o
n
l
y
)
U
X
R
e
a
d
D
a
t
a
R
e
g
i
s
t
e
P
r
S
y
s
t
e
m
W
a
k
e
-
u
p
(
P
A
o
n
l
y
)
A
W
a
k
e
-
u
p
O
p
t
i
o
n
I
N
T
f
o
r
P
F
0
O
n
l
y
P
F
D
f
o
r
P
B
0
O
n
l
y
,
C
o
n
t
r
o
l
=
P
B
0
D
a
t
a
R
e
g
Input/Output Ports
Rev. 1.40
16
May 22, 2009
HT48RA1/HT48CA1
After a chip reset, these input/output lines stay at high
levels (pull-high options) or floating state (non-pull-high
options). Each bit of these input/output latches can be
set or cleared by ²SET [m].i² (m=12H, 14H, 16H or 1CH)
instructions. Some instructions first input data and then
follow the output operations. For example, ²SET [m].i²,
²CLR [m].i², ²CPLA [m]² read the entire port states into
the CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or the ac-
cumulator.
Low Voltage Reset - LVR
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will au-
tomatically reset the device internally.
The LVR includes the following specifications:
·
The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
Each line of port A has the capability of waking-up the
device. The highest 2 bits of port C and 7 bits of port F
are not physically implemented; on reading them a ²0² is
returned whereas writing then results in a no-operation.
Pull-high resistors of each port are decided by a option
bit.
·
The LVR uses the ²OR² function with the external
RES signal to perform chip reset.
The relationship between VDD and VLVR is shown below.
V
D
D
The PB0 is pin-shared with PFD signal, respectively. If
the PFD option is selected, the output signal in output
mode of PB0 will be the PFD signal. The input mode al-
ways remain its original functions. The PF0 and PC0 are
pin-shared with INT and TMR0. The INT signal is di-
rectly connected to PF0. The PFD output signal (in out-
put mode) are controlled by the PB0 data register only.
5
.
5
V
V
L
V
R
1
.
8
V
The truth table of PB0/PFD is listed below.
PBC (15H) Bit0
PB0/PFD option
PB0 (14H) Bit0
PB0 pad status
I
x
x
I
O
PB0
D
O
PFD
0
O
PFD
1
0
.
9
V
D
0
PFD
Note:
²I² Input
²O² Output
²D² Data
V
D
D
5
.
5
V
L
V
R
D
e
t
e
c
t
V
L
V
R
0
.
9
V
0
V
R
e
s
e
t
S
i
g
n
a
l
R
e
s
e
t
N
o
r
m
a
l
O
p
e
r
a
t
i
o
n
R
e
s
e
t
*
1
*
2
Low Voltage Reset
Note:
²*1² To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
²*2² Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters
the reset mode.
Rev. 1.40
17
May 22, 2009
HT48RA1/HT48CA1
Options
The following table shows all kinds of code option in the MCU. All of the mask options must be defined to ensure proper
system functioning.
Function
PA0~PA7 wake-up enable or disable options
PC pull-high enable or disable
PA pull-high enable or disable: Byte option
PF pull-high enable or disable
PB pull-high (PB0~PB3, PB4~PB7) enable or disable: Nibble option
PB0 or PFD
CLR WDT instructions
System oscillators: RC or crystal
WDT enable or disable
WDT clock source: WDTOSC or system clock/4
LVR function: enable or disable
LVR voltage: 2.0V or 3.0V
Rev. 1.40
18
May 22, 2009
HT48RA1/HT48CA1
Application Circuits
V
D
D
V
D
D
R
e
s
e
t
V
D
D
1
0
W
0
k
C
i
r
c
u
i
t
P
P
A
B
0
1
~
~
P
P
A
B
7
7
4
R
C
S
y
s
t
e
m
4
7
0
p
F
1
0
W
0
<
k
O
R
S
<
C
8
2
W
0
k
0
m
. F 1
O
O
S
S
C
C
1
2
R
E
S
P
B
0
/
P
F
D
R
O
S
C
0
m
. F 1
f
S
Y
S
P
C
0
/
T
M
R
0
1
C
1
V
S
S
P
C
1
~
P
C
O
O
S
S
C
C
1
2
C
S
r
y
s
t
a
l
/
R
e
s
P
C
5
/
T
M
R
y
s
t
e
m
O
s
c
P
F
0
/
I
N
T
C
2
F
o
r
R
1
,
C
1
,
O
O
S
S
C
C
1
2
R
1
O
S
C
C
i
r
c
u
i
t
O
S
C
C
i
r
c
u
i
t
H
T
4
8
R
A
1
/
H
T
4
8
C
A
1
Note: 1. Crystal/resonator system oscillators
For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For
resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is
not necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator
when VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2
should be selected in consultation with the crystal/resonator manufacturer specifications.
2. Reset circuit
The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and re-
mains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of
the wiring connected to the RES pin is kept as short as possible, to avoid noise interference.
3. For applications where noise may interfere with the reset circuit and for details on the oscillator external
components, refer to Application Note HA0075E for more information.
Rev. 1.40
19
May 22, 2009
HT48RA1/HT48CA1
Example
V
D
D
V
D
D
P
P
P
P
P
P
P
P
P
P
P
P
P
P
A
A
A
A
A
A
A
A
B
B
B
B
B
B
0
1
2
3
4
5
6
7
2
3
4
5
6
7
R
e
s
e
t
1
0
W
0
k
C
i
r
c
u
i
t
0
m
. F 1
R
E
S
0
m
. F 1
V
S
S
3
W
3
V
D
D
1
m
0 F 0
1
W
V
b
a
t
P
C
0
/
T
M
R
0
2
2
W
~
0
1
W
k
P
C
1
P
B
0
/
P
F
D
O
O
S
S
C
C
1
2
O
S
C
C
i
r
c
u
i
t
P
(
F
0
/
I
N
T
L
e
a
r
n
i
n
g
I
n
p
u
t
)
R
e
c
e
i
v
e
r
P
P
P
P
C
C
C
2
3
4
E
E
P
R
O
M
C
5
/
T
M
R
1
H
T
4
8
R
A
1
/
H
T
4
8
C
A
1
Rev. 1.40
20
May 22, 2009
HT48RA1/HT48CA1
Instruction Set
Introduction
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to en-
sure correct handling of carry and borrow data when re-
sults exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Central to the successful operation of any
microcontroller is its instruction set, which is a set of pro-
gram instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of pro-
gramming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several func-
tional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on pro-
gram requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruc-
tion cycle. The exceptions to this are branch, call, or ta-
ble read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be im-
plemented within 1ms. Although instructions which re-
quire one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instruc-
tions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to imple-
ment. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instruc-
tions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the re-
sult of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a sub-
routine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the sub-
routine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made re-
garding the condition of a certain data memory or indi-
vidual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the pro-
gram perhaps determined by the condition of certain in-
put switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific imme-
diate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
Rev. 1.40
21
May 22, 2009
HT48RA1/HT48CA1
Bit Operations
Other Operations
The ability to provide single bit operations on Data Mem-
ory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The fea-
ture removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write pro-
cess is taken care of automatically when these bit oper-
ation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² in-
struction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electro-
magnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be con-
sulted as a basic instruction reference using the follow-
ing listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using regis-
ters. However, when working with large amounts of
fixed data, the volume involved often makes it inconve-
nient to store the fixed data in the Data Memory. To over-
come this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instruc-
tions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Arithmetic
Description
Cycles Flag Affected
ADD A,[m]
ADDM A,[m]
ADD A,x
Add Data Memory to ACC
1
1Note
1
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
Add ACC to Data Memory
Add immediate data to ACC
ADC A,[m]
ADCM A,[m]
SUB A,x
Add Data Memory to ACC with Carry
1
1Note
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
1
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
1
1Note
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1Note
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1Note
1Note
1
OR A,x
1
XOR A,x
1
1Note
CPL [m]
CPLA [m]
Complement Data Memory with result in ACC
1
Increment & Decrement
INCA [m]
INC [m]
Increment Data Memory with result in ACC
1
Z
Z
Z
Z
Increment Data Memory
1Note
DECA [m]
DEC [m]
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
Rev. 1.40
22
May 22, 2009
HT48RA1/HT48CA1
Mnemonic
Rotate
Description
Cycles Flag Affected
RRA [m]
RR [m]
Rotate Data Memory right with result in ACC
Rotate Data Memory right
1
1Note
1
1Note
1
1Note
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
C
None
None
C
RLCA [m]
RLC [m]
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
C
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Branch
JMP addr
SZ [m]
Jump unconditionally
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Skip if Data Memory is zero
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
Return from subroutine
2
RET A,x
RETI
Return from subroutine and load immediate data to ACC
Return from interrupt
2
2
Table Read
TABRDC [m]
TABRDL [m]
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
Miscellaneous
NOP
No operation
1
1Note
1Note
1
None
None
CLR [m]
Clear Data Memory
SET [m]
Set Data Memory
None
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Clear Watchdog Timer
TO, PDF
TO, PDF
TO, PDF
None
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1
1Note
1
None
1
TO, PDF
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
Rev. 1.40
23
May 22, 2009
HT48RA1/HT48CA1
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-
eration. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
Rev. 1.40
24
May 22, 2009
HT48RA1/HT48CA1
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then in-
crements by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruc-
tion.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Operation
Each bit of the specified Data Memory is cleared to 0.
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Operation
Bit i of the specified Data Memory is cleared to 0.
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Description
Operation
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 1.40
25
May 22, 2009
HT48RA1/HT48CA1
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-
sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-
ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Operation
Data in the specified Data Memory is decremented by 1.
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-
mulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 1.40
26
May 22, 2009
HT48RA1/HT48CA1
INC [m]
Increment Data Memory
Description
Operation
Data in the specified Data Memory is incremented by 1.
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-
lator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Description
Operation
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
Operation
The immediate data specified is loaded into the Accumulator.
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Description
Operation
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
Operation
Affected flag(s)
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-
ation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.40
27
May 22, 2009
HT48RA1/HT48CA1
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-
ation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the re-
stored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by set-
ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed be-
fore returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-
main unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.40
28
May 22, 2009
HT48RA1/HT48CA1
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-
tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-
places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.40
29
May 22, 2009
HT48RA1/HT48CA1
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-
sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Operation
Each bit of the specified Data Memory is set to 1.
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Operation
Bit i of the specified Data Memory is set to 1.
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.40
30
May 22, 2009
HT48RA1/HT48CA1
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumu-
lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-
tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.40
31
May 22, 2009
HT48RA1/HT48CA1
SWAP [m]
Description
Operation
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruc-
tion.
Operation
Skip if [m] = 0
None
Affected flag(s)
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-
tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
None
Affected flag(s)
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.40
32
May 22, 2009
HT48RA1/HT48CA1
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-
eration. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.40
33
May 22, 2009
HT48RA1/HT48CA1
Package Information
28-pin SOP (300mil) Outline Dimensions
2
8
1
5
A
B
1
1
4
C
C
'
G
H
D
a
E
F
·
MS-013
Dimensions in mil
Symbol
Min.
393
256
12
697
¾
Nom.
¾
Max.
419
300
20
A
B
C
C¢
D
E
F
¾
¾
713
104
¾
¾
¾
50
¾
4
12
¾
¾
¾
¾
G
H
a
16
8
50
13
0°
8°
Rev. 1.40
34
May 22, 2009
HT48RA1/HT48CA1
28-pin SSOP (209mil) Outline Dimensions
2
8
1
1
5
4
A
B
1
C
C
'
G
H
D
a
E
F
·
MO-150
Dimensions in mm
Symbol
Min.
7.40
5.00
0.22
9.90
¾
Nom.
¾
Max.
8.20
5.60
0.33
10.50
2.00
¾
A
B
C
C¢
D
E
F
¾
¾
¾
0.65
¾
¾
0.05
0.55
0.09
0°
¾
G
H
a
0.95
0.21
8°
¾
¾
¾
Rev. 1.40
35
May 22, 2009
HT48RA1/HT48CA1
Product Tape and Reel Specifications
Reel Dimensions
D
T
2
C
A
B
T
1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
330.0±1.0
A
B
Reel Outer Diameter
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
100.0±1.5
+0.5/-0.2
13.0
C
D
2.0±0.5
+0.3/-0.2
24.8
T1
T2
Space Between Flange
Reel Thickness
30.2±0.2
SSOP 28S (209mil)
Symbol
Description
Reel Outer Diameter
Reel Inner Diameter
Dimensions in mm
330.0±1.0
A
B
100.0±1.5
+0.5/-0.2
13.0
C
Spindle Hole Diameter
Key Slit Width
D
2.0±0.5
+0.3/-0.2
28.4
T1
T2
Space Between Flange
Reel Thickness
31.1 (max.)
Rev. 1.40
36
May 22, 2009
HT48RA1/HT48CA1
Carrier Tape Dimensions
P
0
P
1
t
D
E
F
W
B
0
C
D
1
P
K
0
A
0
R
e
e
l
H
o
l
e
I
C
p
a
c
k
a
g
e
p
i
n
1
a
n
d
t
a
r
e
l
o
c
a
t
e
d
o
n
t
h
e
s
a
m
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
24.0±0.3
W
P
Carrier Tape Width
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
11.5±0.1
+0.1/-0.0
D
1.5
+0.25/-0.00
D1
P0
P1
A0
B0
K0
t
1.50
4.0±0.1
2.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
10.85±0.10
18.34±0.10
2.97±0.10
0.35±0.01
21.3±0.1
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
SSOP 28S (209mil)
Symbol
Description
Carrier Tape Width
Cavity Pitch
Dimensions in mm
24.0±0.3
W
P
12.0±0.1
E
Perforation Position
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
1.75±0.10
F
11.5±0.1
+0.1/-0.0
D
1.5
+0.25/-0.00
D1
P0
P1
A0
B0
K0
t
1.50
4.0±0.2
2.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
8.4±0.1
Cavity Width
10.65±0.10
2.4±0.1
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
0.30±0.05
21.3±0.1
C
Rev. 1.40
37
May 22, 2009
HT48RA1/HT48CA1
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103
Tel: 86-21-5422-4590
Fax: 86-21-5422-4705
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2009 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.40
38
May 22, 2009
相关型号:
©2020 ICPDF网 联系我们和版权申明