HT48CA3 [HOLTEK]
8-Bit Remote Type MCU; 8位遥控型MCU![HT48CA3](http://pdffile.icpdf.com/pdf1/p00073/img/icpdf/HT48CA3_383680_icpdf.jpg)
型号: | HT48CA3 |
厂家: | ![]() |
描述: | 8-Bit Remote Type MCU |
文件: | 总36页 (文件大小:267K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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HT48CA3
8-Bit Remote Type MCU
Features
·
·
·
·
·
·
Operating voltage: 2.2V~3.6V
PFD supported
23 bidirectional I/O lines (max.)
1 interrupt input shared with an I/O line
HALT function and wake-up feature reduce power
consumption
·
·
8-level subroutine nesting
8-bit programmable timer/event counter with overflow
interrupt and 8-stage prescaler (TMR0)
Up to 1ms instruction cycle with 4MHz system clock at
V
DD=3V
·
16-bit programmable timer/event counter and
overflow interrupts (TMR1)
·
·
·
·
·
Bit manipulation instruction
·
·
·
On-chip crystal and RC oscillator
Watchdog Timer
16-bit table read instruction
63 powerful instructions
24K´16 program memory ROM
(8K´16 bits´3 banks)
All instructions in one or two machine cycles
28-pin SKDIP/SOP package
·
224´8 data memory RAM
General Description
The HT48CA3 is an 8-bit high performance, RISC archi-
tecture microcontroller device specifically designed for
multiple I/O control product applications. The data ROM
can be used to store remote control codes. This device
is the mask version which is fully pin and functionally
compatible with the OTP version HT48RA3 device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, watchdog timer,
programmable frequency divider, HALT and wake-up
functions, as well as low cost, enhance the versatility of
this device to suit a wide range of application possibili-
ties such as industrial control, consumer products, sub-
system controllers, and particularly suitable for use in
products such as universal remote controller (URC).
Block Diagram
S
Y
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P
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S
Rev. 1.40
1
July 16, 2003
HT48CA3
Pin Assignment
P
B
B
A
A
A
A
6
7
4
5
6
7
P
B
5
1
2
3
4
5
6
7
8
9
1
1
1
1
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
8
7
6
5
4
3
2
1
0
9
8
7
6
5
P
P
B
4
P
P
A
3
P
P
A
2
P
P
A
1
P
P
A
0
O
S
S
C
C
2
1
P
B
3
O
P
P
B
B
2
1
V
D
D
R
E
S
P
B
0
/
P
V
F
S
D
0
1
2
3
4
P
C
5
/
T
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1
S
P
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4
P
F
0
/
I
N
T
P
P
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C
3
2
P
C
0
/
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0
P
1
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T
4
8
C
A
3
2
8
S
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I
P
-
A
/
S
O
P
-
A
Pin Description
ROM Code
Option
Pin Name
RES
I/O
Description
I
Schmitt trigger reset input, active low.
¾
Bidirectional 8-bit input/output port. Each bit can be configured as a
wake-up input by a mask option. Software instructions determine the
CMOS output or Schmitt trigger input with/without pull-high resistor. The
pull-high resistor of each input/output line is also optional.
Wake-up*
PA0~PA7
I/O
Pull-high***
Bidirectional 8-bit input/output port. Software instructions determine
the CMOS output or Schmitt trigger input with/without pull-high resis-
tor. The pull-high resistor of each input/output line is also optional. The
output mode of PB0 can be used as an internal PFD signal output and
it can be used as a various frequency carrier signal.
PB0/PFD
PB1~PB7
Pull-high**
I/O
PB0 or PFD
VSS
Negative power supply, ground
¾
¾
Bidirectional 6-bit input/output port. Software instructions determine
the CMOS output or Schmitt trigger input with/without pull-high resis-
tor. The pull-high resistor of each input/output line is also optional. PC0
and PC5 are pin shared with TMR0 and TMR1 function pins.
PC0/TMR0
PC1~PC4
PC5/TMR1
I/O
Pull-high*
Bidirectional 1-bit input/output port. Software instructions determine
the CMOS output or Schmitt trigger input with/without pull-high resis-
tor. The pull-high resistor of this input/output line is also optional. PF0
is pin shared with the INT function pin.
PF0/INT
VDD
I/O
Pull-high*
Positive power supply
¾
¾
OSC1, OSC2 are connected to an RC network or Crystal (determined
by hardware option) for the internal system clock. In the case of RC op-
eration, OSC2 is the output terminal for 1/4 system clock.
OSC1
OSC2
I
Crystal
or RC
O
Note: * Bit option
** Nibble option
*** Byte option
Rev. 1.40
2
July 16, 2003
HT48CA3
Absolute Maximum Ratings
Supply Voltage...........................VSS-0.3V to VSS+4.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
Storage Temperature............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Ta=25°C
Test Conditions
Conditions
¾
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
VDD
IDD
Operating Voltage
2.2
3.6
5
V
mA
mA
mA
V
¾
3
No load, fSYS=4MHz
Operating Current
3V
¾
ISTB1
ISTB2
VIL1
VIH1
VIL2
VIH2
IOL
Standby Current (WDT Enabled)
Standby Current (WDT Disabled)
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
Input Low Voltage (RES Ports)
Input High Voltage (RES Ports)
I/O Port Sink Current
3V No load, system HALT
3V No load, system HALT
5
10
¾
0.1
¾
¾
¾
¾
10
-5
-8
60
1
¾
0.2VDD
VDD
0.4VDD
VDD
0
0.8VDD
0
¾
¾
¾
¾
V
V
¾
¾
0.9VDD
5
V
¾
¾
VOL=0.1VDD
VOH=0.9VDD
VOH=0.8VDD
3V
3V
3V
3V
mA
mA
mA
kW
¾
¾
¾
80
IOH1
IOH2
RPH
I/O Port Source Current
-2
I/O Port Source Current
-4
Pull-high Resistance
40
¾
A.C. Characteristics
Ta=25°C
Test Conditions
Conditions
¾
Symbol
Parameter
System Clock
Min.
Typ.
Max.
Unit
VDD
fSYS
3V
400
0
4000
4000
180
kHz
kHz
ms
¾
¾
90
fTIMER
tWDTOSC
Timer I/P Frequency (TMR0/TMR1) 3V 50% duty
Watchdog Oscillator
3V
45
¾
Watchdog Time-out Period
(WDT OSC)
tWDT1
3V Without WDT prescaler 11.5
23
46
ms
tWDT2
tRES
Watchdog Time-out Period (fSYS/4)
External Reset Low Pulse Width
tSYS
3V Without WDT prescaler
1024
¾
¾
¾
1
¾
¾
¾
¾
ms
Power-up, reset or
wake-up from HALT
tSST
tSYS
System Start-up Timer Period
1024
¾
¾
tINT
Interrupt Pulse Width
1
1
¾
¾
¾
¾
¾
¾
¾
¾
ms
ms
tACC
Data ROM Access Time
Note: tSYS=1/(fSYS
)
Rev. 1.40
3
July 16, 2003
HT48CA3
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the MCU is derived from either a
crystal or an RC oscillator. The system clock is internally
divided into four non-overlapping clocks. One instruc-
tion cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip ex-
ecution, loading register, subroutine call or return from
subroutine, initial reset, internal interrupt, external inter-
rupt or return from interrupts, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed to the next instruction.
Program Counter - PC
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of pro-
gram memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
S
y
s
t
e
m
C
l
o
c
k
O
S
C
2
(
R
C
o
n
l
y
)
P
C
P
C
+
1
P
C
+
2
P
C
F
e
t
c
h
I
N
S
T
(
P
C
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
-
1
)
F
e
t
c
h
I
N
S
T
(
P
C
+
1
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
)
F
e
t
c
h
I
N
S
T
(
P
C
+
2
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
+
1
)
Execution flow
Program Counter
Mode
*14~*8
*7
0
*6
*5
0
*4
0
*3
0
*2
0
*1
0
*0
0
Initial Reset
External Interrupt
0000000
0000000
0000000
0000000
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
Skip
0
0
0
1
0
0
0
0
0
0
1
1
0
0
*14~*13, (*12~*0+2): (within current bank)
Loading PCL
*14~*8
@7
#7
@6
#6
@5
#5
@4
#4
@3
#3
@2
#2
@1
#1
@0
#0
Jump, Call Branch
Return (RET, RETI)
BP(1~0), #12~#8
S14~S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *14~*0: Program counter bits
#14~#0: Instruction code bits
1 bank: 8K words
S14~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.40
4
July 16, 2003
HT48CA3
0
0
0
0
0
4
H
H
Program Memory - ROM
D
e
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I
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a
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i
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a
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o
n
P
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g
r
a
m
The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192´16 bits´3 banks, addressed by the program coun-
ter and table pointer.
E
x
t
e
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0
0
8
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0
0
C
H
T
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r
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1
I
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p
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S
u
b
r
o
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t
i
n
e
Certain locations in the program memory are reserved
for special usage:
P
r
o
g
r
a
m
M
e
m
o
r
y
n
0
0
H
·
Location 000H
L
o
o
k
-
u
p
T
a
b
l
e
(
2
5
6
w
o
r
d
s
)
This area is reserved for program initialization. After
chip reset, the program always begins execution at lo-
cation 000H.
n
F
F
H
·
Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
L
o
o
k
-
u
p
T
a
b
l
e
(
2
5
6
w
o
r
d
s
)
5
F
F
F
H
1
6
b
i
t
s
N
o
t
e
:
n
r
a
n
g
e
s
f
r
o
m
0
t
o
5
F
·
·
Location 008H
Program memory
This area is reserved for the Timer/Event Counter 0 in-
terrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, and if the in-
terrupt is enabled and the stack is not full, the program
begins execution at location 008H.
terrupt(s) is supposed to be disabled prior to the table
read instruction. It (They) will not be enabled until the
TBLH in the main routine has been backup. All table
related instructions require 2 cycles to complete the
operation.
Location 00CH
This location is reserved for the Timer/Event Counter
1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and the inter-
rupt is enabled and the stack is not full, the program
begins execution at location 00CH.
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
·
Table location
Any location in the program memory can be used as
look-up tables. The instructions ²TABRDC [m]² (page
specified by TBHP) and ²TABRDL [m]² (the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the higher-order byte to
TBLH(08H). The higher-order byte table pointer
TBHP(1FH) and lower-order byte table pointer TBLP
(07H) are read/write registers, which indicate the table
locations. Before accessing the table, the location has
to be placed in TBHP and TBLP. The TBLH is read
only and cannot be restored. If the main routine and
the ISR (interrupt service routine) both employ the ta-
ble read instruction, the contents of TBLH in the main
routine are likely to be changed by the table read in-
struction used in the ISR. Errors are thus brought
about. Given this, using the table read instruction in
the main routine and the ISR simultaneously should
be avoided. However, if the table read instruction has
to be applied in both main routine and the ISR, the in-
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is sub-
Table Location
Instruction
*14~*8
TBHP
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TABRDL [m]
@7
@7
@6
@6
@5
@5
@4
@4
@3
@3
@2
@2
@1
@1
@0
@0
1011111
Table location
Note: *14~*0: Table location bits
Rev. 1.40
@7~@0: Table pointer bits
5
July 16, 2003
HT48CA3
I
I
n
n
d
d
i
i
r
r
e
e
c
c
t
t
A
A
d
d
d
d
r
r
e
s
s
s
s
i
i
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n
g
g
R
R
e
e
g
g
i
i
s
s
t
t
e
e
r
r
0
1
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return ad-
dresses are stored).
M
e
P
P
0
1
M
B
P
Data Memory - RAM
A
C
C
The data memory is designed with 250´8 bits. The
data memory is divided into two functional groups: spe-
cial function registers and general purpose data mem-
ory (224´8). Most are read/write, but some are read
only.
P
C
L
T
B
L
P
T
B
L
H
W
D
T
S
S
T
A
T
U
S
0
0
A
B
H
H
I
N
T
C
The special function registers include the indirect ad-
dressing registers (R0;00H, R1;02H) bank pointer
(BP;04H), Timer/Event Counter 0 (TMR0;0DH),
Timer/Event Counter 0 control register (TMR0C;0EH),
Timer/Event Counter 1 higher order byte register
(TMR1H;0FH), Timer/Event Counter 1 lower order byte
register (TMR1L;10H), Timer/Event Counter 1 control
register (TMR1C;11H), program counter lower-order
byte register (PCL;06H), memory pointer registers
(MP0;01H, MP1;03H), accumulator (ACC;05H), table
pointer (TBLP;07H, TBHP;1FH), table higher-order
byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register (INTC;0BH),
Watchdog Timer option setting register (WDTS;09H),
I/O registers (PA;12H, PB;14H, PC;16H, PF;1CH, and
I/O control registers (PAC;13H, PBC;15H, PCC;17H,
PFC;1DH). The remaining space before the 20H is re-
served for future expanded usage and reading these
locations will get ²00H². The general purpose data
memory, addressed from 20H to FFH, is used for data
and control information under instruction commands.
0
0
C
D
H
H
S
p
e
c
i
a
l
P
u
r
p
o
s
e
T
M
R
0
D
A
T
A
M
E
M
O
R
Y
T
T
M
M
R
R
0
1
C
H
0
E
H
0
F
H
H
H
H
H
H
H
H
H
H
H
T
M
R
1
L
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
T
M
R
1
C
P
P
A
B
P
P
A
B
C
C
P
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:
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H
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1
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C
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H
H
P
F
P
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C
1
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1
F
H
T
B
H
P
2
0
H
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0 or MP1).
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4
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F
F
H
Indirect Addressing Register
RAM mapping
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] ([02H]) will access data memory pointed
to by MP0 (MP1). Reading location 00H (02H) itself indi-
rectly will return the result 00H. Writing indirectly results
in no operation.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic opera-
tions. The ALU provides the following functions:
·
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
·
·
·
·
·
Logic operations (AND, OR, XOR, CPL)
Increment and decrement (INC, DEC)
Rotation (RL, RR, RLC, RRC)
The memory pointer registers (MP0 and MP1) are 8-bit
registers.
Accumulator
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The accumulator is closely related to ALU operations. It
is also mapped to location of the data memory and can
carry out immediate data operations. The data move-
ment between two data memory locations must pass
through the accumulator.
The ALU not only saves the results of a data operation
but also changes the status register.
Rev. 1.40
6
July 16, 2003
HT48CA3
Status Register - STATUS
EMI bit and the corresponding bit of the INTC may be set
to allow interrupt nesting. If the stack is full, the interrupt
request will not be acknowledged, even if the related in-
terrupt is enabled, until the SP is decremented. If immedi-
ate service is desired, the stack must be prevented from
becoming full.
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PD), and watchdog time-out flag (TO).
It also records the status information and controls the
operation sequence.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
With the exception of the TO and PD flags, bits in the
status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PD flag. In addition
operations related to the status register may give dif-
ferent results from those intended. The TO flag can
be affected only by system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² in-
struction. The PD flag can be affected only by execut-
ing the ²HALT² or ²CLR WDT² instruction or during a
system power-up.
External interrupts are triggered by a high to low transi-
tion of the INT and the related interrupt request flag (EIF;
bit 4 of INTC) will be set. When the interrupt is enabled,
the stack is not full and the external interrupt is active, a
subroutine call to location 04H will occur. The interrupt
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F;bit 5 of INTC), caused by a timer 0
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further in-
terrupts.
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
to set the enable/disable and the interrupt request flags.
The internal Timer/Event Counter 1 interrupt is initial-
ized by setting the Timer/Event Counter 1 interrupt re-
quest flag (T1F;bit 6 of INTC), caused by a timer 1
overflow. When the interrupt is enabled, the stack is not
full and the T1F is set, a subroutine call to location 0CH
will occur. The related interrupt request flag (T1F) will be
reset and the EMI bit cleared to disable further inter-
rupts.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
Labels
Bits
Function
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
C
0
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
AC
Z
1
2
3
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
OV
PD is cleared by system power-up or executing the ²CLR WDT² instruction. PD is set by exe-
cuting the ²HALT² instruction.
PD
4
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
TO
5
6~7
¾
Undefined, read as ²0²
Status register
Rev. 1.40
7
July 16, 2003
HT48CA3
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the ²RETI² in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an in-
terrupt service, but RET will not.
Oscillator Configuration
There are 2 oscillator circuits in the MCU.
O
S
C
1
O
S
C
1
S
Y
S
O
S
C
2
O
S
C
2
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
N
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R
C
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o
r
System oscillator
There are 2 oscillator circuits implemented in the mi-
cro-controller.
Interrupt Source
External Interrupt
Priority Vector
Both of them are designed for system clocks, namely
the RC oscillator and the crystal oscillator, which are de-
termined by options. No matter what oscillator type is
selected, the signal provides the system clock. The
HALT mode stops the system oscillator and resists the
external signal to conserve power.
1
2
3
04H
08H
0CH
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), external interrupt request flag (EIF), enable
Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), en-
able external interrupt bit (EEI) and enable master inter-
rupt bit (EMI) constitute an interrupt control register
(INTC) which is located at 0BH in the data memory. EMI,
EEI, ET0I and ET1I are used to control the enabling/dis-
abling of interrupts. These bits prevent the requested in-
terrupt from being serviced. Once the interrupt request
flags (T0F, T1F, EIF) are set, they will remain in the INTC
register until the interrupts are serviced or cleared by a
software instruction.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance should
range from 100kW to 820kW. The system clock, divided
by 4, is available on OSC2, which can be used to syn-
chronize external logic. The internal RC oscillator pro-
vides the most cost effective solution. However, the
frequency of oscillation may vary with VDD, tempera-
tures and the chip itself due to process variations. It is,
therefore, not suitable for timing sensitive operations
where an accurate oscillator frequency is desired.
If the crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are demanded. Instead of a crystal, the
resonator can also be connected between OSC1 and
OSC2 to get a frequency reference, but two external ca-
pacitors in OSC1 and OSC2 are required.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. In-
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the ²CALL² operates in the interrupt subrou-
tine.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
Register
Bit No.
Label
EMI
EEI
Function
0
1
2
3
4
5
6
7
Controls the master (global) interrupt (1=enabled; 0=disabled)
Controls the external interrupt (1=enabled; 0=disabled)
Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
External interrupt request flag (1= active; 0= inactive)
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
Unused bit, read as ²0²
ET0I
ET1I
EIF
INTC
(0BH)
T0F
T1F
¾
INTC register
Rev. 1.40
8
July 16, 2003
HT48CA3
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit ²TO². But in the HALT
mode, the overflow will initialize a ²warm reset² and only
the PC and SP are reset to zero. To clear the contents of
WDT (including the WDT prescaler), three methods are
adopted; external reset (a low level to RES), software in-
struction and a ²HALT² instruction. The software instruc-
tion include ²CLR WDT² and the other set - ²CLR
WDT1² and ²CLR WDT2². Of these two types of instruc-
tion, only one can be active depending on the ROM
code option - ²CLR WDT times selection option². If the
²CLR WDT² is selected (i.e. CLR WDT times equal
one), any execution of the ²CLR WDT² instruction will
clear the WDT. In the case that ²CLR WDT1² and ²CLR
WDT2² are chosen (i.e. CLR WDT times equal two),
these two instructions must be executed to clear the
WDT; otherwise, the WDT may reset the chip as a result
of time-out.
period of approximately 90ms. The WDT oscillator can
be disabled by ROM code option to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), instruction clock (system
clock divided by 4), determines the ROM code option.
This timer is designed to prevent a software malfunction
or sequence from jumping to an unknown location with
unpredictable results. The Watchdog Timer can be dis-
abled by ROM code option. If the Watchdog Timer is dis-
abled, all the executions related to the WDT result in no
operation.
Once the internal WDT oscillator (RC oscillator with a
period of 90ms@3V normally) is selected, it is first di-
vided by 256 (8-stage) to get the nominal time-out pe-
riod of 23ms@3V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.9s/3V
seconds. If the WDT oscillator is disabled, the WDT
clock may still come from the instruction clock and oper-
ates in the same manner except that in the HALT state
the WDT may stop counting and lose its protecting pur-
pose. In this situation the logic can only be restarted by
external logic. The high nibble and bit 3 of the WDTS are
reserved for user¢s defined flags, which can be used to
indicate some specified status.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
·
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
·
·
The contents of the on chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
·
·
All of the I/O ports maintain their original status.
The PD flag is set and the TO flag is cleared.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². After the TO and PD flags are ex-
amined, the reason for chip reset can be determined.
The PD flag is cleared by system power-up or executing
the ²CLR WDT² instruction and is set when executing
the ²HALT² instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the PC and SP; the others remain in their original status.
WS2
WS1
WS0
Division Ratio
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
WDTS register
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4
W
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8
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7
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8
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M
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X
W
S
0
~
W
S
2
W
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Watchdog Timer
9
Rev. 1.40
July 16, 2003
HT48CA3
in port A can be independently selected to wake up the
device by mask option. Awakening from an I/O port
stimulus, the program will resume execution of the next
instruction. If it awakens from an interrupt, two se-
quence may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
will resume execution at the next instruction. If the inter-
rupt is enabled and the stack is not full, the regular inter-
rupt response takes place. If an interrupt request flag is
set to ²1² before entering the HALT mode, the wake-up
function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
The functional unit chip reset status are shown below.
PC
000H
Interrupt
Prescaler
Disable
Clear
Clear. After master reset,
WDT begins counting
WDT
Timer/Event Counter Off
Input/output Ports
SP
Input mode
Points to the top of the stack
V
D
D
R
E
S
t
S S T
S
S
T
T
i
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-
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t
C
h
i
p
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s
e
t
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset timing chart
Reset
Therearethreewaysinwhicharesetcanoccur:
V
D
D
·
·
·
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
R
E
S
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the PC and SP, leaving the other cir-
cuits in their original state. Some registers remain un-
changed during other reset conditions. Most registers
are reset to the ²initial condition² when the reset condi-
tions are met. By examining the PD and TO flags, the
program can distinguish between different ²chip resets².
Reset circuit
H
A
L
T
W
a
r
m
R
e
s
e
t
W
D
T
TO PD
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
0
u
0
1
1
0
u
1
u
1
R
E
S
C
o
l
d
R
e
s
e
t
S
S
T
1
0
-
b
i
t
R
i
p
p
l
e
O
S
C
1
C
o
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t
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r
WDT time-out during normal operation
WDT wake-up HALT
S
y
s
t
e
m
R
e
s
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t
Note: ²u² stands for unchanged
Reset configuration
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
Rev. 1.40
10
July 16, 2003
HT48CA3
The states of the registers is summarized in the table.
Reset
WDT Time-out
RES Reset
RES Reset
(HALT)
WDT Time-out
(HALT)*
Register
(Power On)
(Normal Operation)
(Normal Operation)
MP0
MP1
BP
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
Program
Counter
0000H
0000H
0000H
0000H
0000H
TBLP
TBLH
WDTS
STATUS
INTC
TMR0
TMR0C
TMR1H
TMR1L
TMR1C
PA
xxxx xxxx
--xx xxxx
0000 0111
--00 xxxx
--00 -000
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
uuuu uuuu
--uu uuuu
0000 0111
--1u uuuu
--00 -000
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
uuuu uuuu
--uu uuuu
0000 0111
--uu uuuu
--00 -000
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
uuuu uuuu
--uu uuuu
0000 0111
--01 uuuu
--00 -000
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
uuuu uuuu
--uu uuuu
uuuu uuuu
--11 uuuu
--uu -uuu
uuuu uuuu
uu-u uuuu
uuuu uuuu
uuuu uuuu
uu-u u---
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
--11 1111
---- ---1
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
--11 1111
---- ---1
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
--11 1111
---- ---1
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
--11 1111
---- ---1
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
---- ---u
PAC
PB
PBC
PC
PCC
PF
PFC
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.40
11
July 16, 2003
HT48CA3
Timer/Event Counter
register and issues the interrupt request just like the
other two modes.
Two timer/event counters are implemented in the de-
vice. The Timer/Event Counter 0 contains an 8-bit pro-
grammable count-up counter and the clock may come
from an external source or the system clock. The
Timer/Event Counter 1 contains an 16-bit programma-
ble count-up counter and the clock may come from an
external source or the system clock divided by 4.
To enable the counting operation, the timer ON bit (TON;
bit 4 of TMR0C) should be set to 1. In the pulse width
measurement mode, the TON will be cleared automati-
cally after the measurement cycle is complete. But in the
other two modes the TON can only be reset by instruc-
tions. The overflow of the Timer/Event Counter 0 is one
of the wake-up sources. No matter what the operation
mode is, writing a 0 to ET0I can disabled the corre-
sponding interrupt service.
Of the two timer/event counters, using external clock in-
put allows the user to count external events, measure
time internals or pulse widths, or generate an accurate
time base. While using the internal clock allows the user
to generate an accurate time base.
In the case of Timer/Event Counter 0 Off condition, writ-
ing data to the Timer/Event Counter 0 preload register
will also load the data to Timer/Event Counter 0. But if
the Timer/Event Counter 0 is turned On, data written to
the Timer/Event Counter 0 will only be kept in the
Timer/Event Counter 0 preload register. The
Timer/Event Counter 0 will still operate until the overflow
occurs (a Timer/Event Counter 0 reloading will occur at
the same time).
Only the Timer/Event Counter 0 can generate PFD sig-
nal by using external or internal clock, and PFD fre-
quency is determine by the equation fINT/[2´(256-N)].
There are 2 registers related to Timer/Event Counter 0;
TMR0(0DH), TMR0C(0EH). In Timer/Event Counter 0
counting mode (TON=1), writing TMR0 will only put the
written data to preload register (8 bits). The Timer/Event
Counter 0 preload register is changed by each writing
TMR0 operations. Reading TMR0 will also latch the
TMR0 to the destination. The TMR0C is the Timer/Event
Counter 0 control register, which defines the operating
mode, counting enable or disable and active edge.
When the Timer/Event Counter 0 (reading TMR0) is
read, the clock will be blocked to avoid errors. As this
may results in a counting error, this must be taken into
consideration by the programmer.
The bit 0~2 of the TMR0C can be used to define the
pre-scaling stages of the internal clock sources of
Timer/Event Counter 0. The definitions are as shown.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR0) pin. The timer mode functions as a normal timer
with the clock source coming from the fINT clock. The
pulse width measurement mode can be used to count
the high or low level duration of the external signal
(TMR0). The counting is based on the fINT clock.
Label
Bits
Function
(TMR0C)
To define the prescaler stages,
PSC2, PSC1, PSC0=
000: fINT=fSYS/2
001: fINT=fSYS/4
PSC0~
PSC2
010: fINT=fSYS/8
In the event count or timer mode, once the Timer/Event
Counter 0 starts counting, it will count from the current
contents in the Timer/Event Counter 0 to FFH. Once
overflow occurs, the counter is reloaded from the
Timer/Event Counter 0 preload register and generates
the corresponding interrupt request flag (T0F; bit 5 of
INTC) at the same time.
0~2
011: fINT=fSYS/16
100: fINT=fSYS/32
101: fINT=fSYS/64
110: fINT=fSYS/128
111: fINT=fSYS/256
To define the TMR0 active edge of
Timer/Event Counter 0
TE
3
In pulse width measurement mode with the TON and TE
bits are equal to one, once the TMR0 has received a
transition from low to high (or high to low if the TE bit is 0)
it will start counting until the TMR0 returns to the original
level and reset the TON. The measured result will re-
main in the Timer/Event Counter 0 even if the activated
transition occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it re-
ceives further transition pulse. Note that, in this operat-
ing mode, the Timer/Event Counter 0 starts counting not
according to the logic level but according to the transi-
tion edges. In the case of counter overflows, the counter
0 is reloaded from the Timer/Event Counter 0 preload
(0=active on low to high;
1=active on high to low)
To enable/disable timer 0 counting
(0=disabled; 1=enabled)
TON
4
5
¾
Unused bit, read as ²0²
To define the operating mode
01=Event count mode (external
clock)
TM0
TM1
6
7
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C register
Rev. 1.40
12
July 16, 2003
HT48CA3
There are 3 registers related to Timer/Event Counter 1;
TMR1H(0FH), TMR1L(10H), TMR1C(11H). Writing
TMR1L will only put the written data to an internal
lower-order byte buffer (8 bits) and writing TMR1H will
transfer the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L preload
registers, respectively. The Timer/Event Counter 1
preload register is changed by each writing TMR1H op-
erations. Reading TMR1H will latch the contents of
TMR1H and TMR1L counters to the destination and the
lower-order byte buffer, respectively. Reading the
TMR1L will read the contents of the lower-order byte
buffer. The TMR1C is the Timer/Event Counter 1 control
register, which defines the operating mode, counting en-
able or disable and active edge.
In pulse width measurement mode with the TON and TE
bits are equal to one, once the TMR1 has received a
transition from low to high (or high to low if the TE bit is 0)
it will start counting until the TMR1 returns to the original
level and reset the TON. The measured result will re-
main in the Timer/Event Counter 1 even if the activated
transition occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it re-
ceives further transition pulse. Note that, in this operat-
ing mode, the Timer/Event Counter 1 starts counting not
according to the logic level but according to the transi-
tion edges. In the case of counter overflows, the counter
1 is reloaded from the Timer/Event Counter 1 preload
register and issues the interrupt request just like the
other two modes.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR1) pin. The timer mode functions as a normal timer
with the clock source coming from the instruction clock.
The pulse width measurement mode can be used to
count the high or low level duration of the external signal
(TMR1). The counting is based on the instruction clock.
To enable the counting operation, the timer ON bit (TON;
bit 4 of TMR1C) should be set to 1. In the pulse width
measurement mode, the TON will be cleared automati-
cally after the measurement cycle is complete. But in the
other two modes the TON can only be reset by instruc-
tions. The overflow of the Timer/Event Counter 1 is one
of the wake-up sources. No matter what the operation
mode is, writing a 0 to ET1I can disabled the corre-
sponding interrupt service.
In the event count or timer mode, once the Timer/Event
Counter 1 starts counting, it will count from the current
contents in the Timer/Event Counter 1 to FFFFH. Once
overflow occurs, the counter is reloaded from the
Timer/Event Counter 1 preload register and generates
the corresponding interrupt request flag (T1F;bit 6 of
INTC) at the same time.
In the case of Timer/Event Counter 1 OFF condition,
writing data to the Timer/Event Counter 1 preload regis-
ter will also load the data to Timer/Event Counter 1. But
if the Timer/Event Counter 1 is turned on, data written to
the Timer/Event Counter 1 will only be kept in the
(
1
/
2
~
1
/
2
5
6
)
8
-
s
t
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e
P
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T
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P
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P
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8
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b
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e
a
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m
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t
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i
m
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T
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M
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t
r
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l
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r
f
l
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w
t
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t
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r
r
u
p
t
(
T
M
R
0
)
T
O
N
¸
2
P
F
D
Timer/Event Counter 0
D
a
t
a
B
u
s
T
T
M
M
1
0
f
S
Y
S
/
4
1
6
-
b
i
t
L
o
w
B
y
t
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T
i
m
e
r
/
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v
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t
C
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t
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r
T
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B
u
f
f
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P
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g
i
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t
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r
R
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1
6
-
b
i
t
P
u
l
s
e
W
i
d
t
h
T
i
m
e
r
/
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v
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t
C
o
u
n
t
e
r
T
M
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M
e
a
s
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r
e
m
e
n
t
O
v
e
r
f
l
o
w
(
T
M
R
1
H
/
T
M
R
1
L
)
T
M
0
M
o
d
e
C
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n
t
r
o
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r
r
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p
t
T
O
N
Timer/Event Counter 1
13
Rev. 1.40
July 16, 2003
HT48CA3
Timer/Event Counter 1 preload register. The
Timer/Event Counter 1 will still operate until the overflow
occurs (a Timer/Event Counter 1 reloading will occur at
the same time).
structions). The input paths (pad state or latches) of
read-modify-write instructions are dependent on the
control register bits. For output function, CMOS is the
only configuration. These control registers are mapped
to locations 13H, 15H, 17H and 1DH.
When the Timer/Event Counter 1 (reading TMR1H) is
read, the clock will be blocked to avoid errors. As this
may results in a counting error, this must be taken into
consideration by the programmer.
After a chip reset, these input/output lines stay at high
levels (pull-high options) or floating state (non-pull-high
options). Each bit of these input/output latches can be
set or cleared by ²SET [m].i² (m = 12H, 14H, 16H or
1CH) instructions. Some instructions first input data and
then follow the output operations. For example, ²SET
[m].i², ²CLR [m].i², ²CPLA [m]² read the entire port
states into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
The definitions of the TMR1C are as shown.
Label
Bits
Function
(TMR1C)
0~2
¾
Unused bit, read as ²0²
To define the active edge of TMR1
pin input signal
TE
3
(0/1: active on low to high/high to low)
Each line of port A has the capability of waking-up the
device. The highest 2 bits of port C and 7 bits of port F
are not physically implemented; on reading them a ²0² is
returned whereas writing then results in a no-operation.
Pull-high resistors of each port are decided by a option
bit.
To enable/disable timer 1 counting
(0/1: disabled/enabled)
TON
4
5
¾
Unused bit, read as ²0²
To define the operating mode
01=Event count mode (external
clock)
TM0
TM1
6
7
The PB0 is pin-shared with PFD signal, respectively. If
the PFD option is selected, the output signal in output
mode of PB0 will be the PFD signal. The input mode al-
ways remain its original functions. The PF0 and PC0 are
pin-shared with INT and TMR 0. The INT signal is di-
rectly connected to PF0. The PFD output signal (in out-
put mode) are controlled by the PB0 data register only.
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C register
Input/Output Ports
There are 23 bi-directional input/output lines in the mi-
cro-controller, labeled from PA to PC and PF, which are
mapped to the data memory of [12H], [14H], [16H] and
[1CH], respectively. All of these I/O ports can be used as
input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready
at the T2 rising edge of instruction ²MOV A,[m]² (m =
12H, 14H, 16H or 1CH). For output operation, all the
data is latched and remains unchanged until the output
latch is rewritten.
The truth table of PB0/PFD is listed below.
PBC (15H) Bit0
PB0/PFD Option
PB0 (14H) Bit0
PB0 Pad Status
I
x
x
I
O
PB0
D
O
PFD
0
O
PFD
1
D
0
PFD
Note: I: Input; O: Output; D: Data
Bank Pointer
Each I/O line has its own control register (PAC, PBC,
PCC, PFC) to control the input/output configuration.
With this control register, CMOS output or Schmitt trig-
ger input with or without (depends on options) pull-high
resistor structures can be reconfigured dynamically (i.e.,
on-the fly) under software control. To function as an in-
put, the corresponding latch of the control register has to
be set as ²1². The pull-high resistor (if the pull-high re-
sistor is enabled) will be exhibited automatically. The in-
put sources also depends on the control register. If the
control register bit is ²1², the input will read the pad state
(²mov² and read-modify-write instructions”). If the con-
trol register bit is 0, the contents of the latches will move
to internal data bus (²mov² and read-modify-write in-
There is a bank pointer used to control the program flow
to go to any banks. A bank contains 8K´16 address
space. The contents of bank pointer are load into pro-
gram counter when the JMP or CALL instruction is exe-
cuted. The program counter is a 15-bit register whose
contents are used to specify the executed instruction
addresses.
When calling a subroutine or an interrupt event occur-
ring, the contents of the program counter are save into
stack registers. If a returning from subroutine occurs,
the contents of the program counter will restore from
stack registers.
Rev. 1.40
14
July 16, 2003
HT48CA3
V
D
D
C
o
n
t
r
o
l
B
i
t
P
U
D
a
t
a
B
u
s
D
C
Q
K
Q
B
W
r
i
t
e
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
S
C
h
i
p
R
e
s
e
t
P
A
0
~
P
A
7
P
B
0
1
/
~
P
F
D
P
B
P
B
7
R
e
a
d
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
P
P
C
F
0
~
P
C
5
D
a
t
a
B
i
t
0
D
C
Q
K
Q
B
W
r
i
t
e
D
a
t
a
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e
g
i
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t
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r
S
M
U
P
B
0
(
P
B
0
O
n
l
y
)
X
P
F
D
P
F
D
E
N
M
(
P
B
0
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)
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a
d
D
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r
S
y
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t
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m
W
a
k
e
-
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p
O
P
0
~
O
P
7
(
P
A
o
n
l
y
)
I
N
T
f
o
r
P
F
0
O
n
l
y
P
F
D
f
o
r
P
B
0
o
n
l
y
,
c
o
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t
r
o
l
=
P
B
0
d
a
t
a
r
e
g
i
s
t
e
r
Input/output ports
Options
The following table shows all kinds of mask option in the MCU. All of the mask options must be defined to ensure proper
system functioning.
Function
PA0~PA7 wake-up enable or disable
PC pull-high enable or disable
PA pull-high enable or disable: Byte option
PF pull-high enable or disable
PB pull-high (PB0~PB3, PB4~PB7) enable or disable: Nibble option
PB0 or PFD
CLR WDT instructions
System oscillators: RC or crystal
WDT enable or disable
WDT clock source: WDTOSC or system clock/4 (T1D)
Rev. 1.40
15
July 16, 2003
HT48CA3
Application Circuits
RC Oscillator for Multiple I/O Applications
Crystal or Ceramic Resonator for Multiple I/O
Applications
V
D
D
V
D D
V
O
D
D
P
P
A
B
0
1
~
~
P
P
A
B
7
7
V
D
D
P
P
A
B
0
1
~
~
P
P
A
B
7
7
S
C
1
1
0
0
k
1
0
0
k
C
*
R
*
P
C
1
~
P
C
4
P
C
1
~
P
C
4
O
O
S
S
C
C
1
2
P
C
5
/
T
M
R
1
P
C
5
/
T
M
R
1
X
'
t
a
l
R
O
S
C
(
s
e
e
N
o
t
e
)
0
.
1
m
F
m
0 . 1 F
C
*
P
B
0
/
P
F
D
P
B
0
/
P
F
D
O
S
C
2
N
M
O
S
0
.
1
m
F
m
0 . 1 F
o
p
e
n
d
r
a
i
n
R
E
S
R
E
S
V
I
S
S
V
S
S
N
T
/
P
F
0
I
T
N
T
/
P
F
0
T
M
R
0
/
P
C
0
M
R
0
/
P
C
0
H
T
4
8
C
A
3
H
T
4
8
C
A
3
V
D
D
P
A
0
V
D
D
C
*
R
*
P
A
1
O
S
S
C
C
1
2
1
W
4
m
7 F
X
'
t
a
l
P
A
2
(
s
e
e
N
o
t
e
)
P
A
3
O
V
P
A
4
C
*
S
S
P
A
5
R
E
S
P
A
6
P
A
7
1
2
0
P
B
2
P
B
0
/
P
F
D
P
B
3
P
B
4
P
(
F
0
/
I
N
T
P
B
5
L
e
a
r
n
i
n
g
I
n
p
u
t
)
R
e
c
e
i
v
e
r
P
P
B
B
6
7
P
C
2
P
C
3
E
E
P
R
O
M
P
C
0
/
T
M
R
C
0
P
P
C
C
4
5
P
1
/
T
M
R
1
H
T
4
8
C
A
3
Note: The resistance and capacitance for reset circuit should be designed to ensure that the VDD is stable and re-
mains in a valid range of the operating voltage before bringing RES to high.
The following table shows the R* and C* value according different crystal values.
Crystal or Resonator
4MHz Crystal
C*
R*
0pF
10kW
12kW
12kW
10kW
10kW
10kW
27kW
10kW
10kW
9.1kW
4MHz Resonator (3 pin)
4MHz Resonator (2 pin)
3.58MHz Crystal
0pF
10pF
0pF
3.58MHz Resonator (2 pin)
2MHz Crystal & Resonator (2 pin)
1MHz Crystal
25pF
25pF
35pF
300pF
300pF
300pF
429kHz Resonator
455kHz Resonator
480kHz Resonator
Rev. 1.40
16
July 16, 2003
HT48CA3
Instruction Set Summary
Instruction
Cycle
Flag
Mnemonic
Arithmetic
Description
Affected
ADD A,[m]
ADDM A,[m]
ADD A,x
Add data memory to ACC
1
1(1)
1
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
Add ACC to data memory
Add immediate data to ACC
ADC A,[m]
ADCM A,[m]
SUB A,x
Add data memory to ACC with carry
1
1(1)
Add ACC to data memory with carry
Subtract immediate data from ACC
1
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Subtract data memory from ACC
1
1(1)
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1(1)
Logic Operation
AND A,[m]
OR A,[m]
AND data memory to ACC
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
OR data memory to ACC
XOR A,[m]
ANDM A,[m]
ORM A,[m]
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
1
1(1)
1(1)
1(1)
1
XORM A,[m] Exclusive-OR ACC to data memory
AND A,x
OR A,x
AND immediate data to ACC
OR immediate data to ACC
1
XOR A,x
CPL [m]
CPLA [m]
Exclusive-OR immediate data to ACC
Complement data memory
1
1(1)
Complement data memory with result in ACC
1
Increment & Decrement
INCA [m]
INC [m]
Increment data memory with result in ACC
1
Z
Z
Z
Z
Increment data memory
1(1)
DECA [m]
DEC [m]
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
Rotate
RRA [m]
RR [m]
Rotate data memory right with result in ACC
Rotate data memory right
1
1(1)
1
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
1(1)
C
1
None
None
C
1(1)
1
RLCA [m]
RLC [m]
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1(1)
C
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Rev. 1.40
17
July 16, 2003
HT48CA3
Instruction
Cycle
Flag
Mnemonic
Branch
Description
Affected
JMP addr
SZ [m]
Jump unconditionally
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Skip if data memory is zero
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
Return from subroutine
2
RET A,x
RETI
Return from subroutine and load immediate data to ACC
Return from interrupt
2
2
Table Read
TABRDC [m] Read ROM code (current page) to data memory and TBLH
TABRDL [m] Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
Miscellaneous
NOP
No operation
1
1(1)
1(1)
1
None
None
CLR [m]
Clear data memory
SET [m]
Set data memory
None
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Clear Watchdog Timer
TO,PD
TO(4),PD(4)
TO(4),PD(4)
None
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1
1(1)
1
None
1
TO,PD
Note: x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1): If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2): If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3)
:
(1) and (2)
(4): The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared.
Otherwise the TO and PD flags remain unchanged.
Rev. 1.40
18
July 16, 2003
HT48CA3
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
Rev. 1.40
19
July 16, 2003
HT48CA3
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND op-
eration. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND op-
eration. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
Operation
The contents of the specified data memory are cleared to 0.
[m] ¬ 00H
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Rev. 1.40
20
July 16, 2003
HT48CA3
CLR [m].i
Clear bit of data memory
Description
Operation
The bit i of the specified data memory is cleared to 0.
[m].i ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PD and TO ¬ 0
Affected flag(s)
TC2
TC1
TO
0
PD
0
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of
this instruction without the other preclear instruction just sets the indicated flag which im-
plies this instruction has been executed and the TO and PD flags remain unchanged.
Operation
WDT ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
0*
PD
0*
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of
this instruction without the other preclear instruction, sets the indicated flag which implies
this instruction has been executed and the TO and PD flags remain unchanged.
Operation
WDT ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
0*
PD
0*
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
Rev. 1.40
21
July 16, 2003
HT48CA3
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-
lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-
justment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Operation
Data in the specified data memory is decremented by 1.
[m] ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
Rev. 1.40
22
July 16, 2003
HT48CA3
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PD) is set and the WDT time-out bit (TO) is cleared.
Operation
PC ¬ PC+1
PD ¬ 1
TO ¬ 0
Affected flag(s)
TC2
TC1
TO
0
PD
1
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Operation
Data in the specified data memory is incremented by 1
[m] ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
PC ¬addr
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV A,[m]
Description
Operation
Move data memory to the accumulator
The contents of the specified data memory are copied to the accumulator.
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Rev. 1.40
23
July 16, 2003
HT48CA3
MOV A,x
Move immediate data to the accumulator
The 8-bit data specified by the code is loaded into the accumulator.
ACC ¬ x
Description
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
Operation
Affected flag(s)
No operation is performed. Execution continues with the next instruction.
PC ¬ PC+1
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) per-
form a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
Rev. 1.40
24
July 16, 2003
HT48CA3
RET
Return from subroutine
Description
Operation
Affected flag(s)
The program counter is restored from the stack. This is a 2-cycle instruction.
PC ¬ Stack
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the speci-
fied 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
Operation
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Rev. 1.40
25
July 16, 2003
HT48CA3
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-
places the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
Operation
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
Rev. 1.40
26
July 16, 2003
HT48CA3
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-
cles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Rev. 1.40
27
July 16, 2003
HT48CA3
SET [m]
Set data memory
Description
Operation
Each bit of the specified data memory is set to 1.
[m] ¬ FFH
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Operation
Bit i of the specified data memory is set to 1.
[m].i ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the fol-
lowing instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory re-
mains unchanged. If the result is 0, the following instruction, fetched during the current in-
struction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-
wise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Rev. 1.40
28
July 16, 2003
HT48CA3
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumula-
tor, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memo-
ries) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writ-
ing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Rev. 1.40
29
July 16, 2003
HT48CA3
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Rev. 1.40
30
July 16, 2003
HT48CA3
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-
sive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-
sive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-
eration. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
Rev. 1.40
31
July 16, 2003
HT48CA3
Package Information
28-pin SKDIP (300mil) Outline Dimensions
A
2
8
1
1
5
4
B
1
H
C
D
I
a
E
F
G
Dimensions in mil
Symbol
Min.
1375
278
125
125
16
Nom.
¾
Max.
A
B
C
D
E
F
G
H
I
1395
298
135
145
20
¾
¾
¾
¾
50
70
¾
100
¾
¾
295
330
0°
315
375
15°
¾
¾
¾
a
Rev. 1.40
32
July 16, 2003
HT48CA3
28-pin SOP (300mil) Outline Dimensions
2
8
1
5
A
B
1
1
4
C
C
'
G
H
D
a
E
F
Dimensions in mil
Symbol
Min.
394
290
14
697
92
¾
Nom.
¾
Max.
A
B
C
C¢
D
E
F
419
300
20
¾
¾
713
104
¾
¾
¾
50
4
¾
¾
¾
¾
¾
G
H
a
32
4
38
12
0°
10°
Rev. 1.40
33
July 16, 2003
HT48CA3
Product Tape and Reel Specifications
Reel Dimensions
D
T
2
C
A
B
T
1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
330±1.0
A
B
Reel Outer Diameter
Reel Inner Diameter
62±1.5
13.0+0.5
-0.2
C
D
Spindle Hole Diameter
Key Slit Width
2.0±0.5
24.8+0.3
-0.2
T1
T2
Space Between Flange
Reel Thickness
30.2±0.2
Rev. 1.40
34
July 16, 2003
HT48CA3
Carrier Tape Dimensions
P
0
P
1
t
D
E
F
W
B
0
C
D
1
P
K
0
A
0
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
24.0±0.3
12.0±0.1
1.75±0.1
11.5±0.1
1.5+0.1
W
P
Carrier Tape Width
Cavity Pitch
E
Perforation Position
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
D
D1
P0
P1
A0
B0
K0
t
1.5+0.25
4.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
2.0±0.1
10.85±0.1
18.34±0.1
2.97±0.1
0.35±0.01
21.3
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
Rev. 1.40
35
July 16, 2003
HT48CA3
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Sales Office)
11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Shanghai) Inc.
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor (Hong Kong) Ltd.
Block A, 3/F, Tin On Industrial Building, 777-779 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Holmate Semiconductor, Inc.
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2003 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.40
36
July 16, 2003
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