G569CS8U [GMT]
CD-RW Laser Diode Current Driver; CD - RW激光二极管电流驱动器
| 型号： | G569CS8U |
| 厂家： | 
GLOBAL MIXED-MODE TECHNOLOGY INC |
| 描述： | CD-RW Laser Diode Current Driver |
| 文件： | 总11页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Global Mixed-mode Technology Inc.
CD-RW Laser Diode Current Driver
General Description
G569C
Features
Single +5V supply
The G569C is a single chip solution for the various
functions relating to laser diode operation in a CD-RW
drive. The G569C integrates nine functional blocks in
one chip. It has five voltage-to-current converters, one
current-to-voltage converters which is called FSA, one
OP-AMP, one eight-channels D/A converter, and one
voltage subtracter with output clamping capability
called Dalpha.
Laser diode read current driver
Laser diode write current driver
Laser diode Erase current driver
Deltap circuit to control write current
FSA circuit to integrate photo diode current
Cagain circuit to convert Vcagain into current
Dalpha circuit to perform voltage subtraction
and limiting
Three of the five V-to-I converters provide the laser
diode currents for Read, Write, and Erase operations,
respectively; another one of the V-I converters
provides the Cagain current; and the other one
provides Deltap current which can selectively shunt a
certain amount of laser diode current for write
operation. For the Write and Erase operations, the
voltage to current conversion ratio can be adjusted
using an external or internal DAC resistor array. The
FSA circuit performs integration on the output current
of an external photo diode, and sample-and-hold the
peak voltage. It is used to monitor the laser diode
power. The internal eight-channel D/A converter is
used to provide the input voltage for above functional
blocks. The G569C is available in a 48-pin SSOP
surface-mount package.
3-wire interface to control internal DAC
A build-in OP-AMP
48-pin SSOP package
Applications
CD-RW Drive
Pin configuration
Ordering Information
G569C
TEMP.
RANGE
ORDER ORDER NUMBER
PACKAGE
NUMBER
(Pb free)
IW_IN
LS_DELTA
TST1
1
2
3
48
47
46
WDB
LS_WRITE
PWRITE
LD
G569CS8U
G569CS8Uf
0°C to 85°C SSOP-48
Note: S8: SSOP-48
U: Tape & Reel
PWO
DALPHA
PWO_I
4
5
6
7
45
44
43
42
41
DI
CLK
PWB
PWMAX
PWMIN
/RESET
VSS
8
9
VOUT
40 VI-
10
39
38
37
36
35
VI+
VSS 11
VDD
FSOF
FSWS
EDB
LS_ERASE
PERASE
12
13
14
15
16
FSCLR
FSW
34
33
32
31
30
29
RECORD
CDR
IFSA
17
18
19
20
21
S2V9
FSR
CAGAIN2
CAGS_I
DCAGAIN
CAGAIN
FSRS
VDD
SELN4_IN
28 PR_I
RCAGAIN1 22
27
26
25
LS_READ
IR
23
RCAGAIN2
24
PRCOARSE
PRFINE
SSOP-48
TEL: 886-3-5788833
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Ver: 1.0
Oct 02, 2000
1
Global Mixed-mode Technology Inc.
G569C
derate .7mW/°C about 70°C)…………….……… 695mW
Operating Temperature Range…….…-10°C to +100°C
Junction Temperature……………………...…….+150°C
Storage temperature Range…….…….-65°C to +165°C
Reflow Temperature (soldering, 10sec)………..+260°C
Absolute Maximum Ratings
VCC to GND…………………………….……..-0.3V to +6V
Dalpha to GND………………………………....-3V to +6V
All other pin to GND…………………………-0.3V to +6V
ESD protetion (human body model)………………2000V
Continuous power dissipation (TA=70°C),
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Recommended Operating Conditions
PARAMETER
Supply voltage
SYMBOL
MIN
4.75
2
TYP
MAX
UNITS
VDD
VIH
VIL
TA
5
5.5
V
V
High-level input voltage
Low-level input voltage
0.8
70
V
Operating free-air temperature
0
°C
Electrical Characteristics (VCC = 5V, TA = 0°C to +70°C, unless otherwise noted)
PARAMETER
Supply voltage range
CONDITIONS
MIN
4.75
0
TYP
MAX
5.5
UNITS
5.0
V
V
PWO output voltage
Dalpha input voltage
PWO_I input voltage
PWB output voltage
PWMAX output voltage
PWMIN output voltage
IE output current
VS2V9
3.5
-3.0
0
V
1.5
V
0
VS2V9
VS2V9
VS2V9
130
V
0
V
0
V
0
mA
V
S2V9 input voltage
VS2V9
2.9
Cagain output current
PRFine output voltage
PRCoarse output voltage
IR output current
0
0
0
0
0
0
0
0
0
0
1.2
VS2V9
VS2V9
160
2.16
3.0
mA
V
V
mA
V
PR_I input voltage
FSR output voltage
FSW output voltage
VI- input voltage
V
3.0
V
3.5
V
VI+ input voltage
3.5
V
IW output current
160
mA
mA
Operation current
41
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Ver: 1.0
Oct 02, 2000
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Global Mixed-mode Technology Inc.
G569C
Pin Description
PIN NO. PIN NAME I/O
PIN FUNCTION
A diode of type BAS216 should be connected between this pin and node IW. This pin provides
the path for sinking IW current.
1
IW_IN
I
2
3
LS_DELTA
TST1
O
I
Connect a 10Ω resistor from this pin to VSS
Test pin. Connect to ground for normal operation.
DAC output, connect to PWO_I through a resistor divider
Control voltage input
4
PWO
O
I
5
DALPHA
PWO_I
PWB
6
I
Control voltage input
7
O
O
O
I
Voltage output
8
PWMAX
PWMIN
/RESET
VSS
Voltage output
9
Voltage output
10
11,42
12
13
14
15
16
17
Logic input. A Low on this pin reset all DAC latches to 0.
Ground pin
I
EDB
O
I
Connect to the base node of external PNP BJT (Type BC808).
Connect a 6.8Ω (1206 type) resistor from this pin to VDD
Connect a DAC resistor array from this pin to VSS
Logic input, a high indicates in recording mode.
Logic input, a high indicates in CD-R mode.
Voltage input. Contribute to current output on CAGAIN pin and provides internal DAC reference
voltage.
LS_ERASE
PERASE
RECORD
CDR
O
I
I
S2V9
I
18
19
20
21
22
23
24
25
26
27
28
29
CAGAIN2
CAGS_I
O
I
Tristate output. Connect 62KΩ to pin CAGAIN.
Logic input, 0~2V swing.
DCAGAIN
CAGAIN
RCAGAIN1
RCAGAIN2
PRFINE
O
O
O
O
O
O
O
I
An optional resistor may be added to modify the output current on CAGAIN
Current output
A 16.2KΩ resistor should be connected from this pin to VSS
A 3.9KΩ resistor should be connected from this pin to VSS
DAC output, connect to PR_I through a resistor divider
DAC output, connect to PR_I through a resistor divider
Read current output for laser diode
PRCOARSE
IR
LS_READ
PR_I
Connect two 22Ω (1206 type) resistors from this pin to VDD
Voltage input which controls the current on IR pin
Logic input. This pin can be shorted to pin CDR or be connected to the voltage divider formed by
CDR and SELN4.
I
SELN4_IN
I
30,38
31
VDD
I
I
Supply voltage input. Each VDD pin should have a 0.1µF bypass capacitor to VSS.
Logic input, when FSRS=1, the voltage on pin FSCLR is sampled onto pin FSR, else FSR is in hold
mode.
FSRS
32
33
FSR
O
I
Sampled voltage output, controlled by FSRS
IFSA
If internal integration control circuitry is used, connect a photo diode from this pin to +30V. connect it
to VDD otherwise
34
35
36
FSW
FSCLR
FSWS
O
O
I
Sampled voltage output, controlled by FSWS
Sampling capacitors and resistor are connected to this pin.
Logic input, when FSWS=1, the voltage on pin FSCLR is sampled onto pin FSW, else FSW is in
hold mode.
37
FSOF
I
If internal integration control circuitry is used, connect the control signal to this pin. A logic low enable
the current charging on the capacitors on pin FSCLR with the current from IFSA. Connect this pin to
VDD if internal integration control circuitry is not used.
Non-inverting input of Op Amp
39
40
41
43
44
45
46
47
48
VI+
VI-
I
I
Inverting input of Op Amp
VOUT
CLK
O
I
Op Amp output
Clock input of I2S bus
DI
I
Data input of I2S bus
LD
I
Latch data input of I2S bus
PWRITE
LS_WRITE
WDB
O
I
Connect a DAC resistor network from this pin to VSS
Connect a 6.8Ω (1206type) from this pin to VDD
Connect to the base node of external PNP BJT. (Type BC807-40)
O
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Oct 02, 2000
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G569C
Detail Description
programming of the OTA's transconductance. An
internal DAC can be enabled through I2S bus to
replace the external DAC resistor array. The maximum
RPWRITE is 7.5KΩ. The maximum IW is 130 mA.
Since IW must flow through the external 6.8Ω resistors
connected between VDD and LS_WRITE pin, type
1206 SMD resistors must be used to handle the power
dissipation.
The typical application circuit of G569C is shown in Fig.
1. The block diagram of G569C is shown in Fig. 2. It
contains nine circuit blocks. The operation of these
blocks is described below.
READ Block
This block is equivalent to an operational
transconductance amplifier (OTA). The voltage on
PR_I pin is the input voltage, VPR_I; the output current,
IR, is delivered on pin IR. The relationship between
DELTAP Block
This block is a current sink used to selectively sink the
IW current. When DP4 is low, the current sink reduces
the output current on IW by the amount of the
magnitude of the current sink. The magnitude of the
current sink, Is, is given by:
V
PR_I and IR is given by:
IR = 820 x VPR_I /( R232 ∥R233)
where IR is in mA, VPR_I is in volt, and R is in Ω. The
recommended values for R232 and R233 are 22Ω, the
maximum VPR_I is 2.16 V, thus the maximum IR is
160mA. Since IR must flow through the two external
22Ω resistors connected between VDD and LS_READ
pin, type 1206 SMD resistors must be used to handle
the power dissipation.
3
20
Is =
x VDELTAP / RLS_DELTA,
where Is is in mA; VDELTAP, in volt, is an internal DAC
output; and RLS_DELTA, in KΩ, is the resistance from pin
LS_DELTA to ground. Type 1206 SMD resistors must
be used for RLS_DELTA to handle the power dissipation.
When DP4 is high, the current output on IW current is
not affected.
ERASE Block
This block is also equivalent to an operational
transconductance amplifier (OTA). The voltage on
PWD node is the input voltage, VPWD; the output
voltage, VEDB, can be used to drive an external PNP
BJT to provides desired IE current. The relationship
between VPWD and IE is given by:
DALPHA Block
The function of this block is a voltage subtracter. The
voltage on pin PWB, VPWB, is given by:
VPWB = 2 x VPWO_I - VDALPHA
,
1800
R235
IE =
x VPWD / RPERASE
,
where VPWO_I and VDALPHA are the voltages on pins
PWO_I and DALPHA, respectively. In addition, the
magnitude of the output voltage VPWB is limited by
VPWMAX and VPWMIN, which are the voltages on pins
PWMAX and PWMIN.
where IE is in mA, VPWD is in volt, and RPERASE, in KΩ,
is the total resistance from pin PEARSE to ground.
Typically, a digital-to-analog converter (DAC) resistor
array is connected at PERASE pin to allow digital
programming of the OTA's transconductance. The
maximum RPERASE is 7.5KΩ. An internal DAC can
be enabled through I2S bus to replace the external
DAC resistor array. The maximum IE is 130 mA. Since
IE must flow through the external 6.8Ω resistors
connected between VDD and LS_ERASE pin, type
1206 SMD resistors must be used to handle the power
dissipation.
When 2xVPWO_I - VDALPHA < VPWMIN, then VPWB = VPWMIN
.
When 2xVPWO_I - VDALPHA, > VPWMAX, then VPWB
=
VPWMAX
.
The input voltage ranges of VPWMAX and VPWMIN are 0 to
VS2V9 which is the voltage input at S2V9 pin, and the
condition VPWMAX > VPWMIN must hold. Note that the
input voltage range of VDALPHA is -3V to +3.5V.
CAGAIN Block
WRITE Block
This block is also an operational transconductance
amplifier (OTA). The voltage on VCAGAIN pin is the
input voltage, VVCAGAIN; the output current, ICAGAIN, is
delivered on pin CAGAIN. Let the voltages on pins
This block is also an operational transconductance
amplifier (OTA). The voltage on PWD node is the input
voltage, VPWD; the output voltage, VWDB, can be used
to drive an external PNP BJT to provides desired IW
current. The relationship between VPWD and IW is
given by:
CDR, CAGS, CAGAIN and S2V9 be denoted as VCDR
,
VCAGS, VCAGAIN, VS2V9, respectively. The relationship
between VVCAGAIN and ICAGAIN is given by:
1800
R234
When VCDR = 5V, VCAGS = 5V
ICAGAIN = 1.2 x VCAGAIN / (R108∥R109) + (VS2V9
IW =
x VPWD / RPWRITE,
-
V
CAGAIN) / R195,
When VCDR = 5V, VCAGS = 0V
ICAGAIN (VS2V9 - VCAGAIN) / R195
where IW is in mA, VPWD is in volt, and RPWRITE, in KΩ
is the total resistance from pin PWRITE to ground.
Typically, a digital-to-analog converter (DAC) resistor
array is connected at PWRITE pin to allow digital
=
TEL: 886-3-5788833
Ver: 1.0
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Oct 02, 2000
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Global Mixed-mode Technology Inc.
G569C
When VCDR = 0V, VCAGS = 5V, VRECORD = 0V
CAGAIN = 1.2 x VCAGAIN / R108 + (VS2V9 - VCAGAIN) / R195,
When VFSOF = 0V, the FSCLR pin is charged by IFSA
.
I
When VFSOF = 5V, the FSCLR pin is not charged by IFSA
.
When VCDR = 0V, VCAGS = 5V, VRECORD = 5V
CAGAIN = 1.2 x VCAGAIN / R108
The FSCLR, RDGAIN1, RDGAIN2, and RDGAIN3
pins are driven by an open-drain buffer, i.e., the
voltages on these pins are either 0V or Hi-Z. The
capacitance values of the three capacitors connecting
to the FSCLR may need to be changed if loader other
than CDL4800 is used.
I
When VCDR = 0V, VCAGS = 0V, VRECORD = 0V
ICAGAIN (VS2V9 - VCAGAIN) / R195,
=
When VCDR = 0V, VCAGS = 0V, VRECORD = 5V
ICAGAIN = 0 mA,
When VFSCLR = 0V, the charges on the capacitors are
discharged to 0V.
Where ICAGAIN is in mA; all voltages are in volt, and all
resistance are in KΩ.
When VFSCLR = Hi-Z, the charging of FSCLR node is
allowed.
FSA Block
The FSOF/FSON control the integration of the
photodiode current, IFSA, on the capacitors connected
on pin FSCLR to obtain a voltage. The voltage on
FSCLR pin is connected to two sample-and-hold
circuit. The voltages sampled by the control voltage on
FSWS and FSRS pins are output on FSW and FSR
pins, respectively. Namely,
When VRDGAIN1 = 0V, the VFSCLR is given by:
VFSCLR = IFSA x R187.
When VRDGAIN1 = Hi-Z, the charging of FSCLR node is
allowed.
When VRDGAIN2 = 0V, the capacitor C123 is in parallel
with C116
.
When VFSWS = 5V, VFSW = VFSCLR
,
When VRDGAIN2 = Hi-Z, the capacitor C123 has no effect.
When VRDGAIN3 = 0V, the capacitor C117 is in parallel
When VFSWS = 0V, VFSW = the previously sampled
value;
with C116
.
When VFSRS = 5V, VFSR = VFSCLR
,
When VRDGAIN3 = Hi-Z, the capacitor C117 has no effect.
When VFSRS = 0V, VFSR = the previously sampled
value.
The charging of FSCLR node is controlled by signals
VFSOF and VFSON.
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Global Mixed-mode Technology Inc.
G569C
5V
5V
IFSA
R69
100
R68
R71
100
R70
820
FSOF
30V
BF824
FSON
820
5V
CAGAIN
CAGAIN (pin 21)
CAGAIN2 (pin 18)
VDD (pin 30,38)
R195
0.1μF
62K
R108
R187
22K
VRDGAIN1
IFSA (pin 33)
RCAGAIN1 (pin 22)
16.2K
R109
FSCLR(pin 35)
RCAGAIN2 (pin 23)
CDR (pin 16)
FSCLR (pin 35)
3.9K
CDR
100K
10K
C123
C117
C116
2.2nF
1.5nF
VRDGAIN3
VRDGAIN2
560pF
SELN4_IN (pin 29)
CAGS_I (pin 19)
SELN4
R67
CAGS
12V
330
C113
330pF
R66
220
R234
(1206)
R302
2.2K
6.8
LS_WRITE (pin 47)
5V
R230
4.7K
C127
R191
220
PRCOARSE (pin 25)
R210
47
100nF
R231
150K
BC807_40
IW
WDB (pin 48)
IW_IN (pin 1)
PRFINE (pin 24)
PR_I (pin 28)
BAS216
R192
330
R124
5V
R229
6.8K
5V
270
BC847B
DP4
R232
(1206)
R232
(1206)
22 22
PWRITE (pin 46)
C52
68pF
LS_READ (pin 27)
IR (pin 26)
TST1 (pin 3)
IR
5V
R36
1M
12V
LS_DELTA (pin 2)
R236
10
(1206)
6.8
(1206)
R226
1.5K
R235
LS_ERASE (pin 13)
R236
150K
R92
220
PWO (pin 4)
C135
100nF
EDB (pin 12)
PWO_I (pin 6)
BC808
R211
47
IE
150K
C53
1nF
PERASE (pin 14)
5V
R96
1M
FSOF (pin 37)
FSOF
VSS (pin 11,42)
Fig 1. Typical application circuit
Note: The circuits in the dotted-line are the suggested circuit when internal integration circuit is not used.
Please refer to pin description for details.
TEL: 886-3-5788833
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Ver: 1.0
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Global Mixed-mode Technology Inc.
G569C
Fig 2. Block Diagram of G569C
TEL: 886-3-5788833
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Ver: 1.0
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Global Mixed-mode Technology Inc.
G569C
Internal DAC Digital Format
12BIT SERIAL DATA
(LSB)
1
2
3
4
5
6
7
8
9
10
D2
11
D1
12
DATA
CLK
D11
D10
D9
D8
D7
D6
D5
D4
D3
D0
Data Assignment
D0
D1
D9
D2
D3
D4
D5
D6
D7
: DAC DATA
(LSB)
(MSB)
D8
D10
D11
: DAC SELECT DATA
(MSB)
(LSB)
DAC Select Data
D8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D9
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D10
D11
0
DAC Selection
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Don’t Care
1
PRCOARSE Selection
PRFINE Selection
VCAGAIN Selection
PWMIN Selection
PWMAX Selection
PWO Selection
DELTAP Selection
PWD Selection
WRITE Selection
ERASE Selection
Don’t Care
0
1
0
1
0
1
0
1
0
1
0
Don’t Care
1
Don’t Care
0
Don’t Care
1
Don’t Care
Digital Data Format for Internal DAC
D0
0
D1
0
D2
0
D3
0
D4
0
D5
0
D6
0
D7
0
DAC Output
0
1
0
0
0
0
0
0
0
VIN / 256 × 1
VIN / 256 × 2
VIN / 256 × 3
¦
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
¦
¦
¦
¦
¦
¦
¦
¦
1
1
1
1
1
1
1
1
VIN / 256 × 255
Digital Data Format for WRITE and ERASE
D0
0
D1
×
D2
×
D3
×
D4
×
D5
×
D6
×
D7
Comments
×
Disable Internal R2R Network
1
0/1
0/1
0/1
0/1
0/1
0/1
0/1 Enable Internal R2R Network D1 is LSB , D7 is MSB
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Ver: 1.0
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Global Mixed-mode Technology Inc.
G569C
Timing Chart
R
LSB
D0
MSB
D11
DI
D9
D10
CLK
LD
VO
*Input data carried out LD signal Low besides CLK signal positive edge. CLK, LD is keep generally HIGH level.
AC Characteristics
Symbol
tCKL
Parameter
Clock “L” Pulse Width
Clock “H” Pulse Width
Clock Rise Time
Measurement Condition
Limit
Unit
nS
200
200
tCKH
tCR
nS
200
nS
tCF
Clock Fall Time
tDCH
tCHD
tCHL
tLDC
tLDH
tDo
Data Set Up Time
Data Hold Time
60
100
200
100
100
70
nS
nS
nS
nS
nS
nS
LD Set Up Time
LD Hold Time
LD “H” Pulse Duration Time
Data Output Delay Time
D-A Output Setting Time
CL=100pF
350
300
tLDD
CL ≤ 100pF,VAO:0.1< = > 2.6V
This Time Until The Output Becomes The final Value Of 1/2
LSB
µS
Timing Chart
tCR
tCF
tCKH
CLK
tCKL
tLDC
DI
tDCH
tCHD
tLDH
tCHL
LD
tLDD
D-A OUTPUT
Do OUTPUT
tDo
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Global Mixed-mode Technology Inc.
G569C
Package Information
L
E1
E
h x
45
°
D
A
A1
0.004
C
SEATING PLANE
b
e
DIMENSION IN MM
DIMENSION IN INCH
SYMBOL
MIN.
NOM.
2.591
0.305
MAX.
2.794
0.406
0.343
0.254
16.00
MIN.
0.095
0.008
0.008
0.005
0.620
NOM.
0.102
0.012
MAX.
0.110
0.016
0.0135
0.010
0.630
A
A1
b
2.413
0.203
0.203
0.127
15.75
c
D
e
15.88
0.625
0.635 BASIC
0.025 BASIC
E
10.033
7.391
0.381
0.508
0
10.668
7.595
0.635
1.016
θ
0.395
0.291
0.015
1.020
0
0.420
0.289
0.025
0.040
θ
E1
h
7.493
0.295
L
θ
TEL: 886-3-5788833
http://www.gmt.com.tw
Ver: 1.0
Oct 02, 2000
10
Global Mixed-mode Technology Inc.
G569C
Package Description: SSOP-48
Quantity /Reel
Reel Diameter
: 1000 / Reel
: 13”
Carrier Tape (Width)
Carrier Tape (Pitch)
: 32mm
: 16mm
Mechanical Polarization
Top View Shown With Cover Tape Removed
EIA-JEDEC SO Package Outline Style
Termination No.1
User Direction of Feed
GMT Inc. does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications.
TEL: 886-3-5788833
http://www.gmt.com.tw
Ver: 1.0
Oct 02, 2000
11
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