MB95F476KPMC2-G-SNE2 [FUJITSU]
Microcontroller, 8-Bit, FLASH, F2MC-8 CPU, 16.25MHz, CMOS, PQFP64, 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64;
| 型号： | MB95F476KPMC2-G-SNE2 |
| 厂家： | 
FUJITSU |
| 描述： | Microcontroller, 8-Bit, FLASH, F2MC-8 CPU, 16.25MHz, CMOS, PQFP64, 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64 微控制器 |
| 文件： | 总84页 (文件大小：3887K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12628-2E
8-bit Microcontrollers
CMOS
New 8FX MB95310L/370L Series
MB95F314E/F314L/F316E/F316L/F318E/F318L
MB95F374E/F374L/F376E/F376L/F378E/F378L
■ DESCRIPTION
MB95310L/370L is a series of general-purpose, single-chip microcontrollers. In addition to a compact
instruction set, the microcontrollers of this series contain a variety of peripheral resources.
■ FEATURES
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
• Clock
• Selectable main clock source
Main OSC clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz)
External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz)
Main CR clock (1/8/10/12.5 MHz 2%, maximum machine clock frequency: 12.5 MHz)
Main PLL clock (up to 16.25 MHz, maximum machine clock frequency: 16.25 MHz)
• Selectable subclock source
Sub-OSC clock (32.768 kHz)
External clock (32.768 kHz)
Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz)
• Timer
• 8/16-bit composite timer
• 8/16-bit PPG
• 16-bit reload timer
• Event counter
• Time-base timer
• Watch prescaler
• UART-SIO
• Capable of clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer
• Full duplex double buffer
(Continued)
For the information for microcontroller supports, see the following website.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2010-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.5
MB95310L/370L Series
(Continued)
• I2C
Built-in wake-up function
• External interrupt
• Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
• Can be used to wake up the device from different low power consumption (standby) modes
• 8/10-bit A/D converter
8-bit or 10-bit resolution can be selected
• LCD controller (LCDC)
• 40 SEG × 4 COM (MB95F314E/F314L/F316E/F316L/F318E/F318L)
• 32 SEG × 4 COM (MB95F374E/F374L/F376E/F376L/F378E/F378L)
• Internal divider resistor
• With blinking function
• Low power consumption (standby) modes
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
• I/O port
• MB95F314E/F314L/F316E/F316L/F318E/F318L (maximum no. of I/O ports: 71)
General-purpose I/O ports (N-ch open drain)
General-purpose I/O ports (CMOS I/O)
: 3
: 68
• MB95F374E/F374L/F376E/F376L/F378E/F378L (maximum no. of I/O ports: 55)
General-purpose I/O ports (N-ch open drain)
General-purpose I/O ports (CMOS I/O)
: 3
: 52
• On-chip debug
• 1-wire serial control
• Serial writing supported (asynchronous mode)
• Hardware/software watchdog timer
• Built-in hardware watchdog timer
• Built-in software watchdog timer
• Low-voltage detection reset circuit
• Built-in low-voltage detector
• Three configurable low-voltage detection levels for generating reset
• Five configurable low-voltage detection levels for generating interrupts
• Clock supervisor counter
Built-in clock supervisor counter function
• Programmable port input voltage level
CMOS input level / hysteresis input level
• Dual operation Flash memory
The program/erase operation and the read operation can be executed in different banks (upper bank/lower
bank) simultaneously.
• Flash memory security function
Protects the content of the Flash memory
2
DS07-12628-2E
MB95310L/370L Series
■ PRODUCT LINE-UP
• MB95310L Series
Part number
MB95F314E
MB95F316E
MB95F318E
MB95F314L
MB95F316L
MB95F318L
Parameter
Type
Flash memory product
It supervises the main clock oscillation.
Clock
supervisor
counter
Flash memory
capacity
20 Kbyte
36 Kbyte
1008 bytes
Yes
60 Kbyte
20 Kbyte
496 bytes
36 Kbyte
1008 bytes
No
60 Kbyte
RAM capacity
496 bytes
2032 bytes
2032 bytes
Low-voltage
detection reset
Reset input
Dedicated
• Number of basic instructions
• Instruction bit length
• Instruction length
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8 and 16 bits
CPU functions
• Data bit length
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 71
General-
purpose I/O
• CMOS I/O
: 68
• N-ch open drain: 3
Time-base timer Interval time: 0.256 ms - 8.3 s (external clock frequency = 4 MHz)
Hardware/
software
• Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace three bytes of data.
1 channel
• Master/Slave sending and receiving
• Bus error function and arbitration function
• Detecting transmitting direction function
• Start condition repeated generation and detection functions
• Built-in wake-up function
I2C
2 channels
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate
generator and an error detection function.
• It uses the NRZ type transfer format.
UART/SIO
• LSB-first data transfer and MSB-first data transfer are available to use.
• Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer is enabled.
4 channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
(Continued)
DS07-12628-2E
3
MB95310L/370L Series
(Continued)
Part number
MB95F314E
MB95F316E
MB95F318E
MB95F314L
MB95F316L
MB95F318L
Parameter
2 channels
• Each timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
• It has built-in timer function, PWC function, PWM function and input capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
8/16-bit
composite timer
• COM output: 4 (Max)
• SEG output: 40 (Max)
• LCD drive power supply (bias) pin: 4 (Max)
• 40 SEG × 4 COM: 160 pixels can be displayed
• Duty LCD mode
LCD controller
(LCDC)
• Operate in LCD standby mode
• Blinking function
• Internal divider resistor for LCD drive
1 channel
• Two clock modes and two counter operating modes can be selected
• Square waveform output
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• Counter operating mode: reload mode or one-shot mode can be selected
16-bit reload
timer
By configuring the 16-bit reload timer and the 8/16-bit composite timer ch. 1, event counter
Event counter function can be implemented. When the event counter function is used, the 16-bit reload timer
and the 8/16-bit composite timer ch. 1 are unavailable.
2 channels
8/16-bit PPG
• Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1 channel”
• Counter operating clock: Eight selectable clock sources
• Count clock: Four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s)
Watch counter • Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting
clock source of 1 second and setting counter value to 60)
8 channels
External
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
• It can be used to wake up the device from the standby mode.
• 1-wire serial control
On-chip debug
• It supports serial writing. (asynchronous mode)
Eight different time intervals can be selected.
Watch prescaler
(62.5 ms, 125 ms, 250 ms, 500 ms, 1 s, 2 s, 4 s, 8 s)
• It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/
erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
• Number of program/erase cycles: 100000
Flash memory
• Data retention time: 20 years
• Flash security feature for protecting the content of the Flash memory
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
Package
FPT-80P-M37
4
DS07-12628-2E
MB95310L/370L Series
• MB95370L Series
Part number
MB95F374E
MB95F376E
MB95F378E
MB95F374L
MB95F376L
MB95F378L
Parameter
Type
Flash memory product
It supervises the main clock oscillation.
Clock
supervisor
counter
Flash memory
capacity
20 Kbyte
36 Kbyte
1008 bytes
Yes
60 Kbyte
20 Kbyte
496 bytes
36 Kbyte
1008 bytes
No
60 Kbyte
RAM capacity
496 bytes
2032 bytes
2032 bytes
Low-voltage
detection reset
Reset input
Dedicated
• Number of basic instructions
• Instruction bit length
• Instruction length
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8 and 16 bits
CPU functions
• Data bit length
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max): 55
• CMOS I/O: 52
• N-ch open drain: 3
General-
purpose I/O
Time-base timer Interval time: 0.256 ms - 8.3 s (external clock frequency = 4 MHz)
Hardware/
software
• Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace three bytes of data.
1 channel
• Master/Slave sending and receiving
• Bus error function and arbitration function
• Detecting transmitting direction function
• Start condition repeated generation and detection functions
• Built-in wake-up function
I2C
2 channels
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate
generator and an error detection function.
• It uses the NRZ type transfer format.
UART/SIO
• LSB-first data transfer and MSB-first data transfer are available to use.
• Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer is enabled.
4 channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
2 channels
• Each timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
• It has built-in timer function, PWC function, PWM function and input capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
8/16-bit
composite timer
(Continued)
DS07-12628-2E
5
MB95310L/370L Series
(Continued)
Part number
MB95F374E
MB95F376E
MB95F378E
MB95F374L
MB95F376L
MB95F378L
Parameter
• COM output: 4 (Max)
• SEG output: 32 (Max)
• LCD drive power supply (bias) pin: 3 (Max)
• 32 SEG × 4 COM: 128 pixels can be displayed
• Duty LCD mode
LCD controller
(LCDC)
• Operate in LCD standby mode
• Blinking function
• Internal divider resistor for LCD drive
1 channel
• Two clock modes and two counter operating modes can be selected
• Square waveform output
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• Counter operating mode: reload mode or one-shot mode can be selected
16-bit reload
timer
By configuring the 16-bit reload timer and the 8/16-bit composite timer ch. 1, event counter
Event counter function can be implemented. When the event counter function is used, the 16-bit reload timer
and the 8/16-bit composite timer ch. 1 are unavailable.
2 channels
8/16-bit PPG
• Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1 channel“
• Counter operating clock: Eight selectable clock sources
• Count clock: Four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s)
Watch counter • Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting
clock source of 1 second and setting counter value to 60)
8 channels
External
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
• It can be used to wake up the device from the standby mode.
• 1-wire serial control
On-chip debug
• It supports serial writing. (asynchronous mode)
Eight different time intervals can be selected.
Watch prescaler
(62.5 ms, 125 ms, 250 ms, 500 ms, 1 s, 2 s, 4 s, 8 s)
• It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/
erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
• Number of program/erase cycles: 100000
Flash memory
• Data retention time: 20 years
• Flash security feature for protecting the content of the Flash memory
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
FPT-64P-M38
FPT-64P-M39
Package
6
DS07-12628-2E
MB95310L/370L Series
■ OSCILLATION STABILIZATION WAIT TIME
The main CR clock oscillation stabilization wait time is fixed to the maximum value. Below is the maximum
value.
Oscillation stabilization wait time
Remarks
(210 − 2) / FCRH
Approx. 128 µs (when the main CR clock is 8 MHz)
The main PLL clock oscillation stabilization wait time is fixed to the maximum value. Below is the maximum
value.
Oscillation stabilization wait time
Remarks
(214 − 2) / FCH
Approx. 14.1 ms (when the main PLL clock is 4 MHz)
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
MB95F314E
MB95F316E
MB95F318E
MB95F314L
MB95F316L
MB95F318L
Package
FPT-80P-M37
FPT-64P-M38
FPT-64P-M39
O
X
X
Part number
MB95F374E
MB95F376E
MB95F378E
MB95F374L
MB95F376L
MB95F378L
Package
FPT-80P-M37
FPT-64P-M38
FPT-64P-M39
X
O
O
O: Available
X : Unavailable
DS07-12628-2E
7
MB95310L/370L Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION
• Current consumption
When using the on-chip debug function, take account of the current consumption of flash erase/write.
For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSION”.
• Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, see “■ ELECTRICAL CHARACTERISTICS”.
• On-chip debug function
The on-chip debug function requires that VCC, VSS and 1 serial-wire be connected to an evaluation tool. For
details of the connection method, refer to “CHAPTER 31 EXAMPLE OF SERIAL PROGRAMMING CON-
NECTION” in the hardware manual of the MB95310L/370L Series.
8
DS07-12628-2E
MB95310L/370L Series
■ PIN ASSIGNMENT
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AVcc
PPG10/P16
PPG11/P15
UCK0/P14
ADTG/P13
DBG/P12
UO0/P11
UI0/P10
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PE0/SEG24
P67/SEG23
P66/SEG22
P65/SEG21
P64/SEG20
P63/SEG19
P62/SEG18
P61/SEG17
P60/SEG16
PC7/SEG15
PC6/SEG14
PC5/SEG13
PC4/SEG12
PC3/SEG11
PC2/SEG10
PC1/SEG09
PC0/SEG08
PB7/SEG07
PB6/SEG06
PB5/SEG05
3
4
5
6
7
8
(TOP VIEW)
MB95310L Series
TO0/P53
TI0/P52
9
10
11
12
13
14
15
16
17
18
19
20
EC0/P51
TO01/P50
SDA0/P24
SCL0/P23
TO00/P22
PPG01/P21
PPG00/P20
X0
(FPT-80P-M37)
X1
Vss
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
(Continued)
DS07-12628-2E
9
MB95310L/370L Series
(Continued)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc
PPG10/P16
PPG11/P15
UCK0/EC0/TI0/P14
ADTG/TO01/P13
DBG/P12
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PE0/SEG20
P67/SEG19
P66/SEG18
P65/SEG17
P64/SEG16
P63/SEG15
P62/SEG14
P61/SEG13
P60/SEG12
PC3/SEG11
PC2/SEG10
PC1/SEG09
PC0/SEG08
PB7/SEG07
PB6/SEG06
PB5/SEG05
3
4
5
6
(TOP VIEW)
MB95370L Series
UO0/P11
7
UI0/P10
8
SDA0/P24
SCL0/P23
TO00/P22
PPG01/P21
PPG00/P20
X0
9
(FPT-64P-M38)
(FPT-64P-M39)
10
11
12
13
14
15
16
X1
Vss
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
10
DS07-12628-2E
MB95310L/370L Series
■ PIN DESCRIPTION (MB95310L Series)
Pin no.
Pin name
AVCC
P16
I/O circuit type*
Function
1
—
A/D converter power supply pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
UART/SIO ch. 0 clock I/O pin
General-purpose I/O port
A/D trigger input (ADTG) pin
General-purpose I/O port
DBG input pin
2
3
4
5
6
7
8
9
H
H
H
H
C
H
G
H
PPG10
P15
PPG11
P14
UCK0
P13
ADTG
P12
DBG
P11
General-purpose I/O port
UART/SIO ch. 0 data output pin
General-purpose I/O port
UART/SIO ch. 0 data input pin
General-purpose I/O port
16-bit reload timer ch. 0 output pin
General-purpose I/O port
UO0
P10
UI0
P53
TO0
P52
16-bit reload timer ch. 0 input pin
The pin can also be used as the event counter input pin when the
event counter function is used.
10
H
TI0
P51
EC0
P50
General-purpose I/O port
8/16-bit composite timer ch. 0 clock input pin
General-purpose I/O port
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
I2C data I/O pin
11
12
13
14
15
16
17
H
H
I
TO01
P24
SDA0
P23
General-purpose I/O port
I2C clock I/O pin
I
SCL0
P22
General-purpose I/O port
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
Main clock oscillation pin
H
H
H
TO00
P21
PPG01
P20
PPG00
X0
18
19
A
A
X1
Main clock oscillation pin
(Continued)
DS07-12628-2E
11
MB95310L/370L Series
Pin no.
20
Pin name
Vss
I/O circuit type*
Function
—
—
Power supply pin (GND)
Power supply pin
21
VCC
PG0
UCK1
X1A
General-purpose I/O port
22
H
UART/SIO ch. 1 clock I/O pin
Subclock oscillation pin (32 kHz)
Subclock oscillation pin (32 kHz)
Reset pin
23
24
25
A
A
B
X0A
RST
P90
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
UART/SIO ch. 0 data output pin
General-purpose I/O port
UART/SIO ch. 0 data input pin
General-purpose I/O port
LCDC COM output pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
R
R
V3
P91
V2
P92
R
V1
P93
R
V0
P94
H
UO1
P95
G
M
M
M
M
M
M
M
M
M
UI1
PA0
COM0
PA1
General-purpose I/O port
LCDC COM output pin
COM1
PA2
General-purpose I/O port
LCDC COM output pin
COM2
PA3
General-purpose I/O port
LCDC COM output pin
COM3
PB0
General-purpose I/O port
LCDC SEG output pin
SEG00
PB1
General-purpose I/O port
LCDC SEG output pin
SEG01
PB2
General-purpose I/O port
LCDC SEG output pin
SEG02
PB3
General-purpose I/O port
LCDC SEG output pin
SEG03
PB4
General-purpose I/O port
LCDC SEG output pin
SEG04
(Continued)
12
DS07-12628-2E
MB95310L/370L Series
Pin no.
Pin name
PB5
I/O circuit type*
Function
General-purpose I/O port
41
M
SEG05
PB6
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
SEG06
PB7
SEG07
PC0
SEG08
PC1
SEG09
PC2
SEG10
PC3
SEG11
PC4
SEG12
PC5
SEG13
PC6
SEG14
PC7
SEG15
P60
SEG16
P61
SEG17
P62
SEG18
P63
SEG19
P64
SEG20
P65
SEG21
P66
SEG22
(Continued)
DS07-12628-2E
13
MB95310L/370L Series
Pin no.
Pin name
P67
I/O circuit type*
Function
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
59
M
SEG23
PE0
60
61
62
63
64
65
66
67
68
M
M
M
M
M
M
N
SEG24
PE1
SEG25
PE2
SEG26
PE3
SEG27
PE4
SEG28
PE5
SEG29
PE6
SEG30
PE7
M
M
SEG31
P43
SEG32
P42
69
70
71
72
73
SEG33
TO11
P41
M
M
M
Q
Q
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
SEG34
TO10
P40
LCDC SEG output pin
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
SEG35
EC1
LCDC SEG output pin
8/16-bit composite timer ch. 1 clock input pin
General-purpose I/O port
P07
INT07
SEG36
P06
External interrupt input pin
LCDC SEG output pin
General-purpose I/O port
INT06
SEG37
External interrupt input pin
LCDC SEG output pin
(Continued)
14
DS07-12628-2E
MB95310L/370L Series
(Continued)
Pin no.
Pin name
I/O circuit type*
Function
P05
General-purpose I/O port
74
75
76
77
78
INT05
SEG38
P04
Q
External interrupt input pin
LCDC SEG output pin
General-purpose I/O port
External interrupt input pin
LCDC SEG output pin
INT04
SEG39
P03
Q
J
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT03
AN03
P02
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT02
AN02
P01
J
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT01
AN01
P00
J
General-purpose I/O port
External interrupt input pin
A/D analog input pin
79
80
INT00
AN00
AVss
J
—
A/D converter power supply pin (GND)
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS07-12628-2E
15
MB95310L/370L Series
s
■ PIN DESCRIPTION (MB95370L Series)
Pin no.
Pin name
AVCC
I/O circuit type*
Function
A/D converter power supply pin
1
—
P16
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
UART/SIO ch. 0 clock I/O pin
2
3
H
H
PPG10
P15
PPG11
P14
UCK0
8/16-bit composite timer ch. 0 clock input pin
The pin can also be used as the event counter input pin when the
event counter function is used.
4
5
H
H
EC0
TI0
P13
16-bit reload timer ch. 0 input pin
General-purpose I/O port
A/D trigger input (ADTG) pin
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
DBG input pin
ADTG
TO01
P12
6
7
C
H
G
I
DBG
P11
General-purpose I/O port
UART/SIO ch. 0 data output pin
General-purpose I/O port
UART/SIO ch. 0 data input pin
General-purpose I/O port
I2C data I/O pin
UO0
P10
8
UI0
P24
9
SDA0
P23
General-purpose I/O port
I2C clock I/O pin
10
11
12
13
I
SCL0
P22
General-purpose I/O port
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
Main clock oscillation pin
Main clock oscillation pin
Power supply pin (GND)
Power supply pin
H
H
H
TO00
P21
PPG01
P20
PPG00
X0
14
15
16
17
A
A
X1
Vss
—
—
VCC
P90
General-purpose I/O port
LCDC drive power supply pin
18
R
V3
(Continued)
16
DS07-12628-2E
MB95310L/370L Series
Pin no.
19
Pin name
X1A
I/O circuit type*
Function
Subclock oscillation pin (32 kHz)
A
B
R
20
X0A
Subclock oscillation pin (32 kHz)
Reset pin
21
RST
P91
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
V2
P92
R
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
V1
PA0
COM0
PA1
COM1
PA2
COM2
PA3
COM3
PB0
SEG00
PB1
SEG01
PB2
SEG02
PB3
SEG03
PB4
SEG04
PB5
SEG05
PB6
SEG06
PB7
SEG07
PC0
SEG08
PC1
SEG09
PC2
SEG10
(Continued)
DS07-12628-2E
17
MB95310L/370L Series
Pin no.
Pin name
PC3
I/O circuit type*
Function
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
39
M
SEG11
P60
40
41
42
43
44
45
46
47
48
49
50
51
52
M
M
M
M
M
M
M
M
M
M
M
M
M
SEG12
P61
SEG13
P62
SEG14
P63
SEG15
P64
SEG16
P65
SEG17
P66
SEG18
P67
SEG19
PE0
SEG20
PE1
SEG21
PE2
SEG22
PE3
SEG23
PE4
SEG24
PE5
53
54
55
SEG25
TO0
M
N
16-bit reload timer ch. 0 output pin
General-purpose I/O port
LCDC SEG output pin
PE6
SEG26
UI1
UART/SIO ch. 1 data input pin
General-purpose I/O port
LCDC SEG output pin
PE7
SEG27
UO1
M
UART/SIO ch. 1 data output pin
(Continued)
18
DS07-12628-2E
MB95310L/370L Series
(Continued)
Pin no.
Pin name
I/O circuit type*
Function
P07
General-purpose I/O port
INT07
SEG28
UCK1
P06
External interrupt input pin
LCDC SEG output pin
56
57
58
59
Q
UART/SIO ch. 1 clock I/O pin
General-purpose I/O port
External interrupt input pin
LCDC SEG output pin
INT06
SEG29
TO11
P05
Q
Q
Q
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
External interrupt input pin
LCDC SEG output pin
INT05
SEG30
TO10
P04
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
External interrupt input pin
LCDC SEG output pin
INT04
SEG31
EC1
8/16-bit composite timer ch. 1 clock input pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
P03
60
61
62
INT03
AN03
P02
J
J
J
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT02
AN02
P01
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT01
AN01
P00
General-purpose I/O port
External interrupt input pin
A/D analog input pin
63
64
INT00
AN00
AVss
J
—
A/D converter power supply pin (GND)
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS07-12628-2E
19
MB95310L/370L Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Oscillation circuit
A
• High-speed side
Feedback resistance:
approx. 1 MΩ
X1 (X1A)
X0 (X0A)
Clock input
N-ch
• Low-speed side
Feedback resistance:
approx. 24 MΩ
Standby control
Dumping resistance:
approx. 144 kΩ
B
C
Reset input
Reset input
• N-ch open drain output
• Hysteresis input
Standby control
Hysteresis input
Digital output
N-ch
G
• CMOS output
• Hysteresis input
• CMOS input
Pull-up control
R
P-ch
Digital output
Digital output
• Pull-up control available
P-ch
N-ch
Standby control
Hysteresis input
CMOS input
H
• CMOS output
• Hysteresis input
• Pull-up control available
Pull-up control
R
P-ch
N-ch
Digital output
Digital output
P-ch
Standby control
Hysteresis input
(Continued)
20
DS07-12628-2E
MB95310L/370L Series
Type
Circuit
Remarks
I
• N-ch open drain output
• CMOS input
• Hysteresis input
Standby control
CMOS input
Hysteresis input
Digital output
N-ch
J
• CMOS output
• Hysteresis input
• Analog input
Pull-up control
R
P-ch
Digital output
Digital output
• Pull-up control available
P-ch
N-ch
Analog input
A/D control
Standby control
Hysteresis input
M
• CMOS output
• LCD output
• Hysteresis input
P-ch
N-ch
Digital output
Digital output
LCD output
LCD control
Standby control
Hysteresis input
N
• CMOS output
• LCD output
• Hysteresis input
• CMOS input
P-ch
N-ch
Digital output
Digital output
LCD output
LCD control
Standby control
Hysteresis input
CMOS input
(Continued)
DS07-12628-2E
21
MB95310L/370L Series
(Continued)
Type
Circuit
Remarks
• CMOS output
• LCD output
Q
P-ch
N-ch
Digital output
Digital output
• Hysteresis input
LCD output
LCD control
Standby control
External interrupt
control
Hysteresis input
R
• CMOS output
• LCD power supply
• Hysteresis input
P-ch
Digital output
Digital output
N-ch
LCD internal divider
resistor I/O
LCD control
Standby control
Hysteresis input
22
DS07-12628-2E
MB95310L/370L Series
■ NOTES ON DEVICE HANDLING
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that
is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating
range of power supply voltage mentioned in “1. Absolute Maximum Ratings” of “■ ELECTRICAL CHARAC-
TERISTICS” is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be
thermally destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within
the guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value)
at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient
fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from subclock mode or stop mode.
■ PIN CONNECTION
• Treatment of unused input pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions
or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an
unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it
the same as an unused input pin. If there is an unused output pin, leave it unconnected.
• Notes on handling the external clock pins while using the CR clock
Connect the X0 pin and the X0A pin to the VSS pin and leave the X1 pin and the X1A pin unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase
in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS
pin to the power supply and ground outside the device. In addition, connect the current supply source to the
VCC pin and the VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between
the VCC pin and the VSS pin at a location close to this device.
• DBG pin
Connect the DBG pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance
between the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The DBG pin should not stay at “L” level after power-on until the reset output is released.
• RST pin
Connect the RST pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance
between the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board.
DS07-12628-2E
23
MB95310L/370L Series
• DBG/RST pins connection diagram
*
DBG
RST
*: Since the DBG input pin becomes a communication pin in on-chip debug mode,
set a pull-up resistor value suiting the input/output specifications of P12/DBG.
24
DS07-12628-2E
MB95310L/370L Series
■ RECOMMENDED LAYOUT
• GND wire should be placed around X0, X1, X0A and X1A
The recommended layout method illustrated in following diagram aims to avoid noise coupled between the
oscillator pins and GPIO, which may cause the main oscillator or the suboscillator to malfunction.
MB95310L/370L Series
P20
X0
GND
X1
Vss
GND
DS07-12628-2E
25
MB95310L/370L Series
■ BLOCK DIAGRAM (MB95310L Series)
F2MC-8FX CPU
Flash with security function
(60/36/20 Kbyte)
RST
Reset with LVD
X1
X0
RAM (2032/1008/496 bytes)
Oscillator
circuit
CR
oscillator
Main PLL
X1A
X0A
Interrupt controller
P22/TO00
P50/TO01
P51/EC0
8/16-bit composite
Clock control
timer ch. 0
Watch counter
P00/AN00-P03/AN03
P13/ADTG
P12/DBG
On-chip debug
8/10-bit A/D converter
AVCC
Wild register
AVss
P00/INT00-P07/INT07
P14/UCK0
External interrupt
P90/V3-P93/V0
PA0/COM0-PA3/COM3
PB0/SEG00-PB7/SEG07
P11/UO0
UART/SIO ch. 0
UART/SIO ch. 1
PC0/SEG08-PC7/SEG15
P60/SEG16-P67/SEG23
P10/UI0
LCDC
(40 SEG × 4 COM)
PG0/UCK1
PE0/SEG24-PE7/SEG31
P43/SEG32-P40/SEG35
P07/SEG36-P04/SEG39
P94/UO1
P95/UI1
P20/PPG00
*
8/16bit PPG ch. 0
8/16bit PPG ch. 1
P52/TI0
P21/PPG01
P16/PPG10
P15/PPG11
P23/SCL0
P24/SDA0
16-bit reload timer
P53/TO0
P42/TO11
P41/TO10
P40/EC1
8/16-bit composite
timer ch. 1
2
I C
Port
Port
*: 8/16-bit composite timer ch. 1 and 16-bit reload timer ch. 0 can be used as an event counter when the event counter operating mode is enabled.
26
DS07-12628-2E
MB95310L/370L Series
■ BLOCK DIAGRAM (MB95370L Series)
F2MC-8FX CPU
Flash with security function
(60/36/20 Kbyte)
RST
Reset with LVD
X1
X0
RAM (2032/1008/496 bytes)
Interrupt controller
P22/TO00
Oscillator
circuit
CR
oscillator
Main PLL
X1A
X0A
8/16-bit composite
Clock control
P13/TO01
timer ch. 0
P14/EC0
Watch counter
P00/AN00-P03/AN03
P13/ADTG
P12/DBG
On-chip debug
8/10-bit A/D converter
AVCC
Wild register
AVss
P00/INT00-P07/INT07
P14/UCK0
External interrupt
P90/V3-P92/V1
PA0/COM0-PA3/COM3
PB0/SEG00-PB7/SEG07
P11/UO0
UART/SIO ch. 0
UART/SIO ch. 1
PC0/SEG08-PC3/SEG11
P10/UI0
LCDC
(32 SEG × 4 COM)
P60/SEG12-P67/SEG19
P07/UCK1
PE0/SEG20-PE7/SEG27
P07/SEG28-P04/SEG31
PE7/UO1
PE6/UI1
P20/PPG00
*
8/16bit PPG ch. 0
8/16bit PPG ch. 1
P14/TI0
P21/PPG01
P16/PPG10
P15/PPG11
P23/SCL0
P24/SDA0
16-bit reload timer
PE5/TO0
P05/TO10
P06/TO11
P04/EC1
8/16-bit composite
timer ch. 1
2
I C
Port
Port
*: 8/16-bit composite timer ch. 1 and 16-bit reload timer ch. 0 can be used as an event counter when the event counter operating mode is enabled.
DS07-12628-2E
27
MB95310L/370L Series
■ CPU CORE
• Memory Space
The memory space of the MB95310L/370L Series is 64 Kbyte in size, and consists of an I/O area, a data
area, and a program area. The memory space includes areas intended for specific purposes such as
general-purpose registers and a vector table. The memory maps of the MB95310L/370L Series are shown
below.
• Memory Maps
MB95F314E/F314L
MB95F374E/F374L
MB95F316E/F316L
MB95F376E/F376L
MB95F318E/F318L
MB95F378E/F378L
0000
H
0000
H
0000
H
I/O area
I/O area
I/O area
0080
0090
0100
H
H
0080
0090
0100
H
0080
0090
0100
H
Access prohibited
RAM 496 bytes
Access prohibited
RAM 1008 bytes
Access prohibited
RAM 2032 bytes
H
H
H
H
H
Registers
Registers
Registers
0200
H
H
0200
H
0200
H
0280
0480
H
Access prohibited
Access prohibited
0880
H
H
Access prohibited
Extended I/O area
0F80
H
0F80
H
0F80
Extended I/O area
Flash 4 Kbyte
Extended I/O area
Flash 4 Kbyte
1000
2000
H
H
1000
H
H
1000
H
2000
Vacant
Vacant
7FFF
H
Flash 60 Kbyte
BFFF
H
H
Flash 32 Kbyte
Flash 16 Kbyte
FFFF
FFFF
H
FFFF
H
28
DS07-12628-2E
MB95310L/370L Series
■ I/O MAP (MB95310L Series)
Register
Address
Register name
R/W Initial value
abbreviation
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
PDR0
DDR0
PDR1
DDR1
—
Port 0 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port 0 direction register
Port 1 data register
Port 1 direction register
(Disabled)
—
—
WATR
PLLC
SYCC
STBC
RSRR
TBTC
WPCR
WDTC
SYCC2
PDR2
DDR2
Oscillation stabilization wait time setting register
PLL control register
R/W 11111111B
R/W 00000000B
R/W XXXXXX11B
R/W 00000XXXB
R/W 000XXXXXB
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W XX100011B
R/W 00000000B
R/W 00000000B
System clock control register
Standby control register
Reset source register
Time-base timer control register
Watch prescaler control register
Watchdog timer control register
System clock control register 2
Port 2 data register
Port 2 direction register
0010H,
0011H
—
(Disabled)
—
—
0012H
0013H
0014H
0015H
0016H
0017H
PDR4
DDR4
PDR5
DDR5
PDR6
DDR6
Port 4 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port 4 direction register
Port 5 data register
Port 5 direction register
Port 6 data register
Port 6 direction register
0018H
to
—
(Disabled)
—
—
001BH
001CH
001DH
001EH
001FH
0020H
0021H
0022H
0023H
PDR9
DDR9
PDRA
DDRA
PDRB
DDRB
PDRC
DDRC
Port 9 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port 9 direction register
Port A data register
Port A direction register
Port B data register
Port B direction register
Port C data register
Port C direction register
0024H,
0025H
—
(Disabled)
—
—
(Continued)
DS07-12628-2E
29
MB95310L/370L Series
Register
abbreviation
Address
Register name
R/W Initial value
0026H
0027H
PDRE
Port E data register
R/W 00000000B
R/W 00000000B
DDRE
Port E direction register
0028H,
0029H
—
(Disabled)
—
—
002AH
002BH
002CH
002DH
002EH
PDRG
DDRG
PUL0
PUL1
PUL2
Port G data register
Port G direction register
Port 0 pull-up register
Port 1 pull-up register
Port 2 pull-up register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
002FH,
0030H
—
PUL5
—
(Disabled)
(Disabled)
—
—
0031H
Port 5 pull-up register
R/W 00000000B
0032H,
0033H
—
—
0034H
0035H
0036H
0037H
0038H
0039H
003AH
003BH
003CH
003DH
003EH
003FH
PUL9
PULG
Port 9 pull-up register
Port G pull-up register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
T01CR1
T00CR1
T11CR1
T10CR1
PC01
8/16-bit composite timer 01 status control register 1 ch. 0
8/16-bit composite timer 00 status control register 1 ch. 0
8/16-bit composite timer 11 status control register 1 ch. 1
8/16-bit composite timer 10 status control register 1 ch. 1
8/16-bit PPG01 control register ch. 0
PC00
8/16-bit PPG00 control register ch. 0
PC11
8/16-bit PPG11 control register ch. 1
PC10
8/16-bit PPG10 control register ch. 1
TMCSRH
TMCSRL
16-bit reload timer control status register upper ch. 0
16-bit reload timer control status register lower ch. 0
0040H
to
—
(Disabled)
—
—
0047H
0048H
0049H
004AH
004BH
EIC00
EIC10
EIC20
EIC30
External interrupt circuit control register ch. 0/ch. 1
External interrupt circuit control register ch. 2/ch. 3
External interrupt circuit control register ch. 4/ch. 5
External interrupt circuit control register ch. 6/ch. 7
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
004CH,
004DH
—
(Disabled)
—
—
004EH
004FH
LVDR
LVDC
LVD reset voltage selection ID register
LVD control register
R/W 00000000B
R/W X000000XB
0050H
to
—
(Disabled)
—
—
0055H
(Continued)
30
DS07-12628-2E
MB95310L/370L Series
Register
abbreviation
Address
Register name
R/W Initial value
0056H
0057H
0058H
0059H
005AH
005BH
005CH
005DH
005EH
005FH
0060H
0061H
0062H
0063H
0064H
0065H
SMC10
SMC20
SSR0
UART/SIO serial mode control register 1 ch. 0
UART/SIO serial mode control register 2 ch. 0
UART/SIO serial status register ch. 0
UART/SIO output data register ch. 0
UART/SIO input data register ch. 0
UART/SIO serial mode control register 1 ch. 1
UART/SIO serial mode control register 2 ch. 1
UART/SIO serial status register ch. 1
UART/SIO output data register ch. 1
UART/SIO input data register ch. 1
I2C bus control register 0
R/W 00000000B
R/W 00100000B
R/W 00000001B
R/W 00000000B
TDR0
RDR0
R
00000000B
SMC11
SMC21
SSR1
R/W 00000000B
R/W 00100000B
R/W 00000001B
R/W 00000000B
TDR1
RDR1
R
00000000B
IBCR00
IBCR10
IBCR0
IDDR0
IAAR0
ICCR0
R/W 00000001B
R/W 00000000B
I2C bus control register 1
I2C bus status register
I2C data register
R
00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
I2C address register
I2C clock control register
0066H
to
—
(Disabled)
—
—
006BH
006CH
006DH
006EH
006FH
0070H
0071H
0072H
0073H
0074H
0075H
0076H
0077H
ADC1
ADC2
ADDH
ADDL
WCSR
FSR2
FSR
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register upper
8/10-bit A/D converter data register lower
Watch counter status register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 000X0000B
R/W 00000000B
Flash memory status register 2
Flash memory status register
SWRE0
FSR3
—
Flash memory sector write control register 0
Flash memory status register 3
R
00000000B
—
(Disabled)
—
WREN
WROR
Wild register address compare enable register
Wild register data test setting register
R/W 00000000B
R/W 00000000B
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
0078H
—
—
—
(Continued)
DS07-12628-2E
31
MB95310L/370L Series
Register
abbreviation
Address
Register name
R/W Initial value
0079H
007AH
007BH
007CH
007DH
007EH
007FH
0F80H
0F81H
0F82H
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
ILR0
Interrupt level setting register 0
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Interrupt level setting register 4
Interrupt level setting register 5
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
ILR1
ILR2
ILR3
ILR4
ILR5
—
(Disabled)
—
—
WRARH0 Wild register address setting register (upper) ch. 0
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
WRARL0
WRDR0
Wild register address setting register (lower) ch. 0
Wild register data setting register ch. 0
WRARH1 Wild register address setting register (upper) ch. 1
WRARL1
WRDR1
Wild register address setting register (lower) ch. 1
Wild register data setting register ch. 1
WRARH2 Wild register address setting register (upper) ch. 2
WRARL2
WRDR2
Wild register address setting register (lower) ch. 2
Wild register data setting register ch. 2
0F89H
to
—
(Disabled)
—
—
0F91H
0F92H
0F93H
0F94H
0F95H
T01CR0
T00CR0
T01DR
T00DR
8/16-bit composite timer 01 status control register 0 ch. 0
8/16-bit composite timer 00 status control register 0 ch. 0
8/16-bit composite timer 01 data register ch. 0
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
8/16-bit composite timer 00 data register ch. 0
8/16-bit composite timer 00/01 timer mode control register
ch. 0
0F96H
TMCR0
R/W 00000000B
0F97H
0F98H
0F99H
0F9AH
T11CR0
T10CR0
T11DR
T10DR
8/16-bit composite timer 11 status control register 0 ch. 1
8/16-bit composite timer 10 status control register 0 ch. 1
8/16-bit composite timer 11 data register ch. 1
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
8/16-bit composite timer 10 data register ch. 1
8/16-bit composite timer 10/11 timer mode control register
ch. 1
0F9BH
TMCR1
R/W 00000000B
0F9CH
0F9DH
0F9EH
0F9FH
0FA0H
0FA1H
0FA2H
0FA3H
PPS01
PPS00
PDS01
PDS00
PPS11
PPS10
PDS11
PDS10
8/16-bit PPG01 cycle setting buffer register ch. 0
8/16-bit PPG00 cycle setting buffer register ch. 0
8/16-bit PPG01 duty setting buffer register ch. 0
8/16-bit PPG00 duty setting buffer register ch. 0
8/16-bit PPG11 cycle setting buffer register ch. 1
8/16-bit PPG10 cycle setting buffer register ch. 1
8/16-bit PPG11 duty setting buffer register ch. 1
8/16-bit PPG10 duty setting buffer register ch. 1
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
(Continued)
32
DS07-12628-2E
MB95310L/370L Series
Register
abbreviation
Address
Register name
R/W Initial value
0FA4H
0FA5H
PPGS
REVC
8/16-bit PPG start register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
8/16-bit PPG output inversion register
16-bit reload timer timer register upper
TMRH0
0FA6H
0FA7H
TMRLRH0 16-bit reload timer reload register upper
TMRL0 16-bit reload timer timer register lower
TMRLRL0 16-bit reload timer reload register lower
0FA8H
to
—
(Disabled)
—
—
0FBDH
UART/SIO dedicated baud rate generator prescaler selecting
register ch. 0
0FBEH
0FBFH
0FC0H
0FC1H
PSSR0
BRSR0
PSSR1
BRSR1
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
UART/SIO dedicated baud rate generator baud rate setting
register ch. 0
UART/SIO dedicated baud rate generator prescaler selecting
register ch. 1
UART/SIO dedicated baud rate generator baud rate setting
register ch. 1
0FC2H
0FC3H
0FC4H
0FC5H
0FC6H
0FC7H
0FC8H
0FC9H
0FCAH
0FCBH
0FCCH
—
(Disabled)
A/D input disable register (lower)
LCDC control register
—
—
AIDRL
R/W 00000000B
R/W 00010000B
R/W 00110000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
LCDCC
LCDCE1
LCDCE2
LCDCE3
LCDCE4
LCDCE5
LCDCE6
LCDCB1
LCDCB2
LCDC enable register 1
LCDC enable register 2
LCDC enable register 3
LCDC enable register 4
LCDC enable register 5
LCDC enable register 6
LCDC blinking setting register 1
LCDC blinking setting register 2
0FCDH
to
LCDRAM
LCDC display RAM
R/W 00000000B
0FE0H
0FE1H
0FE2H
0FE3H
0FE4H
0FE5H
—
(Disabled)
Event counter control register
—
—
EVCR
WCDR
CRTH
CRTL
R/W 00000000B
R/W 00111111B
R/W 0XXXXXXXB
R/W 00XXXXXXB
Watch counter data register
Main CR clock trimming register (upper)
Main CR clock trimming register (lower)
0FE6H
to
—
(Disabled)
—
—
0FE8H
0FE9H
0FEAH
CMCR
CMDR
Clock monitoring control register
Clock monitoring data register
R/W XX000000B
R
00000000B
(Continued)
DS07-12628-2E
33
MB95310L/370L Series
(Continued)
Register
Address
Register name
R/W Initial value
abbreviation
WDTH
WDTL
—
0FEBH
0FECH
0FEDH
0FEEH
0FEFH
Watchdog timer selection ID register (upper)
Watchdog timer selection ID register (lower)
(Disabled)
R
R
XXXXXXXXB
XXXXXXXXB
—
—
ILSR
Input level select register
R/W 00000000B
R/W 01000000B
WICR
Interrupt pin control register
0FF0H
to
—
(Disabled)
—
—
0FFFH
• R/W access symbols
R/W : Readable / Writable
: Read only
R
• Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is indeterminate.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
34
DS07-12628-2E
MB95310L/370L Series
■ I/O MAP (MB95370L Series)
Register
Address
Register name
R/W Initial value
abbreviation
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
PDR0
DDR0
PDR1
DDR1
—
Port 0 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port 0 direction register
Port 1 data register
Port 1 direction register
(Disabled)
—
—
WATR
PLLC
SYCC
STBC
RSRR
TBTC
WPCR
WDTC
SYCC2
PDR2
DDR2
Oscillation stabilization wait time setting register
PLL control register
R/W 11111111B
R/W 00000000B
R/W XXXXXX11B
R/W 00000XXXB
R/W 000XXXXXB
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W XX100011B
R/W 00000000B
R/W 00000000B
System clock control register
Standby control register
Reset source register
Time-base timer control register
Watch prescaler control register
Watchdog timer control register
System clock control register 2
Port 2 data register
Port 2 direction register
0010H
to
—
(Disabled)
—
—
0015H
0016H
0017H
PDR6
DDR6
Port 6 data register
R/W 00000000B
R/W 00000000B
Port 6 direction register
0018H
to
—
(Disabled)
—
—
001BH
001CH
001DH
001EH
001FH
0020H
0021H
0022H
0023H
PDR9
DDR9
PDRA
DDRA
PDRB
DDRB
PDRC
DDRC
Port 9 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port 9 direction register
Port A data register
Port A direction register
Port B data register
Port B direction register
Port C data register
Port C direction register
0024H,
0025H
—
(Disabled)
—
—
0026H
0027H
PDRE
DDRE
Port E data register
R/W 00000000B
R/W 00000000B
Port E direction register
0028H
to
—
(Disabled)
—
—
002BH
002CH
002DH
002EH
PUL0
PUL1
PUL2
Port 0 pull-up register
Port 1 pull-up register
Port 2 pull-up register
R/W 00000000B
R/W 00000000B
R/W 00000000B
(Continued)
DS07-12628-2E
35
MB95310L/370L Series
Register
abbreviation
Address
Register name
R/W Initial value
002FH
to
—
(Disabled)
—
—
0033H
0034H
0035H
0036H
0037H
0038H
0039H
003AH
003BH
003CH
003DH
003EH
003FH
PUL9
—
Port 9 pull-up register
R/W 00000000B
(Disabled)
—
—
T01CR1
T00CR1
T11CR1
T10CR1
PC01
8/16-bit composite timer 01 status control register 1 ch. 0
8/16-bit composite timer 00 status control register 1 ch. 0
8/16-bit composite timer 11 status control register 1 ch. 1
8/16-bit composite timer 10 status control register 1 ch. 1
8/16-bit PPG01 control register ch. 0
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
PC00
8/16-bit PPG00 control register ch. 0
PC11
8/16-bit PPG11 control register ch. 1
PC10
8/16-bit PPG10 control register ch. 1
TMCSRH
TMCSRL
16-bit reload timer control status register upper ch. 0
16-bit reload timer control status register lower ch. 0
0040H
to
—
(Disabled)
—
—
0047H
0048H
0049H
004AH
004BH
EIC00
EIC10
EIC20
EIC30
External interrupt circuit control register ch. 0/ch. 1
External interrupt circuit control register ch. 2/ch. 3
External interrupt circuit control register ch. 4/ch. 5
External interrupt circuit control register ch. 6/ch. 7
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
004CH,
004DH
—
(Disabled)
—
—
004EH
004FH
LVDR
LVDC
LVD reset voltage selection ID register
LVD control register
R/W 00000000B
R/W X000000XB
0050H
to
—
(Disabled)
—
—
0055H
0056H
0057H
0058H
0059H
005AH
005BH
005CH
005DH
005EH
005FH
SMC10
SMC20
SSR0
UART/SIO serial mode control register 1 ch. 0
UART/SIO serial mode control register 2 ch. 0
UART/SIO serial status register ch. 0
UART/SIO output data register ch. 0
R/W 00000000B
R/W 00100000B
R/W 00000001B
R/W 00000000B
TDR0
RDR0
SMC11
SMC21
SSR1
UART/SIO input data register ch. 0
R
00000000B
UART/SIO serial mode control register 1 ch. 1
UART/SIO serial mode control register 2 ch. 1
UART/SIO serial status register ch. 1
UART/SIO output data register ch. 1
R/W 00000000B
R/W 00100000B
R/W 00000001B
R/W 00000000B
TDR1
RDR1
UART/SIO input data register ch. 1
R
00000000B
(Continued)
36
DS07-12628-2E
MB95310L/370L Series
Register
abbreviation
Address
Register name
R/W Initial value
0060H
0061H
0062H
0063H
0064H
0065H
IBCR00
IBCR10
IBCR0
IDDR0
IAAR0
ICCR0
I2C bus control register 0
I2C bus control register 1
I2C bus status register
I2C data register
R/W 00000001B
R/W 00000000B
R
00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
I2C address register
I2C clock control register
0066H
to
—
(Disabled)
—
—
006BH
006CH
006DH
006EH
006FH
0070H
0071H
0072H
0073H
0074H
0075H
0076H
0077H
ADC1
ADC2
ADDH
ADDL
WCSR
FSR2
FSR
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register upper
8/10-bit A/D converter data register lower
Watch counter status register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 000X0000B
R/W 00000000B
Flash memory status register 2
Flash memory status register
SWRE0
FSR3
—
Flash memory sector write control register 0
Flash memory status register 3
R
00000000B
—
(Disabled)
—
WREN
WROR
Wild register address compare enable register
Wild register data test setting register
R/W 00000000B
R/W 00000000B
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
0078H
—
—
—
0079H
007AH
007BH
007CH
007DH
007EH
007FH
0F80H
0F81H
0F82H
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
ILR0
ILR1
ILR2
ILR3
ILR4
ILR5
—
Interrupt level setting register 0
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Interrupt level setting register 4
Interrupt level setting register 5
(Disabled)
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
—
—
WRARH0 Wild register address setting register (upper) ch. 0
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
(Continued)
WRARL0
WRDR0
Wild register address setting register (lower) ch. 0
Wild register data setting register ch. 0
WRARH1 Wild register address setting register (upper) ch. 1
WRARL1
WRDR1
Wild register address setting register (lower) ch. 1
Wild register data setting register ch. 1
WRARH2 Wild register address setting register (upper) ch. 2
WRARL2
WRDR2
Wild register address setting register (lower) ch. 2
Wild register data setting register ch. 2
DS07-12628-2E
37
MB95310L/370L Series
Register
abbreviation
Address
Register name
R/W Initial value
0F89H
to
—
(Disabled)
—
—
0F91H
0F92H
0F93H
0F94H
0F95H
T01CR0
T00CR0
T01DR
T00DR
8/16-bit composite timer 01 status control register 0 ch. 0
8/16-bit composite timer 00 status control register 0 ch. 0
8/16-bit composite timer 01 data register ch. 0
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
8/16-bit composite timer 00 data register ch. 0
8/16-bit composite timer 00/01 timer mode control register
ch. 0
0F96H
TMCR0
R/W 00000000B
0F97H
0F98H
0F99H
0F9AH
T11CR0
T10CR0
T11DR
T10DR
8/16-bit composite timer 11 status control register 0 ch. 1
8/16-bit composite timer 10 status control register 0 ch. 1
8/16-bit composite timer 11 data register ch. 1
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
8/16-bit composite timer 10 data register ch. 1
8/16-bit composite timer 10/11 timer mode control register
ch. 1
0F9BH
TMCR1
R/W 00000000B
0F9CH
0F9DH
0F9EH
0F9FH
0FA0H
0FA1H
0FA2H
0FA3H
0FA4H
0FA5H
PPS01
PPS00
PDS01
PDS00
PPS11
PPS10
PDS11
PDS10
PPGS
8/16-bit PPG01 cycle setting buffer register ch. 0
8/16-bit PPG00 cycle setting buffer register ch. 0
8/16-bit PPG01 duty setting buffer register ch. 0
8/16-bit PPG00 duty setting buffer register ch. 0
8/16-bit PPG11 cycle setting buffer register ch. 1
8/16-bit PPG10 cycle setting buffer register ch. 1
8/16-bit PPG11 duty setting buffer register ch. 1
8/16-bit PPG10 duty setting buffer register ch. 1
8/16-bit PPG start register
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
REVC
8/16-bit PPG output inversion register
TMRH0
16-bit reload timer timer register upper
0FA6H
0FA7H
TMRLRH0 16-bit reload timer reload register upper
TMRL0 16-bit reload timer timer register lower
TMRLRL0 16-bit reload timer reload register lower
0FA8H
to
—
(Disabled)
—
—
0FBDH
UART/SIO dedicated baud rate generator prescaler selecting
register ch. 0
0FBEH
0FBFH
0FC0H
0FC1H
PSSR0
BRSR0
PSSR1
BRSR1
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
UART/SIO dedicated baud rate generator baud rate setting
register ch. 0
UART/SIO dedicated baud rate generator prescaler selecting
register ch. 1
UART/SIO dedicated baud rate generator baud rate setting
register ch. 1
0FC2H
0FC3H
0FC4H
—
(Disabled)
A/D input disable register (lower)
LCDC control register
—
—
AIDRL
LCDCC
R/W 00000000B
R/W 00010000B
(Continued)
38
DS07-12628-2E
MB95310L/370L Series
(Continued)
Register
abbreviation
Address
Register name
R/W Initial value
0FC5H
0FC6H
0FC7H
0FC8H
0FC9H
0FCAH
0FCBH
0FCCH
LCDCE1
LCDCE2
LCDCE3
LCDCE4
LCDCE5
—
LCDC enable register 1
LCDC enable register 2
LCDC enable register 3
LCDC enable register 4
LCDC enable register 5
R/W 00110000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
(Disabled)
—
—
LCDCB1
LCDCB2
LCDC blinking setting register 1
LCDC blinking setting register 2
R/W 00000000B
R/W 00000000B
0FCDH
to
0FDCH
LCDRAM
—
LCDC display RAM
R/W 00000000B
0FDDH
to
(Disabled)
—
—
0FE1H
0FE2H
0FE3H
0FE4H
0FE5H
EVCR
WCDR
CRTH
CRTL
Event counter control register
R/W 00000000B
R/W 00111111B
R/W 0XXXXXXXB
R/W 00XXXXXXB
Watch counter data register
Main CR clock trimming register (upper)
Main CR clock trimming register (lower)
0FE6H
to
—
(Disabled)
—
—
0FE8H
0FE9H
0FEAH
0FEBH
0FECH
0FEDH
0FEEH
0FEFH
CMCR
CMDR
WDTH
WDTL
—
Clock monitoring control register
Clock monitoring data register
Watchdog timer selection ID register (upper)
Watchdog timer selection ID register (lower)
(Disabled)
R/W XX000000B
R
R
00000000B
XXXXXXXXB
XXXXXXXXB
—
R
—
ILSR
Input level select register
R/W 00000000B
R/W 01000000B
WICR
Interrupt pin control register
0FF0H
to
—
(Disabled)
—
—
0FFFH
• R/W access symbols
R/W : Readable / Writable
: Read only
R
• Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is indeterminate.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
DS07-12628-2E
39
MB95310L/370L Series
■ INTERRUPT SOURCE TABLE
Vector table address
Priority order of in-
terrupt sources of
the same level
Interrupt
request
number
Bit name of
Interrupt source
interrupt level
Upper
FFFAH
FFF8H
FFF6H
FFF4H
FFF2H
Lower
FFFBH
FFF9H
FFF7H
FFF5H
FFF3H
setting register (occurring simul-
taneously)
External interrupt ch. 0
External interrupt ch. 4
External interrupt ch. 1
External interrupt ch. 5
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
UART/SIO ch. 0
High
IRQ00
IRQ01
IRQ02
IRQ03
IRQ04
L00 [1:0]
L01 [1:0]
L02 [1:0]
L03 [1:0]
L04 [1:0]
Low-voltage detection reset circuit
8/16-bit composite timer ch. 0
(lower)
IRQ05
IRQ06
FFF0H
FFEEH
FFF1H
FFEFH
L05 [1:0]
L06 [1:0]
8/16-bit composite timer ch. 0
(upper)
—
IRQ07
IRQ08
FFECH
FFEAH
FFEDH
FFEBH
L07 [1:0]
L08 [1:0]
—
8/16-bit PPG ch. 1 (lower)
UART/SIO ch. 1
IRQ09
FFE8H
FFE9H
L09 [1:0]
8/16-bit PPG ch. 1 (upper)
16-bit reload timer ch. 0
8/16-bit PPG ch. 0 (upper)
8/16-bit PPG ch. 0 (lower)
IRQ10
IRQ11
IRQ12
IRQ13
FFE6H
FFE4H
FFE2H
FFE0H
FFE7H
FFE5H
FFE3H
FFE1H
L10 [1:0]
L11 [1:0]
L12 [1:0]
L13 [1:0]
8/16-bit composite timer ch. 1
(upper)
IRQ14
FFDEH
FFDFH
L14 [1:0]
—
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
FFDCH
FFDAH
FFD8H
FFD6H
FFD4H
FFDDH
FFDBH
FFD9H
FFD7H
FFD5H
L15 [1:0]
L16 [1:0]
L17 [1:0]
L18 [1:0]
L19 [1:0]
I2C
—
8/10-bit A/D converter
Time-base timer
Watch prescaler
Watch counter
—
IRQ20
FFD2H
FFD3H
L20 [1:0]
IRQ21
IRQ22
IRQ23
FFD0H
FFCEH
FFCCH
FFD1H
FFCFH
FFCDH
L21 [1:0]
L22 [1:0]
8/16-bit composite timer ch. 1
(lower)
Low
Flash memory
L23 [1:0]
40
DS07-12628-2E
MB95310L/370L Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
Power supply voltage*1
VCC, AVCC
VSS − 0.3
VSS − 0.3
VSS + 4.0
V
V
*2
Powersupplyvoltagefor
LCD
Products with LCD internal division
resistance*3
V0 to V3
VSS + 4.0
VSS − 0.3
VSS − 0.3
VSS − 0.3
−2.0
VSS + 6.0
VSS + 4.0
VSS + 4.0
+2.0
V
V
V
P23,P24*4
Other than P23,P24*4
Input voltage*1
VI
Output voltage*1
VO
*4
Maximum clamp current
ICLAMP
mA Applicable to specific pins*5
Total maximum clamp
current
Σ|ICLAMP|
—
—
20
15
mA Applicable to specific pins*5
“L” level maximum
output current
IOL
mA Applicable to specific pins*5
Applicable to specific pins*5
Average output current =
operating current × operating ratio
(1 pin)
“L” level average current
IOLAV
—
4
mA
“L” level total maximum
output current
ΣIOL
ΣIOLAV
IOH
—
—
—
100
50
mA
Total average output current =
mA operating current × operating ratio
(Total number of pins)
“L” level total average
output current
“H” level maximum
output current
-15
mA Applicable to specific pins*5
Applicable to specific pins*5
“H” level average
current
Average output current =
mA
IOHAV
—
-4
operating current × operating ratio
(1 pin)
“H” level total maximum
output current
ΣIOH
—
—
-100
-50
mA
Total average output current =
mA operating current × operating ratio
(Total number of pins)
“H” level total average
output current
ΣIOHAV
Power consumption
Operating temperature
Storage temperature
Pd
TA
—
320
+85
mW
°C
−40
−55
Tstg
+150
°C
*1: These parameters are based on the condition that VSS is 0.0 V.
*2: Apply equal potential to VCC and AVCC.
*3: V0 to V3 should not exceed VCC + 0.3 V.
*4: VI and VO must not exceed VCC + 0.3 V. VI must not exceed the rated voltage. However, if the maximum
current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of
the VI rating.
(Continued)
DS07-12628-2E
41
MB95310L/370L Series
(Continued)
*5: Applicable to the following pins: P00 to P07, P10, P11, P13 to P16, P20 to P22, P40 to P43, P50 to P53,
P60 to P67, P90 to P95, PA0 to PA3, PB0 to PB7, PC0 to PC7, PE0 to PE7, PG0
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor
between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistance should be set so that when the HV (High Voltage) signal is applied the
inputcurrentto the microcontroller pindoes notexceed ratedvalues, eitherinstantaneouslyor for prolonged
periods.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High
Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin, and
thus affects other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since
power is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage
of power supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit
• Input/Output equivalent circuit
Protective diode
VCC
P-ch
Limiting
resistor
HV(High Voltage) input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
42
DS07-12628-2E
MB95310L/370L Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Value
Parameter
Symbol
Unit
Remarks
Min
Max
In normal operation,
TA = -10°C to +85°C
1.8*1*2*3
3.6
Other than on-chip debug
mode
In normal operation,
TA = -40°C to +85°C
2.0
3.6
Power supply
voltage
VCC,
AVCC
V
1.5
3.10*3
1.5
3.6
3.6
Hold condition in stop mode
TA = +5°C to +35°C
On-chip debug mode
3.6
Hold condition in stop mode
−40
+5
+85
+35
Other than on-chip debug mode
On-chip debug mode
Operating
temperature
TA
°C
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range.
*2: The value is initially 2.03 V when the low-voltage detection reset is used.
*3: The threshold voltage can be set to be 2.03 V, 2.55 V, 3.10 V by software.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
onthedatasheet.Usersconsideringapplicationoutsidethelistedconditionsareadvisedtocontact
their representatives beforehand.
DS07-12628-2E
43
MB95310L/370L Series
3. DC Characteristics
(VCC = 3.0 V 10%, VSS = 0.0 V, TA = -40°C to +85°C)
Value
Typ*5
Parameter Symbol
Pin name
Condition
Unit
Remarks
Min
Max
P10, P95*1,
PE6*2
VIHI1
VIHI2
*3
*3
0.7 VCC
0.7 VCC
—
VCC + 0.3
VSS + 5.5
V
V
When selecting
CMOS input level
P23, P24
—
P00 to P07,
P10 to P16,
P20 to P22,
P40 to P43*1,
P50 to P53*1,
P60 to P67,
P90 to P92,
P93 to P95*1,
PA0 to PA3,
PB0 to PB7,
PC0 to PC3,
PC4 to PC7*1,
PE0 to PE7,
PG0*1
“H” level
input voltage
VIHS1
*3
0.8 VCC
—
VCC + 0.3
V
Hysteresis input
VIHS2 P23, P24
*3
—
0.8 VCC
0.8 VCC
—
—
VSS + 5.5
VCC + 0.3
V
V
VIHM
RST
P10, P23, P24,
P95*1, PE6*2
When selecting
CMOS input level
VIL
*3
VSS − 0.3
—
0.3 VCC
V
P00 to P07,
P10 to P16,
P20 to P24,
P40 to P43*1,
P50 to P53*1,
P60 to P67,
P90 to P92,
P93 to P95*1,
PA0 to PA3,
PB0 to PB7,
PC0 to PC3,
PC4 to PC7*1,
PE0 to PE7,
PG0*1
“L” level
input voltage
VILS
*3
—
VSS − 0.3
—
0.2 VCC
V
Hysteresis input
VILM
VOH
RST
VSS − 0.3
—
—
0.2 VCC
—
V
V
“H” level
output
voltage
Output pin other
than P12, P23,
P24
IOH = 4.0 mA VCC − 0.5
“L” level
output
voltage
Output pin other
than RST
VOL
IOL = 4.0 mA
—
—
0.4
V
(Continued)
44
DS07-12628-2E
MB95310L/370L Series
(VCC = 3.0 V 10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter
Symbol
Pin name
Condition
Unit
Remarks
Min
Typ*5
Max
Inputleakage
current (Hi-Z
output
When pull-up
µA resistance is
disabled
Ports otherthan
P12, P23, P24
ILI
0.0 V<VI<VCC
−5
—
+5
leakage
current)
Open-drain
output
leakage
voltage
ILIOD
P12, P23, P24 0.0 V<VI<VSS + 5.5 V
—
—
5
µA
P00 to P03,
P10, P11,
P13 to P16,
When pull-up
kΩ resistance is
enabled
Pull-up
resistance
RPULL P20 to P22,
P50 to P53*1,
P94, P95*1,
VI = 0.0 V
f = 1 MHz
25
50
5
100
15
PG0*1
Input
capacitance
Other than VCC
and VSS
CIN
—
—
pF
Except during
Flash memory
programming
16.5 27.7
38.1 44.9
mA
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
and erasing
ICC
During Flash
memory
mA
—
—
programming
and erasing
VCC
Powersupply
current*4
(External clock
operation)
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
ICCS
9
15.9
mA
FCL = 32 kHz
FMPL = 16 kHz
Subclock mode
(divided by 2)
TA = +25°C
ICCL
—
22.6 37.9
µA
(Continued)
DS07-12628-2E
45
MB95310L/370L Series
(VCC = 3.0 V 10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter
Symbol
Pin name
Condition
Unit
Remarks
Typ*5
Min
Max
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = +25°C
ICCLS
—
11.2 16.5
µA
FCL = 32 kHz
Watch mode
Main stop mode
TA = +25°C
ICCT
—
—
—
6.7
9
µA
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
10.1 19.2
16.2 30.7
mA
ICCMPLL
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
VCC
(External clock
operation)
mA
mA
FCRH = 12.5 MHz
FMP = 12.5 MHz
Main CR clock mode
ICCMCR
—
—
7.9
13.2
Powersupply
current*4
Sub-CR clock mode
(divided by 2)
ICCSCR
77.8 138.5 µA
TA = +25°C
FCH = 32 MHz
Time-base timer
mode
ICTS
ICCH
IA
—
—
—
4.3
1
7.4
5
mA
µA
TA = +25°C
Substop mode
TA = +25°C
Current
consumption for
A/D conversion at
16 MHz
0.8
1.9
mA
AVCC
Current
consumption for
stopping A/D
conversion at
16 MHz
IAH
—
1
5
µA
(Continued)
46
DS07-12628-2E
MB95310L/370L Series
(Continued)
(VCC = 3.0 V 10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter
Symbol
Pin name
Condition
Current
Unit
Remarks
Typ*5
Min
Max
consumption for the
low-voltage
ILVD
—
6
9.8
µA
detection reset
circuit
Current
consumption for the
main CR oscillator
Powersupply
current*4
ICRH
VCC
—
—
0.5
20
0.6
72
mA
µA
Current
consumption for the
sub-CR oscillator
oscillating at
100 kHz
ICRL
LCD internal
division
resistance
RLCD
—
Between V3 and VSS
—
—
300
—
—
5
kΩ
kΩ
COM0 to
COM3 output RVCOM COM0 to COM3
impedance
V1 to V3 = 3.6 V
SEG00 to
SEG39
output
impedance
SEG00 to
SEG39
RVSEG
—
—
—
7
kΩ
V0 to V3,
COM0 to
COM3, SEG00
to SEG39
LCD leakage
current
ILCDL
—
−1
+1
µA
*1: It is for MB95310L Series.
*2: It is for MB95370L Series.
*3: The input level can be switched between “CMOS input level” and “hysteresis input level”. The input level
selection register (ILSR) is used to switch between the two input levels.
*4: • The power supply current is determined by the external clock. When the low-voltage detection option is
selected, the power-supply current will be the sum of adding the current consumption of the low-voltage
detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection
option and the CR oscillator are selected, the power supply current will be the sum of adding up the current
consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL)
and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit
are always enabled, and current consumption therefore increases accordingly.
• See “4. AC Characteristics: (1) Clock Timing” for FCH and FCL.
• See “4. AC Characteristics: (2) Source Clock/Machine Clock” for FMP and FMPL.
*5: VCC = 3.0 V, TA = +25°C
DS07-12628-2E
47
MB95310L/370L Series
4. AC Characteristics
(1) Clock Timing
(VCC = 3.0 V 10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter Symbol Pin name Condition
Min
Unit
Remarks
Typ
Max
When the main oscillation
circuit is used
1.00
1.00
—
16.25 MHz
32.50 MHz
When the main external
clock is used
—
FCH
X0, X1
3.00
3.00
3.00
12.25
9.8
—
—
—
12.5
10
8
8.13
6.5
MHz Main PLL multiplied by 2
MHz Main PLL multiplied by 2.5
MHz Main PLL multiplied by 4
4.06
12.75 MHz
Operating conditions:
• The main CR clock is used.
• TA = −10°C to +85°C
10.2
8.16
1.02
MHz
MHz
MHz
—
—
7.84
0.98
Clock
—
1
frequency
FCRH
12.1875 12.5 12.8125 MHz
Operating conditions:
9.75
7.8
10
8
10.25 MHz
• The main CR clock is used.
• TA = −40°C to −10°C
8.2
MHz
0.975
1
1.025 MHz
When the sub-oscillation
circuit is used
—
—
32.768
32.768
100
—
—
kHz
kHz
kHz
ns
FCL
X0A, X1A
—
When the sub-external clock
is used
When the sub-CR clock is
used
FCRL
50
200
1000
When the main oscillation
circuit is used
61.5
—
tHCYL
X0, X1
Clock cycle
time
—
—
When the external clock is
used
30.8
—
—
30.5
—
1000
—
ns
tLCYL
X0A, X1A
X0
µs When the subclock is used
tWH1
tWL1
61.5
—
ns
µs
When using external clock
and the duty ratio is about
30% to 70%
Input clock
pulse width
tWH2
tWL2
X0A
—
—
15.2
—
—
5
Input clock
rise time
and fall time
tCR
tCF
When the external clock is
used
X0, X0A X1: open
ns
When the main CR clock is
used
tCRHWK
tCRLWK
—
—
—
—
—
—
—
—
150
10
µs
µs
CR
oscillation
start time
When the sub-CR clock is
used
48
DS07-12628-2E
MB95310L/370L Series
• Input waveform generated when an external clock (main clock) is used
t
HCYL
t
WH1
t
WL1
t
CR
tCF
X0, X1
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When a crystal oscillator or When the external clock is used When the external clock is used
a ceramic oscillator is used (X1 is open)
X0
X1
X0
X1
X0
X1
Open
FCH
F
CH
FCH
• Input waveform generated when an external clock (subclock) is used
t
LCYL
tWH2
t
WL2
t
CR
t
CF
X0A
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
When the external clock is used
X0A X1A
X0A X1A
Open
F
CL
FCL
DS07-12628-2E
49
MB95310L/370L Series
(2) Source Clock/Machine Clock
(VCC = 3.0 V 10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Pin
Parameter
Symbol
Unit
Remarks
name
Min
Typ
Max
When the main oscillation clock is used
Min: FCH = 8.125 MHz, multiplied by the
PLL multiplier of 2
61.5
—
2000
ns
Max: FCH = 1 MHz, divided by 2
When the main CR clock is used
ns Min: FCRH = 12.5 MHz
Max: FCRH = 1 MHz
Source clock
cycle time*1
80
—
1000
tSCLK
—
When the sub-oscillation clock is used
FCL = 32.768 kHz, divided by 2
—
—
61
20
—
—
µs
When the sub-CR clock is used
µs
FCRL = 100 kHz, divided by 2
0.50
1
—
—
16.25 MHz When the main oscillation clock is used
FSP
12.5
—
MHz When the main CR clock is used
Source clock
frequency
—
—
—
—
16.384
kHz When the sub-oscillation clock is used
FSPL
When the sub-CR clock is used
kHz
—
50
—
FCRL = 100 kHz, divided by 2
When the main oscillation clock is used
ns Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
61.5
—
32000
When the main CR clock is used
ns Min: FSP = 12.5 MHz
Machine clock
cycle time*2
(minimum
instruction
execution
time)
80
61
20
—
—
—
16000
976.5
320
Max: FSP = 1 MHz, divided by 16
tMCLK
When the sub-oscillation clock is used
µs Min: FSPL = 16.393 kHz, no division
Max: FSPL = 16.393 kHz, divided by 16
When the sub-CR clock is used
µs Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
0.031
0.0625
1.024
—
—
—
16.25 MHz When the main oscillation clock is used
12.5 MHz When the main CR clock is used
FMP
Machine clock
frequency
16.384 kHz When the sub-oscillation clock is used
When the sub-CR clock is used
FMPL
3.125
—
50
kHz
FCRL = 100 kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock divide ratio select
bits (SYCC:DIV1 and DIV0). This source clock is divided to become a machine clock according to the division
ratio set by the machine clock divide ratio select bits (SYCC:DIV1 and DIV0). In addition, a source clock can
be selected from the following.
• Main clock divided by 2
• PLL multiplication of main clock (select from 2, 2.5, 4 multiplication)
• Main CR clock divided by 2
• Subclock divided by 2
• Sub-CR clock divided by 2
(Continued)
50
DS07-12628-2E
MB95310L/370L Series
(Continued)
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
• Schematic diagram of the clock generation block
Main PLL
× 2
× 2.5
× 4
Divided
by 2
FCH
(main oscillation)
Division
circuit
FCRH
(Main CR clock)
MCLK
SCLK
(source clock)
×
1
Divided
by 2
× 1/4
× 1/8
×1/16
(machine clock)
FCL
(sub-oscillation)
Divided
by 2
FCRL
(Sub-CR clock)
Clock mode select bits
(SYCC2: RCS1, RCS0)
Machine clock divide ratio select bits
(SYCC: DIV1, DIV0)
DS07-12628-2E
51
MB95310L/370L Series
• Operating voltage - Operating frequency (When TA = −10°C to +85°C)
Without the on-chip debug function
3.6
2.7
1.8
16 kHz
3 MHz
5 MHz
16.25 MHz
Source clock frequency (FSP/FSPL
)
• Operating voltage - Operating frequency (When TA = −40°C to +85°C)
Without the on-chip debug function
3.6
2.7
2.0
16 kHz
3 MHz
7.5 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
52
DS07-12628-2E
MB95310L/370L Series
• Operating voltage - Operating frequency (When TA = +5°C to +35°C)
With the on-chip debug function
3.6
*3
2.7
*1
2.03
*2
*4
16 kHz
3 MHz
7.875 MHz
16.25 MHz
Source clock frequency (FSP
)
*1: This is the default LVD reset clear threshold: 1.93 V 0.10 V. It can also be set to 2.40 V 0.15 V or
2.95 V 0.15 V.
*2: If the LVD reset clear threshold is set to 2.95 V 0.15 V, the slope from 10 MHz to 16.25 MHz should be a
horizontal line.
*3: The operating voltage becomes 3.1 V if the LVD reset clear threshold is set to 2.95 V 0.15 V.
*4: The source clock frequency becomes 14.375 MHz if the LVD reset clear threshold is set to 2.40 V 0.15 V.
DS07-12628-2E
53
MB95310L/370L Series
(3) External Reset
(VCC = 3.0 V 10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter
Symbol
Unit
Remarks
Min
Max
2 tMCLK*1
—
ns In normal operation
In stop mode, subclock mode,
µs subsleep mode, watch mode, and
power-on
RST “L” level
pulse width
Oscillation time of the
tRSTL
—
—
oscillator*2 + 100
100
µs In time-base timer mode
*1: See “(2) Source Clock/Machine Clock” for tMCLK.
*2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has
an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of
between hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator
clock has an oscillation time of between several µs and several ms.
• In normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, subclock mode, subsleep mode, watch mode and power-on
t
RSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
100 μs
Oscillation
time of
oscillator
Oscillation stabilization wait time
Internal reset
Execute instruction
54
DS07-12628-2E
MB95310L/370L Series
(4) Power-on Reset
Parameter
(VSS = 0.0 V, TA = −40°C to +85°C)
Value
Symbol
Condition
Unit
Remarks
Min
—
1
Max
50
Power supply rising time
Power supply cutoff time
tR
—
—
ms
tOFF
—
ms Wait time until power-on
t
R
tOFF
1.5 V
0.2 V
0.2 V
0.2 V
VCC
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the
power supply voltage during the operation, set the slope of rising to a value below within 20 mV/ms as
shown below.
VCC
Set the slope of rising to
a value below 20 mV/ms.
1.5 V
Hold condition in stop mode
V
SS
DS07-12628-2E
55
MB95310L/370L Series
(5) Peripheral Input Timing
(VCC = 3.0 V 10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter
Symbol
Pin name
Unit
Min
Max
—
*
*
Peripheral input “H” pulse width
Peripheral input “L” pulse width
tILIH
2 tMCLK
2 tMCLK
ns
ns
INT00 to INT07, EC0, EC1,
ADTG
tIHIL
—
*: See “(2) Source Clock/Machine Clock” for tMCLK.
t
ILIH
t
IHIL
0.8 VCC 0.8 VCC
INT00 to INT07,
EC0, EC1, ADTG
0.2 VCC
0.2 VCC
56
DS07-12628-2E
MB95310L/370L Series
(6) UART/SIO, Serial I/O Timing
(VCC = 3.0 V 10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter
Serial clock cycle time
UCK ↓→ UO time
Symbol
Pin name
Condition
Unit
ns
Min
Max
tSCYC
UCK0, UCK1
UCK0, UCK1,
UO0, UO1
4 tMCLK*
—
tSLOVI
−190
+190
—
ns
Internal clock
operation output pin:
CL = 80 pF + 1 TTL
UCK0, UCK1,
UI0, UI1
UCK0, UCK1,
UI0, UI1
UCK0, UCK1
UCK0, UCK1
Valid UI → UCK ↑
tIVSHI
2 tMCLK*
2 tMCLK*
ns
ns
UCK ↑→ valid UI hold time
tSHIXI
tSHSL
tSLSH
—
Serial clock “H” pulse width
Serial clock “L” pulse width
4 tMCLK*
4 tMCLK*
—
—
ns
ns
UCK0, UCK1,
UO0, UO1
UCK0, UCK1,
UI0, UI1
UCK ↓→ UO time
tSLOVE
tIVSHE
tSHIXE
External clock
operation output pin:
CL = 80 pF + 1 TTL
—
190
—
ns
ns
ns
Valid UI → UCK ↑
2 tMCLK*
2 tMCLK*
UCK0, UCK1,
UI0, UI1
UCK ↑→ valid UI hold time
—
*: See “(2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
t
SCYC
2.4 V
UCK0,
UCK1
0.8 V
0.8 V
t
SLOVI
2.4 V
UO0,
UO1
0.8 V
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
UI0,
UI1
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
UCK0,
UCK1
0.2 VCC
0.2 VCC
t
SLOVE
2.4 V
0.8 V
UO0,
UO1
tIVSHE
tSHIXE
0.8 VCC 0.8 VCC
UI0,
UI1
0.2 VCC 0.2 VCC
DS07-12628-2E
57
MB95310L/370L Series
(7) Low-voltage Detection
(VSS = 0.0 V, VCC = 1.8 V to 3.6 V, TA = −40°C to +85°C)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
1.83
1.80
2.25
2.20
2.80
2.70
2.03
2.00
2.25
2.20
2.46
2.40
2.67
2.60
2.90
2.80
—
Max
2.03
2.00
2.55
2.50
3.10
3.00
2.33
2.30
2.55
2.50
2.76
2.70
2.97
2.90
3.30
3.20
1.8
Power release voltage 0
Power detection voltage 0
Power release voltage 1
Power detection voltage 1
Power release voltage 2
Power detection voltage 2
Interrupt release voltage 0
Interrupt detection voltage 0
Interrupt release voltage 1
Interrupt detection voltage 1
Interrupt release voltage 2
Interrupt detection voltage 2
Interrupt release voltage 3
Interrupt detection voltage 3
Interrupt release voltage 4
Interrupt detection voltage 4
Power supply start voltage
Power supply end voltage
VPDL0+
VPDL0-
VPDL1+
VPDL1-
VPDL2+
VPDL2-
VIDL0+
VIDL0-
VIDL1+
VIDL1-
VIDL2+
VIDL2-
VIDL3+
VIDL3-
VIDL4+
VIDL4-
Voff
1.93
1.90
2.40
2.35
2.95
2.85
2.18
2.15
2.40
2.35
2.61
2.55
2.82
2.75
3.10
3.00
—
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
At power supply rise
At power supply fall
At power supply rise
At power supply fall
At power supply rise
At power supply fall
At power supply rise
At power supply fall
At power supply rise
At power supply fall
At power supply rise
At power supply fall
At power supply rise
At power supply fall
At power supply rise
At power supply fall
Von
3.3
—
—
Power supply voltage
change time
(at power supply rise)
Slope of power supply that the reset
µs release signal generates within the
rating (VPDL+/VIDL+)
tr
tf
3000
3000
—
—
—
—
Power supply voltage
change time
(at power supply fall)
Slope of power supply that the reset
µs detection signal generates within
the rating (VPDL-/VIDL-)
(Continued)
58
DS07-12628-2E
MB95310L/370L Series
(Continued)
(VSS = 0.0 V, VCC = 1.8 V to 3.6 V, TA = −40°C to +85°C)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
Power reset release delay
time
tdp1
tdp2
tdi1
tdi2
10
—
—
—
—
300
µs
µs
µs
µs
Power reset detection
delay time
—
10
—
150
200
150
Interrupt reset release
delay time
Interrupt reset detection
delay time
VCC
Von
Voff
time
tf
tr
VCC
VPDL+/VIDL+
V
PDL-/VIDL-
Reset/Interrupt
time
tdp2/tdi2
tdp1/tdi1
DS07-12628-2E
59
MB95310L/370L Series
(8) I2C Timing
(VCC = 3.0 V 10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter Symbol Pin name Conditions
Standard-mode
Min Max
Fast-mode
Unit
Min
Max
SCL clock
frequency
fSCL
SCL0
0
100
0
400
kHz
(Repeat)
Start
condition
hold time
SDA ↓ →
SCL ↓
SCL0,
SDA0
tHD;STA
4.0
—
0.6
—
µs
SCL clock
“L” width
tLOW
tHIGH
SCL0
SCL0
4.7
4.0
—
—
1.3
0.6
—
—
µs
µs
SCL clock
“H” width
(Repeat)
Start
condition
setup time
SCL ↑ →
SDA ↓
SCL0,
SDA0
tSU;STA
4.7
—
0.6
—
µs
R = 1.7 kΩ,
Data hold
time
SCL ↓ →
SDA ↓ ↑
C = 50 pF*1
SCL0,
SDA0
tHD;DAT
0
3.45*2
—
0
0.9*3
—
µs
µs
Data setup
time
SDA ↓ ↑ →
SCL ↑
SCL0,
SDA0
tSU;DAT
0.25
0.1
Stop
condition
setup time
SCL ↑ →
SDA ↑
SCL0,
SDA0
tSU;STO
4.0
4.7
—
—
0.6
1.3
—
—
µs
µs
Bus free
time
between
stop
condition
and start
condition
SCL0,
SDA0
tBUF
*1: R represents the pull-up resistor of the SCL0 and SDA0 lines, and C the load capacitor of the SCL0 and
SDA0 lines.
*2: The maximum tHD;DAT in the Standard-modeis applicable only when the time during which the device is holding
the SCL signal at “L” (tLOW) does not extend.
*3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition
of tSU;DAT ≥ 250 ns is fulfilled.
(Continued)
60
DS07-12628-2E
MB95310L/370L Series
(Continued)
Note: The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending
on the load capacitance or pull-up resistor.
Be sure to adjust the pull-up resistor of SDA0 and SCL0 if the rating of the input data set-up time cannot be
satisfied.
tWAKEUP
SDA0
tHD;STA
tHD;DAT
tHIGH
tBUF
tLOW
SCL0
tSU;STO
tHD;STA
tSU;DAT
fSCL
tSU;STA
DS07-12628-2E
61
MB95310L/370L Series
(VCC = 3.0 V 10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value*2
Parameter Symbol Pin name Conditions
Unit
Remarks
Min
Max
SCL clock
“L” width
(2 + nm / 2) tMCLK − 20
(nm / 2)tMCLK − 20
tLOW
tHIGH
SCL0
SCL0
—
ns Master mode
ns Master mode
SCL clock
“H” width
(nm / 2)tMCLK + 20
Master mode
Maximum
value is
Start
condition
hold time
applied when
ns m, n = 1, 8.
Otherwise,
the minimum
value is
SCL0,
SDA0
(−1 + nm / 2) tMCLK − 20 (−1 + nm)tMCLK + 20
tHD;STA
applied.
Stop
condition
setup time
SCL0,
SDA0
(1 + nm / 2) tMCLK − 20 (1 + nm / 2)tMCLK + 20
tSU;STO
ns Master mode
Start
condition
setup time
SCL0,
SDA0
tSU;STA
(1 + nm / 2)tMCLK − 20 (1 + nm / 2)tMCLK + 20 ns Master mode
Busfreetime
between
stop
condition
and start
condition
R = 1.7 kΩ,
C = 50 pF*1
SCL0,
SDA0
(2 nm + 4)tMCLK − 20
tBUF
—
—
ns
Data hold
time
SCL0,
SDA0
3 tMCLK − 20
tHD;DAT
ns Master mode
Master mode
When
assuming that
“L” of SCL is
not extended,
the minimum
value is
Data setup
time
SCL0,
SDA0
(−2 + nm / 2)tMCLK − 20 (−1 + nm / 2)tMCLK + 20
tSU;DAT
ns applied to first
bit of
continuous
data.
Otherwise,
the maximum
value is
applied.
(Continued)
62
DS07-12628-2E
MB95310L/370L Series
(VCC = 3.0 V 10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value*2
Parameter Symbol Pin name Conditions
Unit
Remarks
Min
Max
Minimum
value is
Setup time
between
clearing
interrupt
and SCL
rising
applied to
interrupt at
9th SCL↓.
Maximum
value is
applied to
interrupt at
8th SCL↓.
(nm / 2)tMCLK − 20
(1 + nm / 2)tMCLK + 20
tSU;INT
SCL0
ns
SCL clock
“L” width
tLOW
tHIGH
SCL0
SCL0
4 tMCLK − 20
4 tMCLK − 20
—
—
ns At reception
SCL clock
“H” width
ns At reception
Not detected
Start
condition
detection
SCL0,
SDA0
when 1 tMCLK
is used at
2 tMCLK − 20
2 tMCLK − 20
2 tMCLK − 20
tHD;STA
tSU;STO
tSU;STA
—
—
—
ns
reception
Not detected
Stop
condition
detection
SCL0,
SDA0
when 1 tMCLK
is used at
ns
R = 1.7 kΩ,
reception
C = 50 pF*1
Restart
Not detected
condition
detection
condition
SCL0,
SDA0
when 1 tMCLK
is used at
ns
reception
Bus free
time
SCL0,
SDA0
2 tMCLK − 20
2 tMCLK − 20
tBUF
—
—
ns At reception
At slave
ns transmission
mode
Data hold
time
SCL0,
SDA0
tHD;DAT
At slave
ns transmission
mode
Data setup
time
SCL0,
SDA0
tLOW − 3 tMCLK − 20
tSU;DAT
—
Data hold
time
SCL0,
SDA0
tHD;DAT
tSU;DAT
0
—
—
ns At reception
ns At reception
Data setup
time
SCL0,
SDA0
tMCLK − 20
SDA↓→
SCL↑
(at wakeup
function)
Oscillation
stabilization wait
time + 2 tMCLK − 20
SCL0,
SDA0
tWAKEUP
—
ns
(Continued)
DS07-12628-2E
63
MB95310L/370L Series
(Continued)
*1: R represents the pull-up resistor of the SCL0 and SDA0 lines, and C the load capacitor of the SCL0 and
SDA0 lines.
*2: • See “(2) Source Clock/Machine Clock” for tMCLK.
• m represents the CS4 bit and CS3 bit (bit4 and bit3) in the I2C clock control register (ICCR0).
• n represents the CS2 bit to CS0 bit (bit2 to bit0) in the I2C clock control register (ICCR0).
• The actual timing of I2C is determined by the values of m and n set by the machine clock (tMCLK) and the
CS4 to CS0 bits in the ICCR0 register.
• Standard-mode:
m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
: 0.9 MHz < tMCLK ≤ 2 MHz
: 0.9 MHz < tMCLK ≤ 4 MHz
: 0.9 MHz < tMCLK ≤ 10 MHz
: 0.9 MHz < tMCLK ≤ 16.25 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4)
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8)
(m, n) = (1, 98), (5, 22), (6, 22), (7, 22)
(m, n) = (8, 22)
• Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK ≤ 4 MHz
: 3.3 MHz < tMCLK ≤ 8 MHz
: 3.3 MHz < tMCLK ≤ 10 MHz
: 3.3 MHz < tMCLK ≤ 16.25 MHz
(m, n) = (1, 22), (5, 4)
(m, n) = (1, 38), (6, 4), (7, 4), (8, 4)
(m, n) = (5, 8)
64
DS07-12628-2E
MB95310L/370L Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Typ
—
Parameter
Resolution
Symbol
Unit
Remarks
Min
—
Max
10
bit
Total error
−3
—
+3
LSB
LSB
—
Linearity error
−2.5
—
+2.5
Differential linear
error
−1.9
—
+1.9
LSB
AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
AVSS − 0.5 LSB AVSS + 1.5 LSB AVSS + 3.5 LSB
AVCC − 3.5 LSB AVCC − 1.5 LSB AVCC + 0.5 LSB
AVCC − 2.5 LSB AVCC − 0.5 LSB AVCC + 1.5 LSB
V
V
V
V
2.7 V ≤ VCC ≤ 3.6 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 3.6 V
1.8 V ≤ VCC < 2.7 V
Zero transition
voltage
VOT
VFST
—
Full-scale transition
voltage
0.6
20
—
—
140
140
µs 2.7 V ≤ VCC ≤ 3.6 V
µs 1.8 V ≤ VCC < 2.7 V
Compare time
2.7 V ≤ VCC ≤ 3.6 V, with
µs external impedance
< 1.8 kΩ
0.4
30
—
—
∞
∞
Sampling time
—
1.8 V ≤ VCC < 2.7 V, with
µs external impedance
< 14.8 kΩ
Analog input current
Analog input voltage
IAIN
−0.3
—
—
+0.3
µA
V
VAIN
AVSS
AVCC
DS07-12628-2E
65
MB95310L/370L Series
(2) Notes on Using the A/D Converter
• External impedance of analog input and its sampling time
• The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient
sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is
insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision
standard, considering the relationship between the external impedance and minimum sampling time, either
adjust the register value and operating frequency or decrease the external impedance so that the sampling
time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect
a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
VCC
R
C
2.7 V ≤ VCC ≤ 3.6V
1.8 V ≤ VCC < 2.7 V
1.7 kΩ (Max)
8.4 kΩ (Max)
14.5 pF (Max)
25.2 pF (Max)
Note: The values are reference values.
• Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 100 kΩ]
(VCC ≥ 2.7 V)
[External impedance = 0 kΩ to 20 kΩ]
100
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
(VCC ≥ 2.7 V)
6
(VCC ≥ 1.8 V)
4
2
0
0
5
10
15
20
25
30
35
0
1
2
3
4
Minimum sampling time [μs]
Minimum sampling time [μs]
• A/D conversion error
As |VCC−VSS| decreases, the A/D conversion error increases proportionately.
66
DS07-12628-2E
MB95310L/370L Series
(3) Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting
the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device to
the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) of the same device.
• Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an
ideal value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a
zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
Total error
3FFH
3FEH
3FDH
3FFH
3FEH
3FDH
VFST
Actual conversion
characteristic
2 LSB
{1 LSB × (N-1) + 0.5 LSB}
004H
003H
002H
001H
004H
003H
002H
001H
VOT
VNT
Actual conversion
characteristic
1 LSB
Ideal characteristic
0.5 LSB
VSS
Analog input
VCC - VSS
VCC
VSS
Analog input
VCC
VNT - {1 LSB × (N - 1) + 0.5 LSB}
1 LSB
Total error of
digital output N
1 LSB =
(V)
=
[LSB]
1024
N
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
(Continued)
DS07-12628-2E
67
MB95310L/370L Series
(Continued)
Zero transition error
Full-scale transition error
004H
Ideal characteristic
Actual conversion
characteristic
3FFH
3FEH
3FDH
3FCH
Actual conversion
characteristic
003H
VFST
002H
(measurement
value)
Actual conversion
Ideal
characteristic
characteristic
001H
Actual conversion
characteristic
VOT (measurement value)
Analog input
VSS
VCC
VSS
Analog input
VCC
Linearity error
Differential linearity error
Ideal characteristic
Actual conversion
characteristic
3FFH
3FEH
3FDH
(N+1)H
NH
Actual conversion
characteristic
{1 LSB × N + VOT}
V(N+1)T
VFST
(measurement
value)
VNT
004H
003H
002H
001H
VNT
(N-1)H
(N-2)H
Actual conversion
characteristic
Ideal
Actual conversion
characteristic
characteristic
VOT (measurement value)
Analog input
VSS
VCC
VSS
Analog input
VCC
V(N+1)T - VNT
VNT - {1 LSB × N + VOT}
1 LSB
Differential linear error
of digital output N
Linearity error
of digital output N
=
- 1
=
1 LSB
N
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
VOT (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC - 2 LSB [V]
68
DS07-12628-2E
MB95310L/370L Series
6. Flash Memory Program/Erase Characteristics
Value
Parameter
Unit
Remarks
Min
Typ
Max
Sector erase time
(2 Kbyte sector)
The time of programming 00H prior
to erasure is excluded.
—
0.2*1
0.5*2
s
s
Sector erase time
(16 Kbyte sector)
The time of programming 00H prior
to erasure is excluded.
—
0.5*1
7.5*2
Byte programming time
Program/erase cycle
—
21
—
6100*2
—
µs System-level overhead is excluded.
cycle
100000
Power supply voltage at
program/erase
2.7
3.0
—
3.6
—
V
Flash memory data retention
time
20*3
year Average TA = +85°C
*1: TA = +25°C, VCC = 3.0 V, 100000 cycles
*2: TA = +85°C, VCC = 2.7 V, 100000 cycles
*3: This value is converted from the result of a technology reliability assessment. (The value is converted from
the result of a high temperature accelerated test using the Arrhenius equation with the average temperature
being +85°C).
DS07-12628-2E
69
MB95310L/370L Series
■ SAMPLE CHARACTERISTICS
• Power supply current temperature characteristics
ICC − VCC
ICC − TA
VCC = 3.0 V, FMP = 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
25
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
25
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
F
F
MP = 16 MHz
MP = 10 MHz
20
20
15
10
5
15
10
5
0
0
−50
0
+50
+100
+150
1
2
3
4
5
TA[°C]
VCC[V]
ICCS − VCC
ICCS − TA
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
VCC = 3.0 V, FMP = 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
Main sleep mode with the external clock operating
20
20
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
F
F
MP = 16 MHz
MP = 10 MHz
15
10
5
15
10
5
0
0
−50
0
+50
+100
+150
1
2
3
4
5
TA[°C]
V
CC[V]
ICCL − VCC
ICCL − TA
TA = +25°C, FMPL = 16 kHz (divided by 2)
VCC = 3.0 V, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
Subclock mode with the external clock operating
40
100
75
50
25
0
30
20
10
0
−50
0
+50
+100
+150
1
2
3
4
5
TA[°C]
VCC[V]
(Continued)
70
DS07-12628-2E
MB95310L/370L Series
ICCLS − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
100
ICCLS − TA
VCC = 3.0 V, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
100
75
50
25
0
75
50
25
0
−50
0
+50
+100
+150
1
2
3
4
5
TA[°C]
VCC[V]
ICCT − VCC
ICCT − TA
TA = +25°C, FMPL = 16 kHz (divided by 2)
VCC = 3.0 V, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
100
Watch mode with the external clock operating
100
75
50
25
0
75
50
25
0
−50
0
+50
+100
+150
1
2
3
4
5
TA[°C]
VCC[V]
ICTS − VCC
ICTS − TA
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
VCC = 3.0 V, FMP = 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock operating
Time-base timer mode with the external clock operating
10
10
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
F
F
MP = 16 MHz
MP = 10 MHz
8
6
4
2
0
8
6
4
2
0
−50
0
+50
[°C]
+100
+150
1
2
3
4
5
T
A
V
CC[V]
(Continued)
DS07-12628-2E
71
MB95310L/370L Series
(Continued)
ICCH − VCC
TA = +25°C, FMPL = (stop)
Substop mode with the external clock stopping
+10
ICCH − TA
VCC = 3.0 V, FMPL = (stop)
Substop mode with the external clock stopping
+10
+8
+6
+4
+2
0
+8
+6
+4
+2
0
−2
−2
1
2
3
4
5
−50
0
+50
+100
+150
VCC[V]
TA
[°C]
ICCMCR − VCC
ICCMCR − TA
TA = +25°C, FMP = 1, 8, 10, 12.5 MHz (no division)
VCC = 3.0 V, FMP = 1, 8, 10, 12.5 MHz (no division)
Main clock mode with the main CR clock operating
Main clock mode with the main CR clock operating
20
20
FMP = 12.5 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 1 MHz
FMP = 12.5 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 1 MHz
15
10
5
15
10
5
0
0
1
2
3
4
5
−50
0
+50
+100
+150
V
CC[V]
TA[°C]
ICCSCR − VCC
ICCSCR − TA
TA = +25°C, FMPL = 50 kHz (divided by 2)
VCC = 3.0 V, FMPL = 50 kHz (divided by 2)
Subclock mode with the sub-CR clock operating
Subclock mode with the sub-CR clock operating
160
160
140
120
100
80
140
120
100
80
60
60
40
40
20
20
0
0
1
2
3
4
5
−50
0
+50
+100
+150
VCC[V]
TA[°C]
72
DS07-12628-2E
MB95310L/370L Series
• Input voltage characteristics
VIHI1 − VCC and VIL − VCC
VIHI2 − VCC and VIL − VCC
TA = +25°C
TA = +25°C
4
4
VIHI1
VIL
VIHI2
VIL
3
2
1
0
3
2
1
0
1
2
3
4
5
1
2
3
4
5
VCC[V]
VCC[V]
VIHS1 − VCC and VILS − VCC
VIHS2 − VCC and VILS − VCC
TA = +25°C
TA = +25°C
4
3
2
1
0
4
3
2
1
0
VIHS1
VILS
VIHS2
VILS
1
2
3
4
5
1
2
3
4
5
VCC[V]
VCC[V]
VIHM − VCC and VILM − VCC
TA = +25°C
4
VIHM
VILM
3
2
1
0
1
2
3
4
5
VCC[V]
DS07-12628-2E
73
MB95310L/370L Series
• Output voltage characteristics
(VCC − VOH) − IOH
VOL − IOL
TA = +25°C
TA = +25°C
1.0
1.0
0.8
0.6
0.4
0.2
0.0
0.8
0.6
0.4
0.2
0.0
0
−2
−4
−6
−8
−10
0
2
4
6
8
10
IOH[mA]
IOL[mA]
VCC = 1.8 V
VCC = 2.0 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
VCC = 1.8 V
VCC = 2.0 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
74
DS07-12628-2E
MB95310L/370L Series
• Pull-up characteristics
RPULL − VCC
TA = +25°C
250
200
150
100
50
0
1
2
3
4
5
VCC[V]
DS07-12628-2E
75
MB95310L/370L Series
■ MASK OPTIONS
MB95F314E
MB95F314L
MB95F316L
MB95F318L
MB95F374L
MB95F376L
MB95F378L
MB95F316E
MB95F318E
MB95F374E
MB95F376E
MB95F378E
Part Number
No.
Selectable/Fixed
Fixed
1
Low-voltage detection reset With low-voltage detection reset Without low-voltage detection reset
76
DS07-12628-2E
MB95310L/370L Series
■ ORDERING INFORMATION
Part Number
Package
MB95F314EPMC-G-SNE2
MB95F314LPMC-G-SNE2
MB95F316EPMC-G-SNE2
MB95F316LPMC-G-SNE2
MB95F318EPMC-G-SNE2
MB95F318LPMC-G-SNE2
80-pin plastic LQFP
(FPT-80P-M37)
MB95F374EPMC1-G-SNE2
MB95F374LPMC1-G-SNE2
MB95F376EPMC1-G-SNE2
MB95F376LPMC1-G-SNE2
MB95F378EPMC1-G-SNE2
MB95F378LPMC1-G-SNE2
64-pin plastic LQFP
(FPT-64P-M38)
MB95F374EPMC2-G-SNE2
MB95F374LPMC2-G-SNE2
MB95F376EPMC2-G-SNE2
MB95F376LPMC2-G-SNE2
MB95F378EPMC2-G-SNE2
MB95F378LPMC2-G-SNE2
64-pin plastic LQFP
(FPT-64P-M39)
DS07-12628-2E
77
MB95310L/370L Series
■ PACKAGE DIMENSION
80-pin plastic LQFP
Lead pitch
0.50 mm
12.00 mm × 12.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.47 g
Sealing method
Mounting height
Weight
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00 0.20(.551 .008)SQ
*12.00 0.10(.472 .004)SQ
0.145 0.055
(.006 .002)
60
41
Details of "A" part
61
40
1.50 –+00..1200
(Mounting height)
.059 –+..000048
0.25(.010)
0~8°
0.08(.003)
0.50 0.20
(.020 .008)
0.10 0.05
(.004 .002)
(Stand off)
0.60 0.15
(.024 .006)
INDEX
80
21
"A"
1
20
0.50(.020)
0.22 0.05
(.009 .002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
78
DS07-12628-2E
MB95310L/370L Series
64-pin plastic LQFP
Lead pitch
0.50 mm
10.00 mm × 10.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.32 g
Sealing method
Mounting height
Weight
(FPT-64P-M38)
64-pin plastic LQFP
(FPT-64P-M38)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00 0.20(.472 .008)SQ
*10.00 0.10(.394 .004)SQ
0.145 0.055
(.006 .002)
48
33
Details of "A" part
49
32
1.50 –+00..1200
0.08(.003)
(Mounting height)
.059 –+..000048
0.25(.010)
0~8°
INDEX
0.50 0.20
(.020 .008)
0.10 0.10
(.004 .004)
(Stand off)
64
17
0.60 0.15
(.024 .006)
"A"
1
16
0.50(.020)
0.22 0.05
(.009 .002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS07-12628-2E
79
MB95310L/370L Series
(Continued)
64-pin plastic LQFP
Lead pitch
0.65 mm
12.00 mm × 12.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.47 g
(FPT-64P-M39)
64-pin plastic LQFP
(FPT-64P-M39)
Note 1) Pins width and pins thickness include plating thickness.
14.00 0.20(.551 .008)SQ
12.00 0.10(.472 .004)SQ
48
33
Details of "A" part
49
32
1.50 +0.20
.059 +.008
–0.10
–.004
0~8˚
0.10(.004)
0.10 0.10
(.004 .004)
INDEX
0.50 0.20
(.020 .008)
0.25(.010)BSC
64
17
0.60 0.15
(.024 .006)
1
16
"A"
0.65(.026)
0.32 0.05
(.013 .002)
M
0.13(.005)
C
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
80
DS07-12628-2E
MB95310L/370L Series
■ MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
Details
1
Changed the family name.
—
F2MC-8FX → New 8FX
1
■ FEATURES
Changed the main CR clock oscillation frequency.
1/8/10 MHz 3%, maximum machine clock frequency:
10 MHz
→
1/8/10/12.5 MHz 2%, maximum machine clock
frequency: 12.5 MHz
23
46
■ PIN CONNECTION
Added “• Notes on handling the external clock pins while
using the CR clock”.
■ ELECTRICAL CHARACTERISTICS Changed the condition for the power supply current
3. DC Characteristics
(ICCMCR).
FCRH = 10 MHz
FMP = 10 MHz
Main CR clock mode
→
FCRH = 12.5 MHz
FMP = 12.5 MHz
Main CR clock mode
Changed the condition for the power supply current
(ICCSCR).
FCL = 32 kHz
FMPL = 16 kHz
Sub-CR clock mode
(divided by 2)
TA = +25°C
→
Sub-CR clock mode
(divided by 2)
TA = +25°C
47
Changed the condition for the power supply current (ICRH).
Current consumption for the main CR oscillator at 10 MHz
→
Current consumption for the main CR oscillator
48
58
■ ELECTRICAL CHARACTERISTICS Changed the values of the clock frequency (FCRH).
4. AC Characteristics
(1) Clock Timing
■ ELECTRICAL CHARACTERISTICS Deleted the following parameters:
4. AC Characteristics
(7) Low-voltage Detection
Power hysteresis width 0, Power hysteresis width 1,
Power hysteresis width 2, Interrupt hysteresis width 0,
Interrupt hysteresis width 1, Interrupt hysteresis width 2,
Interrupt hysteresis width 3, Interrupt hysteresis width 4
59
64
Deleted VPHYS/VIHYS from the diagram.
■ ELECTRICAL CHARACTERISTICS Changed the settings related to the machine clock shown
4. AC Characteristics
in *2.
(8) I2C Timing
70 to 75 ■ SAMPLE CHARACTERISTICS
Added “■ SAMPLE CHARACTERISTICS”.
DS07-12628-2E
81
MB95310L/370L Series
MEMO
82
DS07-12628-2E
MB95310L/370L Series
MEMO
DS07-12628-2E
83
MB95310L/370L Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-
ing in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-
current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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