MB95F478HPMC1-G-SNE2 [SPANSION]
Microcontroller, CMOS;
| 型号： | MB95F478HPMC1-G-SNE2 |
| 厂家： | 
SPANSION |
| 描述： | Microcontroller, CMOS 微控制器 外围集成电路 |
| 文件： | 总85页 (文件大小：4211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Spansion® Analog and Microcontroller
Products
The following document contains information on Spansion analog and microcontroller products. Although the
document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion
will continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Spansion product. Any changes that
have been made are the result of normal document improvements and are noted in the document revision
summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a
revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “MB”. To order these products, please use
only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory, analog, and
microcontroller products and solutions.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS702-00004-1v0-E
8-bit Microcontrollers
CMOS
New 8FX MB95410H/470H Series
MB95F414H/F414K/F416H/F416K/F418H/F418K
MB95F474H/F474K/F476H/F476K/F478H/F478K
■ DESCRIPTION
MB95410H/470H is a series of general-purpose, single-chip microcontrollers. In addition to a compact
instruction set, the microcontrollers of this series contain a variety of peripheral resources.
■ FEATURES
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
• Clock
• Selectable main clock source
Main OSC clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz)
External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz)
Main CR clock (1/8/10/12.5 MHz 2%, maximum machine clock frequency: 12.5 MHz)
Main PLL clock (up to 16.25 MHz, maximum machine clock frequency: 16.25 MHz)
• Selectable subclock source
Sub-OSC clock (32.768 kHz)
External clock (32.768 kHz)
Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz)
• Timer
• 8/16-bit composite timer × 2 channels
• 8/16-bit PPG × 2 channels
• 16-bit reload timer × 1 channel
• Event counter × 1 channel
• Time-base timer × 1 channel
• Watch prescaler × 1 channel
• UART-SIO
• Capable of clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer
• Full duplex double buffer
(Continued)
For the information for microcontroller supports, see the following website.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2010-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.5
MB95410H/470H Series
(Continued)
• I2C
Built-in wake-up function
• External interrupt
• Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
• Can be used to wake up the device from different low power consumption (standby) modes
• 8/10-bit A/D converter
• 8-bit or 10-bit resolution can be selected
• LCD controller (LCDC)
• On MB95F414H/F414K/F416H/F416K/F418H/F418K, LCD output can be selected from 40 SEG × 4 COM
to 36 SEG × 8 COM.
• On MB95F474H/F474K/F476H/F476K/F478H/F478K, LCD output can be selected from 32 SEG × 4 COM
to 28 SEG × 8 COM.
• Internal divider resistor whose resistance value can be selected from 10 kΩ or 100 kΩ through software
• Interrupt in sync with the LCD module frame frequency
• Blinking function
• Inverted display function
• Low power consumption (standby) modes
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
• I/O port
• MB95F414H/F416H/F418H (maximum no. of I/O ports: 74)
General-purpose I/O ports (N-ch open drain)
General-purpose I/O ports (CMOS I/O)
: 3
: 71
• MB95F414K/F416K/F418K (maximum no. of I/O ports: 75)
General-purpose I/O ports (N-ch open drain)
General-purpose I/O ports (CMOS I/O)
: 4
: 71
• MB95F474H/F476H/F478H (maximum no. of I/O ports: 58)
General-purpose I/O ports (N-ch open drain)
General-purpose I/O ports (CMOS I/O)
: 3
: 55
• MB95F474K/F476K/F478K (maximum no. of I/O ports: 59)
General-purpose I/O ports (N-ch open drain)
General-purpose I/O ports (CMOS I/O)
: 4
: 55
• On-chip debug
• 1-wire serial control
• Serial writing supported (asynchronous mode)
• Hardware/software watchdog timer
• Built-in hardware watchdog timer
• Built-in software watchdog timer
• Low-voltage detection reset circuit
Built-in low-voltage detector
• Clock supervisor counter
Built-in clock supervisor counter function
• Programmable port input voltage level
CMOS input level / hysteresis input level
• Dual operation Flash memory
The program/erase operation and the read operation can be executed in different banks (upper bank/lower
bank) simultaneously.
• Flash memory security function
Protects the content of the Flash memory
2
DS702-00004-1v0-E
MB95410H/470H Series
■ PRODUCT LINE-UP
• MB95410H Series
Part number
MB95F414H
MB95F416H
MB95F418H
MB95F414K
MB95F416K
MB95F418K
Package
Type
Flash memory product
It supervises the main clock oscillation.
Clock
supervisor
counter
Program ROM
capacity
RAM capacity
20 Kbyte
36 Kbyte
1008 bytes
No
60 Kbyte
20 Kbyte
496 bytes
36 Kbyte
1008 bytes
Yes
60 Kbyte
496 bytes
2032 bytes
2032 bytes
Low-voltage
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
• Instruction bit length
• Instruction length
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8 and 16 bits
CPU functions
• Data bit length
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 74
• I/O ports (Max) : 75
General-
purpose I/O
• CMOS I/O
: 71
• CMOS I/O
: 71
• N-ch open drain: 3
• N-ch open drain: 4
Time-base timer Interval time: 0.256 ms - 8.3 s (external clock frequency = 4 MHz)
Hardware/
software
• Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace three bytes of data.
1 channel
• Master/Slave sending and receiving
• Bus error function and arbitration function
• Detecting transmitting direction function
• Start condition repeated generation and detection functions
• Built-in wake-up function
I2C
3 channels
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate
generator and an error detection function.
• It uses the NRZ type transfer format.
UART/SIO
• LSB-first data transfer and MSB-first data transfer are available to use.
• Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer is enabled.
8 channels
8-bit or 10-bit resolution can be selected.
8/10-bit A/D
converter
(Continued)
DS702-00004-1v0-E
3
MB95410H/470H Series
(Continued)
Part number
MB95F414H
MB95F416H
MB95F418H
MB95F414K
MB95F416K
MB95F418K
Package
2 channels
• Each timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
• It has built-in timer function, PWC function, PWM function and input capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
8/16-bit
composite timer
• COM output: 4 or 8 (selectable)
• SEG output: 36 or 40 (selectable)
- If the number of COM outputs is 4, the maximum number of SEG outputs is 40, and the
maximum number of pixels that can be displayed 160 (4×40).
- If the number of COM outputs is 8, the maximum number of SEG outputs is 36, and the
maximum number of pixels that can be displayed 288 (8×36).
• LCD drive power supply (bias) pins: 5 (Max)
LCD controller
(LCDC)
• Duty LCD mode
• LCD standby mode
• Blinking function
• Internaldividerresistorwhoseresistancevaluecanbeselectedfrom10kΩ or100kΩ through
software
• Interrupt in sync with the LCD module frame frequency
• Inverted display function
1 channel
• Two clock modes and two counter operating modes can be selected
• Square waveform output
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• Counter operating mode: reload mode or one-shot mode can be selected
16-bit reload
timer
By configuring the 16-bit reload timer and the 8/16-bit composite timer ch. 1, event counter
Event counter function can be implemented. When the event counter function is used, the 16-bit reload timer
and the 8/16-bit composite timer ch. 1 are unavailable.
2 channels
8/16-bit PPG
• Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1 channel”
• Counter operating clock: Eight selectable clock sources
• Count clock: Four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s)
Watch counter • Counter value can be set from 0 to 63. (Capable of counting for 1 minute when the clock
source is 1 second and the counter value is to 60)
8 channels
External
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
• It can be used to wake up the device from the standby mode.
• 1-wire serial control
• It supports serial writing. (asynchronous mode)
On-chip debug
Eight different time intervals can be selected.
(62.5 ms, 125 ms, 250 ms, 500 ms, 1 s, 2 s, 4 s, 8 s)
Watch prescaler
• It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/
erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
• Number of program/erase cycles: 100000
Flash memory
• Data retention time: 20 years
• Flash security feature for protecting the content of the Flash memory
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
Package
FPT-80P-M37
4
DS702-00004-1v0-E
MB95410H/470H Series
• MB95470H Series
Part number
MB95F474H
MB95F476H
MB95F478H
MB95F474K
MB95F476K
MB95F478K
Package
Type
Flash memory product
It supervises the main clock oscillation.
Clock
supervisor
counter
Program ROM
capacity
RAM capacity
20 Kbyte
36 Kbyte
1008 bytes
No
60 Kbyte
20 Kbyte
496 bytes
36 Kbyte
1008 bytes
Yes
60 Kbyte
496 bytes
2032 bytes
2032 bytes
Low-voltage
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
• Instruction bit length
• Instruction length
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8 and 16 bits
CPU functions
• Data bit length
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 58
• I/O ports (Max) : 59
General-
purpose I/O
• CMOS I/O
: 55
• CMOS I/O
: 55
• N-ch open drain: 3
• N-ch open drain: 4
Time-base timer Interval time: 0.256 ms - 8.3 s (external clock frequency = 4 MHz)
Hardware/
software
• Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace three bytes of data.
1 channel
• Master/Slave sending and receiving
• Bus error function and arbitration function
• Detecting transmitting direction function
• Start condition repeated generation and detection functions
• Built-in wake-up function
I2C
3 channels
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate
generator and an error detection function.
• It uses the NRZ type transfer format.
UART/SIO
• LSB-first data transfer and MSB-first data transfer are available to use.
• Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer is enabled.
8 channels
8-bit or 10-bit resolution can be selected.
2 channels
8/10-bit A/D
converter
• Each timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
• It has built-in timer function, PWC function, PWM function and input capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
8/16-bit
composite timer
(Continued)
DS702-00004-1v0-E
5
MB95410H/470H Series
(Continued)
Part number
MB95F474H
MB95F476H
MB95F478H
MB95F474K
MB95F476K
MB95F478K
Package
• COM output: 4 or 8 (selectable)
• SEG output: 28 or 32 (selectable)
- If the number of COM outputs is 4, the maximum number of SEG outputs is 32, and the
maximum number of pixels that can be displayed 128 (4×32).
- If the number of COM outputs is 8, the maximum number of SEG outputs is 28, and the
maximum number of pixels that can be displayed 224 (8×28).
LCD controller
(LCDC)
• LCD drive power supply (bias) pins: 4 (Max)
• Duty LCD mode
• LCD standby mode
• Blinking function
• Internaldividerresistorwhoseresistancevaluecanbeselectedfrom10kΩ or100kΩ through
software
• Inverted display function
1 channel
• Two clock modes and two counter operating modes can be selected
• Square waveform output
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• Counter operating mode: reload mode or one-shot mode can be selected
16-bit reload
timer
By configuring the 16-bit reload timer and the 8/16-bit composite timer ch. 1, event counter
Event counter function can be implemented. When the event counter function is used, the 16-bit reload timer
and the 8/16-bit composite timer ch. 1 are unavailable.
2 channels
8/16-bit PPG
• Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1 channel“
• Counter operating clock: Eight selectable clock sources
• Count clock: Four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s)
Watch counter • Counter value can be set from 0 to 63. (Capable of counting for 1 minute when the clock
source is 1 second and the counter value is to 60)
8 channels
External
Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
It can be used to wake up the device from the standby mode.
• 1-wire serial control
• It supports serial writing. (asynchronous mode)
On-chip debug
Eight different time intervals can be selected.
(62.5 ms, 125 ms, 250 ms, 500 ms, 1 s, 2 s, 4 s, 8 s)
Watch prescaler
• It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/
erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
• Number of program/erase cycles: 100000
Flash memory
• Data retention time: 20 years
• Flash security feature for protecting the content of the Flash memory
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
FPT-64P-M38
FPT-64P-M39
Package
6
DS702-00004-1v0-E
MB95410H/470H Series
■ OSCILLATION STABILIZATION WAIT TIME
The main CR clock oscillation stabilization wait time is fixed to the maximum value. Below is the maximum
value.
Oscillation stabilization wait time
Remarks
(210 − 2) / FCRH
Approx. 128 µs (when the main CR clock is 8 MHz)
The main PLL clock oscillation stabilization wait time is fixed to the maximum value. Below is the maximum
value.
Remarks
Oscillation stabilization wait time
(214 − 2) / FCH
Approx. 14.1 ms (when the main PLL clock is 4 MHz)
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
MB95F414H
MB95F474H
MB95F416H
MB95F476H
MB95F418H
MB95F478H
MB95F414K
MB95F474K
MB95F416K
MB95F476K
MB95F418K
MB95F478K
Package
FPT-80P-M37
O
Part number
Package
FPT-64P-M38
FPT-64P-M39
O
O
O: Available
DS702-00004-1v0-E
7
MB95410H/470H Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION
• Current consumption
When using the on-chip debug function, take account of the current consumption of flash erase/write.
For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSION”.
• Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, see “■ ELECTRICAL CHARACTERISTICS”.
• On-chip debug function
The on-chip debug function requires that VCC, VSS and 1 serial-wire be connected to an evaluation tool. For
details of the connection method, refer to “CHAPTER 31 EXAMPLE OF SERIAL PROGRAMMING
CONNECTION” in the hardware manual of the MB95410H/470H Series.
8
DS702-00004-1v0-E
MB95410H/470H Series
■ PIN ASSIGNMENT
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AVcc
P07/INT07/AN07/SEG30
P06/INT06/AN06/SEG31
P05/INT05/AN05/SEG32/UCK1
P04/INT04/AN04/SEG33/UI1
P03/INT03/AN03/SEG34/UO1
P02/INT02/AN02/SEG35/UCK2
P01/INT01/AN01/SEG36/UI2
P00/INT00/AN00/UO2
P16/PPG10
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P60/SEG10
PC7/SEG09
PC6/SEG08
PC5/SEG07
PC4/SEG06
PC3/SEG05
PC2/SEG04
PC1/SEG03
PC0/SEG02
PB1/SEG01
PB0/SEG00
P17/CMPO
PF2/RST
Vcc
3
4
5
6
7
8
(TOP VIEW)
MB95410H Series
9
10
11
12
13
14
15
16
17
18
19
20
P15/PPG11
(FPT-80P-M37)
P14/UCK0
P13/ADTG
P12/DBG
P11/UO0
PG1/X0A
PG2/X1A
C
P10/UI0
P53/TO0
P52/TI0/TO00
PF0/X0
P51/EC0
PF1/X1
P50/TO01
Vss
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
(Continued)
DS702-00004-1v0-E
9
MB95410H/470H Series
(Continued)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc
P07/INT07/AN07/SEG22
P06/INT06/AN06/SEG23
P05/INT05/AN05/SEG24/UCK1
P04/INT04/AN04/SEG25/UI1
P03/INT03/AN03/SEG26/UO1
P02/INT02/AN02/SEG27/UCK2
P01/INT01/AN01/SEG28/TO00/UI2
P00/INT00/AN00/SEG29/UO2
P16/SEG30/PPG10
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P60/SEG06
PC3/SEG05
PC2/SEG04
PC1/SEG03
PC0/SEG02
PB1/SEG01
PB0/SEG00
P17/CMPO
PF2/RST
Vcc
3
4
5
6
(TOP VIEW)
MB95470H Series
7
8
9
(FPT-64P-M38)
(FPT-64P-M39)
10
11
12
13
14
15
16
P15/SEG31/PPG11
PG1/X0A
PG2/X1A
C
P14/UCK0/EC0/TI0
P13/ADTG/TO01
P12/DBG
PF0/X0
P11/UO0
PF1/X1
P10/UI0/TO0
Vss
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
10
DS702-00004-1v0-E
MB95410H/470H Series
■ PIN DESCRIPTION (MB95410H Series)
Pin no. Pin name I/O circuit type*
Function
1
AVCC
P07
—
A/D converter power supply pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT07
AN07
SEG30
P06
2
S
LCDC SEG output pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT06
AN06
SEG31
P05
3
4
S
S
LCDC SEG output pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT05
AN05
SEG32
UCK1
P04
LCDC SEG output pin
UART/SIO ch. 1 clock I/O pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT04
AN04
SEG33
UI1
5
6
7
8
V
S
S
V
LCDC SEG output pin
UART/SIO ch. 1 data input pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
P03
INT03
AN03
SEG34
UO1
LCDC SEG output pin
UART/SIO ch. 1 data output pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
P02
INT02
AN02
SEG35
UCK2
P01
LCDC SEG output pin
UART/SIO ch. 2 clock I/O pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT01
AN01
SEG36
UI2
LCDC SEG output pin
UART/SIO ch. 2 data input pin
(Continued)
DS702-00004-1v0-E
11
MB95410H/470H Series
Pin no. Pin name I/O circuit type*
Function
P00
INT00
AN00
UO2
P16
General-purpose I/O port
External interrupt input pin
A/D analog input pin
9
W
UART/SIO ch. 2 data output pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
UART/SIO ch. 0 clock I/O pin
General-purpose I/O port
A/D trigger input (ADTG) pin
General-purpose I/O port
DBG input pin
10
11
12
13
14
15
16
17
Y
Y
H
H
D
H
G
H
PPG10
P15
PPG11
P14
UCK0
P13
ADTG
P12
DBG
P11
General-purpose I/O port
UART/SIO ch. 0 data output pin
General-purpose I/O port
UART/SIO ch. 0 data input pin
General-purpose I/O port
16-bit reload timer output pin
General-purpose I/O port
16-bit reload timer input pin
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
8/16-bit composite timer ch. 0 clock input pin
General-purpose I/O port
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
I2C data I/O pin
UO0
P10
UI0
P53
TO0
P52
18
TI0
H
TO00
P51
19
20
21
22
H
H
I
EC0
P50
TO01
P23
SDA
P22
General-purpose I/O port
I2C clock I/O pin
I
SCL
P21
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
Voltage comparator input pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
Voltage comparator input pin
23
24
PPG01
CMPP
P20
T
T
PPG00
CMPN
(Continued)
12
DS702-00004-1v0-E
MB95410H/470H Series
Pin no. Pin name I/O circuit type*
Function
P90
General-purpose I/O port
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
R
R
V4
P91
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC SEG output pin
V3
P92
R
V2
P93
R
V1
P94
R
V0
PB2
M
M
M
M
M
M
M
M
M
M
SEG37
PB3
General-purpose I/O port
LCDC SEG output pin
SEG38
PB4
General-purpose I/O port
LCDC SEG output pin
SEG39
PA0
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
Power supply pin (GND)
General-purpose I/O port
Main clock oscillation pin
General-purpose I/O port
Main clock oscillation pin
COM0
PA1
COM1
PA2
COM2
PA3
COM3
PA4
COM4
PA5
COM5
PA6
COM6
PA7
40
41
42
M
—
B
COM7
VSS
PF1
X1
PF0
43
B
X0
(Continued)
DS702-00004-1v0-E
13
MB95410H/470H Series
Pin no. Pin name I/O circuit type*
Function
44
C
—
Capacitor connection pin
General-purpose I/O port
PG2
X1A
PG1
X0A
VCC
45
C
Subclock oscillation pin (32 kHz)
General-purpose I/O port
Subclock oscillation pin (32 kHz)
Power supply pin
46
47
C
—
PF2
General-purpose I/O port
48
A
Reset pin
RST
Dedicate reset pin for MB95F414H/F416H/F418H
P17
CMPO
PB0
General-purpose I/O port
Voltage comparator output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
49
50
51
52
53
54
55
56
57
58
59
60
61
62
H
M
M
M
M
M
M
M
M
M
M
M
M
M
SEG00
PB1
SEG01
PC0
SEG02
PC1
SEG03
PC2
SEG04
PC3
SEG05
PC4
SEG06
PC5
SEG07
PC6
SEG08
PC7
SEG09
P60
SEG10
P61
SEG11
P62
SEG12
(Continued)
14
DS702-00004-1v0-E
MB95410H/470H Series
Pin no. Pin name I/O circuit type*
Function
P63
General-purpose I/O port
63
64
65
66
67
68
69
70
71
72
73
74
75
76
M
M
M
M
M
M
M
M
M
M
M
M
M
M
SEG13
P64
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
SEG14
P65
General-purpose I/O port
LCDC SEG output pin
SEG15
P66
General-purpose I/O port
LCDC SEG output pin
SEG16
P67
General-purpose I/O port
LCDC SEG output pin
SEG17
P43
General-purpose I/O port
LCDC SEG output pin
SEG18
P42
General-purpose I/O port
LCDC SEG output pin
SEG19
P41
General-purpose I/O port
LCDC SEG output pin
SEG20
P40
General-purpose I/O port
LCDC SEG output pin
SEG21
PE0
General-purpose I/O port
LCDC SEG output pin
SEG22
PE1
General-purpose I/O port
LCDC SEG output pin
SEG23
PE2
General-purpose I/O port
LCDC SEG output pin
SEG24
PE3
General-purpose I/O port
LCDC SEG output pin
SEG25
PE4
General-purpose I/O port
LCDC SEG output pin
SEG26
PE5
General-purpose I/O port
LCDC SEG output pin
77
78
SEG27
TO11
PE6
M
M
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
LCDC SEG output pin
SEG28
TO10
8/16-bit composite timer ch. 1 output pin
(Continued)
DS702-00004-1v0-E
15
MB95410H/470H Series
(Continued)
Pin no. Pin name I/O circuit type*
Function
PE7
SEG29
EC1
General-purpose I/O port
LCDC SEG output pin
79
M
8/16-bit composite timer ch. 1 clock input pin
A/D converter power supply pin (GND)
80
AVSS
—
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
16
DS702-00004-1v0-E
MB95410H/470H Series
s
■ PIN DESCRIPTION (MB95470H Series)
Pin no. Pin name I/O circuit type*
Function
1
AVCC
P07
—
A/D converter power supply pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT07
AN07
SEG22
P06
2
S
LCDC SEG output pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT06
AN06
SEG23
P05
3
4
S
S
LCDC SEG output pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT05
AN05
SEG24
UCK1
P04
LCDC SEG output pin
UART/SIO ch. 1 clock I/O pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT04
AN04
SEG25
UI1
5
6
7
V
S
S
LCDC SEG output pin
UART/SIO ch. 1 data input pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
P03
INT03
AN03
SEG26
UO1
LCDC SEG output pin
UART/SIO ch. 1 data output pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
P02
INT02
AN02
SEG27
UCK2
P01
LCDC SEG output pin
UART/SIO ch. 2 clock I/O pin
General-purpose I/O port
External interrupt input pin
A/D analog input pin
INT01
AN01
SEG28
TO00
UI2
8
V
LCDC SEG output pin
8/16-bit composite timer ch. 0 output pin
UART/SIO ch. 2 data input pin
(Continued)
DS702-00004-1v0-E
17
MB95410H/470H Series
Pin no. Pin name I/O circuit type*
Function
P00
INT00
AN00
SEG29
UO2
General-purpose I/O port
External interrupt input pin
A/D analog input pin
9
S
LCDC SEG output pin
UART/SIO ch. 2 data output pin
General-purpose I/O port
LCDC SEG output pin
P16
10
11
SEG30
PPG10
P15
M
M
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
LCDC SEG output pin
SEG31
PPG11
P14
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
UART/SIO ch. 0 clock I/O pin
8/16-bit composite timer ch. 0 clock input pin
16-bit reload timer input pin
General-purpose I/O port
A/D trigger input (ADTG) pin
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
DBG input pin
UCK0
EC0
12
13
H
H
TI0
P13
ADTG
TO01
P12
14
15
D
H
DBG
P11
General-purpose I/O port
UART/SIO ch. 0 data output pin
General-purpose I/O port
UART/SIO ch. 0 data input pin
16-bit reload timer output pin
General-purpose I/O port
I2C data I/O pin
UO0
P10
16
UI0
G
TO0
P23
17
18
I
I
SDA
P22
General-purpose I/O port
I2C clock I/O pin
SCL
P21
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
Voltage comparator input pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
Voltage comparator input pin
19
20
PPG01
CMPP
P20
T
T
PPG00
CMPN
(Continued)
18
DS702-00004-1v0-E
MB95410H/470H Series
Pin no. Pin name I/O circuit type*
Function
P90
General-purpose I/O port
21
22
23
24
25
26
27
28
29
30
31
R
R
V4
P91
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC COM output pin
V3
P92
R
V2
P93
R
V1
PA0
COM0
PA1
COM1
PA2
COM2
PA3
COM3
PA4
COM4
PA5
COM5
PA6
COM6
PA7
COM7
VSS
M
M
M
M
M
M
M
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
32
33
34
M
—
B
Power supply pin (GND)
General-purpose I/O port
Main clock oscillation pin
General-purpose I/O port
Main clock oscillation pin
Capacitor connection pin
General-purpose I/O port
Subclock oscillation pin (32 kHz)
General-purpose I/O port
Subclock oscillation pin (32 kHz)
Power supply pin
PF1
X1
PF0
X0
35
36
37
B
—
C
C
PG2
X1A
PG1
X0A
VCC
38
39
C
—
PF2
General-purpose I/O port
40
A
Reset pin
RST
Dedicated reset pin for MB95F474H/F476H/F478H
(Continued)
DS702-00004-1v0-E
19
MB95410H/470H Series
Pin no. Pin name I/O circuit type*
Function
P17
CMPO
PB0
General-purpose I/O port
Voltage comparator output pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
H
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
SEG00
PB1
SEG01
PC0
SEG02
PC1
SEG03
PC2
SEG04
PC3
SEG05
P60
SEG06
P61
SEG07
P62
SEG08
P63
SEG09
P64
SEG10
P65
SEG11
P66
SEG12
P67
SEG13
PE0
SEG14
PE1
SEG15
(Continued)
20
DS702-00004-1v0-E
MB95410H/470H Series
(Continued)
Pin no. Pin name I/O circuit type*
Function
PE2
General-purpose I/O port
58
59
60
M
M
M
SEG16
PE3
LCDC SEG output pin
General-purpose I/O port
SEG17
PE4
LCDC SEG output pin
General-purpose I/O port
SEG18
PE5
LCDC SEG output pin
General-purpose I/O port
61
62
SEG19
TO11
PE6
M
M
LCDC SEG output pin
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
SEG20
TO10
PE7
LCDC SEG output pin
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
63
64
SEG21
EC1
M
LCDC SEG output pin
8/16-bit composite timer ch. 1 clock input pin
A/D converter power supply pin (GND)
AVSS
—
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS702-00004-1v0-E
21
MB95410H/470H Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• N-ch open drain output
• Hysteresis input
• Reset output
Reset input / Hysteresis input
Reset output / Digital output
N-ch
B
• Oscillation circuit
• High-speed side
Feedback resistance:
approx. 1 MΩ
Port select
P-ch
Digital output
Digital output
N-ch
Standby control
Hysteresis input
• CMOS output
• Hysteresis input
Clock input
X1
X0
Standby control / Port select
Port select
P-ch
Digital output
Digital output
N-ch
Standby control
Hysteresis input
C
• Oscillation circuit
• Low-speed side
Feedback resistance:
approx. 10 MΩ
Port select
R
Pull-up control
P-ch
N-ch
P-ch
Digital output
Digital output
• CMOS output
• Hysteresis input
• Pull-up control available
Standby control
Hysteresis input
Clock input
X1A
X0A
Standby control / Port select
Port select
R
Pull-up control
Digital output
P-ch
Digital output
Digital output
N-ch
Standby control
Hysteresis input
(Continued)
22
DS702-00004-1v0-E
MB95410H/470H Series
Type
Circuit
Remarks
D
• N-ch open drain output
• Hysteresis input
Standby control
Hysteresis input
Digital output
N-ch
G
• CMOS output
• Hysteresis input
Pull-up control
R
• CMOS input
• Pull-up control available
P-ch
Digital output
P-ch
Digital output
N-ch
Standby control
Hysteresis input
CMOS input
H
• CMOS output
• Hysteresis input
Pull-up control
R
• Pull-up control available
P-ch
N-ch
Digital output
P-ch
Digital output
Standby control
Hysteresis input
I
• N-ch open drain output
• CMOS input
• Hysteresis input
Standby control
CMOS input
Hysteresis input
Digital output
N-ch
J
• CMOS output
• Hysteresis input
Pull-up control
R
• Analog input
• Pull-up control available
P-ch
N-ch
Digital output
P-ch
Digital output
Analog input
A/D control
Standby control
Hysteresis input
(Continued)
DS702-00004-1v0-E
23
MB95410H/470H Series
Type
Circuit
Remarks
• CMOS output
• LCD output
M
P-ch
N-ch
Digital output
Digital output
• Hysteresis input
LCD output
LCD control
Standby control
Hysteresis input
N
• CMOS output
• LCD output
• Hysteresis input
• CMOS input
P-ch
N-ch
Digital output
Digital output
LCD output
LCD control
Standby control
Hysteresis input
CMOS input
Q
• CMOS output
• LCD output
• Hysteresis input
P-ch
N-ch
Digital output
Digital output
LCD output
LCD control
Standby control
External interrupt
control
Hysteresis input
R
• CMOS output
• LCD power supply
• Hysteresis input
P-ch
Digital output
Digital output
N-ch
LCD internal divider
resistor I/O
LCD control
Standby control
Hysteresis input
(Continued)
24
DS702-00004-1v0-E
MB95410H/470H Series
Type
Circuit
Remarks
S
• CMOS output
• LCD output
• Hysteresis input
• Analog input
P-ch
N-ch
Digital output
Digital output
Analog input
LCD output
LCD control
A/D control
Standby control
Hysteresis input
T
• CMOS output
• Hysteresis input
• Analog input
Pull-up control
R
P-ch
N-ch
• Pull-up control available
Digital output
Digital output
Analog input
Analog input control
Standby control
Hysteresis input
V
• CMOS output
• LCD output
• Hysteresis input
• Analog input
• CMOS input
P-ch
N-ch
Digital output
Digital output
Analog input
LCD output
LCD control
A/D control
Standby control
Hysteresis input
CMOS input
W
• CMOS output
• Hysteresis input
• Analog input
P-ch
N-ch
Digital output
Digital output
Analog input
Analog input control
Standby control
Hysteresis input
(Continued)
DS702-00004-1v0-E
25
MB95410H/470H Series
(Continued)
Type
Circuit
Remarks
• CMOS output
• Hysteresis input
Y
P-ch
N-ch
Digital output
Digital output
Standby control
Hysteresis input
26
DS702-00004-1v0-E
MB95410H/470H Series
■ NOTES ON DEVICE HANDLING
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that
is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating
range of power supply voltage mentioned in "1. Absolute Maximum Ratings" of “■ ELECTRICAL CHARAC-
TERISTICS” is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be
thermally destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within
the guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value)
at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient
fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from subclock mode or stop mode.
■ PIN CONNECTION
• Treatment of unused input pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions
or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an
unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it
the same as an unused input pin. If there is an unused output pin, leave it unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase
in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS
pin to the power supply and ground outside the device. In addition, connect the current supply source to the
VCC pin and the VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between
the VCC pin and the VSS pin at a location close to this device.
• DBG pin
Connect the DBG pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance
between the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The DBG pin should not stay at “L” level after power-on until the reset output is released.
• RST pin
Connect the RST pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance
between the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output function
of the PF2/RST pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function or
the general purpose I/O function can be selected by the RSTEN bit in the SYSC register.
• Analog power supply
Always set the same potential to AVCC and VCC pins. When VCC is larger than AVCC, the current may flow
through the AN00 to AN07 pins.
DS702-00004-1v0-E
27
MB95410H/470H Series
• Treatment of power supply pins on the A/D converter
Ensure that AVCC is equal to VCC and AVSS equal to VSS even when the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. Therefore, connect a ceramic capacitor of
0.1 µF (approx.) as a bypass capacitor between the AVCC pin and the AVSS pin in the vicinity of this device.
• C pin
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for
the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see
the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise,
minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing
the layout of a printed circuit board.
• DBG/RST/C pins connection diagram
DBG
C
RST
Cs
28
DS702-00004-1v0-E
MB95410H/470H Series
■ BLOCK DIAGRAM (MB95410H Series)
F2MC-8FX CPU
PF2*1/RST*2
Reset with LVD
Flash with security function
(60/36/20 Kbyte)
PF1/X1*2
PF0/X0*2
PG2/X1A*2
PG1/X0A*2
RAM (2032/1008/496 bytes)
Interrupt controller
Oscillator
circuit
CR
oscillator
Clock control
P52/TO00
P50/TO01
P51/EC0
C
8/16-bit composite timer ch. 0
8/10-bit A/D converter
Watch counter
On-chip debug
Wild register
P12*1/DBG
P00/AN00 to P07/AN07
P13/ADTG
4 COM:
8 COM:
P00/INT00 to P07/INT07
External interrupt
P90/V4 to P94/V0
P90/V4 to P94/V0
PA0/COM0 to PA3/COM3
PB0/SEG00, PB1/SEG01
PC0/SEG02 to PC7/SEG09
P60/SEG10 to P67/SEG17
P43/SEG18 to P40/SEG21
PE0/SEG22 to PE7/SEG29
P07/SEG30 to P01/SEG36
PB2/SEG37 to PB4/SEG39
PA0/COM0 to PA7/COM7
PB0/SEG00, PB1/SEG01
PC0/SEG02 to PC7/SEG09
P60/SEG10 to P67/SEG17
P43/SEG18 to P40/SEG21
PE0/SEG22 to PE7/SEG29
P07/SEG30 to P02/SEG35
P14/UCK0
P11/UO0
P10/UI0
UART/SIO ch. 0
UART/SIO ch. 1
UART/SIO ch. 2
LCDC
(4 COM or 8 COM)
P05/UCK1
P03/UO1
P04/UI1
*3
P02/UCK2
P00/UO2
P01/UI2
P52/TI0
16-bit reload timer
P53/TO0
P20/PPG00
P21/PPG01
PE5/TO11
PE6/TO10
PE7/EC1
8/16-bit PPG ch. 0
8/16-bit PPG ch. 1
8/16-bit composite timer ch. 1
P16/PPG10
P15/PPG11
P20/CMPN
P21/CMPP
P17/CMPO
P22/SCL*1
P23/SDA*1
Voltage comparator
I2C
Port
Port
Vcc
*1: PF2, P12, P22 and P23 are N-ch open drain pins.
*2: Software option
Vss
*3: 8/16-bit composite timer ch. 1 and 16-bit reload timer can be used as an event counter
when the event counter operating mode is enabled.
DS702-00004-1v0-E
29
MB95410H/470H Series
■ BLOCK DIAGRAM (MB95470H Series)
F2MC-8FX CPU
PF2*1/RST*2
Reset with LVD
Flash with security function
(60/36/20 Kbyte)
PF1/X1*2
PF0/X0*2
PG2/X1A*2
PG1/X0A*2
RAM (2032/1008/496 bytes)
Interrupt controller
Oscillator
circuit
CR
oscillator
Clock control
P01/TO00
P13/TO01
P14/EC0
C
8/16-bit composite timer ch. 0
8/10-bit A/D converter
Watch counter
On-chip debug
Wild register
P12*1/DBG
P00/AN00 to P07/AN07
P13/ADTG
4 COM:
8 COM:
P00/INT00 to P07/INT07
External interrupt
P90/V4 to P93/V1
P90/V4 to P93/V1
PA0/COM0 to PA3/COM3
PB0/SEG00, PB1/SEG01
PC0/SEG02 to PC3/SEG05
P60/SEG06 to P67/SEG13
PE0/SEG14 to PE7/SEG21
P07/SEG22 to P00/SEG29
P16/SEG30, P15/SEG31
PA0/COM0 to PA7/COM7
PB0/SEG00, PB1/SEG01
PC0/SEG02 to PC3/SEG05
P60/SEG06 to P67/SEG13
PE0/SEG14 to PE7/SEG21
P07/SEG22 to P02/SEG27
P14/UCK0
P11/UO0
P10/UI0
UART/SIO ch. 0
UART/SIO ch. 1
UART/SIO ch. 2
LCDC
(4 COM or 8 COM)
P05/UCK1
P03/UO1
P04/UI1
*3
P02/UCK2
P00/UO2
P01/UI2
P14/TI0
16-bit reload timer
P10/TO0
P20/PPG00
P21/PPG01
PE5/TO11
PE6/TO10
PE7/EC1
8/16-bit PPG ch. 0
8/16-bit PPG ch. 1
8/16-bit composite timer ch. 1
P16/PPG10
P15/PPG11
P20/CMPN
P21/CMPP
P17/CMPO
P22*1/SCL
P23*1/SDA
Voltage comparator
I2C
Port
Port
Vcc
*1: PF2, P12, P22 and P23 are N-ch open drain pins.
*2: Software option
Vss
*3: 8/16-bit composite timer ch. 1 and 16-bit reload timer can be used as an event counter
when the event counter operating mode is enabled.
30
DS702-00004-1v0-E
MB95410H/470H Series
■ CPU CORE
• Memory Space
The memory space of the MB95410H/470H Series is 64 Kbyte in size, and consists of an I/O area, a data
area, and a program area. The memory space includes areas intended for specific purposes such as
general-purpose registers and a vector table. The memory maps of the MB95410H/470H Series are shown
below.
• Memory Maps
MB95F414H/F414K
MB95F474H/F474K
MB95F416H/F416K
MB95F476H/F476K
MB95F418H/F418K
MB95F478H/F478K
0000
H
0000
H
0000
H
I/O area
I/O area
I/O area
0080
0090
0100
H
H
0080
0090
0100
H
0080
0090
0100
H
Access prohibited
RAM 496 bytes
Access prohibited
RAM 1008 bytes
Access prohibited
RAM 2032 bytes
H
H
H
H
H
Registers
Registers
Registers
0200
H
H
0200
H
0200
H
0280
0480
H
Access prohibited
Access prohibited
0880
H
H
Access prohibited
Extended I/O area
0F80
H
0F80
H
0F80
Extended I/O area
Flash 4 Kbyte
Extended I/O area
Flash 4 Kbyte
1000
2000
H
H
1000
H
H
1000
H
2000
Vacant
Vacant
7FFF
H
Flash 60 Kbyte
BFFF
H
H
Flash 32 Kbyte
Flash 16 Kbyte
FFFF
FFFF
H
FFFF
H
DS702-00004-1v0-E
31
MB95410H/470H Series
■ I/O MAP (MB95410H Series)
Register
Address
Register name
R/W Initial value
abbreviation
PDR0
DDR0
PDR1
DDR1
—
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
Port 0 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port 0 direction register
Port 1 data register
Port 1 direction register
(Disabled)
—
—
WATR
PLLC
Oscillation stabilization wait time setting register
PLL control register
R/W 11111111B
R/W 00000000B
R/W XXXXXX11B
R/W 00000XXXB
R/W 000XXXXXB
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W XX100011B
R/W 00000000B
R/W 00000000B
SYCC
STBC
RSRR
TBTC
System clock control register
Standby control register
Reset source register
Time-base timer control register
Watch prescaler control register
Watchdog timer control register
System clock control register 2
Port 2 data register
WPCR
WDTC
SYCC2
PDR2
DDR2
Port 2 direction register
0010H,
0011H
—
(Disabled)
—
—
0012H
0013H
0014H
0015H
0016H
0017H
PDR4
DDR4
PDR5
DDR5
PDR6
DDR6
Port 4 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port 4 direction register
Port 5 data register
Port 5 direction register
Port 6 data register
Port 6 direction register
0018H
to
—
(Disabled)
—
—
001BH
001CH
001DH
001EH
001FH
0020H
0021H
0022H
0023H
PDR9
DDR9
PDRA
DDRA
PDRB
DDRB
PDRC
DDRC
Port 9 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port 9 direction register
Port A data register
Port A direction register
Port B data register
Port B direction register
Port C data register
Port C direction register
0024H,
0025H
—
(Disabled)
—
—
(Continued)
32
DS702-00004-1v0-E
MB95410H/470H Series
Register
abbreviation
Address
Register name
R/W Initial value
0026H
0027H
0028H
0029H
002AH
002BH
002CH
002DH
002EH
PDRE
DDRE
PDRF
DDRF
PDRG
DDRG
—
Port E data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port E direction register
Port F data register
Port F direction register
Port G data register
Port G direction register
(Disabled)
—
—
PUL1
PUL2
Port 1 pull-up register
Port 2 pull-up register
R/W 00000000B
R/W 00000000B
002FH,
0030H
—
(Disabled)
(Disabled)
—
—
0031H
PUL5
Port 5 pull-up register
R/W 00000000B
0032H
to
—
—
—
0034H
0035H
0036H
0037H
0038H
0039H
003AH
003BH
003CH
003DH
003EH
003FH
PULG
T01CR1
T00CR1
T11CR1
T10CR1
PC01
Port G pull-up register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
8/16-bit composite timer 01 status control register 1
8/16-bit composite timer 00 status control register 1
8/16-bit composite timer 11 status control register 1
8/16-bit composite timer 10 status control register 1
8/16-bit PPG01 control register
PC00
8/16-bit PPG00 control register
PC11
8/16-bit PPG11 control register
PC10
8/16-bit PPG10 control register
TMCSRH0 16-bit reload timer control status register upper
TMCSRL0 16-bit reload timer control status register lower
0040H
to
—
(Disabled)
—
—
0047H
0048H
0049H
004AH
004BH
EIC00
EIC10
EIC20
EIC30
External interrupt circuit control register ch. 0/ch. 1
External interrupt circuit control register ch. 2/ch. 3
External interrupt circuit control register ch. 4/ch. 5
External interrupt circuit control register ch. 6/ch. 7
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
004CH
to
—
(Disabled)
—
—
004EH
004FH
0050H
LCDCC2
CMR0
LCDC control register 2
R/W 00010100B
R/W 000X0001B
Voltage comparator control register
0051H
to
—
(Disabled)
—
—
0055H
(Continued)
DS702-00004-1v0-E
33
MB95410H/470H Series
Register
Address
Register name
R/W Initial value
abbreviation
SMC10
SMC20
SSR0
0056H
0057H
0058H
0059H
005AH
005BH
005CH
005DH
005EH
005FH
0060H
0061H
0062H
0063H
0064H
0065H
0066H
0067H
0068H
0069H
006AH
006BH
006CH
006DH
006EH
006FH
0070H
0071H
0072H
0073H
0074H
0075H
0076H
0077H
UART/SIO serial mode control register 1 ch. 0
UART/SIO serial mode control register 2 ch. 0
UART/SIO serial status register ch. 0
UART/SIO serial output data register ch. 0
UART/SIO serial input data register ch. 0
UART/SIO serial mode control register 1 ch. 1
UART/SIO serial mode control register 2 ch. 1
UART/SIO serial status register ch. 1
UART/SIO serial output data register ch. 1
UART/SIO serial input data register ch. 1
I2C bus control register 0
R/W 00000000B
R/W 00100000B
R/W 00000001B
R/W 00000000B
TDR0
RDR0
SMC11
SMC21
SSR1
R
00000000B
R/W 00000000B
R/W 00100000B
R/W 00000001B
R/W 00000000B
TDR1
RDR1
IBCR00
IBCR10
IBCR0
IDDR0
IAAR0
ICCR0
SMC12
SMC22
SSR2
R
00000000B
R/W 00000001B
R/W 00000000B
I2C bus control register 1
I2C bus status register
I2C data register
R
00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00100000B
R/W 00000001B
R/W 00000000B
I2C address register
I2C clock control register
UART/SIO serial mode control register 1 ch. 2
UART/SIO serial mode control register 2 ch. 2
UART/SIO serial status register ch. 2
UART/SIO serial output data register ch. 2
UART/SIO serial input data register ch. 2
(Disabled)
TDR2
RDR2
—
R
00000000B
—
—
ADC1
ADC2
ADDH
ADDL
WCSR
FSR2
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register upper
8/10-bit A/D converter data register lower
Watch counter status register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 000X0000B
R/W 00000000B
Flash memory status register 2
FSR
Flash memory status register
SWRE0
FSR3
Flash memory sector write control register 0
Flash memory status register 3
R
00000000B
—
—
(Disabled)
—
WREN
WROR
Wild register address compare enable register
Wild register data test setting register
R/W 00000000B
R/W 00000000B
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
0078H
—
—
—
(Continued)
34
DS702-00004-1v0-E
MB95410H/470H Series
Register
abbreviation
Address
Register name
R/W Initial value
0079H
007AH
007BH
007CH
007DH
007EH
007FH
0F80H
0F81H
0F82H
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
ILR0
ILR1
ILR2
ILR3
ILR4
ILR5
—
Interrupt level setting register 0
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Interrupt level setting register 4
Interrupt level setting register 5
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
(Disabled)
—
—
WRARH0 Wild register address setting register (upper) ch. 0
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
WRARL0
WRDR0
Wild register address setting register (lower) ch. 0
Wild register data setting register ch. 0
WRARH1 Wild register address setting register (upper) ch. 1
WRARL1
WRDR1
Wild register address setting register (lower) ch. 1
Wild register data setting register ch. 1
WRARH2 Wild register address setting register (upper) ch. 2
WRARL2
WRDR2
Wild register address setting register (lower) ch. 2
Wild register data setting register ch. 2
0F89H
to
—
(Disabled)
—
—
0F91H
0F92H
0F93H
0F94H
0F95H
0F96H
0F97H
0F98H
0F99H
0F9AH
0F9BH
0F9CH
0F9DH
0F9EH
0F9FH
0FA0H
0FA1H
0FA2H
0FA3H
T01CR0
T00CR0
T01DR
T00DR
TMCR0
T11CR0
T10CR0
T11DR
T10DR
TMCR1
PPS01
PPS00
PDS01
PDS00
PPS11
PPS10
PDS11
PDS10
8/16-bit composite timer 01 status control register 0
8/16-bit composite timer 00 status control register 0
8/16-bit composite timer 01 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
(Continued)
8/16-bit composite timer 00 data register
8/16-bit composite timer 00/01 timer mode control register
8/16-bit composite timer 11 status control register 0
8/16-bit composite timer 10 status control register 0
8/16-bit composite timer 11 data register
8/16-bit composite timer 10 data register
8/16-bit composite timer 10/11 timer mode control register
8/16-bit PPG01 cycle setting buffer register
8/16-bit PPG00 cycle setting buffer register
8/16-bit PPG01 duty setting buffer register
8/16-bit PPG00 duty setting buffer register
8/16-bit PPG11 cycle setting buffer register
8/16-bit PPG10 cycle setting buffer register
8/16-bit PPG11 duty setting buffer register
8/16-bit PPG10 duty setting buffer register
DS702-00004-1v0-E
35
MB95410H/470H Series
Register
abbreviation
Address
Register name
R/W Initial value
0FA4H
0FA5H
PPGS
8/16-bit PPG start register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
REVC
8/16-bit PPG output inversion register
16-bit reload timer timer register upper
TMRH0
0FA6H
0FA7H
TMRLRH0 16-bit reload timer reload register upper
TMRL0 16-bit reload timer timer register lower
TMRLRL0 16-bit reload timer reload register lower
UART/SIO dedicated baud rate generator prescaler select
0FA8H
0FA9H
0FAAH
0FABH
0FACH
0FADH
PSSR0
BRSR0
PSSR1
BRSR1
PSSR2
BRSR2
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
register ch. 0
UART/SIO dedicated baud rate generator baud rate setting
register ch. 0
UART/SIO dedicated baud rate generator prescaler select
register ch. 1
UART/SIO dedicated baud rate generator baud rate setting
register ch. 1
UART/SIO dedicated baud rate generator prescaler select
register ch. 2
UART/SIO dedicated baud rate generator baud rate setting
register ch. 2
0FAEH
0FAFH
0FB0H
0FB1H
0FB2H
0FB3H
0FB4H
0FB5H
0FB6H
0FB7H
0FB8H
0FB9H
0FBAH
—
(Disabled)
A/D input disable register (lower)
LCDC control register 1
(Disabled)
—
—
AIDRL
R/W 00000000B
R/W 00000000B
LCDCC1
—
—
—
LCDCE1
LCDCE2
LCDCE3
LCDCE4
LCDCE5
LCDCE6
LCDCE7
LCDCB1
LCDCB2
LCDC enable register 1
LCDC enable register 2
LCDC enable register 3
LCDC enable register 4
LCDC enable register 5
LCDC enable register 6
LCDC enable register 7
LCDC blinking setting register 1
LCDC blinking setting register 2
R/W 00111110B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
0FBBH,
0FBCH
—
(Disabled)
—
—
0FBDH
to
LCDRAM
LCDC display RAM (36 bytes)
R/W 00000000B
0FE0H
0FE1H
0FE2H
0FE3H
—
(Disabled)
Event counter control register
Watch counter data register
—
—
EVCR
WCDR
R/W 00000000B
R/W 00111111B
(Continued)
36
DS702-00004-1v0-E
MB95410H/470H Series
(Continued)
Register
abbreviation
Address
Register name
R/W Initial value
0FE4H
0FE5H
CRTH
CRTL
Main CR clock trimming register (upper)
Main CR clock trimming register (lower)
R/W 0XXXXXXXB
R/W 00XXXXXXB
0FE6H,
0FE7H
—
(Disabled)
—
—
0FE8H
0FE9H
0FEAH
0FEBH
0FECH
0FEDH
0FEEH
0FEFH
SYSC
CMCR
CMDR
WDTH
WDTL
—
System configuration register
Clock monitoring control register
Clock monitoring data register
Watchdog timer selection ID register (upper)
Watchdog timer selection ID register (lower)
(Disabled)
R/W 11000011B
R/W XX000000B
R
R
00000000B
XXXXXXXXB
XXXXXXXXB
—
R
—
ILSR
Input level select register
R/W 00000000B
R/W 01000000B
WICR
Interrupt pin control register
0FF0H
to
—
(Disabled)
—
—
0FFFH
• R/W access symbols
R/W : Readable / Writable
: Read only
R
• Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is indeterminate.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
DS702-00004-1v0-E
37
MB95410H/470H Series
■ I/O MAP (MB95470H Series)
Register
Address
Register name
R/W Initial value
abbreviation
PDR0
DDR0
PDR1
DDR1
—
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
Port 0 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port 0 direction register
Port 1 data register
Port 1 direction register
(Disabled)
—
—
WATR
PLLC
Oscillation stabilization wait time setting register
PLL control register
R/W 11111111B
R/W 00000000B
R/W XXXXXX11B
R/W 00000XXXB
R/W 000XXXXXB
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W XX100011B
R/W 00000000B
R/W 00000000B
SYCC
STBC
RSRR
TBTC
System clock control register
Standby control register
Reset source register
Time-base timer control register
Watch prescaler control register
Watchdog timer control register
System clock control register 2
Port 2 data register
WPCR
WDTC
SYCC2
PDR2
DDR2
Port 2 direction register
0010H
to
—
(Disabled)
—
—
0015H
0016H
0017H
PDR6
DDR6
Port 6 data register
R/W 00000000B
R/W 00000000B
Port 6 direction register
0018H
to
—
(Disabled)
—
—
001BH
001CH
001DH
001EH
001FH
0020H
0021H
0022H
0023H
PDR9
DDR9
PDRA
DDRA
PDRB
DDRB
PDRC
DDRC
Port 9 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port 9 direction register
Port A data register
Port A direction register
Port B data register
Port B direction register
Port C data register
Port C direction register
0024H,
0025H
—
(Disabled)
—
—
0026H
0027H
0028H
0029H
002AH
002BH
002CH
PDRE
DDRE
PDRF
DDRF
PDRG
DDRG
—
Port E data register
Port E direction register
Port F data register
Port F direction register
Port G data register
Port G direction register
(Disabled)
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
—
—
(Continued)
38
DS702-00004-1v0-E
MB95410H/470H Series
Register
abbreviation
Address
Register name
R/W Initial value
002DH
002EH
PUL1
PUL2
Port 1 pull-up register
Port 2 pull-up register
R/W 00000000B
R/W 00000000B
002FH
to
—
(Disabled)
—
—
0034H
0035H
0036H
0037H
0038H
0039H
003AH
003BH
003CH
003DH
003EH
003FH
PULG
T01CR1
T00CR1
T11CR1
T10CR1
PC01
Port G pull-up register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
8/16-bit composite timer 01 status control register 1
8/16-bit composite timer 00 status control register 1
8/16-bit composite timer 11 status control register 1
8/16-bit composite timer 10 status control register 1
8/16-bit PPG01 control register
PC00
8/16-bit PPG00 control register
PC11
8/16-bit PPG11 control register
PC10
8/16-bit PPG10 control register
TMCSRH0 16-bit reload timer control status register upper
TMCSRL0 16-bit reload timer control status register lower
0040H
to
—
(Disabled)
—
—
0047H
0048H
0049H
004AH
004BH
EIC00
EIC10
EIC20
EIC30
External interrupt circuit control register ch. 0/ch. 1
External interrupt circuit control register ch. 2/ch. 3
External interrupt circuit control register ch. 4/ch. 5
External interrupt circuit control register ch. 6/ch. 7
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
004CH
to
—
(Disabled)
—
—
004EH
004FH
0050H
LCDCC2
CMR0
LCDC control register 2
R/W 00010100B
R/W 000X0001B
Voltage comparator control register
0051H
to
—
(Disabled)
—
—
0055H
0056H
0057H
0058H
0059H
005AH
005BH
005CH
005DH
005EH
SMC10
SMC20
SSR0
UART/SIO serial mode control register 1 ch. 0
UART/SIO serial mode control register 2 ch. 0
UART/SIO serial status register ch. 0
R/W 00000000B
R/W 00100000B
R/W 00000001B
R/W 00000000B
TDR0
UART/SIO serial output data register ch. 0
UART/SIO serial input data register ch. 0
UART/SIO serial mode control register 1 ch. 1
UART/SIO serial mode control register 2 ch. 1
UART/SIO serial status register ch. 1
RDR0
SMC11
SMC21
SSR1
R
00000000B
R/W 00000000B
R/W 00100000B
R/W 00000001B
R/W 00000000B
(Continued)
TDR1
UART/SIO serial output data register ch. 1
DS702-00004-1v0-E
39
MB95410H/470H Series
Register
Address
Register name
R/W Initial value
00000000B
abbreviation
RDR1
IBCR00
IBCR10
IBCR0
IDDR0
IAAR0
ICCR0
SMC12
SMC22
SSR2
005FH
0060H
0061H
0062H
0063H
0064H
0065H
0066H
0067H
0068H
0069H
006AH
006BH
006CH
006DH
006EH
006FH
0070H
0071H
0072H
0073H
0074H
0075H
0076H
0077H
UART/SIO serial input data register ch. 1
I2C bus control register 0
R
R/W 00000001B
R/W 00000000B
I2C bus control register 1
I2C bus status register
I2C data register
R
00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00100000B
R/W 00000001B
R/W 00000000B
I2C address register
I2C clock control register
UART/SIO serial mode control register 1 ch. 2
UART/SIO serial mode control register 2 ch. 2
UART/SIO serial status register ch. 2
UART/SIO serial output data register ch. 2
UART/SIO serial input data register ch. 2
(Disabled)
TDR2
RDR2
—
R
00000000B
—
—
ADC1
ADC2
ADDH
ADDL
WCSR
FSR2
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register upper
8/10-bit A/D converter data register lower
Watch counter status register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 000X0000B
R/W 00000000B
Flash memory status register 2
Flash memory status register
FSR
SWRE0
FSR3
Flash memory sector write control register 0
Flash memory status register 3
(Disabled)
R
00000000B
—
—
—
WREN
WROR
Wild register address compare enable register
Wild register data test setting register
R/W 00000000B
R/W 00000000B
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
0078H
—
—
—
0079H
007AH
007BH
007CH
007DH
007EH
007FH
0F80H
0F81H
0F82H
ILR0
ILR1
ILR2
ILR3
ILR4
ILR5
—
Interrupt level setting register 0
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Interrupt level setting register 4
Interrupt level setting register 5
(Disabled)
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
—
—
WRARH0 Wild register address setting register (upper) ch. 0
R/W 00000000B
R/W 00000000B
R/W 00000000B
(Continued)
WRARL0
WRDR0
Wild register address setting register (lower) ch. 0
Wild register data setting register ch. 0
40
DS702-00004-1v0-E
MB95410H/470H Series
Register
abbreviation
Address
Register name
R/W Initial value
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
WRARH1 Wild register address setting register (upper) ch. 1
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
WRARL1
WRDR1
Wild register address setting register (lower) ch. 1
Wild register data setting register ch. 1
WRARH2 Wild register address setting register (upper) ch. 2
WRARL2
WRDR2
Wild register address setting register (lower) ch. 2
Wild register data setting register ch. 2
0F89H
to
—
(Disabled)
—
—
0F91H
0F92H
0F93H
0F94H
0F95H
0F96H
0F97H
0F98H
0F99H
0F9AH
0F9BH
0F9CH
0F9DH
0F9EH
0F9FH
0FA0H
0FA1H
0FA2H
0FA3H
0FA4H
0FA5H
T01CR0
T00CR0
T01DR
T00DR
TMCR0
T11CR0
T10CR0
T11DR
T10DR
TMCR1
PPS01
PPS00
PDS01
PDS00
PPS11
PPS10
PDS11
PDS10
PPGS
8/16-bit composite timer 01 status control register 0
8/16-bit composite timer 00 status control register 0
8/16-bit composite timer 01 data register
8/16-bit composite timer 00 data register
8/16-bit composite timer 00/01 timer mode control register
8/16-bit composite timer 11 status control register 0
8/16-bit composite timer 10 status control register 0
8/16-bit composite timer 11 data register
8/16-bit composite timer 10 data register
8/16-bit composite timer 10/11 timer mode control register
8/16-bit PPG01 cycle setting buffer register
8/16-bit PPG00 cycle setting buffer register
8/16-bit PPG01 duty setting buffer register
8/16-bit PPG00 duty setting buffer register
8/16-bit PPG11 cycle setting buffer register
8/16-bit PPG10 cycle setting buffer register
8/16-bit PPG11 duty setting buffer register
8/16-bit PPG10 duty setting buffer register
8/16-bit PPG start register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
REVC
8/16-bit PPG output inversion register
TMRH0
16-bit reload timer timer register upper
0FA6H
0FA7H
TMRLRH0 16-bit reload timer reload register upper
TMRL0 16-bit reload timer timer register lower
TMRLRL0 16-bit reload timer reload register lower
UART/SIO dedicated baud rate generator prescaler select
register ch. 0
0FA8H
0FA9H
0FAAH
0FABH
PSSR0
BRSR0
PSSR1
BRSR1
R/W 00000000B
R/W 00000000B
R/W 00000000B
UART/SIO dedicated baud rate generator baud rate setting
register ch. 0
UART/SIO dedicated baud rate generator prescaler select
register ch. 1
UART/SIO dedicated baud rate generator baud rate setting
register ch. 1
R/W 00000000B
(Continued)
DS702-00004-1v0-E
41
MB95410H/470H Series
Register
Address
0FACH
Register name
R/W Initial value
R/W 00000000B
R/W 00000000B
abbreviation
UART/SIO dedicated baud rate generator prescaler select
register ch. 2
PSSR2
UART/SIO dedicated baud rate generator baud rate setting
register ch. 2
0FADH
BRSR2
0FAEH
0FAFH
0FB0H
0FB1H
0FB2H
0FB3H
0FB4H
0FB5H
0FB6H
0FB7H
0FB8H
0FB9H
0FBAH
—
(Disabled)
A/D input disable register (lower)
LCDC control register 1
(Disabled)
—
—
AIDRL
R/W 00000000B
R/W 00000000B
LCDCC1
—
—
—
LCDCE1
LCDCE2
LCDCE3
LCDCE4
LCDCE5
LCDCE6
—
LCDC enable register 1
LCDC enable register 2
LCDC enable register 3
LCDC enable register 4
LCDC enable register 5
LCDC enable register 6
(Disabled)
R/W 00111100B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
—
—
LCDCB1
LCDCB2
LCDC blinking setting register 1
LCDC blinking setting register 2
R/W 00000000B
R/W 00000000B
0FBBH,
0FBCH
—
(Disabled)
—
—
0FBDH
to
LCDRAM
LCDC display RAM (28 bytes)
R/W 00000000B
0FD8H
0FD9H
to
—
(Disabled)
—
—
0FE1H
0FE2H
0FE3H
0FE4H
0FE5H
EVCR
WCDR
CRTH
CRTL
Event counter control register
R/W 00000000B
R/W 00111111B
R/W 0XXXXXXXB
R/W 00XXXXXXB
Watch counter data register
Main CR clock trimming register (upper)
Main CR clock trimming register (lower)
0FE6H,
0FE7H
—
(Disabled)
—
—
0FE8H
0FE9H
0FEAH
0FEBH
0FECH
SYSC
CMCR
CMDR
WDTH
WDTL
System configuration register
R/W 11000011B
R/W XX000000B
Clock monitoring control register
Clock monitoring data register
R
R
R
00000000B
XXXXXXXXB
XXXXXXXXB
(Continued)
Watchdog timer selection ID register (upper)
Watchdog timer selection ID register (lower)
42
DS702-00004-1v0-E
MB95410H/470H Series
(Continued)
Register
Address
Register name
(Disabled)
R/W Initial value
abbreviation
0FEDH
0FEEH
0FEFH
—
—
—
ILSR
WICR
Input level select register
Interrupt pin control register
R/W 00000000B
R/W 01000000B
0FF0H
to
—
(Disabled)
—
—
0FFFH
• R/W access symbols
R/W : Readable / Writable
: Read only
R
• Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is indeterminate.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
DS702-00004-1v0-E
43
MB95410H/470H Series
■ INTERRUPT SOURCE TABLE
Vector table address
Priority order of
interrupt sourc-
interrupt level es of the same
setting register level (occurring
simultaneously)
Interrupt
request
number
Bit name of
Interrupt source
Upper
Lower
External interrupt ch. 0
External interrupt ch. 4
External interrupt ch. 1
External interrupt ch. 5
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
UART/SIO ch. 0
High
IRQ00
IRQ01
IRQ02
IRQ03
FFFAH
FFF8H
FFF6H
FFF4H
FFFBH
FFF9H
FFF7H
FFF5H
L00 [1:0]
L01 [1:0]
L02 [1:0]
L03 [1:0]
IRQ04
IRQ05
FFF2H
FFF0H
FFF3H
FFF1H
L04 [1:0]
L05 [1:0]
8/16-bit composite timer ch. 0
(lower)
8/16-bit composite timer ch. 0
(upper)
IRQ06
FFEEH
FFEFH
L06 [1:0]
UART/SIO ch. 2
IRQ07
IRQ08
FFECH
FFEAH
FFEDH
FFEBH
L07 [1:0]
L08 [1:0]
LCD controller
8/16-bit PPG ch. 1 (lower)
UART/SIO ch. 1
IRQ09
FFE8H
FFE9H
L09 [1:0]
8/16-bit PPG ch. 1 (upper)
16-bit reload timer ch. 0
8/16-bit PPG ch. 0 (upper)
8/16-bit PPG ch. 0 (lower)
IRQ10
IRQ11
IRQ12
IRQ13
FFE6H
FFE4H
FFE2H
FFE0H
FFE7H
FFE5H
FFE3H
FFE1H
L10 [1:0]
L11 [1:0]
L12 [1:0]
L13 [1:0]
8/16-bit composite timer ch. 1
(upper)
IRQ14
FFDEH
FFDFH
L14 [1:0]
Voltage comparator
I2C
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
FFDCH
FFDAH
FFD8H
FFD6H
FFD4H
FFDDH
FFDBH
FFD9H
FFD7H
FFD5H
L15 [1:0]
L16 [1:0]
L17 [1:0]
L18 [1:0]
L19 [1:0]
—
8/10-bit A/D converter
Time-base timer
Watch prescaler
Watch counter
—
IRQ20
FFD2H
FFD3H
L20 [1:0]
IRQ21
IRQ22
IRQ23
FFD0H
FFCEH
FFCCH
FFD1H
FFCFH
FFCDH
L21 [1:0]
L22 [1:0]
8/16-bit composite timer ch. 1
(lower)
Low
Flash memory
L23 [1:0]
44
DS702-00004-1v0-E
MB95410H/470H Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VSS + 6
VSS + 6
VSS + 6
+2
Power supply voltage*1
Input voltage*1
Output voltage*1
VCC
VI
VSS − 0.3
VSS − 0.3
VSS − 0.3
−2
V
V
V
*2
*2
VO
Maximum clamp current
ICLAMP
mA Applicable to specific pins*3
Total maximum clamp
current
Σ|ICLAMP|
—
—
20
15
mA Applicable to specific pins*3
“L” level maximum
output current
ICL
mA
Average output current =
mA operating current × operating ratio
(1 pin)
“L” level average current
ICLAV
—
—
—
—
—
—
—
4
“L” level total maximum
output current
ΣIOL
100
50
mA
Total average output current =
mA operating current × operating ratio
(Total number of pins)
“L” level total average
output current
ΣIOLAV
“H” level maximum
output current
ICH
−15
−4
mA
Average output current =
mA operating current × operating ratio
(1 pin)
“H” level average
current
ICHAV
“H” level total maximum
output current
ΣIOH
−100
−50
mA
Total average output current =
mA operating current × operating ratio
(Total number of pins)
“H” level total average
output current
ΣIOHAV
Power consumption
Operating temperature
Storage temperature
Pd
TA
—
320
+85
mW
°C
−40
−55
Tstg
+150
°C
*1: These parameters are based on the condition that VSS = 0.0 V.
*2: VI and VO must not exceed VCC + 0.3 V. VI must not exceed the rated voltage. However, if the maximum
current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of
the VI rating.
(Continued)
DS702-00004-1v0-E
45
MB95410H/470H Series
(Continued)
*3: Applicable to the following pins: P00 to P07, P10, P11, P13 to P16, P20 to P22, P40 to P43, P50 to P53,
P60 to P67, P90 to P94, PA0 to PA7, PB0 to PB4, PC0 to PC7, PE0 to PE7, PF0, PF1, PG1 and PG2 (P40
to P43, P50 to P53, P94, PB2 to PB4 and PC4 to PC7 are only available on the MB95410H Series.)
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor
between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistance should be set so that when the HV (High Voltage) signal is applied the
inputcurrentto the microcontroller pindoes notexceed ratedvalues, eitherinstantaneouslyor for prolonged
periods.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High
Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin, and
thus affects other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since
power is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage
of power supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit
• Input/Output equivalent circuit
Protective diode
VCC
P-ch
Limiting
resistor
HV(High Voltage) input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
46
DS702-00004-1v0-E
MB95410H/470H Series
2. Recommended Operating Conditions
Value
(VSS = 0.0 V)
Parameter Symbol
Unit
Remarks
Min
2.4*1*2
2.3
Max
5.5*1
5.5
In normal operation
Other than on-chip debug
mode
Hold condition in stop mode
In normal operation
Power supply
voltage
VCC,
AVCC
V
2.9
5.5
On-chip debug mode
2.3
5.5
Hold condition in stop mode
Smoothing
capacitor
CS
TA
0.022
1
µF *3
−40
+5
+85
+35
Other than on-chip debug mode
Operating
temperature
°C
On-chip debug mode
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range.
*2: The value is initially 2.88 V when the low-voltage detection reset is used.
*3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for
the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see
the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise,
minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing
the layout of a printed circuit board.
• DBG / RST / C pins connection diagram
*
DBG
C
RST
Cs
*: Since the DBG pin becomes a communication pin in on-chip debug mode,
set a pull-up resistor value suiting the input/output specifications of P12/DBG.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
onthedatasheet.Usersconsideringapplicationoutsidethelistedconditionsareadvisedtocontact
their representatives beforehand.
DS702-00004-1v0-E
47
MB95410H/470H Series
3. DC Characteristics
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter Symbol
Pin name
Condition
Unit
Remarks
Min
Typ
Max
When CMOS
input level
(hysteresis input)
is selected
P01, P04, P10,
P22, P23
VIHI
*1
0.7 VCC
—
VCC + 0.3
V
P00 to P07,
P10 to P17,
P20 to P23,
P40 to P43*2,
P50 to P53*2,
P60 to P67,
P90 to P93,
P94*2,
"H" level
input
voltage
VIHS
*1
0.8 VCC
—
VCC + 0.3
V
Hysteresis input
PA0 to PA7,
PB0, PB1,
PB2 to PB4*2,
PC0 to PC3,
PC4 to PC7*2,
PE0 to PE7,
PF0, PF1,
PG1, PG2
VIHM
PF2
—
*1
0.7 VCC
—
—
VCC + 0.3
V
V
Hysteresis input
When CMOS
input level
(hysteresis input)
is selected
P01, P04, P10,
P22, P23
VIL
VSS − 0.3
0.3 VCC
P00 to P07,
P10 to P17,
P20 to P23,
P40 to P43*2,
P50 to P53*2,
P60 to P67,
P90 to P93,
P94*2,
“L” level
input
voltage
VILS
*1
VSS − 0.3
—
0.2 VCC
V
Hysteresis input
PA0 to PA7,
PB0, PB1,
PB2 to PB4*2,
PC0 to PC3,
PC4 to PC7*2,
PE0 to PE7,
PF0, PF1,
PG1, PG2
VILM
PF2
—
—
VSS − 0.3
VSS − 0.3
—
—
0.3 VCC
V
V
Hysteresis input
Open-drain
output
application
voltage
P12, P22, P23,
PF2
VD
VSS + 5.5
“H” level
Output pins
output
voltage
VOH1
otherthanP12, IOH = −4 mA
P22, P23, PF2
VCC − 0.5
—
—
V
(Continued)
48
DS702-00004-1v0-E
MB95410H/470H Series
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Typ*4
Parameter Symbol
Pin name
Condition
Unit
Remarks
Min
Max
“L”leveloutput
VOL1
All output pins IOL = 4 mA
—
—
0.4
V
voltage
Input leak
current (Hi-Z
output leak
current)
When pull-up
µA resistance is
disabled
ILI
All input pins
0.0 V < VI < VCC
−5
—
+5
P10, P11, P13,
P14, P17, P20,
P21,
When pull-up
kΩ resistance is
enabled
Pull-up
RPULL
VI = 0 V
25
50
100
resistance
P50 to P53*2,
PG1, PG2
Input
capacitance
Other than VCC
and VSS
CIN
f = 1 MHz
—
—
5
15
17
pF
Except during
Flash memory
14.1
mA
VCC = 5.5 V
programming
and erasing
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
ICC
During Flash
memory
mA
—
—
20
39.5
9
programming
and erasing
VCC = 5.5 V
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
ICCS
6.6
mA
VCC = 5.5 V
VCC
Power supply
FCL = 32 kHz
FMPL = 16 kHz
Subclock mode
(divided by 2)
TA = +25°C
(External clock
operation)
current*3
ICCL
—
60
153
µA
µA
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = +25°C
ICCLS
—
—
9
84
30
VCC = 5.5 V
FCL = 32 kHz
Watch mode
Main stop mode
TA = +25°C
ICCT
4.3
µA
(Continued)
DS702-00004-1v0-E
49
MB95410H/470H Series
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Min Typ*4 Max
Parameter Symbol
Pin name
Condition
Unit
Remarks
VCC = 5.5 V
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
TA = +25°C
—
—
9.7
12.5
20
mA
VCC
ICCMPLL
(External clock
operation)
VCC = 5.5 V
FCH = 6.44 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
TA = +25°C
13.9
mA
VCC = 5.5 V
FCRH = 12.5 MHz
FMP = 12.5 MHz
Main CR clock
mode
ICCMCR
—
—
—
11
112
1
13.2
410
3
mA
µA
VCC
VCC = 5.5 V
Sub-CR clock
mode
(multiplied by 2.5)
TA = +25°C
ICCSCR
Power supply
current*3
VCC = 5.5 V
FCH = 32 MHz
Time-base timer
mode
ICCTS
mA
VCC
(External clock
operation)
TA = +25°C
VCC = 5.5 V
Substop mode
TA = +25°C
Main stop
ICCH
—
—
3.1
1.5
22.5
4.7
µA mode with one
clock selected
Current
consumption for
A/D conversion at
16 MHz
IA
mA
Current
consumption for
stopping
A/D conversion at
16 MHz
IAH
AVCC
—
—
1
5
µA
Current
consumption of
voltage comparator
at 16 MHz
IV
113
350
µA
(Continued)
50
DS702-00004-1v0-E
MB95410H/470H Series
(Continued)
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Typ*4
Parameter Symbol
Pin name
Condition
Current
Unit
Remarks
Min
Max
consumption of the
low-voltage
ILVD
—
31
54
µA
detection circuit
Current
Powersupply
current*3
ICRH
consumption of the
main CR oscillator
—
—
0.5
20
0.6
72
mA
µA
VCC
Current
consumption of the
sub-CR oscillator
oscillating at
100 kHz
ICRL
LCD internal
division
resistance
—
—
400
40
—
—
kΩ
kΩ
RLCD
—
Between V4 and VSS
COM0 to
COM7 output RVCOM COM0 to COM7
impedance
—
—
—
—
5
7
kΩ
kΩ
V1 to V4 = 4.1 V
SEG00 to
SEG39
output
SEG00 to
SEG39
RVSEG
impedance
V0 to V4,
COM0 to
COM7,
SEG00 to
SEG39
LCD leakage
current
ILCDL
—
−1
—
+1
µA
*1: The input levels of P01, P04, P10, P22 and P23 can be switched between “CMOS input level” and “hysteresis
input level”. The input level selection register (ILSR) is used to switch between the two input levels.
*2: P40 to P43, P50 to P53, P94, PB2 to PB4 and PC4 to PC7 are only available on the MB95410H Series.
*3: • The power supply current is determined by the external clock. When the low-voltage detection option is
selected, the power-supply current will be the sum of adding the current consumption of the low-voltage
detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection
option and the CR oscillator are selected, the power supply current will be the sum of adding up the current
consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL)
and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit
are always enabled, and current consumption therefore increases accordingly.
• See "4. AC Characteristics: (1) Clock Timing" for FCH and FCL.
• See "4. AC Characteristics: (2) Source Clock/Machine Clock" for FMP and FMPL.
*4: VCC = 5.0 V, TA = +25°C
DS702-00004-1v0-E
51
MB95410H/470H Series
4. AC Characteristics
(1) Clock Timing
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Typ
Parameter Symbol Pin name Condition
Min
Unit
Remarks
Max
16.25 MHz
12 MHz
32.5 MHz
When the main oscillation
circuit is used
X0, X1
X0
—
1
—
X1: open
1
1
—
—
—
—
—
12.5
10
8
When the main external
clock is used
*
FCH
—
—
—
3
3
8.13 MHz Main PLL multiplied by 2
6.5 MHz Main PLL multiplied by 2.5
X0, X1
—
3
4.06 MHz Main PLL multiplied by 4
12.75 MHz
12.25
9.8
7.84
0.98
Operating conditions:
10.2 MHz
—
• The main CR clock is used.
• TA = −10°C to +85°C
8.16 MHz
1.02 MHz
Clock
1
frequency
FCRH
12.1875 12.5 12.8125 MHz
Operating conditions:
• The main CR clock is used.
• TA = −40°C to −10°C
9.75
7.8
0.975
10
8
1
10.25 MHz
MHz
1.025 MHz
—
—
—
8.2
When the sub-oscillation
circuit is used
When the sub-external clock
is used
When the sub-CR clock is
used
When the main oscillation
circuit is used
—
—
32.768
32.768
100
—
—
kHz
kHz
kHz
ns
FCL
X0A, X1A
FCRL
—
—
—
50
200
1000
X0, X1
61.5
—
tHCYL
Clock cycle
time
X0
X1: open
83.4
30.8
—
33.4
12.4
—
—
30.5
—
1000
1000
—
ns
ns
When the external clock is
used
X0, X1
X0A, X1A
X0
*
tLCYL
—
X1: open
*
µs When the subclock is used
ns
—
tWH1
tWL1
When the external clock is
Input clock
pulse width
X0, X1
—
—
ns used, the duty ratio should
range between 40% and
tWH2
tWL2
X0A
X0
—
X1: open
*
—
—
—
15.2
—
—
5
µs
60%.
Input clock
rise time
and fall time
ns
tCR
tCF
When the external clock is
used
X0, X1
—
5
ns
µs
µs
When the main CR clock is
used
When the sub-CR clock is
used
tCRHWK
tCRLWK
—
—
—
—
—
—
—
—
80
10
CR
oscillation
start time
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
52
DS702-00004-1v0-E
MB95410H/470H Series
• Input waveform generated when an external clock (main clock) is used
t
HCYL
t
WH1
t
WL1
t
CR
tCF
0.8 VCC 0.8 VCC
0.2 VCC
X0, X1
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When a crystal oscillator or When the external clock is used When the external clock is used
a ceramic oscillator is used (X1 is open)
X0
X1
X0
X1
X0
X1
Open
FCH
F
CH
FCH
• Input waveform generated when an external clock (subclock) is used
t
LCYL
tWH2
t
WL2
t
CR
t
CF
0.8 VCC 0.8 VCC
0.2 VCC
X0A
0.2 VCC
0.2 VCC
• Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
When the external clock is used
X0A X1A
X0A X1A
Open
F
CL
FCL
DS702-00004-1v0-E
53
MB95410H/470H Series
(2) Source Clock/Machine Clock
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Typ
Pin
name
Parameter Symbol
Unit
Remarks
Min
Max
When the main oscillation clock is used
61.5
—
—
—
2000
ns Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
When the main oscillation clock is used
Min: FCH = 8.125 MHz, multiplied by the
PLL multiplier of 2
61.5
80
2000
1000
ns
Max: FCH = 1 MHz, divided by 2
Source clock
tSCLK
—
cycle time*1
When the main CR clock is used
ns Min: FCRH = 12.5 MHz
Max: FCRH = 1 MHz
When the sub-oscillation clock is used
FCL = 32.768 kHz, divided by 2
—
—
61
20
—
—
µs
When the sub-CR clock is used
µs
FCRL = 100 kHz, divided by 2
0.50
1
—
—
16.25 MHz When the main oscillation clock is used
FSP
12.5
—
MHz When the main CR clock is used
Source clock
frequency
—
—
—
—
16.384
kHz When the sub-oscillation clock is used
FSPL
When the sub-CR clock is used
kHz
—
50
—
FCRL = 100 kHz, divided by 2
When the main oscillation clock is used
ns Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
61.5
—
32000
When the main CR clock is used
ns Min: FSP = 12.5 MHz
Machine clock
cycle time*2
(minimum
instruction
execution
time)
80
61
20
—
—
—
16000
976.5
320
Max: FSP = 1 MHz, divided by 16
tMCLK
When the sub-oscillation clock is used
µs Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
When the sub-CR clock is used
µs Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
0.031
0.0625
1.024
—
—
—
16.25 MHz When the main oscillation clock is used
12.5 MHz When the main CR clock is used
FMP
Machine clock
frequency
16.384 kHz When the sub-oscillation clock is used
FMPL
When the sub-CR clock is used
FCRL = 100 kHz
3.125
—
50
kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock divide ratio select
bits (SYCC:DIV1, DIV0). This source clock is divided to become a machine clock according to the division
ratio set by the machine clock divide ratio select bits (SYCC:DIV1, DIV0). In addition, a source clock can be
selected from the following.
• Main clock divided by 2
• PLL multiplication of main clock (select from 2, 2.5, 4 multiplication)
• Main CR clock divided by 2
• Subclock divided by 2
• Sub-CR clock divided by 2
(Continued)
DS702-00004-1v0-E
54
MB95410H/470H Series
(Continued)
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
• Schematic diagram of the clock generation block
Main PLL
× 2
× 2.5
× 4
Divided
by 2
FCH
(main oscillation)
Division
circuit
FCRH
(Main CR clock)
MCLK
SCLK
(source clock)
×
1
Divided
by 2
× 1/4
× 1/8
×1/16
(machine clock)
FCL
(sub-oscillation)
Divided
by 2
FCRL
(Sub-CR clock)
Clock mode select bits
(SYCC2: RCS1, RCS0)
Machine clock divide ratio select bits
(SYCC: DIV1, DIV0)
DS702-00004-1v0-E
55
MB95410H/470H Series
• Operating voltage - Operating frequency (When TA = −40°C to +85°C)
Without the on-chip debug function
5.5
5.0
A/D converter operation range
4.0
3.5
3.0
2.4
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP/FSPL
)
• Operating voltage - Operating frequency (When TA = −40°C to +85°C)
With the on-chip debug function
5.5
5.0
A/D converter operation range
4.0
3.5
3.0
2.9
16 kHz
3 MHz
12.5 MHz
16.25 MHz
Source clock frequency (FSP)
56
DS702-00004-1v0-E
MB95410H/470H Series
(3) External Reset
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter Symbol
Unit
Remarks
Min
Max
2 tMCLK*1
—
ns In normal operation
In stop mode, subclock mode,
µs subsleep mode, watch mode, and
power-on
RST “L” level
tRSTL
Oscillation time of the
—
—
pulse width
oscillator*2 + 100
100
µs In time-base timer mode
*1: See “(2) Source Clock/Machine Clock” for tMCLK.
*2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has
an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of
between hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator
clock has an oscillation time of between several µs and several ms.
• In normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, subclock mode, subsleep mode, watch mode and power-on
t
RSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
100 μs
Oscillation
time of
oscillator
Oscillation stabilization wait time
Internal reset
Execute instruction
DS702-00004-1v0-E
57
MB95410H/470H Series
(4) Power-on Reset
(VSS = 0.0 V, TA = −40°C to +85°C)
Value
Max
Parameter
Symbol
Condition
Unit
Remarks
Min
—
1
Power supply rising time
Power supply cutoff time
tR
—
—
50
—
ms
tOFF
ms Wait time until power-on
t
R
tOFF
2.5 V
0.2 V
0.2 V
0.2 V
VCC
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the
power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as
shown below.
VCC
Set the slope of rising to
a value below 30 mV/ms.
2.3 V
Hold condition in stop mode
V
SS
58
DS702-00004-1v0-E
MB95410H/470H Series
(5) Peripheral Input Timing
Parameter
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Symbol
Pin name
Unit
Min
Max
—
Peripheral input “H” pulse width
Peripheral input “L” pulse width
tILIH
tIHIL
2 tMCLK*
2 tMCLK*
ns
ns
INT00 to INT07, EC0, EC1, ADTG
—
*: See “(2) Source Clock/Machine Clock” for tMCLK.
t
ILIH
t
IHIL
0.8 VCC 0.8 VCC
INT00 to INT07,
EC0, EC1, ADTG
0.2 VCC
0.2 VCC
DS702-00004-1v0-E
59
MB95410H/470H Series
(6) UART/SIO, Serial I/O Timing
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter
Serial clock cycle time
UCK ↓→ UO time
Symbol
tSCYC
Pin name
Condition
Unit
ns
Min
Max
UCK0, UCK1, UCK2
4 tMCLK*
—
UCK0, UCK1, UCK2,
UO0, UO1, UO2
UCK0, UCK1, UCK2,
UI0, UI1, UI2
UCK0, UCK1, UCK2,
UI0, UI1, UI2
tSLOVI
−190
+190
—
ns
Internal clock
operation output pin:
CL = 80 pF + 1 TTL
Valid UI → UCK ↑
tIVSHI
2 tMCLK*
2 tMCLK*
ns
ns
UCK ↑→ valid UI hold time
tSHIXI
tSHSL
tSLSH
—
Serial clock “H” pulse width
Serial clock “L” pulse width
UCK0, UCK1, UCK2
UCK0, UCK1, UCK2
4 tMCLK*
—
—
ns
ns
4 tMCLK*
UCK0, UCK1, UCK2,
UO0, UO1, UO2
UCK ↓→ UO time
tSLOVE
tIVSHE
tSHIXE
External clock
operation output pin:
CL = 80 pF + 1 TTL
—
190
—
ns
ns
ns
UCK0, UCK1, UCK2,
UI0, UI1, UI2
UCK0, UCK1, UCK2,
UI0, UI1, UI2
Valid UI → UCK ↑
2 tMCLK*
2 tMCLK*
UCK ↑→ valid UI hold time
—
*: See “(2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
2.4 V
UCK0,
UCK1,
0.8 V
0.8 V
UCK2
tSLOVI
UO0,
UO1,
UO2
2.4 V
0.8 V
tIVSHI
tSHIXI
UI0,
UI1,
UI2
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
t
SLSH
t
SHSL
UCK0,
UCK1,
UCK2
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
t
SLOVE
UO0,
UO1,
UO2
2.4 V
0.8 V
t
IVSHE
t
SHIXE
UI0,
UI1,
UI2
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
60
DS702-00004-1v0-E
MB95410H/470H Series
(7) Low-voltage Detection
Parameter
(VSS = 0.0 V, TA = −40°C to +85°C)
Value
Typ
2.7
Symbol
Unit
Remarks
Min
2.52
2.42
70
Max
2.88
2.78
—
Release voltage
VDL+
VDL-
VHYS
Voff
V
V
At power supply rise
Detection voltage
2.6
At power supply fall
Hysteresis width
100
—
mV
V
Power supply start voltage
Power supply end voltage
—
2.3
Von
4.9
—
—
V
Power supply voltage
change time
(at power supply rise)
Slope of power supply that the reset
µs release signal generates within the
rating (VDL+)
tr
tf
3000
300
—
—
—
—
Power supply voltage
change time
(at power supply fall)
Slope of power supply that the reset
µs detection signal generates within the
rating (VDL-)
Reset release delay time
Reset detection delay time
td1
td2
—
—
—
—
300
20
µs
µs
VCC
Von
Voff
time
tf
tr
V
V
DL+
V
HYS
DL-
Internal reset signal
time
td2
td1
DS702-00004-1v0-E
61
MB95410H/470H Series
(8) I2C Timing
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value
Standard-
mode
Parameter
Symbol Pin name Conditions
Fast-mode Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
SCL
0
100
0
400 kHz
(Repeat) Start condition hold time
SDA ↓ → SCL ↓
tHD;STA SCL, SDA
4.0
—
0.6
—
µs
SCL clock “L” width
SCL clock “H” width
tLOW
tHIGH
SCL
SCL
4.7
4.0
—
—
1.3
0.6
—
—
µs
µs
(Repeat) Start condition setup time
SCL ↑ → SDA ↓
tSU;STA SCL, SDA
tHD;DAT SCL, SDA
tSU;DAT SCL, SDA
tSU;STO SCL, SDA
4.7
0
—
3.45*2
—
0.6
0
—
µs
R = 1.7 kΩ,
C = 50 pF*1
Data hold time
SCL ↓ → SDA ↓ ↑
0.9*3 µs
Data setup time
SDA ↓ ↑ → SCL ↑
0.25
4.0
4.7
0.1
0.6
1.3
—
—
—
µs
µs
µs
Stop condition setup time
SCL ↑ → SDA ↑
—
Bus free time between stop condition
and start condition
tBUF
SCL, SDA
—
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2: The maximum tHD;DAT in the Standard-modeis applicable only when the time during which the device is holding
the SCL signal at “L” (tLOW) does not extend.
*3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition
of tSU;DAT ≥ 250 ns is fulfilled.
tWAKEUP
SDA
tHD;STA
tHD;DAT
tHIGH
tBUF
tLOW
SCL
tSU;STO
tHD;STA
tSU;DAT
fSCL
tSU;STA
(Continued)
62
DS702-00004-1v0-E
MB95410H/470H Series
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value*2
Pin
name
Parameter Symbol
Conditions
Unit
Remarks
Min
Max
SCL clock
tLOW
(2 + nm / 2)tMCLK − 20
SCL
SCL
—
ns Master mode
ns Master mode
“L” width
SCL clock
tHIGH
(nm / 2)tMCLK − 20
(nm / 2)tMCLK + 20
“H” width
Master mode
Maximum value
is applied when
ns m, n = 1, 8.
Otherwise, the
minimum value is
applied.
Start
condition
hold time
SCL,
SDA
(− 1 + nm / 2)tMCLK − 20 (− 1 + nm)tMCLK + 20
(1 + nm / 2)tMCLK − 20 (1 + nm / 2)tMCLK + 20
tHD;STA
Stop
condition
setup time
SCL,
SDA
tSU;STO
ns Master mode
Start
condition
setup time
SCL,
SDA
tSU;STA
(1 + nm / 2)tMCLK − 20 (1 + nm / 2)tMCLK + 20 ns Master mode
Busfreetime
between
stop
condition
and start
condition
SCL,
SDA
(2 nm + 4)tMCLK − 20
tBUF
—
—
ns
R = 1.7 kΩ,
C = 50 pF*1
Data hold
time
SCL,
SDA
3 tMCLK − 20
tHD;DAT
ns Master mode
Master mode
When assuming
that “L” of SCL is
not extended, the
minimum value is
Data setup
time
SCL,
SDA
tSU;DAT
(− 2 + nm / 2)tMCLK − 20 (− 1 + nm / 2)tMCLK + 20 ns applied to first bit
of continuous
data.
Otherwise, the
maximum value
is applied.
Minimum value is
applied to
interrupt at 9th
Setup time
between
(nm / 2)tMCLK − 20
(1 + nm / 2)tMCLK + 20
clearing
interrupt and
SCL rising
tSU;INT SCL
ns SCL↓. Maximum
value is applied
to interrupt at 8th
SCL↓.
SCL clock
“L” width
4 tMCLK − 20
4 tMCLK − 20
tLOW
tHIGH
SCL
SCL
—
—
ns At reception
SCL clock
“H” width
ns At reception
(Continued)
DS702-00004-1v0-E
63
MB95410H/470H Series
(Continued)
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value*2
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Not detected when
ns 1 tMCLK is used at
reception
Start condition
detection
SCL,
SDA
2 tMCLK − 20
2 tMCLK − 20
2 tMCLK − 20
tHD;STA
—
Not detected when
ns 1 tMCLK is used at
reception
Stop condition
detection
SCL,
SDA
tSU;STO
—
—
Not detected when
ns 1 tMCLK is used at
reception
Restart condition
detection condition
SCL,
SDA
tSU;STA
SCL,
SDA
Bus free time
tBUF
2 tMCLK − 20
2 tMCLK − 20
tLOW − 3 tMCLK − 20
0
—
—
—
—
—
ns At reception
R = 1.7 kΩ,
SCL,
SDA
At slave
ns
C = 50 pF*1
Data hold time
Data setup time
Data hold time
Data setup time
tHD;DAT
tSU;DAT
tHD;DAT
tSU;DAT
transmission mode
SCL,
SDA
At slave
ns
transmission mode
SCL,
SDA
ns At reception
ns At reception
SCL,
SDA
tMCLK − 20
Oscillation
stabilization wait
time
SDA↓→SCL↑
(at wakeup
function)
SCL,
SDA
tWAKEUP
—
ns
+ 2 tMCLK − 20
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2: • See “(2) Source Clock/Machine Clock” for tMCLK.
• m represents the CS4 bit and CS3 bit (bit4 and bit3) in the I2C clock control register (ICCR0).
• n represents the CS2 bit to CS0 bit (bit2 to bit0) in the I2C clock control register (ICCR0).
• The actual timing of I2C is determined by the values of m and n set by the machine clock (tMCLK) and the
CS4 to CS0 bits in the ICCR0 register.
• Standard-mode:
m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
: 0.9 MHz < tMCLK ≤ 2 MHz
: 0.9 MHz < tMCLK ≤ 4 MHz
: 0.9 MHz < tMCLK ≤ 10 MHz
: 0.9 MHz < tMCLK ≤ 16.25 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4)
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8)
(m, n) = (1, 98), (5, 22), (6, 22), (7, 22)
(m, n) = (8, 22)
• Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK ≤ 4 MHz
: 3.3 MHz < tMCLK ≤ 8 MHz
: 3.3 MHz < tMCLK ≤ 10 MHz
: 3.3 MHz < tMCLK ≤ 16.25 MHz
(m, n) = (1, 22), (5, 4)
(m, n) = (1, 38), (6, 4), (7, 4), (8, 4)
(m, n) = (5, 8)
64
DS702-00004-1v0-E
MB95410H/470H Series
(9) Voltage Comparator Timing
(AVCC = 4.0 V to 5.5 V, AVSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter
Voltage range
Pin name
Unit
Remarks
Min
0
Typ
—
Max
AVCC − 1.3
+10
CMPP, CMPN
CMPP, CMPN
V
Offset voltage
−10
—
—
mV
650
140
1210
ns 5 mV overdrive
ns 50 mV overdrive
Delay time
CMPO
—
420
Power down recovery
PD: 1 → 0
—
—
1210
ns
CMPO
Power down delay
Power down effective
ns PD: 0 → 1
0
—
—
Output: “H” level
Output stabilization
ns
CMPO
—
Power up stabilization time
Bandgap reference voltage
—
—
1210
1.27
time at power up
1.17
1.22
V
DS702-00004-1v0-E
65
MB95410H/470H Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVCC = VCC = 4.0 V to 5.5 V, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value
Typ
—
Parameter
Resolution
Symbol
Unit
Remarks
Min
—
Max
10
bit
Total error
−3
—
+3
LSB
LSB
—
Linearity error
−2.5
—
+2.5
Differential linear
error
−1.9
—
+1.9
LSB
V
Zero transition
voltage
VOT
AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
AVCC − 4.5 LSB AVCC − 2 LSB AVCC + 0.5 LSB
Full-scale transition
voltage
VFST
V
0.9
1.8
—
—
16500
16500
µs 4.5 V ≤ VCC ≤ 5.5 V
µs 4.0 V ≤ VCC < 4.5 V
Compare time
Sampling time
—
4.5V≤ VCC ≤ 5.5V, with
µs external impedance
< 5.4 kΩ
0.6
1.2
—
—
∞
∞
—
4.0 V ≤ VCC < 4.5V, with
µs external impedance
< 2.4 kΩ
Analog input current
Analog input voltage
IAIN
−0.3
—
—
+0.3
µA
V
VAIN
AVSS
AVCC
66
DS702-00004-1v0-E
MB95410H/470H Series
(2) Notes on Using the A/D Converter
• External impedance of analog input and its sampling time
• The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient
sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is
insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision
standard, considering the relationship between the external impedance and minimum sampling time, either
adjust the register value and operating frequency or decrease the external impedance so that the sampling
time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect
a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
VCC
R
C
4.5 V ≤ VCC ≤ 5.5 V
4.0 V ≤ VCC < 4.5 V
1.95 kΩ (Max)
8.98 kΩ (Max)
17 pF (Max)
17 pF (Max)
Note: The values are reference values.
• Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 100 kΩ]
[External impedance = 0 kΩ to 20 kΩ]
100
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
(VCC ≥ 4.5 V)
(VCC ≥ 4.0 V)
(VCC ≥ 4.5 V)
(VCC ≥ 4.0 V)
6
4
2
0
0
2
4
6
8
10
12
14
0
1
2
3
4
Minimum sampling time [μs]
Minimum sampling time [μs]
• A/D conversion error
As |VCC−VSS| decreases, the A/D conversion error increases proportionately.
DS702-00004-1v0-E
67
MB95410H/470H Series
(3) Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting
the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device to
the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) of the same device.
• Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an
ideal value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a
zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
Total error
3FFH
3FEH
3FDH
3FFH
3FEH
3FDH
VFST
Actual conversion
characteristic
2 LSB
{1 LSB × (N-1) + 0.5 LSB}
004H
003H
002H
001H
004H
003H
002H
001H
VOT
VNT
Actual conversion
characteristic
1 LSB
Ideal characteristic
0.5 LSB
VSS
Analog input
VCC - VSS
VCC
VSS
Analog input
VCC
VNT - {1 LSB × (N - 1) + 0.5 LSB}
1 LSB
Total error of
digital output N
1 LSB =
(V)
=
[LSB]
1024
N
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
(Continued)
68
DS702-00004-1v0-E
MB95410H/470H Series
(Continued)
Zero transition error
Full-scale transition error
Ideal characteristic
004H
003H
002H
001H
Actual conversion
characteristic
3FFH
Actual conversion
characteristic
3FEH
VFST
(measurement
Actual conversion
Ideal
value)
characteristic
3FDH
characteristic
Actual conversion
characteristic
3FCH
VOT (measurement value)
Analog input
VSS
VCC
VSS
Analog input
VCC
Linearity error
Differential linearity error
Ideal characteristic
Actual conversion
characteristic
3FFH
3FEH
3FDH
(N+1)H
Actual conversion
characteristic
{1 LSB × N + VOT}
V(N+1)T
VFST
NH
(N-1)H
(N-2)H
(measurement
value)
VNT
004H
003H
002H
001H
VNT
Actual conversion
characteristic
Ideal
characteristic
Actual conversion
characteristic
VOT (measurement value)
Analog input
VSS
VCC
VSS
Analog input
VCC
V(N+1)T - VNT
VNT - {1 LSB × N + VOT}
1 LSB
Differential linear error
of digital output N
Linearity error
of digital output N
=
- 1
=
1 LSB
N
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
VOT (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC - 2 LSB [V]
DS702-00004-1v0-E
69
MB95410H/470H Series
6. Flash Memory Program/Erase Characteristics
Value
Parameter
Unit
Remarks
Min
Typ
Max
Sector erase time
(2 Kbyte sector)
The time of writing 00H prior to
erasure is excluded.
—
0.2*1
0.5*2
s
s
Sector erase time
(16 Kbyte sector)
The time of writing 00H prior to
erasure is excluded.
—
0.5*1
7.5*2
Byte writing time
—
21
—
6100*2
—
µs System-level overhead is excluded.
cycle
Program/erase cycle
100000
Power supply voltage at
program/erase
3.0
—
—
5.5
—
V
Flash memory data retention
time
20*3
year Average TA = +85°C
*1: TA = +25°C, VCC = 5.0 V, 100000 cycles
*2: TA = +85°C, VCC = 3.0 V, 100000 cycles
*3: This value is converted from the result of a technology reliability assessment. (The value is converted from
the result of a high temperature accelerated test using the Arrhenius equation with the average temperature
being +85°C).
70
DS702-00004-1v0-E
MB95410H/470H Series
■ SAMPLE CHARACTERISTICS
• Power supply current temperature characteristics
ICC − VCC
ICC − TA
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
20
20
FMP = 16 MHz
FMP = 16 MHz
FMP = 10 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
15
15
10
5
10
5
0
0
2
3
4
5
6
7
−50
0
+50
+100
+150
VCC[V]
T
A[°C]
ICCS − VCC
ICCS − TA
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
Main sleep mode with the external clock operating
20
20
FMP = 16 MHz
FMP = 16 MHz
FMP = 10 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
15
15
10
5
10
5
0
0
2
3
4
5
6
7
−50
0
+50
+100
+150
VCC[V]
ICCL − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
T
A
[°C]
ICCL − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
Subclock mode with the external clock operating
100
100
75
50
25
0
75
50
25
0
2
3
4
5
6
7
−50
0
+50
[°C]
+100
+150
VCC[V]
T
A
(Continued)
DS702-00004-1v0-E
71
MB95410H/470H Series
ICCLS − VCC
ICCLS − TA
TA = +25°C, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
100
75
50
25
0
100
75
50
25
0
2
3
4
5
6
7
−50
0
+50
+100
+150
VCC[V]
T
A[°C]
ICCT − VCC
ICCT − TA
TA = +25°C, FMPL = 16 kHz (divided by 2)
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
Watch mode with the external clock operating
100
100
75
50
25
0
75
50
25
0
2
3
4
5
6
7
−50
0
+50
+100
+150
VCC[V]
T
A[°C]
ICCTS − VCC
ICCTS − TA
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock operating
Time-base timer mode with the external clock operating
2.0
2.0
FMP = 16 MHz
FMP = 16 MHz
FMP = 10 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
1.5
1.5
1.0
0.5
0.0
1.0
0.5
0.0
2
3
4
5
6
7
−50
0
+50
[°C]
+100
+150
VCC[V]
T
A
(Continued)
72
DS702-00004-1v0-E
MB95410H/470H Series
(Continued)
ICCH − VCC
ICCH − TA
TA = +25°C, FMPL = (stop)
VCC = 5.5 V, FMPL = (stop)
Substop mode with the external clock stopping
Substop mode with the external clock stopping
20
20
15
10
5
15
10
5
0
0
2
3
4
5
6
7
−50
0
+50
+100
+150
VCC[V]
T
A[°C]
ICCMCR − VCC
ICCMCR − TA
TA = +25°C, FMP = 1, 8, 10, 12.5 MHz (no division)
VCC = 5.5 V, FMP = 1, 8, 10, 12.5 MHz (no division)
Main clock mode with the main CR clock operating
Main clock mode with the main CR clock operating
20
20
FMP = 12.5 MHz
FMP = 12.5 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 1 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 1 MHz
15
10
5
15
10
5
0
0
2
3
4
5
6
7
−50
0
+50
+100
+150
VCC[V]
T
A[°C]
ICCSCR − VCC
ICCSCR − TA
TA = +25°C, FMPL = 50 kHz (divided by 2)
VCC = 5.5 V, FMPL = 50 kHz (divided by 2)
Subclock mode with the sub-CR clock operating
Subclock mode with the sub-CR clock operating
160
160
140
120
100
80
140
120
100
80
60
60
40
40
20
20
0
0
2
3
4
5
6
7
−50
0
+50
[°C]
+100
+150
VCC[V]
T
A
DS702-00004-1v0-E
73
MB95410H/470H Series
• Input voltage characteristics
VIHI − VCC and VILI − VCC
VIHS − VCC and VILS − VCC
TA = +25°C
TA = +25°C
5
5
4
3
2
1
0
VIHI
VILI
VIHS
VILS
4
3
2
1
0
2
3
4
5
6
7
2
3
4
5
6
7
VCC[V]
VCC[V]
VIHM − VCC and VILM − VCC
TA = +25°C
5
4
3
2
1
0
VIHM
VILM
2
3
4
5
6
7
VCC[V]
74
DS702-00004-1v0-E
MB95410H/470H Series
• Output voltage characteristics
(VCC − VOH1) − IOH
TA = +25°C
VOL1 − IOL
TA = +25°C
1.0
1.0
0.8
0.8
0.6
0.4
0.2
0.0
0.6
0.4
0.2
0.0
0
−2
−4
−6
−8
−10
0
2
4
6
8
10
IOH [mA]
IOL [mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
DS702-00004-1v0-E
75
MB95410H/470H Series
• Pull-up characteristics
RPULL − VCC
TA = +25°C
250
200
150
100
50
0
2
3
4
5
6
V
CC[V]
76
DS702-00004-1v0-E
MB95410H/470H Series
■ MASK OPTIONS
MB95F414H
MB95F414K
MB95F416K
MB95F418K
MB95F474K
MB95F476K
MB95F478K
MB95F416H
MB95F418H
MB95F474H
MB95F476H
MB95F478H
Part Number
No.
Selectable/Fixed
Fixed
1
2
Low-voltage detection reset Without low-voltage detection reset With low-voltage detection reset
Reset With dedicated reset input Without dedicated reset input
DS702-00004-1v0-E
77
MB95410H/470H Series
■ ORDERING INFORMATION
Part Number
Package
MB95F414HPMC-G-SNE2
MB95F414KPMC-G-SNE2
MB95F416HPMC-G-SNE2
MB95F416KPMC-G-SNE2
MB95F418HPMC-G-SNE2
MB95F418KPMC-G-SNE2
80-pin plastic LQFP
(FPT-80P-M37)
MB95F474HPMC1-G-SNE2
MB95F474KPMC1-G-SNE2
MB95F476HPMC1-G-SNE2
MB95F476KPMC1-G-SNE2
MB95F478HPMC1-G-SNE2
MB95F478KPMC1-G-SNE2
64-pin plastic LQFP
(FPT-64P-M38)
MB95F474HPMC2-G-SNE2
MB95F474KPMC2-G-SNE2
MB95F476HPMC2-G-SNE2
MB95F476KPMC2-G-SNE2
MB95F478HPMC2-G-SNE2
MB95F478KPMC2-G-SNE2
64-pin plastic LQFP
(FPT-64P-M39)
78
DS702-00004-1v0-E
MB95410H/470H Series
■ PACKAGE DIMENSION
80-pin plastic LQFP
Lead pitch
0.50 mm
12.00 mm × 12.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.47 g
Sealing method
Mounting height
Weight
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00 0.20(.551 .008)SQ
*12.00 0.10(.472 .004)SQ
0.145 0.055
(.006 .002)
60
41
Details of "A" part
61
40
1.50 +–00..1200
(Mounting height)
.059 +–..000048
0.25(.010)
0~8°
0.08(.003)
0.50 0.20
(.020 .008)
0.10 0.05
(.004 .002)
(Stand off)
0.60 0.15
(.024 .006)
INDEX
80
21
"A"
1
20
0.50(.020)
0.22 0.05
(.009 .002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS702-00004-1v0-E
79
MB95410H/470H Series
64-pin plastic LQFP
Lead pitch
0.50 mm
10.00 mm × 10.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.32 g
Sealing method
Mounting height
Weight
(FPT-64P-M38)
64-pin plastic LQFP
(FPT-64P-M38)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00 0.20(.472 .008)SQ
*10.00 0.10(.394 .004)SQ
0.145 0.055
(.006 .002)
48
33
Details of "A" part
49
32
1.50 +–00..1200
0.08(.003)
(Mounting height)
.059 +–..000048
0.25(.010)
0~8°
INDEX
0.50 0.20
(.020 .008)
0.10 0.10
(.004 .004)
(Stand off)
64
17
0.60 0.15
(.024 .006)
"A"
1
16
0.50(.020)
0.22 0.05
(.009 .002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
80
DS702-00004-1v0-E
MB95410H/470H Series
(Continued)
64-pin plastic LQFP
Lead pitch
0.65 mm
12.00 mm × 12.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.47 g
(FPT-64P-M39)
64-pin plastic LQFP
(FPT-64P-M39)
Note 1) Pins width and pins thickness include plating thickness.
14.00 0.20(.551 .008)SQ
12.00 0.10(.472 .004)SQ
48
33
Details of "A" part
49
32
1.50 +0.20
.059 +.008
–0.10
–.004
0~8˚
0.10(.004)
0.10 0.10
(.004 .004)
INDEX
0.50 0.20
(.020 .008)
0.25(.010)BSC
64
17
0.60 0.15
(.024 .006)
1
16
"A"
0.65(.026)
0.32 0.05
(.013 .002)
M
0.13(.005)
C
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS702-00004-1v0-E
81
MB95410H/470H Series
■ MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
Details
Changed the family name.
F2MC-8FX → New 8FX
1
—
49 to 51 ■ ELECTRICAL CHARACTERISTICS Changed the values of the following power supply current
3. DC Characteristics
parameters:
ICC, ICCS, ICCL, ICCLS, ICCT, ICCMPLL, ICCMCR, ICCSCR, ICCTS, ICCH, IA,
IV, ILVD.
52
64
■ ELECTRICAL CHARACTERISTICS Changed the values of the clock frequency (FCRH).
4. AC Characteristics
(1) Clock Timing
■ ELECTRICAL CHARACTERISTICS Changed the settings related to the machine clock shown
4. AC Characteristics
in *2.
(8) I2C Timing
71 to 76 ■ SAMPLE CHARACTERISTICS
Added “■ SAMPLE CHARACTERISTICS”.
82
DS702-00004-1v0-E
MB95410H/470H Series
MEMO
DS702-00004-1v0-E
83
MB95410H/470H Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
Specifications are subject to change without notice. For further information please contact each office.
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Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
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The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-
ing in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-
current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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