MB90092_01 [FUJITSU]
ON-Screen Display Controller; 屏幕显示控制器
| 型号： | MB90092_01 |
| 厂家： | 
FUJITSU |
| 描述： | ON-Screen Display Controller |
| 文件： | 总40页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-28824-3E
ASSP for Screen Display Control
CMOS
ON-Screen Display Controller
MB90092
■ DESCRIPTION
The MB90092 is the display controller for displaying text and graphics on the TV screen.
The MB90092 incorporates display memory (VRAM), a font memory interface, and a video signal generator,
allowing text and graphics to be displayed in conjunction with a small number of external components.
The MB90092 can provide two screens, called the main screen and the sub-screen, either independently or
overlayed one on top of the other.
The main screen consists of 24 characters by 12 lines and allows data to be set for each character. The sub-
screen consists of 32 characters by 12 lines or up to 32 characters by 16 lines. Data can be set either for each
line in the former configuration or collectively for the entire screen in the latter configuration.
For output of video signals, the MB90092 has the composite video signal, Y/C-separated video signal, and RGB
digital output pins. The MB90092 also has video signal input pins, allowing superimpose display over either
composite video signals and Y/C-separated video signals.
■ PACKAGE
80-pin Plastic QFP
(FPT-80P-M06)
MB90092
■ FEATURES
• Main Screen Display
• Screen display capacity:24 characters × 12 lines (up to 288 characters)
• Character dot configuration:24 × 32 dots (per character)
• Character types: 16384 different characters (when using a 16 M bit external clock)
• Character sizes: Standard, double width, double height, double width × double height,
quadruple width × double height (Setting possible for each line)
• Display position control :Horizontal display position
Vertical display position
:Set in 1/3-character units
:Set in raster units
Line spacing control
:Set in raster units (0 to 15 rasters)
• Display priority control:Capable of controlling display priority over the sub-screen (for each line)
• Sub-Screen Display
Screen display position: Settable horizontally and vertically in 2-dot units
• Normal screen mode:Screen capacity:32 characters × 12 lines (up to 384 characters)
256 horizontal dots × 384 vertical dots (graphics characters only) (The
actual display screen depends on the television system and dot clock
frequency.) Normal character/graphic character display selectable for
each line (Header display character code is specified for each line.)
Character string length:Selectable from among 1, 2, 4, 8, 16, 24, and 32 digits
• Full-screen mode
Screen capacity: 32 characters × 16 lines (up to 512 characters)
256 horizontal dots × 512 vertical dots
(The actual display screen depends on the television
system and dot clock frequency.)
Virtual screen capacity:Mode A:32 characters × 16 lines (× 32 screens)
256 horizontal dots × 512 vertical dots
Mode B:512 characters × 32 lines
4096 horizontal dots × 1024 vertical dots
Screen Background Display
Screen background color: 8 colors (set for the entire screen)
Analog Inputs
• Composite video signal input
• Y/C-separated inputs
Analog Outputs
• Composite video signal output
• Y/C-separated outputs
Digital Outputs
• G (Green), R (Red), and B (Blue) output
• VOC (character) output, VOB (character + background) output
• Characters, character background, line background, and screen background each capable of being displayed
in eight colors
Internal Synchronization Control (Video Signal Generator)
• Internal video signal generator supporting the NTSC and PAL systems
• Interlaced/noninterlaced display selectable
(Continued)
2
MB90092
(Continued)
External Synchronization Control
• Separated sync signal input/composite sync signal input selectable
External Interface
• 8-bit serial inputs (3 signal input pins)
Chip select: CS
Serial clock: SCLK
Serial data: SIN
Package
• QFP-80
Miscellaneous
• Internal power-on reset circuit
3
MB90092
■ PIN ASSIGNMENT
(TOP VIEW)
TESTI
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
ADR10
ADR9
VCC
VOC
VOB
VSS
2
3
4
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
VSS
B
5
R
6
G
7
CS
8
SCLK
SIN
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VCC
EXHSYN
EXVSYN
HSYNC
VSYNC
VBLNK
EXS
DA7
DA6
DA5
DA4
XS
DA3
TEST1
FSCO
CBCK
PDS
DA2
DA1
DA0
READ
VCC
VSS
AVSS
AVCC1
(FPT-80P-M06)
4
MB90092
■ PIN DESCRIPTION
Circuit
type
Pin no. Pin name I/O
Function
Test signal input pin. Input High level signal during normal operation.
This pin also can be used as a reset signal input pin by Low-level input
to the TEST pin. That is effective only after release of power-on reset.
This pin is a hysteresis input with an internal pull-up resistor.
1
2
3
TESTI
VOC
VOB
I
B
C
C
Character interval signal output pin.
The output signal represents the character dot output interval.
O
O
Character/background internal signal output pin.
During internal synchronization control operation, the output signal rep-
resents the character, character background, line background, or screen
background output interval.
5
6
7
B
R
G
Color signal output pins.
These pins output the character, character background, line back-
ground, and screen background color signals.
O
I
C
B
Chip select pin.
For serial transfer, set this pin to the Low level.
This pin is also used to release a power-on reset.
The pin is a hysteresis input with an internal pull-up resistor.
8
CS
Shift clock input pin for serial transfer.
This pin is a hysteresis input with an internal pull-up resistor.
9
SCLK
SIN
I
I
B
B
Serial data input pin.
The pin is a hysteresis input with an internal pull-up resistor.
10
External horizontal sync signal input pin.
Input negative logic signal.
12
13
14
EXHSYN
EXVSYN
HSYNC
I
I
B
B
C
This pin can also serve as a composite sync signal input pin depending
on the internal register setting.
The pin is a hysteresis input with an internal pull-up resistor.
External vertical sync signal input pin.
Input negative logic signal.
Input to this pin is disabled when composite sync signal input has been
selected by setting the internal register. The pin is a hysteresis input with
an internal pull-up resistor.
Horizontal sync signal output pin.
This pin can also output composite sync signals depending on the inter-
nal register setting.
O
The pin outputs the signal (FSC) resulting from dividing the 4FSC clock
frequency by setting the TEST pin to the Low level.
Vertical sync signal output pin.
This pin is fixed at the High level when composite sync signal output has
been selected by setting the internal register.
The pin outputs the dot clock oscillator signal when the TEST pin goes
into Low.
15
16
VSYNC
VBLNK
O
O
C
C
Vertical blanking interval signal output pin.
This pin outputs the Low-level signal in the vertical blanking interval.
(Continued)
5
MB90092
Circuit
type
Pinno. Pin name I/O
Function
External circuit pins for color burst clock generator.
Connect an external crystal oscillator (14.31818 MHz for NTSC or
17.734475 MHz for PAL) and load capacitance (C) to these pins to form
a crystal oscillator circuit.
17
18
EXS
XS
I
O
H
Internal color burst clock output pin.
20
FSCO
O
C
This pin controls internal color burst clock output depending on the FO
bit of command 7.
21
22
CBCK
PDS
I
G
D
External color burst clock input pin
O
Pin for output of the result of color burst clock phase comparison
Luminance signal output pin.
31
32
34
35
37
YOUT
YIN
O
I
F
E
F
E
F
This pin outputs a signal of 2 VP-P (pedestal level 1.57 V, sync tip level 1
V).
Luminance signal input pin for superimpose display.
This pin inputs a DC-reproduced (DC-clamped) signal of 2 VP-P (pedestal
level 1.57 V, sync tip level 1 V).
Saturation signal output pin.
This pin outputs a signal at 1.57 VDC and a color burst signal amplitude
of 0.57 VP-P.
COUT
CIN
O
I
Saturation signal input pin for superimpose display.
This pin inputs a signal at 1.57 VDC and a color burst signal amplitude
of 0.57 VP-P.
Composite video signal output pin.
This pin outputs a signal of 2 VP-P (pedestal level 1.57 V, sync tip level
1 V).
VOUT
O
Background level control input pin for halftone background display of ex-
ternal input composite video signals (input to the VIN pin and output
from the VOUT pin).
Halftone background display is controlled by setting the KID bit of com-
mand 5 to “1”.
38
39
VKIN
I
E
F
Background level control output pin for halftone background display of
external input composite video signals (input to the VIN pin and output
from the VOUT pin).
VKOUT
O
Halftone background display is controlled by setting the KID bit of com-
mand 5 to “1”.
Composite video signal input pin for superimpose display.
This pin inputs a DC-reproduced (DC-clamped) signal of 2 VP-P (pedestal
level 1.57 V, sync tip level 1 V).
40
43
VIN
I
E
D
External font memory read control pin.
This pin outputs the Low-level signal in the font memory read period.
The pin enters the high impedance state when the TSC pin inputs a
Low-level signal.
READ
O
(Continued)
6
MB90092
Circuit
type
Pin no. Pin name I/O
Function
44
45
46
47
48
49
50
51
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
External font memory data input pins.
These pins are inputs with an internal pull-up resistor.
I
A
External font memory address output pins.
These pins enter the high impedance state when the TSC pin inputs a
Low-level signal.
53
54
55
56
57
58
59
60
61
63
64
66
67
68
69
70
71
72
73
74
75
ADR0
ADR1
ADR2
ADR3
ADR4
ADR5
ADR6
ADR7
ADR0
ADR1
ADR2
Raster address
ADR3
ADR4
ADR5
ADR6
ADR7
1
2
M0, SM0
M1, SM1
M2, SM2
ADR8
ADR9
M3, SM3
M4, SM4
Character code (Lower bits)
ADR8
ADR9
ADR10
ADR11
ADR12
ADR13
ADR14
ADR15
ADR16
ADR17
ADR18
ADR19
ADR20
M5, SM5
M6, SM6
Data distinction bits
ADR10
ADR11
ADR12
ADR13
ADR14
ADR15
ADR16
ADR17
ADR18
ADR19
ADR20
O
D
(12,13 = 00: Left, 10: Center, 01: Right)
M7, SM7
M8, SM8
M9, SM9
MA, SMA
MB, SMB
MC, SMC
MD, SMD
Character code (Higher bits)
*1: M0 to MD are control bits for main screen character
control data setting (the commands 1-1 and 2-1)
*2: SM0 to SMD are control bits for sub-screen character
control data setting (the commands 1-2 and 2-2)
Tristate control input pin for external font memory control bus.
When this pin inputs a Low-level signal, the ADR0 to ADR20 pins and
the READ pin enter the high impedance state.
77
78
TSC
I
I
B
The pin is a hysteresis input with an internal pull-up resistor.
Test signal input pin.
This pin usually inputs a High-level (fixed) signal.
TEST
B
I
External circuit pins for display dot clock generator.
Connect these pins to external “L” and “C” to form an LC oscillator cir-
cuit.
79
80
EXD
XD
I
O
(Continued)
7
MB90092
(Continued)
Circuit
type
Pin no. Pin name I/O
Function
19
25
26
27
28
TEST1
TEST2
TEST3
TEST4
TEST5
O
—
Leave these pins unconnected.
11
42
62
76
VCC
—
—
—
—
Power-supply pins (+5 V)
4
23
52
65
VSS
Ground pins
41
AVCC1
AVCC2
—
—
—
—
Analog power pin for composite video signals (VIN-VOUT)
Analog power pin for luminance (YIN-YOUT) and chroma (CIN-COUT)
signals
33
24
29
30
36
Analog circuit ground pins.
Set these pins to the same level as the VSS pin.
AVSS
—
—
8
MB90092
■ I / O CIRCUIT TYPE
Type
Circuit
Remarks
CMOS level input
A
B
With pull-up resistor: approxi-
mately 50 kΩ
CMOS level, hysteresis input
With pull-up resistor: approxi-
mately 50 kΩ
C
CMOS output
D
CMOS three state output
(Continued)
9
MB90092
(Continued)
Control signal
Analog input
Analog input
CMOS analog SW
E
Control signal
Analog output
CMOS analog SW
F
Analog output
Control signal
G
CMOS level, hysteresis input
XS
EXS
H
Crystal oscillation circuit
Control signal
XD
EXD
I
LC oscillation circuit
Inside
clock signal
Control signal
10
MB90092
■ BLOCK DIAGRAM
SIN
SCLK
CS
Serial input
control
Each control and data
TEST
VIN
YIN
CIN
VOUT
YOUT
COUT
Analog
SW
VKOUT
VKIN
H/V separation
circuit
EXHSYN
EXVSYN
NTSC/PAL
signal
generator
Video signal
generator
HSYNC
VSYNC
VBLNK
B
R
G
VOB
VOC
Displaymemory
control
Output
control
ADR0 ~ ADR20
READ
DA0 ~ DA7
TSC
Font
memory
control
Display memory
(VRAM)
Phase
comparator
(color burst)
4FSC clock
oscillator
XS
EXS
CBCK
PDS
FSCO
Each block
XD
EXD
Dot clock
oscillator
Each block
11
MB90092
■ DISPLAY CONTROL COMMANDS
First byte
Command code/data
76543
10000 VSL RA8 RA7
Second byte
Data
Command
no.
Function
2
1
0
7
6
5
4
3
2
1
0
VRAM address setting
0
0
RA6 RA5 CA4 CA3 CA2 CA1 CA0
Main screen
BG
BR
BB
character control
data setting 1*
1-1
10001 MA MB
10010 M9 M8
10001 SMA SMB
AT
M7
0
0
0
0
0
0
CG CR CB MC
M6 M5 M4 M3
(GR)* (BS)* (MD)*
Main screen
character control
data setting 2
2-1
1-2
2-2
1-3
M2
M1
M0
Sub-screen line
control data setting
1
SCG SCR SCB SMC SGR SDC SMD
SM6 SM5 SM4 SM3 SM2 SM1 SM0
Sub-screen line
control data setting
2
10010 SM9 SM8 SM7
Main screen line
control data setting
1
10001 OF1 OF0
0
0
0
0
PC
PG
PR
PB
Main screen line
2-3
3
control data setting 10010 G2 G1
G0
0
0
SOC VD DG KC
KG
0
KR
0
KB
0
2
VRAM write
control
10011 FIL
10100 IE
0
0
0
0
0
0
4
5
Screen control 1
Screen control 2
IN
EB
0
0
EO CM ZM NP
BH2 BH1 BH0 W3
P2
P0
DC
W0
10101 KID APC GYZ
W2
W1
Main screen line
control
6
10110 G2 G1
10111 EC LP
G0
0
SOC VD DG N3
N2
N1
N0
Main screen vertical
display position
control
7
8
FO
FC
0
0
0
0
Y5
X5
Y4
X4
Y3
X3
Y2
X2
Y1
X1
Y0
X0
Main screen horizontal
display position control
11000 SC
0
Main screen
display mode
control
9
11001
11010
0
0
0
0
GRM
RB
0
RP1 RP0 S16 SF1 DW4 RM1 RM0
BK CC BC UC UG UR UB
SCC SBC SGC SBG SBR SBB
10
11
Color control
0
0
Sub-screen
control
11011 SG2 SG1 SG0
11100 SGA SY7
SX8 SX7
0
Sub-screen vertical
display position
control
12
13
0
0
0
SY6 SY5 SY4 SY3 SY2 SY1 SY0
SX6 SX5 SX4 SX3 SX2 SX1 SX0
Sub-screen horizontal
display position control
11101
0
14
15
(Reserved)
(Reserved)
11110
11111
—
—
—
—
—
—
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
*: Parenthesized bit names are used for extended graphics mode.
Note: DC bit of screen control 1 (command 4) is initialized at “0” and display is off by reset. All command data and
all VRAM are needed to set after release of power-on reset.
12
MB90092
■ COMMAND
1. VRAM Address Setting (Command 0)
MSB
LSB
VSL RA8 RA7
First byte
1
0
0
0
0
0
LSB
CA3 CA2 CA1 CA0
MSB
Second byte
RA6 RA5 CA4
VSL
: VRAM write control
RA8 to RA5 : VRAM row address setting (0H to BH)
CA4 to CA0 : VRAM column address setting (00H to 17H)
2. VRAM Data Settings 1 and 2 (Commands 1 and 2)
(1) Writing main screen character control data (when command 0: VSL = 0)
• Command 1-1 (Main screen character control data setting 1)
MSB
LSB
LSB
First byte
1
0
0
0
1
MA
MB
BR
AT
BB
MSB
Second byte
BG
(GR) (BS)
0
CG
CR
CB
MC
(MD)
*
*: Parenthesized bit names are used for extended graphics mode.
• Command 2-1 (Main screen character control data setting 2)
MSB
LSB
M7
M9
M2
M8
M1
First byte
1
0
0
0
1
0
LSB
MSB
Second byte
M6
M5
M4
M3
M0
(MD), MC to M0 : Character code
AT
: Specify character attribute display.
: Character colors
: Character background colors
: Specify normal character/graphic character display.
: Specify shaded background display.
CG, CR, CB
BG, BR, BB
(GR)
(BS)
13
MB90092
(2) Writing sub-screen line control data (when command 0: VSL = 1, CA0 = 0)
• Command 1-2 (Sub-screen line control data setting 1)
MSB
LSB
SMA SMB
0
First byte
1
0
0
0
0
1
LSB
SCG SCR SCB SMC SGR SDC SMD
MSB
Second byte
• Command 2-2 (Sub-screen line control data setting 2)
MSB
LSB
SM9 SM8 SM7
First byte
1
0
0
1
0
LSB
SM6 SM5 SM4 SM3 SM2 SM1 SM0
MSB
Second byte
0
SMD to SM0
SDC
: Sub-screen line first character code
: Sub-screen line output control
SGR
: Sub-screen line character display control
SCG to SCB
SCG
SCR, SCB
: Sub-screen line character colors (when SGR = 0)
: Sub-screen line graphic color transparency control (when SGR = 1)
: Sub-screen line graphic color phase control (when SGR = 1)
14
MB90092
(3) Writing main screen control data (when command 0: VSL = 1, CA0 = 1)
• Command 1-3 (Main screen line control data setting 1)
MSB
LSB
LSB
First byte
1
0
0
0
0
0
0
1
OF1 OF0
0
MSB
Second byte
0
PC
PG
PR
PB
• Command 2-3 (Main screen line control data setting 2)
MSB
LSB
LSB
First byte
1
0
0
1
0
G2
KG
G1
KR
G0
KB
MSB
Second byte
0
SOC VD
DG
KC
OF1, OF0
PC
PG, PR, PB
G2, G1, G0
SOC
: Character color phase control
: Shaded pattern background color/monochrome control
: Shaded pattern background color
: Character size control
: Output priority control
VD
: Video signal output control
DG
: Digital signal output control
KC
KG, KR, KB
: Line background color/monochrome control
: Line background color
3. VRAM Write Control (Command 3)
MSB
LSB
First byte
1
0
0
0
0
0
1
0
1
0
FIL
0
0
0
0
0
LSB
MSB
Second byte
FIL: VRAM fill control
15
MB90092
4. Screen Control 1 (Command 4)
MSB
LSB
LSB
First byte
1
0
0
1
0
0
IE
IN
EB
MSB
Second byte
EO
CM
ZM
NP
P2
P0
DC
IE
IN
EB
EO
CM
ZM
NP
: Internal/external synchronization control
: Interlaced/noninterlaced display control
: Screen background display control
: Field control
: Color/monochrome display control
: Zoom-in control
: NTSC/PAL control
P2, P0 : Pattern background control
DC : Display control
5. Screen Control 2 (Command 5)
MSB
LSB
APC GYZ
First byte
1
0
0
1
0
1
KID
W2
LSB
MSB
Second byte
BH2 BH1 BH0
W3
W1
W0
KID
APC
GYZ
: Halftone control
: Reserve*
: Main screen line enlargement control
BH2 to BH0 : Reserve*
W3 to W0
: Main screen line spacing control
*: Reserve must be set at “ 0 ”.
16
MB90092
6. Main Screen Line Control (Command 6)
MSB
LSB
LSB
First byte
1
0
0
1
1
0
G2
N2
G1
N1
G0
N0
MSB
Second byte
SOC VD
DG
N3
G2 to G0
SOC
: Character size control
: Output priority control
VD
DG
N3 to N0
: Video signal output control
: Digital signal output control
: Line specification
7. Main Screen Vertical Display Position Control (Command 7)
MSB
LSB
FO
First byte
1
0
0
0
1
1
1
EC
Y2
LP
Y1
LSB
MSB
Second byte
Y5
Y4
Y3
Y0
EC
LP
FO
: Sync signal output control
: Simple NTSC/PAL control
: Color phase signal output control
Y5 to Y0
: Main screen vertical display position control
8. Main Screen Horizontal Display Position Control (Command 8)
MSB
LSB
FC
First byte
1
0
1
0
0
0
0
SC
X2
0
LSB
MSB
Second byte
X5
X4
X3
X1
X0
SC
FC
X5 to X0
: Sync signal input control
: Sync signal input 3 µs filter control
: Main screen horizontal display position control
17
MB90092
9. Main Screen Display Mode Control (Command 9)
MSB
LSB
GRM
First byte
1
0
1
0
0
1
0
0
LSB
RM1 RM0
MSB
Second byte
DW4
SF1
RP1
RP0 S16
GRM: Main screen display mode control
RP1, RPO : Reserve 4*
S16
SF1
DW4
: Reserve 3*
: Reserve 2*
: Reserve 1*
RM1, RM0 : Reserve 0*
*: Reserve 0 to reserve 4 must be set at “0”.
10. Color Control (Command 10)
MSB
LSB
LSB
First byte
1
0
1
0
1
0
0
0
RB
MSB
Second byte
BK
CC
BC
UC
UG
UR
UB
RB
BK
CC
BC
: Main screen solid-fill background display control
: Main screen blink display control
: Main screen character color/monochrome control
: Main screen character background color/monochrome control
(Main screen graphic color/monochrome control)
: Screen background color/monochrome control
UC
UG, UR, UB : Screen background color
18
MB90092
11. Sub-Screen Control (Command 11)
MSB
LSB
SG2 SG1 SG0
First byte
1
0
1
0
0
1
1
LSB
SBG SBR SBB
MSB
Second byte
SGC
SCC SBC
SG2 to SG0
SCC
SBC
: Sub-screen configuration control
: Sub-screen character color/monochrome control
: Sub-screen character background color/monochrome control
: Sub-screen graphic color/monochrome control
SGC
SBG, SBR, SBB : Sub-screen pattern background color
12. Sub-Screen Vertical Display Position Control (Command 12)
MSB
LSB
SY7
First byte
1
0
1
1
0
0
SGA
0
LSB
SY0
MSB
Second byte
SY6
SY5
SY4
SY3 SY2
SY1
SGA
: Sub-screen full-screen mode control
SY7 to SY0 : Sub-screen vertical display position
13. Sub-Screen Horizontal Display Position Control (Command 13)
MSB
LSB
SX7
First byte
1
0
1
1
0
1
0
SX8
SX1
LSB
SX0
MSB
Second byte
SX6
SX5
SX4
SX3 SX2
SX8 to SX0 : Sub-screen horizontal display position
19
MB90092
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Remarks
Min.
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
—
Max.
VSS + 7.0
VSS + 7.0
VSS + 7.0
VSS + 7.0
VSS + 7.0
600
VCC
AVCC1
AVCC2
VIN
V
V
*1
*1
*1
*2
*2
Supply voltage
V
Input voltage
V
Output voltage
VOUT
Pd
V
Power consumption
Operating temperature
Storage temperature
mW
°C
°C
Ta
–40
+85
Tstg
–55
+150
*1: AVSS and VSS must have equal potential.
*2: Neither VIN nor VOUT must exceed “VCC + 0.3 V.”
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
(VSS = AVSS = 0 V)
Value
Parameter
Symbol
Unit
Remarks
Min.
Max.
Specification guarantee
range
VCC
4.5
5.5
V
Supply voltage
AVCC1
AVCC2
VIHS1
VIHS2
VILS1
VILS2
Ta
4.5
4.5
5.5
5.5
V
V
*1, *2
*1, *3
2.2
VCC + 0.3
VCC + 0.3
+ 0.8
V
DA0 to DA7
Except DA0 to DA7
DA0 to DA7
Except DA0 to DA7
“H” level input voltage
“L” level input voltage
0.8 × VCC
–0.3
–0.3
–40
V
V
0.2 × VCC
+85
V
Operating temperature
Analog input voltage
°C
V
AVIN
0
VCC
*1: AVSS and VSS must have equal potential.
*2: “AVCC1 = AVSS” is allowed if composite video signals (VIN-VOUT pins) are not used.
*3: “AVCC2 = AVSS” is allowed if Y/C-separated video signals (YIN-YOUT and CIN-COUT pins) are not used.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
20
MB90092
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(Ta = –40°C to +85°C, VSS = AVSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Conditions
Unit Remarks
Min.
Typ.
Max.
“H” level
output
voltage
VOC, VOB, B,
R, G, HSYNC,
VSYNC,
VBLNK, FSCO,
READ,
VCC = 4.5 V
IOH = –2 mA
VOH
4.0
—
—
V
V
“L” level
output
voltage
VCC = 4.5 V
IOL = 4.0 mA
VOL
—
—
—
0.4
ADR0 to ADR20
TESTI, CS,
SCLK, SIN,
EXHSYN,
EXVSYN,
CBCK,
Input
current
VCC = 5.5 V
VIL = 0.0 V
IIL
–200
–50
µA
DA0 to DA7,
TSC, TEST
VCC = AVCC1 = AVCC2 = 5.5 V
4fsc = 17.734475 MHz
fDC = 16.0 MHz
Supply
current
VCC, AVCC1,
AVCC2
ICC
—
—
—
—
50
30
mA
mA
No load
VCC = AVCC1 = AVCC2 = 5.5 V
4fsc = fDC = 0 MHz
AVIN = 1.65 V
Analog
supply
current
IA
AVCC1, AVCC2
No load
VIN-VOUT,
YIN-YOUT,
CIN-COUT,
VIN-VKOUT,
VKIN-VOUT
ON
resistance
VCC = AVCC1 = AVCC2 = 4.5 V
IOL = 100 µA
RON
—
100
320
Ω
Off
leakage
current
VIN, YIN, CIN,
VKIN
VCC = AVCC1 = AVCC2 = 5.5 V
AVIN = 5.5 V
IOFF
—
0.1
—
10
µA
Output
resistance
VOUT, YOUT,
COUT, VKOUT
VCC = AVCC1 = AVCC2 = 4.5 V
IOL = 100 µA
ROUT
100
1800
Ω
(Continued)
21
MB90092
(Ta = –40°C to +85°C, VSS = AVSS = 0 V)
Value
Sym-
Parameter
bol
Pin
Conditions
Unit
Remarks
Min.
Typ.
Max.
Yellow
VYELH
2.89
3.00
3.11
V
V
V
V
V
V
V
V
V
V
V
V
V
V
High level
Yellow
VYELL
2.03
2.89
1.63
2.66
1.63
2.49
1.46
2.49
1.23
2.15
1.23
1.80
1.12
2.14
3.00
1.74
2.77
1.74
2.60
1.57
2.60
1.34
2.26
1.34
1.91
1.23
2.25
3.11
1.85
2.88
1.85
2.71
1.68
2.71
1.45
2.37
1.45
2.02
1.34
Low level
Cyan
High level
VCYAH
Cyan
Low level
VCYAL
Green
High level
VGREH
Green
Low level
VGREL
Magenta
VMAGH
See Figure
“VOUT out-
put”
High level
VOUT
VCC = AVCC1 = AVCC2 = 5.0 V
Magenta
VMAGL
Low level
Red
High level
VREDH
Red
Low level
VREDL
Blue
High level
VBLUH
Blue
Low level
VBLUL
Color burst
VBSTH
High level
Color burst
VBSTL
Low level
(Continued)
22
MB90092
(Ta = –40°C to +85°C, VSS = AVSS = 0 V)
Values
Sym-
bol
Parameter
Pin
Conditions
Unit
Remarks
Min.
Typ.
Max.
White level 3
φ = – 270°
VWHT3
YWHT3
2.83
2.94
3.05
V
V
V
V
V
V
V
V
V
V
White level 2
φ = – 180°
VWHT2
YWHT2
2.72
2.60
2.49
2.43
2.26
2.15
1.98
1.86
1.69
2.83
2.71
2.60
2.54
2.37
2.26
2.09
1.97
1.80
2.94
2.82
2.71
2.65
2.48
2.37
2.20
2.08
1.91
White level 1
φ = – 90°
VWHT1
YWHT1
White level 0
φ = 0°
VWHT0
YWHT0
Gray
level 6
VGRY6
YGRY6
Gray
level 5
VGRY5
YGRY5
Gray
level 4
VGRY4
YGRY4
Gray
level 3
VGRY3
YGRY3
See
Figures
“VOUT
Output”and
“YOUT
Output”.
Gray
level 2
VGRY2
YGRY2
VOUT,
YOUT
VCC = AVCC1 = AVCC2 = 5.0 V
Gray
level 1
VGRY1
YGRY1
Black
level 3
φ = – 270°
VBLK3
YBLK3
1.92
1.80
1.69
1.57
2.03
1.91
1.80
1.68
2.14
2.02
1.91
1.79
V
V
V
V
Black
level 2
φ = – 180°
VBLK2
YBLK2
Black
level 1
φ = – 90°
VBLK1
YBLK1
Black
level 0
φ = 0°
VBLK0
YBLK0
Pedestal
level
VPDS
YPDS
1.46
0.84
1.57
1.00
1.68
1.16
V
V
VTIP
YTIP
SYNC level
(Continued)
23
MB90092
(Continued)
(Ta = –40°C to +85°C, VSS = AVSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Conditions
Unit
Remarks
Min.
Typ.
Max.
Yellow
High level
CYELH
1.92
2.03
2.14
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Yellow
Low level
CYELL
CCYAH
CCYAL
CGREH
CGREL
CMAGH
CMAGL
CREDH
CREDL
CBLUH
CBLUL
CBSTH
CBSTL
CPDSC
1.00
2.09
0.89
1.98
0.95
1.98
0.95
2.09
0.89
1.92
1.00
1.80
1.12
1.46
1.11
2.20
1.00
2.09
1.06
2.09
1.06
2.20
1.00
2.03
1.11
1.91
1.23
1.57
1.22
2.31
1.11
2.20
1.17
2.20
1.17
2.31
1.11
2.14
1.22
2.02
1.34
1.68
Cyan
High level
Cyan
Low level
Green
High level
Green
Low level
Magenta
High level
See
Magenta
Low level
Figure
“COUT
Output”
COUT
VCC = AVCC1 = AVCC2 = 5.0 V
Red
High level
Red
Low level
Blue
High level
Blue
Low level
Color burst
High level
Color burst
Low level
Pedestal
level
24
MB90092
• VOUT Output
VYELH
VCYAH
VGREH
VWHT0 − 3
VGRY6
VMAGH
VREDH
VGRY5
VBLUH
VGRY4
VGRY3
VGRY2
VYELL
VCYAL
VGRY1
VBLK0 − 3
VPDS
VBSTH
VPDS
VGREL
VMAGL
VBSTL
VREDL
VBLUL
VTIP
• YOUT Output
YWHT0 − 3
YGRY6
YGRY5
YGRY4
YGRY3
YGRY2
YGRY1
YBLK0 − 3
YPDS
YTIP
YPDS
• COUT Output
CCYAH
CMAGH
CGREH
CREDH
CYELH
CBLUH
CBSTH
CPDS
CBSTL
CYELL
CBLUL
CCYAL
CMAGL
CREDL
CGREL
25
MB90092
2. AC Characteristics
(Ta = –40°C to +85°C, VCC = 5.0 V±10%, VSS = 0 V)
Value
Sym-
bol
Parameter
Shift clock cycle time
Shift clock pulse width
Pin
Unit
Remarks
Min. Max.
tCYC SCLK
1000
450
450
—
—
—
—
ns
ns
ns
tWCH
SCLK
tWCL
tCR
200 ns
200 ns
Shift clock signal rise/fall time
SCLK
tCF
—
See Figure “Serial Input
Timings”.
Shift clock start time
Data setup time
tSS SCLK
tSU SIN
200
200
100
500
—
—
—
—
—
ns
ns
ns
ns
Data hold time
tH
SIN
Chip select end time
tEC CS
tCRC
CS
tCFC
200 ns
200 ns
200 ns
200 ns
200 ns
200 ns
Chip select signal rise/fall time
—
Horizontal sync signal rise time
Horizontal sync signal fall time
Vertical sync signal rise time
tHR EXHSYN
tHF EXHSYN
tVR EXVSYN
tVF EXVSYN
tWH EXHSYN
tWV EXVSYN
—
—
See Figure
“Vertical and Horizontal Sync
Signal Input Timings”.
—
Vertical sync signal fall time
—
Horizontal sync signal pulse width*1
Vertical sync signal pulse width *1
4.0 8.0 µs
1
5
H
Horizontal sync detection pulse width *2 tWCSH EXHSYN
4.0 8.0 µs
See Figure “Composite Sync
Signal input Timings”.
28 µs
Vertical sync detection pulse width*2
tWCSV EXHSYN
13
TESTI
tWR
See Figure “Reset Signal In-
put Timing”.
Reset input pulse width
10
—
µs
(TEST = Low)*3
ROM read cycle *4
Address valid delay
READ active delay
Read data setup time
Read data hold time
Address invalid delay
READ inactive delay
trcyc
tab ADR0 to ADR20
READ
—
250 500 ns
—
—
30
30
0
60 ns
38 ns
tra
See Figure “Address Data
Hold Timings”.
tds DA0 to DA7
tdh DA0 to DA7
—
—
—
—
ns
ns
ns
ns
tai
ADR0 to ADR20
READ
tri
0
Tristate address delay
Tristate READ delay
ttad ADR0 to ADR20
ttrd READ
—
—
100 ns
100 ns
See Figure “Address and
READ Signal Delays at TSC
Signal Input”
*1: The values assume H/V-separated sync signal input.
*2: The values assume composite sync signal input.
*3: When the TEST pin is a Low-level input, the TESTI pin serves as a reset pin input. (The TESTI and TEST pins
can be Low level at the same time.)
*4: Depends on the dot clock oscillation frequency. (trcyc = 4/fDC)
26
MB90092
• Serial Input Timings
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
CS
tCRC
tSS
tCYC
tEC
tCFC
0.8 VCC
0.2 VCC
SCLK
tWCH
tWCL
tCR
tCF
tH
tSU
0.8 VCC
0.2 VCC
SIN
• Vertical and Horizontal Sync Signal Input Timings
0.8 VCC
0.2 VCC
0.8 VCC
EXHSYN
0.2 VCC
tHR
tHF
tWH
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
EXVSYN
tVF
tWV
tVR
27
MB90092
• Composite Sync Signal Input Timings
0.8 V CC
0.8 V CC
0.2 V CC
EXHSYN
0.2 V CC
tWCSH
tHR
tHF
0.8 V CC
0.2 V CC
0.8 V CC
0.2 V CC
EXHSYN
tWCSV
H
H
EXHSYN
tWCSV
Vertical sync signal interval
(3H)
• Reset Signal Input Timing
TESTI
0.2 VCC
tWR
0.2 VCC
28
MB90092
• Address Data Hold Timings
t
rcyc
4
1
2
3
4
1
2
3
4
1
0.8 VCC
0.2 VCC
EXD
ADR0
to
ADR20
0.8 VCC
0.2 VCC
Main screen data address *
Sub-screen data address *
t
ab
t
ai
0.8 VCC
0.2 VCC
READ
t
ra
t
ri
DA0
to
DA7
0.8 VCC
0.2 VCC
Main screen data *
Sub-screen data *
t
ds
t
dh
*: The main screen and sub-screen have the same address data timings.
• Address and READ Signal Delays at TSC Signal Input
0.8 VCC
0.2 VCC
ADR0 to ADR20
READ
0.8 VCC
0.2 VCC
TSC
0.2 VCC
ttrd
ttad
29
MB90092
3. Clock Timing Specifications
Value
Typ.
Parameter
Symbol
fDC
Pin
Unit
Remarks
Min.
8
Max.
16
Display dot clock*
EXD, XD
EXS, XS
—
MHz
MHz
MHz
Color burst clock (NTSC)*
Color burst clock (PAL)*
—
14.318185
17.734475
—
4 fSC
—
—
* : Input the signal with a duty cycle of 50%.
4. Power-on Reset Specifications
(Ta = –40°C to +85°C)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min.
Max.
Conditions which activate
the power-on reset circuit
(See Figure “Power ON/
OFF Timing”).
Power-supply rise time
tr
0.05
50
ms
VCC
Conditions in which the cir-
cuit repeatedly operate
normally (See Figure
Power-supply off time
toff
1
—
ms
“Power ON/OFF Timing”).
Time after power-supply rise
Reset cancel pulse width
tWIT
tWRH
tWRL
450
450
450
—
—
—
ns
ns
Power-on reset cancel tim-
ing (See Figure “Power-on
Reset Cancel Timing”).
CS
30
MB90092
• Power ON/OFF Timing
4.5 V
0.2 V
VCC
0.2 V
0.2 V
tr
toff
Note: The power supply must be activated smoothly.
• Power-on Reset Cancel Timing
4.5 V
VCC
Internal reset
CS
tWIT
0.8 V CC
0.2 V CC
CS
tWRL
tWRH
tCRC*
tCFC*
*: See Section 2, “AC Characteristics”.
31
MB90092
5. Recommended Input Timings
(1) Composite sync signal input timing
Parameter
NTSC
PAL
625
Unit Remarks
Lines
Number of frame scan lines
Field frequency
525
60 (59.94)
50
Hz *1
Line frequency
15750 (15734.264)
15625
25
Hz *1
Vertical retrace blanking interval
First equalizing pulse interval
Vertical sync pulse interval
Second equalizing pulse interval
Equalizing pulse width
Equalizing pulse cycle
Cut-in pulse width
19 to 21
H
H
*2
*2
*2
*2
3
2.5
3
2.5
H
3
2.29 to 2.54
0.5
2.5
H
2.34 to 2.36
0.5
µs
H
*2
*2
3.81 to 5.34
0.5
4.5 to 4.9
0.5
µs
H
Cut-in pulse cycle
Horizontal sync signal cycle
63.492 (63.5555)
64
µs
Horizontal sync signal pulse width
4.19 to 5.71 (4.7±0.1)
4.5 to 4.9
11.7 to 12.3
µs *1
µs *1
Horizontal retrace blanking interval 10.2 to 11.4 (10.5 to 11.4)
*1: Parenthesized values are specifications for color information display.
*2: 1 H is assumed to be one horizontal sync signal period.
(2) H/V-separated sync signal input timing
Parameter
NTSC
60 (59.94)
PAL
50
Unit Remarks
Vertical sync signal frequency
Vertical sync signal pulse width
Horizontal sync signal cycle
Horizontal sync signal pulse width
Hz *1
1 to 5
1 to 4
64
H
*2
63.492 (63.5555)
4.19 to 5.71 (4.7±0.1)
µs *1
µs *1
4.5 to 4.9
*1: Parenthesized values are specifications for color information display.
*2: 1 H is assumed to be one horizontal sync signal period.
32
MB90092
6. Output Timings
(1) Horizontal timing
Symbol
NTSC
0
PAL
0
Remarks
HPS
EQP1E
HPE
34
42
68
84
BSTS
76
100
140
186
484
568
610
1050
1106
BSTE
112
143
388
455
489
842
888
HBLKE
SEP1S
EQP2S
EQP2E
SEP2S
HBLKS
See Figure “NTSC/PAL Horizontal Timings”.
1135
(1137)*
IHCLR
910
*: Parenthesized values assume the last raster in each V cycle (field).
Note: The values in the above list are 4fSC count values.
(2) Vertical timing
NTSC
PAL
Symbol
Remarks
Interlaced
Noninterlaced
Interlaced
Noninterlaced
VPS
VPE
0
6
0
6
0
5
0
5
See Figures
“NTSC Vertical
Timings” and
“PAL Vertical
Timings”.
EQPE
VBLKE
VBLKS
VPS
12
36
519
525
12
36
519
526
10
45
620
625
10
45
620
624
Note: The values in the above list are 1/2H count values.
33
MB90092
• NTSC/PAL Horizontal Timings
Video signal
Horizontal sync signal
Horizontal retrace
blanking interval
Burst flag
Equalizing pulse
Cut-in pulse
EQP2E
EQP2S
SEP1S
IHCLR
HBLKS
SEP2S
HBLKE
BSTE
BSTS
HPE
EQP1E
HPS
HBLKS
34
MB90092
• NTSC Vertical Timings
35
MB90092
• PAL Vertical Timings
36
MB90092
■ SAMPLE CIRCUIT
This is a standard example of the circuit to synthesize the character to input video signal or input internal
generation video signal from the outside. Note that composition is different according to the system and parts
used.
MB90092
Composite
IN
Composite OUT
Buffer circuit
Video amplifer &
clamp circuit
VIN
VOUT
Y/C IN
Y/C OUT
YIN
CIN
YOUT
COUT
Video amplifer &
clamp circuit
Buffer circuit
Sync separation
circuit
EXHSYN
D0
D7
D0
D7
CS
Control
microcontroller
ADR0
A0
SCLK
SIN
ADR20
A20
+5 V
READ
OE
CE
AVCC1
AVCC2
(16M − ROM)
+
AVSS
VCC
+5 V
+
EXS
XS
VSS
XD
EXD
3.3 µH
20 pF
20 pF
(Approx. 14 MHz)
NTSC : 14.31818 MHz
PAL : 17.734475 MHz
37
MB90092
■ ORDERING INFORMATION
Part number
Package
Remarks
80-pin, plastic QFP
(QFP-80P-M06)
MB90092PF
38
MB90092
■ PACKAGE DIMENSION
80-pin plastic QFP
(FPT-80P-M06)
Note : Pins width and pins thickness include plating thickness.
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
64
41
65
40
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
80
25
0.25(.010)
3.05 –+00..2300
.120 –+..000182
(Mounting height)
1
24
0~8°
0.80(.031)
0.37±0.05
(.015±.002)
0.17±0.06
(.007±.002)
M
0.20(.008)
0.30 +–00..2150
0.80±0.20
(.031±.008)
"A"
.012 +–..001004
0.88±0.15
(Stand off)
(.035±.006)
C
Dimensions in mm (inches).
2001 FUJITSU LIMITED F80010S-c-4-4
39
MB90092
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0108
FUJITSU LIMITED Printed in Japan
相关型号：
MB90099LGA
CRT Character/Graphics Display Controller, 28 X 12 Characters, CMOS, PBGA20, PLASTIC, FLGA-20
FUJITSU
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