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MB90097-PFV [FUJITSU]

ON-Screen Display Controller; 屏幕显示控制器
MB90097-PFV
型号： MB90097-PFV
厂家： FUJITSU    FUJITSU
描述：

ON-Screen Display Controller
屏幕显示控制器

显示控制器
文件： 总63页 (文件大小：904K)
中文：  中文翻译
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FUJITSU SEMICONDUCTOR  
DATA SHEET  
DS04-28825-4E  
ASSP For Screen Display Control  
CMOS  
ON-Screen Display Controller  
MB90097  
■ DESCRIPTION  
The MB90097 is the on-screen display controller for displaying text and graphics on the TV screen. Since it has  
a three-channel output control function, small package, and low voltage requirement for operation, it is suitable  
for on-screen display on video equipment such as camera-integrated VTRs.  
The MB90097 provides a display screen made up of 28 characters by 12 lines, capable of displaying 512 different  
characters each consisting of 12 × 18 dots. The display functions of the MB90097 includes a wealth of character  
qualifying functions such as character background shading (shadow casting) and individual character size setting,  
supporting 16-color display for each character. They also include the line background, screen background, and  
sprite character display functions, enabling the screen to be displayed in a variety of configurations. The integrated  
font ROM contains 512 different character patterns all of which can be set by the user.  
■ FEATURES  
• Character screen configuration: 28 characters × 12 lines (maximum)  
• Character types: 512 different characters (integrated in ROM, user-definable through the entire area)  
(Continued)  
■ PACKAGE  
20-pin Plastic SSOP  
(FPT-20P-M03)  
MB90097  
(Continued)  
• Font configuration: 12 × 18 dots (font ROM configuration)  
Capable of specifying the horizontal and vertical sizes of characters to be displayed.  
• One of the following three horizontal sizes (S, M, L) can be set for each character:  
S size : 6 dots  
M size : 9 dots  
L size : 12 dots  
• Either of the following two vertical sizes (HA, HB) can be set for each line.  
HA : 18 dots  
HB : 12 dots  
• Display modes: Character trimming Enabled/Disabled (Set for each line)  
Character background None/Solid-fill/Shaded background (concaved)/Shaded  
background (convexed) (Set for each line)  
Horizontal character merge/independent display with  
shaded background (Set for each character)  
Vertical line merge/independent display with shaded  
background (Set for each line)  
Character background extended display ON/OFF for line  
spacings (Set for each line)  
Line background None/Solid-fill/Shaded background (concaved)/Shaded  
background (convexed) (Set for each line)  
(Display extended to the left and right margins of the screen  
and to the line spacing)  
Character enlargement: Four types supported: Normal, Double width, Double height,  
Double width × double height  
(Set for each line)  
Enlarged display dot interpolation function (Set for each line)  
• Character screen display position control:  
Horizontal display position Controlin2-dotunits(movablethroughtheentirescreen)  
Vertical display position  
Line spacing control  
Controlin2-dotunits(movablethroughtheentirescreen)  
Control in 1-dot units (Set between 0 to 7 dots for each  
line; Displayed simultaneously at two areas above and  
below the line.)  
• Sprite character control:  
Sprite character display  
OFF/ON  
Sprite character types  
Sprite character trimming  
Sprite character configuration  
256 types (character codes: 000H to 0FFH)  
Enabled/Disabled  
Two types: 1 character/Stack of 2 characters  
Sprite character horizontal display position Control in 1-dot units (movable through the entire screen)  
Sprite character vertical display position  
Control in 1-dot units (movable through the entire screen)  
(Continued)  
2
MB90097  
(Continued)  
• Screen background control: Screen background color OFF/ON  
Display colors  
Character color:  
16 colors (Set for each character)  
Character trimming color:  
Character background color:  
Line background color:  
Screen background color:  
Sprite character color:  
16 colors (Set for each line)  
16 colors (Set for each character) *  
16 colors (Set for each line)  
16 colors  
16 colors  
Sprite character trimming color:  
16 colors  
Shaded background frame highlight color: 16 colors  
Shaded background frame shadow color: 16 colors  
*: Transparent (Displaying the lower-layer color) when the character  
background color (color code) = “0”  
• Display signal output: Color signal output: 4 bits (Supporting 16 colors)  
Display period signals: 3 channels (Output selector circuit provided)  
• External interface: 16-bit serial inputs  
• Chip select  
• Serial clock  
• Serial data  
• Package : SSOP-20  
• Supply voltage: 3.3 V  
3
MB90097  
■ PIN ASSIGNMENT  
(Top view)  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
HSYNC  
VSYNC  
VC0  
SCLK  
CS  
SIN  
3
4
VC1  
RESET  
VDD  
VC2  
5
6
BLKA  
VC3  
SDR  
XD  
7
8
EXD  
TEST  
GND  
BLKB  
TESTO  
BLKC  
9
10  
11  
(FPT-20P-M03)  
4
MB90097  
■ PIN DESCRIPTIONS  
Pin no.  
Pin name  
I/O  
Function  
Shift clock input pin for serial transfer  
1
SCLK  
I
This pin has an internal pull-up resistor.  
2
CS  
I
Chip select pin  
This pin inputs a Low level signal for serial transfer.  
The pin has an internal pull-up resistor.  
3
4
SIN  
I
I
Serial data input pin  
This pin has an internal pull-up resistor.  
RESET  
Reset input pin  
This pin inputs a Low level signal when turning the power on.  
5
6
VDD  
—
I
+ 3 V power supply pin  
SDR  
Data input direction select pin for serial transfer  
This pin inputs the Low level signal in the LSB-first transfer mode for data  
input; it inputs the High level signal in the MSB-first transfer mode.  
7
8
XD  
EXD  
O
I
External circuit pins for display dot clock generator  
Connect these pins to external “L” and “C” to form an LC oscillator circuit.  
For external input of a display dot clock, input the clock signal to the EXD  
pin and leave the XD pin open.  
9
TEST  
I
LSI test input pin  
Input the Low level signal during normal use.  
10  
20  
19  
GND  
—
Ground pin  
HSYNC  
VSYNC  
I
I
Horizontal sync signal input pin  
Vertical sync signal input pin  
18  
17  
16  
14  
VC0  
VC1  
VC2  
VC3  
O
O
O
O
Color code signal output pin  
15  
13  
11  
12  
BLKA  
BLKB  
O
O
O
O
Display period signal output pin for output channel A  
Display period signal output pin for output channel B  
Display period signal output pin for output channel C  
BLKC  
TESTO  
LSI test output pin  
Leave this pin open (unconnected) during normal use.  
5
MB90097  
■ ABSOLUTE MAXIMUM RATINGS  
(VGND = 0 V)  
Rating  
Parameter  
Symbol  
VDD  
Unit  
Remarks  
Min.  
VGND – 0.3  
VGND – 0.3  
VGND – 0.3  
—
Max.  
VGND + 4.5  
VDD + 0.3  
VDD + 0.3  
100  
Power supply voltage  
Input voltage  
V
V
VIN  
Output voltage  
VOUT  
Pd  
V
Power consumption  
Operating temperature  
Storage temperature  
mW  
°C  
°C  
Ta  
– 40  
+ 85  
Tstg  
– 55  
+ 150  
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,  
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.  
■ RECOMMENDED OPERATING CONDITIONS  
(VGND = 0 V)  
Value  
Parameter  
Symbol  
Unit  
Remarks  
Min.  
3.0  
Max.  
3.6  
Power supply voltage  
“H” level input voltage  
“L” level input voltage  
Operating temperature  
VDD  
VIHS  
VILS  
Ta  
V
V
0.8 × VDD  
VGND  
VDD + 0.3  
0.2 × VDD  
+ 85  
V
– 40  
°C  
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the  
semiconductor device. All of the device's electrical characteristics are warranted when the device is  
operated within these ranges.  
Always use semiconductor devices within their recommended operating condition ranges. Operation  
outside these ranges may adversely affect reliability and could result in device failure.  
No warranty is made with respect to uses, operating conditions, or combinations not represented on  
the data sheet. Users considering application outside the listed conditions are advised to contact their  
FUJITSU representatives beforehand.  
6
MB90097  
■ ELECTRICAL CHARACTERISTICS  
1. DC Characteristics  
(VGND = 0 V, Ta = – 40°C to + 85°C)  
Value  
Unit  
Parameter  
Symbol Pin name  
Conditions  
Min.  
Typ.  
Max.  
VC3  
VC2  
VC1  
VDD = 3.0 V  
IOH = – 4.0 mA  
“H” level output voltage 1  
VDD – 0.5  
—
—
V
V
VOH1  
VC0  
BLKC  
BLKB  
BLKA  
VDD = 3.0 V  
IOL = 4.0 mA  
“L” level output voltage 1  
VOL1  
—
—
0.4  
VDD = 3.0 V  
IOH = – 0.5 mA  
“H” level output voltage 2  
“L” level output voltage 2  
VOH2  
VOL2  
VDD – 0.5  
—
—
—
—
V
V
XD  
VDD = 3.0 V  
IOL = 0.5 mA  
0.4  
SDR  
VDD = 3.3 V  
VIH = VDD  
IIH  
“H” level input current  
“L” level input current  
PULL-UP resistance  
—
—
20  
—
—
—
– 10  
10  
µA  
µA  
kΩ  
HSYNC  
VSYNC  
EXD  
TEST  
RESET  
VDD = 3.3 V  
VIL = 0 V  
IIL  
SIN  
SCLK  
CS  
RPULL  
VDD = 3.3 V  
110  
VDD = 3.0 V  
fDC = 8 MHZ  
—
—
—
4
5
6
7
mA  
mA  
pF  
Power supply current  
Input capacitance  
ICC  
VDD  
VDD = 3.6 V  
fDC = 8 MHZ  
except VDD,  
GND  
C
10  
—
7
MB90097  
2. AC Characteristics  
(1) Serial input timings  
(VDD = 3.0 V to 3.6 V, VGND = 0 V, Ta = – 40°C to + 85°C)  
Value  
Parameter  
Shift clock cycle time  
Shift clock pulse width  
Symbol  
tCYC  
Pin name  
SCLK  
Unit  
Min.  
250  
100  
100  
—
Max.  
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tWCH  
tWCL  
tCR  
—
SCLK  
SCLK  
—
200  
200  
—
Shift clock signal rise/fall time  
tCF  
—
Shift clock start time  
Data setup time  
tSS  
SCLK  
SIN  
SIN  
CS  
100  
100  
50  
tSU  
—
Data hold time  
tH  
—
Chip select end time  
tEC  
100  
—
—
tCRC  
tCFC  
200  
200  
Chip select signal rise/fall time  
CS  
—
0.8 VDD  
0.2 VDD  
0.8 VDD  
0.2 VDD  
CS  
tCRC  
tCFC  
tSS  
tCYC  
tEC  
0.8 VDD  
0.2 VDD  
SCLK  
tCR  
tWCL  
tCR  
tWCH  
tH  
tCF  
tSU  
0.8 VDD  
0.2 VDD  
SIN  
8
MB90097  
(2) Vertical and horizontal sync signal input timings  
(VDD = 3.0 V to 3.6 V, VGND = 0 V, Ta = – 40°C to + 85°C)  
Value  
Parameter  
Symbol  
tHR  
Pin name  
HSYNC  
VSYNC  
Unit  
Min.  
—
—
—
—
18  
—
4
Max.  
200  
200  
200  
200  
—
Horizontal sync signal rise time  
Horizontal sync signal fall time  
Vertical sync signal rise time  
Vertical sync signal fall time  
ns  
tHF  
tVR  
tVF  
ns  
ns  
ns  
Dot clock  
µs  
Horizontal sync signal pulse width*1  
tWH  
HSYNC  
6
Vertical sync signal detection setup time*2  
Vertical sync signal detection hold time  
tVS  
VSYNC  
VSYNC  
1H – 4  
20  
Dot clock  
H
tVH  
2
*1: During the horizontal sync signal pulse period, the MB90097 stops its internal operation, disabling writing to  
the internal VRAM. Therefore, set the horizontal sync signal pulse width and VRAM write cycle (command 2 or  
command 4 issuance cycle) to ensure that: horizontal sync signal pulse width < VRAM write cycle.  
*2: Do not change the vertical sync signal (detection edge) in the vicinity of the horizontal sync signal edge of  
vertical sync signal detection. Otherwise, it results in a deflection in the display when the sync signal fluctuates.  
(1) VSYNC: Leading-edge operation  
HSYNC: VSYNC detection at the trailing edge  
tVF  
tVR  
tVS  
tVH  
VSYNC  
HSYNC  
0.8 VDD  
0.8 VDD  
0.2 VDD  
0.2 VDD  
tHF  
tHR  
tWH  
0.8 VDD  
0.8 VDD  
0.2 VDD  
0.2 VDD  
Note: The above diagrams assume that sync signal input control (SIX bit) of I/O pin control (command 13-0) has  
been set to negative logic (0). The H and L levels are inverted if it has been set to positive logic.  
(Continued)  
9
MB90097  
(Continued)  
(2) VSYNC: Trailing-edge operation  
HSYNC: VSYNC detection at the trailing edge  
tVR  
tVS  
tVF  
tVH  
0.8 VDD  
0.8 VDD  
VSYNC  
HSYNC  
0.2 VDD  
0.2 VDD  
tHF  
tHR  
tWH  
0.8 VDD  
0.8 VDD  
0.2 VDD  
0.2 VDD  
(3) VSYNC: Leading-edge operation  
HSYNC: VSYNC detection at the leading edge  
tVF  
tVS  
tVR  
tVH  
0.8 VDD  
0.8 VDD  
VSYNC  
HSYNC  
0.2 VDD  
0.2 VDD  
tHF  
tHR  
tWH  
0.8 VDD  
0.8 VDD  
0.2 VDD  
0.2 VDD  
(4) VSYNC: Trailing-edge operation  
HSYNC: VSYNC detection at the leading edge  
tVR  
tVS  
tVF  
tVH  
0.8 VDD  
0.8 VDD  
VSYNC  
HSYNC  
0.2 VDD  
0.2 VDD  
tHF  
tHR  
tWH  
0.8 VDD  
0.8 V DD  
0.2 VDD  
0.2 VDD  
10  
MB90097  
(3) Dot clock input timing  
(VDD = 3.0 V to 3.6 V, VGND = 0 V, Ta = – 40°C to + 85°C)  
Value  
Parameter  
Symbol  
tDCYC1  
Pin name  
Unit  
Remarks  
*1  
Min.  
112  
56  
48  
48  
24  
24  
13  
0
Max.  
166  
83  
—
EXD  
EXD  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Dot clock cycle time  
tDCYC2  
tDWH1  
tDWL1  
tDWH2  
tDWL2  
tDS  
*2  
EXD  
EXD  
*1  
—
Dot clock pulse time  
—
*2  
—
HSYNC, VSYNC setup time  
HSYNC, VSYNC hold time  
—
*3  
*3  
HSYNC  
VSYNC  
tDH  
—
VC3,  
VC2,  
VC1,  
VC0,  
BLKA,  
BLKB,  
BLKC  
Data output delay time 1  
Data output delay time 2  
7
tDD2  
45  
ns  
ns  
tDD1  
*3  
tDD2  
tDD1  
*1: Assumes a dot clock LC oscillator circuit or external dot clock input.  
*2: Assumes frequency-doubled external dot clock input.  
*3: Assumes dot clock external input.  
tDCYC1, 2  
tDWL1, 2  
tDWH1, 2  
0.8 VDD  
0.2 VDD  
EXD input  
tDH  
tDS  
0.8 VDD  
0.2 VDD  
HSYNC  
VSYNC  
Inputs  
tDD2  
tDD1  
0.8 VDD  
Valid data  
0.2 VDD  
Previous  
data  
Data output  
Undefined period  
AC measurement conditions  
C = 70 pF  
tr = 5 ns  
tf = 5 ns  
VOH = 0.8 VDD  
VOL = 0.2 VDD  
VIH = 0.8 VDD  
VIL = 0.2 VDD  
Note: Applicable only when the MB90097 is operating with external dot clock input (not applicable with the LC oscillator circuit).  
11  
MB90097  
(4) Reset input timing  
Parameter  
(VDD = 3.0 V to 3.6 V, VGND = 0 V, Ta = – 40°C to + 85°C)  
Value  
Symbol  
Pin name  
Unit  
Remarks  
Min.  
Max.  
—
Reset pulse width  
Clock input time  
tWRST  
tWRSD  
RESET  
EXD  
1
5
µs  
—
Dot clock  
Note  
Note: To feed the EXD pin with the dot clock, it is necessary to input the clock during RESEST. Configuring LC  
oscillator circuit using the external L and C will eliminate this need because it will automatically oscillate.  
t WRST  
t WRSD  
0.2 V DD  
RESET  
EXD  
12  
MB90097  
■ COMMAND LIST  
1. Display Control Commands  
Command code/data  
Command  
Function  
no.  
15 to 12  
11  
10  
9
8
7
6
0
5
0
4
3
2
1
0
VRAM write  
address setting  
0
0000  
0001  
0010  
0011  
0100  
0101  
0101  
0101  
0101  
0101  
AY3 AY2 AY1 AY0  
FL  
AX4 AX3 AX2 AX1 AX0  
Character data  
setting 1  
1
MS1 MS0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0  
MR MO1 MO0 M8 M7 M6 M5 M4 M3 M2 M1 M0  
LHS LW2 LW1 LW0 LFD LFC LFB LFA LF3 LF2 LF1 LF0  
Character data  
setting 2  
2
Line control data  
setting 1  
3
Line control data  
setting 2  
4
LDS LGS LG1 LG0  
LD  
LE  
LM1 LM0  
L3  
0
L2  
L1  
L0  
Screen output  
control 1A  
5-00  
5-01  
5-02  
5-2  
5-3  
0
0
0
1
1
0
0
0
0
1
0
0
1
0
0
0
1
SDS UDS  
0
DSP  
0
OA2 OA1 OA0  
OB2 OB1 OB0  
OC2 OC1 OC0  
Screen output  
control 1B  
SOB BGB BLB  
SOC BGC BLC  
0
Screen output  
control 1C  
0
0
0
Vertical display  
position control  
Y8  
X8  
Y7  
X7  
Y6  
X6  
Y5  
X5  
Y4  
X4  
Y3  
X3  
Y2  
X2  
Y1  
X1  
Y0  
X0  
Horizontal display  
position control  
Shaded  
background frame  
color control  
6-1  
7-3  
0110  
0111  
0
1
1
1
0
0
0
0
BH3 BH2 BH1 BH0 BS3 BS2 BS1 BS0  
Screen  
background  
control  
0
0
0
0
U3  
U2  
U1  
U0  
Sprite character  
control 1  
8-0  
8-1  
9-0  
9-1  
11-0  
1000  
1000  
1001  
1001  
1011  
0
0
0
1
0
0
1
0
0
0
SFB SFA SF3 SF2 SF1 SF0 SC3 SC2 SC1 SC0  
SD1 SD0 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0  
SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0  
SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0  
Sprite character  
control 2  
Sprite character  
control 4  
Sprite character  
control 5  
Screen extension  
control  
0
0
0
0
0
0
EG0  
0
0
0
0
0
0
11-2  
13-0  
Dot clock control 1  
I/O pin control  
1011  
1101  
1
0
0
0
0
0
0
0
0
0
0
DC2 DC1 DC0  
DBX DCX  
VVE VHE HE  
SIX  
0
Horizontal  
blanking control 1  
13-1  
13-2  
1101  
1101  
0
1
1
0
0
0
0
0
0
BB5 BB4 BB3 BB2 BB1 BB0  
Horizontal  
blanking control 2  
BF8 BF7 BF6 BF5 BF4 BF3 BF2 BF1 BF0  
13  
MB90097  
2. Command Description  
• Command 0 (VRAM write address setting)  
Command 0 sets the write address in VRAM and controls execution of “VRAM fill.”  
The sets the write address by specifying the row and column addresses.  
VRAM fill is activated by executing command 2 (character data setting 2).  
15  
0
14  
0
13  
0
12  
0
11  
10  
9
8
7
6
0
5
0
4
3
2
1
0
AY3  
AY2  
AY1  
AY0  
FL  
AX4  
AX3  
AX2  
AX1  
AX0  
AY3 to AY0: Row address  
(0 to BH)  
AX4 to AX0: Column address  
(0 to 1BH)  
FL: VRAM fill control  
(0: OFF, 1: ON)  
• Command 1 (Character data setting 1)  
Command 1 sets character data.  
Executing command 2 (character data setting 2) sets VRAM to reflect it on the screen.  
15  
0
14  
0
13  
0
12  
1
11  
10  
9
8
7
6
5
4
3
2
1
0
MS1  
MS0 MM1 MM0  
MB3 MB2  
MB1 MB0  
MC3 MC2 MC1  
MC0  
MS1, MS0: Character horizontal size control  
(0, 0: S size, 6 dots)  
MC3 to MC0: Character color  
(From among 16 colors)  
MB3 to MB0: Character background color  
(From among 16 colors)  
(0, 1: M size, 9 dots)  
(1, 0: L size, 12 dots)  
(1, 1: Setting prohibited)  
MM1, MM0: Character background control  
(0, 0: OFF)  
(0, 1: Solid-fill display)  
(1, 0: Concaved, shaded background)  
(1, 1: Convexed, shaded background)  
• Command 2 (Character data setting 2)  
Command 2 writes additional character data to the location in VRAM specified by command 0 (VRAM write  
address setting 1), along with the character data set by command 1 (character data setting 1).  
The VRAM write address is incremented automatically after execution of command 2.  
15  
0
14  
0
13  
1
12  
0
11  
10  
9
8
7
6
5
4
3
2
1
0
MR  
MO1 MO0  
M8  
M7  
M6  
M5  
M4  
M3  
M2  
M1  
M0  
MR: Shaded background succeeding character merge control  
(0: Disables succeeding character merge display.)  
(1: Enables succeeding character merge display.)  
M8 to M0: Character code  
MO1, MO0: Character output control  
14  
MB90097  
• Command 3 (Line control data setting 1)  
Command 3 sets line control data.  
Executing command 4 (line control data setting 2) sets VRAM to reflect it on the screen.  
15  
0
14  
0
13  
1
12  
1
11  
10  
9
8
7
6
5
4
3
2
1
0
LHS  
LW2 LW1  
LW0  
LFD  
LFC  
LFB LFA  
LF3  
LF2  
LF1  
LF0  
LHS: Line character vertical size type control  
(0: Character vertical size A)  
(1: Character vertical size B)  
LW2 to LW0: Line spacing control  
(0 to 7 dots in 1-dot units)  
LFD, LFC: Trimming output control  
(0, 0: All OFF)  
(0, 1: Trimming ON for character with no character background)  
(1, 0: Trimming ON for solid-filled character with no character background)  
(1, 1: All ON)  
LF3 to LF0: Trimming color  
LFB, LFA: Trimming control  
(From among 16 colors)  
(0, 0: Trimming OFF)  
(0, 1: Reserved (Setting prohibited))  
(1, 0: Reserved (Setting prohibited))  
(1, 1: Eight-direction trimming)  
• Command 4 (Line control data setting 2)  
Command 4 writes additional line control data to the row address in line RAM specified by command 0  
(VRAM write address setting), along with the line control data set by command 3 (line control data setting1).  
Executing this command will not alter the VRAM write address.  
15  
0
14  
1
13  
0
12  
0
11  
10  
9
8
7
6
5
4
3
2
1
0
LDS  
LGS  
LG1  
LG0  
LD  
LE  
LM1 LM0  
L3  
L2  
L1  
L0  
LDS: Line character output control  
LE: Character background extension control  
(0: Normal, 1: Extended)  
LD: Shaded background succeeding line merge control  
(0: Independent, 1: Merge with the next line)  
LM1, LM0: Line background control  
(0, 0: OFF)  
(Control of character + trimming + character background)  
(0: OFF, 1: ON)  
LGS: Line enlargement interpolation control  
(0: OFF, 1: ON)  
LG1, LG0: Line enlargement control  
(0, 0: Normal)  
(0, 1: Solid-fill display)  
(0, 1: Double width)  
(1, 0: Double height)  
(1, 1: Double width × double height)  
(1, 0: Concaved, shaded display)  
(1, 1: Convexed, shaded display)  
L3 to L0: Line background color  
(From among 16 colors)  
• Command 5-00 (Screen output control 1A)  
Command 5-00 controls screen display output.  
15  
0
14  
1
13  
0
12  
1
11  
0
10  
0
9
0
8
0
7
6
5
0
4
3
0
2
1
0
SDS UDS  
DSP  
OA2 OA1  
OA0  
SDS: Sprite character output control  
(0: OFF, 1: ON)*  
OA2 to OA0: Output-A character control  
(From among eight types)  
UDS: Screen background output control  
(0: OFF, 1: ON)*  
DSP: Display output control  
(Control of character + trimming + character background +  
line background)  
(0: OFF, 1: ON)*  
*: The low level input to the RESET pin initializes the SDS, UDS, and DSP bits to 0.  
15  
MB90097  
• Command 5-01 (Screen output control 1B)  
Command 5-01 controls output-B screen display output.  
15  
0
14  
1
13  
0
12  
1
11  
0
10  
0
9
0
8
1
7
6
5
4
0
3
0
2
1
0
SOB BGB  
BLB  
OB2 OB1  
OB0  
SOB: Output-B sprite character output control  
(0: OFF, 1: ON)  
OB2 to OB0: Output-B character control  
(From among eight types)  
BGB: Output-B screen background output control  
(0: OFF, 1: ON)  
BLB : Output-B line background output control  
(0: OFF, 1: ON)  
• Command 5-02 (Screen output control 1C)  
Command 5-02 controls output-C screen display output.  
15  
0
14  
1
13  
0
12  
1
11  
0
10  
0
9
1
8
0
7
6
5
4
0
3
0
2
1
0
SOC BGC  
BLC  
OC2 OC1  
OC0  
SOC: Output-C sprite character output control  
(0: OFF, 1: ON)  
OC2 to OC0: Output-C character control  
(From among eight types)  
BGC: Output-C screen background output control  
(0: OFF, 1: ON)  
BLC : Output-C line background output control  
(0: OFF, 1: ON)  
• Command 5-2 (Vertical display position control)  
This command controls the vertical display position of the screen.  
15  
0
14  
1
13  
0
12  
1
11  
1
10  
0
9
0
8
7
6
5
4
3
2
1
0
Y8  
Y7  
Y6  
Y5  
Y4  
Y3  
Y2  
Y1  
Y0  
Y8 to Y0: Vertical display position control  
(0 to 1022 in 2-dot units)  
• Command 5-3 (Horizontal display position control)  
This command controls the horizontal display position of the screen.  
15  
0
14  
1
13  
0
12  
1
11  
1
10  
1
9
0
8
7
6
5
4
3
2
1
0
X8  
X7  
X6  
X5  
X4  
X3  
X2  
X1  
X0  
X8 to X0: Horizontal display position control  
(0 to 1022 in 2-dot units)  
16  
MB90097  
• Command 6-1 (Shaded background frame color control)  
Command 6-1 controls the frame color of a shaded background.  
15  
0
14  
1
13  
1
12  
0
11  
0
10  
1
9
0
8
0
7
6
5
4
3
2
1
0
BH3 BH2  
BH1  
BH0  
BS3  
BS2  
BS1  
BS0  
BH3 to BH0: Shaded background frame highlight color  
(From among 16 colors)  
BS3 to BS0: Shaded background frame shadow color  
(From among 16 colors)  
• Command 7-3 (Screen background control)  
Command 7-3 controls the screen background color.  
15  
0
14  
1
13  
1
12  
1
11  
1
10  
1
9
0
8
0
7
0
6
0
5
0
4
0
3
2
1
0
U3  
U2  
U1  
U0  
U3 to U0: Screen background color  
(From among 16 colors)  
• Command 8-0 (Sprite character control 1)  
This command controls sprite characters.  
15  
1
14  
0
13  
0
12  
0
11  
0
10  
0
9
8
7
6
5
4
3
2
1
0
SFB  
SFA  
SF3  
SF2  
SF1  
SF0  
SC3  
SC2  
SC1  
SC0  
SFB, SFA: Sprite character trimming control  
(0, 0: Trimming OFF)  
SF3 to SF0 : Sprite character trimming color  
(From among 16 colors)  
(0, 1: Reserved)  
(1, 0: Reserved)  
SC3 to SC0: Sprite character color  
(From among 16 colors)  
(1, 1: Eight-direction trimming)  
• Command 8-1 (Sprite character control 2)  
Command 8-1 controls sprite characters.  
15  
1
14  
0
13  
0
12  
0
11  
0
10  
1
9
8
7
6
5
4
3
2
1
0
SD1  
SD0  
SM7 SM6  
SM5 SM4 SM3 SM2 SM1  
SM0  
SD1, SD0: Sprite character configuration control  
(0, 0: 1 character)  
SM7 to SM0: Sprite character code  
(000H to 0FFH for 256 different characters)  
(0, 1: Reserved (Setting prohibited))  
(1, 0: Stack of 2 characters)  
(1, 1: Reserved (Setting prohibited))  
17  
MB90097  
• Command 9-0 (Sprite character control 4)  
Command 9-0 controls sprite characters.  
15  
1
14  
0
13  
0
12  
1
11  
0
10  
0
9
8
7
6
5
4
3
2
1
0
SY9  
SY8  
SY7  
SY6  
SY5  
SY4  
SY3  
SY2  
SY1  
SY0  
SY9 to SY0: Sprite character vertical display position control  
(0 to 1023 in 1-dot units)  
• Command 9-1 (Sprite character control 5)  
This command controls sprite characters.  
15  
1
14  
0
13  
0
12  
1
11  
1
10  
0
9
8
7
6
5
4
3
2
1
0
SX9  
SX8  
SX7  
SX6  
SX5  
SX4  
SX3  
SX2  
SX1  
SX0  
SX9 to SX0: Sprite character horizontal display position control  
(0 to 1023 in 1-dot units)  
• Command 11-0 (Screen extension control)  
(Reserved)  
15  
1
14  
0
13  
1
12  
1
11  
0
10  
0
9
0
8
0
7
0
6
5
0
4
0
3
0
2
0
1
0
0
0
EG0  
EG0: (Reserved)  
(0: Normal)*  
(1: Reserved (Setting prohibited))  
*: Set the EG0 bit to “0”.  
• Command 11-2 (Dot clock control 1)  
Command 11-2 controls the dot clock.  
15  
1
14  
0
13  
1
12  
1
11  
1
10  
0
9
0
8
7
0
6
0
5
0
4
0
3
0
2
1
0
0
DC2 DC1  
DC0  
DC2 to DC0: Dot clock selection control  
(0, 0, 0: LC oscillation)  
(0, 1, 0: External dot clock input)  
(0, 1, 1: Frequency-doubled external dot clock input)  
18  
MB90097  
• Command 13-0 (I/O pin control)  
Command 13-0 controls input/output pins.  
15  
1
14  
1
13  
0
12  
1
11  
0
10  
0
9
8
7
6
0
5
4
0
3
0
2
0
1
0
VVE  
VHE  
HE  
SIX  
DBX  
DCX  
VVE: Edge selection for vertical synchronization detection  
(0: Leading edge, 1: Trailing edge)  
SIX : Logic control for sync signal input  
(0: Negative logic, 1: Positive logic)  
VHE: HSYNC edge selection for vertical synchronization detection  
(0: Leading edge, 1: Trailing edge)  
DCX: Logic control for display color signal output  
(0: Positive logic, 1: Negative logic)*  
HE: Edge selection for horizontal synchronization operation  
(0: Trailing edge, 1: Leading edge)  
DBX: Logic control for display output period signal output  
(0: Positive logic, 1: Negative logic)*  
*: The low level input to the RESET pin initializes the DCX and DBX bits to 0.  
• Command 13-1 (Horizontal blanking control 1)  
Command 13-1 controls horizontal blanking (back porch).  
15  
1
14  
1
13  
0
12  
1
11  
0
10  
1
9
0
8
0
7
0
6
0
5
4
3
2
1
0
BB5  
BB4  
BB3  
BB2  
BB1  
BB0  
BB5 to BB0: Back porch control  
(0 to 126 in 2-dot units)  
• Command 13-2 (Horizontal blanking control 2)  
Command 13-2 controls horizontal blanking (front porch).  
15  
1
14  
1
13  
0
12  
1
11  
1
10  
0
9
0
8
7
6
5
4
3
2
1
0
BF8  
BF7  
BF6  
BF5  
BF4  
BF3  
BF2  
BF1  
BF0  
BF8 to BF0: Front porch control  
(0 to 1022 in 2-dot units)  
19  
MB90097  
3. Notes on Issuing Commands  
This section summarizes notes on issuing commands.  
(1) Initialization  
The MB90097 enters the display-off state (*1) upon reset input (input of a LOW-level signal to the RESET pin).  
The contents of VRAM (character RAM and line RAM) are not initialized then (undefined immediately after the  
power supply is turned on).  
When the MB90097 is released from the reset input, issue the following commands to initialize control  
operation:  
• Dot clock control 1 (Command 11-2)  
• I/O pin control (Command 13-0)  
After that, set all of other command data and the contents of VRAM.  
(VRAM setting requires normal dot clock and sync signal inputs.)  
*1: The reset input initializes control bits to 0 as shown below  
Screen output control 1A (command 5-00)  
SDS = 0 Sprite OFF  
UDS = 0 Screen background OFF  
DSP = 0 Character, character background, line  
background OFF  
I/O pin control (command 13-0)  
DCX = 0 Sets the VC0, VC1, VC2, and VC3 pins to  
positive logic output.  
DBX = 0 Sets the BLKA, BLKB, and BLKC pins to positive  
logic output.  
(2) Command refresh  
Command data to the MB90097 and the contents of internal VRAM remain held as long as the MB90097 is  
powered. If the serial control, sync, and dot clock signals are affected by external noise, however, they may  
become abnormal signals, preventing the internal registers and VRAM from being set normally. You should  
therefore refresh all of command data and VRAM data periodically to restore them from the abnormal state.  
(3) Command issuance timing  
When a VRAM write command, such as a character data setting or line control data setting command, or any  
other control command is issued, the command is executed immediately, reflecting the result (command setting)  
on the screen. When such a command is issued during a display period, the display in the relevant field may  
involve transient distortion. To prevent this, you should issue the command during the vertical blanking interval.  
Also, a restriction on the internal circuit configuration may cause deviation of the display position in the first  
display field when the DSP, SDS, or UDS control bit of command 5-00 (screen output control 1A) is set from  
OFF to ON. To prevent this, you should issue command 5-00 within the 2H period after the leading edge of the  
V sync signal.  
20  
MB90097  
■ DISPLAY FUNCTIONS  
1. Screen Configuration  
1. 1 Screen Elements  
The display screen provided by the MB90097 consists of a pile of display screen elements.  
Display screen element name  
Sprite character (+ trimming)  
Character (+ trimming)  
Display configuration  
Display position control  
Horizontal/vertical: 1-dot units  
Horizontal/vertical: 2-dot units  
1 (Maximum of 2 × 2  
characters)  
Top layer  
28 characters × 12 lines  
28 characters × 12 lines  
(Controlled simultaneously with  
the character)  
Character background  
(Controlled simultaneously with  
the character)  
Line background  
12 lines  
Full screen display in single  
color  
Bottom layer  
Screen background  
(None)  
• Screen configuration drawing  
Input image  
Screen background (Screen background color)  
Line 0 Line background (Line background color)  
Line 1  
Character background  
Line 2  
Line 3  
Line 4  
Line 5  
Line 6  
Line 7  
Line 8  
Line 9  
Line 10  
Line 11  
(Character background color)  
Character + trimming  
← Sprite character + trimming  
Note: When a character is displayed on a line, the display of the shaded background shadow frame  
for the line background overrides the character display.  
The display of the shaded background shadow frame for the character background overrides  
the character display and the shaded background shadow frame for the line background.  
21  
MB90097  
1. 2 Screen Display Modes  
Displayscreen  
element name  
Display mode  
Undisplay  
Screen  
background  
Display  
Undisplay  
Solid-fill display  
Line  
background  
Line spacing (0 to 7  
dots)  
Shaded  
Independent  
Merge  
Shaded background concaved display  
Shaded background convexed display  
background  
succeeding  
line merge  
Undisplay  
Solid-fill display  
Shaded  
background  
concaved  
display  
Character  
Independent background  
extended  
Normal  
Independent  
Character  
background  
Shaded  
Shaded  
background  
succeeding  
character  
merge  
background  
succeeding  
line merge  
(enabled  
with line  
spacing)  
Shaded  
background  
convexed  
display  
Merge  
Merge  
Extended  
Undisplay (blank character (Arbitrarily set))  
Undisplay  
Display for characters with no character  
background  
Undisplay  
Character  
Trimming output  
control  
Display  
Display for characters with no character  
background or with solid-filled  
character background  
Trimming  
type  
Eight-  
direction  
trimming  
display  
Display for all characters  
Undisplay  
Display  
Sprite  
character  
Undisplay  
Consisting of a single character  
Consisting of a stack of characters  
Trimming  
type  
Eight-direction  
trimming display  
22  
MB90097  
1. 3 Screen Output Control  
The screen output control commands can control three channels of outputs A, B, and C independently.  
Their output enable period signals are output to the BLKA, BLKB, and BLKC pins, respectively.  
The output-A, -B, and -C control commands can set the character attribute display to OFF, line background  
display, and screen background display arbitrarily based on the basic display screen, allowing three independent  
screens to be configured and output.  
The layer structure of the output screens exists only on the basic display screen. If the output-A, -B, or -C  
control command sets the display of an arbitrary area to OFF, the lower layer cannot be displayed but appears  
transparent.  
The table below shows the relationships between screen output controls and control command bits.  
Basic display screen control  
Three-channel output controls  
Elements to be controlled/Control bit name  
(Unit of control)  
Output-A control Output-B control Output-C control  
Character + trimming + character background +  
line background  
DSP (per screen)  
←
←
←
←
←
←
Character + trimming + character  
background LDS (per line)  
Character M8-M0 (per character)  
OA2-OA0  
(per screen)  
×
OB2-OB0  
(per screen)  
×
OC2-OC0  
(per screen)  
×
Character trimming  
LFD-LFA (per line)  
MO1, MO0*1  
(per character)  
MO1, MO0*1  
(per character)  
MO1, MO0*1  
(per character)  
Character background  
MM1, MM0 (per character)  
BLB*2  
(per screen)  
BLC*2  
(per screen)  
Line background LM1, LM0 (per line)  
←
BGB  
(per screen)  
BGC  
(per screen)  
Screen background color UDS (per screen)  
Sprite character SDS (per screen)  
←
←
←
SOB*3  
(per screen)  
SOC*3  
(per screen)  
Sprite character trimming  
SFB, SFA (per screen)  
*1: If character display is set to OFF with the character/trimming/character background overlapping the line  
background or screen background, the corresponding area of the lower layer is not displayed but appears  
transparent.  
*2: If line background display is set to OFF with the line background overlapping the screen background, the  
corresponding area of the screen background is not displayed but appears transparent.  
*3: If sprite display is set to OFF with the sprite character/trimming overlapping a character, character background,  
line background, or screen background, the corresponding area of the lower layer is not displayed but appears  
transparent.  
Note: Three-channel output control for each character serves as output control within the character area. When  
trimming dots for a character are displayed in part of the area for an adjacent character, the output of the  
trimming dots is controlled by the output control of that adjacent character. If there are trimming dots to the  
left of the leftmost character on a line, they cannot be controlled by three-channel output control for each  
character. In this case, set a blank character at the left end of the line.  
When trimming dots are displayed to the right of the rightmost character on a line, they are controlled with  
the three-channel output attribute of the rightmost character.  
23  
MB90097  
1. 4 Screen Display Position Control  
(1) Display position control on the character screen  
The MB90097 can simultaneously control the display start positions of a character (or a line of characters),  
character trimming, character background, and line background.  
• Vertical display position: Vertical display position control (command 5-2), Bits Y8 to Y0  
Set the vertical display start position*1 relative to the VSYNC position.  
The position can be set between 0 and 1022 dots in 2-dot units.  
(*1: The actual display position is offset from the set value by several tens of dots  
in the positive direction.)  
• Horizontal display position: Horizontal display position control (command 5-3), Bits X8 to X0  
Set the vertical display start position*2 relative to the HSYNC position.  
The position ca*n be set between 0 and 1022 dots in 2-dot units.  
(*2: The actual display position is offset from the set value by several tens of dots  
in the positive direction.)  
• Line spacing: Line control data setting 1 (command 3), Bits LW2 to LW0  
Set the number of dots to specify the height of the areas to be kept above and  
below the characters on each line.  
The spacing specified by the set value will be kept both above and below the  
characters.  
The line spacing can be set between 0 and 7 dots in 1-dot units for each line.  
(Note: When line double-height display is on, the line spacing is doubled as well.)  
VSYNC position*3  
• • •  
HSYNC position*3  
Vertical display position  
Line spacing  
• • •  
• • •  
Character Character Character Character Character Character Character Character Character  
Horizontal  
display position  
Line 0  
Line spacing  
• • •  
Character Character Character Character Character Character Character Character Character  
Line 1  
Line spacing  
• • •  
Character Character Character Character Character Character Character Character Character  
Line 2  
*3: For the VSYNC position, you can select the leading or trailing edge of the vertical sync signal pulse.  
For the HSYNC position, you can select the leading or trailing edge of the horizontal sync signal pulse.  
(For details, see Section 3 “Sync Signal Input” of “■ CONTROL FUNCTIONS.”)  
24  
MB90097  
(2) Display position control of sprite characters  
The MB90097 can control the display start positions of a sprite character and its trimming.  
• Sprite character vertical display position: Sprite character control 4 (command 9-0), Bits SY9 to SY0  
Set the vertical display start position*1 relative to the VSYNC  
position.  
The position can be set between 0 and 1023 dots in 1-dot units.  
(*1: The actual display position is offset from the set value by  
several tens of dots in the positive direction.)  
• Sprite character horizontal display position: Sprite character control 5 (command 9-1), Bits SX9 to SX0  
Set the vertical display start position*2 relative to the HSYNC  
position.  
The position can be set between 0 and 1023 dots in 1-dot units.  
(*2: The actual display position is offset from the set value by  
several tens of dots in the positive direction.)  
VSYNC position*3  
Sprite character  
HSYNC position*3  
vertical display  
position*1  
Sprite character horizontal  
display position  
Sprite character  
*3: For the VSYNC position, you can select the leading or trailing edge of the vertical sync signal pulse.  
For the HSYNC position, you can select the leading or trailing edge of the horizontal sync signal pulse.  
(For details, see Section 3 “Sync Signal Input” of “■ CONTROL FUNCTIONS.”)  
25  
MB90097  
2. Font ROM Configuration  
The font ROM can incorporate 512 characters each made up of 12 × 18 dots.  
• All of 512 characters can be set freely by the user.  
(Note, however, that the blank character must be set as an arbitrary character code because even it is not  
set by default.)  
• The user areas available to sprite characters are from 000H to 0FFH.  
Font ROM  
000 H  
001 H  
002 H  
(User area)  
(User area)  
(User area)  
Areas available  
to sprite characters  
12 dots  
0FE H  
0FF H  
(User area)  
(User area)  
100 H  
(User area)  
(User area)  
(User area)  
101 H  
102 H  
1FE H  
(User area)  
(User area)  
1FF H  
↑
(Character configuration example)  
Character code  
26  
MB90097  
3. Display Memory (VRAM) Configuration  
The display memory (VRAM) consists of the character RAM for setting individual characters and the line RAM  
for setting individual lines.  
• Character RAM: 28 characters × 12 lines (336 characters in total)  
• Line RAM: 12 lines  
3. 1 Display Memory and Display Screen  
Areas of character RAM and those of line RAM correspond to displayed characters and lines on a one-to-one  
basis, respectively.  
• Display memory configuration  
Character RAM  
Line RAM  
0
1
2
3
4
5
6
7
8
9
10  
11  
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2  
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7  
Column addresses  
• Example of display screen configuration (with all characters in normal size)  
VRAM row address  
0
1
2
3
4
5
6
7
8
9
10  
11  
VRAM column address  
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2  
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7  
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MB90097  
3. 2 Writing to Display Memory  
(1) Writing characters to character RAM  
a) Writing a single character  
Use the following commands to write data on an arbitrary character to an arbitrary address in character  
RAM:  
1
*
Set the row and column addresses.  
VRAM write address setting  
Character data setting 1  
(Command 0)  
(Command 1)  
2
*
Write the character data to character RAM.  
Character data setting 2  
(Command 2)  
(The VRAM write address is incremented after writing to VRAM.)  
*1: When writing to consecutive addresses continuously, you can omit this command for the latter character RAM  
write.  
*2: You can also omit this command if the current character data is the same as the one set by the preceding  
“character data setting 1” command.  
Note: Normal writing to VRAM requires input of a normal horizontal sync signal. Input of an invalid horizontal sync  
signal may cause VRAM write to fail.  
Also, you must set the horizontal sync signal pulse width and VRAM write cycle (command 2 or command  
4 issuance cycle) such that: horizontal sync signal pulse width < VRAM write cycle.  
b) Writing multiple characters collectively (VRAM fill)  
Use the following commands to write data on an arbitrary character to an area of character RAM from an  
arbitrary address to the last address, filling the area with that data:  
Set the row and column addresses and specify “VRAM fill”.  
VRAM write address setting  
Character data setting 1  
(Command 0)  
(Command 1)  
3
The character RAM write executes VRAM fill.*  
Character data setting 2  
(Command 2)  
*3: The VRAM fill execution time is about 2 ms for the entire screen.  
During execution of VRAM fill, do not issue command 0 to 4.  
Issuing command 0 (FL = 0) during execution of VRAM fill will abort the VRAM fill.  
(To write to VRAM after VRAM fill has aborted, issue command 0 again to set the VRAM write address.)  
Note: Normal execution of VRAM fill requires input of a normal horizontal sync signal. Input of an invalid horizontal  
sync signal may cause VRAM fill to fail.  
28  
MB90097  
(2) Writing to line RAM  
Use the following commands to write data on an arbitrary line to an arbitrary address in line RAM:  
4
*
Set the row address.  
VRAM write address setting  
Line control data setting 1  
(Command 0)  
(Command 3)  
*5  
Write the line data to line RAM.  
Line control data setting 2  
(Command 4)  
(The VRAM write address remains unchanged.)  
*4: The line RAM fill function is not available. (It is prohibited to specify “Line RAM fill”.)  
*5: You can omit this command if the current line control data is the same as the one set by the preceding “line  
control data setting 1” command.  
Note: Normal writing to VRAM requires input of a normal horizontal sync signal. Input of an invalid horizontal sync  
signal may cause VRAM write to fail.  
Also, you must set the horizontal sync signal pulse width and VRAM write cycle (command 2 or command  
4 issuance cycle) such that: horizontal sync signal pulse width < VRAM write cycle.  
29  
MB90097  
4. Character Display  
4. 1 Displayed Character Configuration  
For each character to be displayed, you can set the vertical and horizontal sizes.  
Each character is displayed by clipping the specified size of the specified character data from font ROM, starting  
at the upper leftmost dot.  
• Character horizontal size control (Setting for each character)  
Character data setting 1 (Command 1): Bits MS1 and MS0  
MS1 MS0  
Character horizontal size  
S size: 6 dots  
0
0
1
1
0
1
0
1
M size: 9 dots  
L size: 12 dots  
(Setting prohibited)  
• Line character vertical size type control (Setting for each line)  
Line control data setting 1 (Command 3): Bit LHS  
LHS  
Line character vertical size type  
Line character vertical size A: 18 dots  
Line character vertical size B: 12 dots  
0
1
30  
MB90097  
• Display examples  
• A character stored in font ROM  
(12 horizontal dots × 18 vertical dots)  
• Display example 1 (character vertical size A: 18 dots)  
L size  
M size  
S size  
M size  
• Display example 2 (character vertical size B: 12 dots)  
L size  
M size  
S size  
M size  
31  
MB90097  
4. 2 Character Trimming  
(1) Trimming output control  
Trimming output control turns ON or OFF the trimming of characters depending on their character background  
type. One of the four character background types can be set for each line.  
• Trimming output control (Setting for each line)  
Line control data setting 1 (Command 3): Bits LFD and LFC  
Trimming output control  
(Setting for each line)  
Character background type  
(Setting for each character)  
Trimming output  
LFD  
LFC  
MM1  
MM0  
Background display  
0
0
0
0
0
1
Undisplay  
×
×
Solid-filled background  
Concaved, shaded  
background  
1
1
0
1
×
×
Convexed, shaded  
background  
0
1
1
0
Undisplay  
0
0
0
1
Solid-filled background  
×
×
Concaved, shaded  
background  
1
1
0
1
Convexed, shaded  
background  
×
Undisplay  
0
0
0
1
Solid-filled background  
Concaved, shaded  
background  
1
1
0
1
×
×
Convexed, shaded  
background  
1
1
Undisplay  
0
0
0
1
Solid-filled background  
Concaved, shaded  
background  
1
1
0
1
Convexed, shaded  
background  
× : Undisplay  
: display  
32  
MB90097  
(2) Trimming type control  
As the type of trimming, you can select “eight-direction trimming” or “undisplay”.  
• Trimming type control (Setting for each screen)  
Line control data  
setting 1 (Command 3): Bits LFB and LFA  
Trimming  
output control  
Trimming output  
LFB  
LFA  
0
0
1
1
0
1
0
1
Undisplay  
Reserved (Setting prohibited)  
Reserved (Setting prohibited)  
Eight-direction trimming  
(3) Trimming colors  
The trimming color can be set to one of 16 different colors for each line.  
• Trimming color (Setting for each line, selected from among 16 colors)  
Line control data setting 1 (Command 1): Bits LF3 to LF0  
(4) Trimming display rules  
The following display rules apply to trimming display:  
• Trimming dots for a character can be displayed in the right or left adjacent character area only when the  
character background types of the two characters are the same.  
• Trimming dots for the character at the left or right end of a line can be displayed beyond the character area  
only when the character background type is “no character background”.  
(When three-channel output control for each character is used, however, do not attempt to display trimming  
dots outside the character area at the left end of a line. Trimming dots for that area cannot be controlled in  
character units. Note also that trimming dot display outside the character area at the right end of a line  
depends on the character output control setting for the rightmost character on the line.)  
• Trimming display for a character does not apply to the areas above and below the character (the area for the  
character on the line above, the area for the character on the line below, the upper line spacing, and the lower  
line spacing).  
• When a line is displayed enlarged, trimming dots on the line are not enlarged but those in the normal dot  
size are displayed around the enlarged character dots.  
Note: For output control of each character using three-channel output control, design the display and font taking  
account of trimming dot display protruding to the area for the adjacent character to the right or left.  
Three-channel output control for each character is display output control of the character area. Turning on  
or off the display of trimming dots protruding to the right or left adjacent character area depends on the  
character output control setting for that adjacent character.  
33  
MB90097  
4. 3 Line Enlarged Display  
Line enlarged display control is used to control the display size of each line including the characters, character  
backgrounds, and line background on that line (as well as the line spacing portions). This also controls  
enlargement of the shadow frames of shaded backgrounds. It does not however control the enlargement of the  
trimming dot width.  
Note that the lines and characters following the line for which line enlarged display has been specified are shifted  
down accordingly.  
• Line enlargement control (Setting for each line)  
Line control data setting 2 (Command 4): Bits LG1 and LG0  
LG1  
LG0  
Display size  
Normal size  
0
0
1
1
0
1
0
1
Double-width size  
Double-height size  
Double-width/height size  
(1) Line enlarged display examples  
• Normal size  
Line spacing  
Line spacing  
Displayed line  
• Double-width size  
Line spacing  
Line spacing  
• Double-height size  
Line spacing  
Line spacing  
34  
MB90097  
• Double-width/height size  
Line spacing  
Line spacing  
(2) Dot interpolation for enlarged display  
Dot interpolation display is enabled only when the line enlargement control is in the double-width size display.  
You can designate the display in line units.  
Dot interpolation is performed in character units; dots are not interpolated between the neighboring characters.  
Outline display is generated and displayed in the character dots and interpolation dots. Outline dot width is not  
displayed enlarged.  
• Line enlargement interpolation control (Setting for each line)  
Line control data setting 2 (Command 4): Bit LGS  
LGS  
Interpolation control  
Interpolation OFF  
Interpolation ON  
0
1
• Interpolated display examples (Basic type)  
Double-width height size  
Normal size  
Character dot  
Arbitrary dot*  
Interpolating dot  
Character dot  
Character dot  
Arbitrary dot*  
Character dot  
Interpolating dot  
*: Blank dot or character dot  
35  
MB90097  
5. Character Background Display  
5. 1 Character Background Display  
For each character, you can set the character background selected from among four types and the character  
background color from among 16 colors.  
• Character background control  
(Setting for each character)  
Character data setting 1 (Command 1) :  
Bits MM1 and MM0  
• Character background color  
(Setting for each character, selected from among 16 colors)  
Character data setting 1 (Command 1) :  
Bits MB3 to MB0  
Note: The character background color is transparent when all of  
MB3 to MB0 have been set to 0.  
MM1 MM0 Character background  
(If character background display has been set for a character  
with the above settings, the corresponding portion of the  
lower layer will be displayed.)  
NO background  
(undisplay)  
0
0
1
0
1
0
• Shaded background highlight color  
(Setting for each screen, selected from among 16 colors)  
Shaded background frame color control (Command 6-1) :  
Bits BH3 to BH0  
Solid-filled background  
Concaved, shaded  
background  
Convexed, shaded  
background  
1
1
• Shaded background shadow color  
(Setting for each screen, selected from among 16 colors)  
Shaded background frame color control (Command 6-1) :  
Bits BS3 to BS0  
• Display examples  
(a) No background  
(b) Solid-filled background  
Character  
Lower-layer  
output (Line  
background  
background color  
color, screen  
background color,  
or no output)  
Character display  
(c) Concaved, shaded background  
(d) Convexed, shaded background  
Shaded  
Shaded  
background  
shadow color  
background  
highlight color  
Shaded  
Shaded  
background  
highlight color  
background  
shadow color  
Character  
Character  
background color  
background color  
* The shaded background frame for a character is  
displayed inside the circumference of the character area.  
36  
MB90097  
5. 2 Shaded Background Succeeding Character Merge Display  
Specifying “shaded background character display” and “shaded background succeeding character merge  
display” for a character undisplays the right line of the shadow frame of the character and the left line of the  
shadow frame of the next (right adjacent) character. This enables two or more characters with shaded  
backgrounds to be joined horizontally.  
• Shaded background succeeding character merge control (Setting for each character)  
Character data setting 2 (Command 2) : Bit MR  
Shaded background succeeding  
MR  
character merge control  
0
1
OFF  
ON  
• Display examples of independent characters with shaded backgrounds  
(Succeeding character merge = OFF) (Succeeding character merge = OFF) (Succeeding character merge = OFF)  
• Display examples of merged characters with shaded backgrounds  
(Succeeding character merge = ON) (Succeeding character merge = ON) (Succeeding character merge = OFF)  
37  
MB90097  
5. 3 Shaded Background Succeeding Line Merge Display  
Specifying “shaded background character display" for characters on a line and both of “character background  
extended display” and “shaded background succeeding line merge display” for the line undisplays the lower  
lines of the shadow frames of the characters on that line and the upper lines of the shadow frames of the  
characters on the next line. (Specify both of “shaded background succeeding line merge display” and “character  
background extended display” for the current line and “character background extended display” for the next line.)  
• Shaded background succeeding line merge control • Character background extended display control  
(Setting for each line)  
Line control data setting 2 (Command 4) :  
Bit LD  
(Setting for each line)  
Line control data setting 2 (Command 4) :  
Bit LE  
Character background  
LE  
Shaded background  
LD  
extended display control  
succeeding line merge control  
0
1
OFF (Normal display)  
ON (Extended display)  
0
1
OFF  
ON  
• Display examples of merged lines of characters with shaded backgrounds  
Succeeding line merge = ON  
and  
Extended display = ON  
Succeeding line merge = OFF  
and  
Extended display = ON  
(Succeeding character merge = ON) (Succeeding character merge = OFF) (Succeeding character merge = OFF)  
Note: If character background extended display is not specified, shaded background succeeding line merge  
display is disabled for character backgrounds. (The setting of shaded background succeeding line merge  
display applies only to the line background shadow frame.)  
38  
MB90097  
5. 4 Character Background Extended Display  
Character background extended display extends character backgrounds to line spacing portions.  
(Note that this setting is required to apply shaded background succeeding line merge display to character  
backgrounds.)  
• Character background extended display (Setting for each line)  
Line control data setting 2 (Command 4): Bit LE  
LE  
0
Character background extended display  
OFF (Normal display)  
1
ON (Extended display)  
• Display example with character background extended display = OFF  
(Line spacing = 2)  
(No character background)  
(Solid-filled background)  
(Concaved, shaded background)  
Line spacing  
• Display example with character background extended display = ON  
(Line spacing = 2)  
(No character background)  
(Solid-filled background)  
(
Concaved, shaded background)  
Line spacing  
39  
MB90097  
6. Line Background Display  
6. 1 Line Background Display  
Line background display for a line displays the line background in the line area of the characters on the line, the  
areas to the right and left of that area, and the line spacing areas above and below it.  
There are four types of line backgrounds are available (None, Solid fill, Concaved shaded background, and  
Convexed shaded background), one of which can be set for each line.  
Shaded line background display is used to display the shaded background frame highlight color and shaded  
background frame shadow color above and below the line background area, respectively, along with the line  
background color display.  
• Line background control  
(Setting for each line)  
Line control data setting 2 (Command 4) :  
• Line background color  
(Setting for each line, selected from among 16 colors)  
Line control data setting 2 (Command 4) :  
Bits L3 to L0  
Bits LM1 and LM0  
• Shaded background highlight color  
(Setting for each screen, selected from among 16 colors)  
Shaded background frame color control (Command 6-1) :  
Bits BH3 to BH0  
LM1 LM0  
Line background  
No background (undisplay)  
Solid-filled background  
0
0
0
1
• Shaded background shadow color  
Concaved, shaded  
background  
1
1
0
1
(Setting for each screen, selected from among 16 colors)  
Shaded background frame color control (Command 6-1) :  
Bits BS3 to BS0  
Convexed, shaded  
background  
• Line background display examples  
No line background  
0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J  
Solid-filled background  
0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J  
0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J  
0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J  
(Shaded background frame highlight color)  
Convexed, shaded background  
(Shaded background frame shadow color)  
(Shaded background frame shadow color)  
Concaved, shaded background  
(Shaded background frame highlight color)  
Character display area  
40  
MB90097  
6. 2 Shaded Background Succeeding Line Merge Display  
Specifying “shaded background succeeding line merge display” for a line enables the line to be displayed with  
the line background merged with that of the next line.  
This undisplays the lower line of the line background shadow frame of the current line and the upper line of the  
line background shadow frame of the next line, allowing two or more lines to be displayed with shaded line  
backgrounds.  
• Shaded background succeeding line merge control (Setting for each line)  
Line control data setting 2 (Command 4): Bit LD  
Shaded background succeeding line  
LD  
merge control  
0
1
OFF  
ON  
• Examples of shaded background succeeding line merge display  
(Shaded background frame highlight color)  
0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J  
0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J  
Convexed, shaded background with  
succeeding line merge ON  
Convexed, shaded background with  
succeeding line merge OFF  
(Shaded background frame shadow color)  
(Shaded background frame shadow color)  
Concaved, shaded background with  
succeeding line merge ON  
0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J  
0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J  
Convexed, shaded background with  
succeeding line merge OFF  
(Shaded background frame shadow color)  
Character display area  
Note: Specifying shaded background succeeding line merge display applies merge control to the character and  
line backgrounds at the same time. If character background extended display is off for a line, however,  
merge control ignores the shaded background characters on that line.  
41  
MB90097  
7. Screen Background Display  
7. 1 Screen Background Color Display  
The screen background color can be output to the bottom layer of display output.  
• Screen background output control  
Screen output control 1A (Command 5-00): Bit UDS  
UDS  
Screen background color display  
0
1
OFF  
ON  
• Screen background color code  
Screen background control 4 (Command 7-3): Bits U3 to U0  
One of 16 colors can be set.  
• Three-channel output control  
When screen background color output is ON (UDS = 1), the screen background outputs to output B and output  
C can be controlled independently. (Output A is controlled only with the UDS bit.)  
• Output-B screen background color output control  
Screen output control 1B (Command 5-01): Bit BGB  
UDS Output-B screen background color output  
0
1
OFF  
ON*  
• Output-C screen background color output control  
Screen output control 1C (Command 5-02): Bit BGC  
UDS Output-C screen background color output  
0
1
OFF  
ON*  
* : Enabled only when screen background color output is ON (UDS = 1).  
42  
MB90097  
8. Sprite Character Display  
Sprite characters are displayed on the top layer of the display screen.  
(1) Sprite character configuration  
• Sprite character display example  
A A A A A A A A A A A A A A A A A A A A A  
A A A A A A A A A A A A A A A A A A A A A  
A A A A A A A A A A A A A A A A A A A A A  
A A A A A A A A A A A A A A A A A A A A A  
A A A A A A A A A A A A A A A A A A A A A  
A A S A A A A A A A A A A A A A A A A A A  
A A A A A A A A A A A A A A A A A A A A A  
A A A A A A A A A A A A A A A A A A A A A  
A A A A A A A A A A A A A A A A A A A A A  
A A A A A A A A A A A A A A A A A A A A A  
A A A A A A A A A A A A A A A A A A A A A  
Sprite character  
(displayed in the L size)  
(2) Sprite character display control  
• Sprite character output control  
Screen output control 1A (Command 5-00): Bit SDS  
SDS  
Sprite character output  
0
1
OFF  
ON  
• Sprite character code  
Sprite character control 2 (Command 8-1): Bits SM7 to SM0  
A sprite character code can be selected from among character codes 00H to FFH for 256 types of characters.  
When the sprite character consists of two characters, only an even-numbered character code can be set.  
• Sprite character color  
Sprite character control 1 (Command 8-0): Bits SC3 to SC0  
One of 16 colors can be set.  
• Sprite character trimming color  
Sprite character control 1 (Command 8-0): Bits SF3 to SF0  
One of 16 colors can be set.  
43  
MB90097  
• Sprite character trimming control  
Sprite character control 1 (Command 8-0): Bits SFB and SFA  
SFB SFA  
Trimming output  
Undisplay  
0
0
1
1
0
1
0
1
Reserved (Setting prohibited)  
Reserved (Setting prohibited)  
Eight-direction trimming  
• Sprite character vertical display position control  
Sprite character control 4 (Command 9-0): Bits SY9 to SY0  
Settable between 0 and 1023 dots in 1-dot units.  
• Sprite character horizontal display position control  
Sprite character control 5 (Command 9-1): Bits SX9 to SX0  
Settable between 0 and 1023 dots in 1-dot units.  
• Sprite character configuration control  
Sprite character control 2 (Command 8-1): Bits SD1 and SD0  
SD1 SD2  
Configuration  
0
0
1
1
0
1
0
1
1 character  
Reserved (Setting prohibited)  
Stack of 2 characters  
Reserved (Setting prohibited)  
• Sprite character configuration example  
• Sprite character code = n  
Character code  
n
Example of a 1-character sprite character (SD1, SD0) = (0, 0)  
A
B
n
A
n+1  
Example of a 2-character sprite character (SD1, SD0) = (1, 0)  
n
A
n+1  
B
44  
MB90097  
(3) Three-channel output control for sprite characters  
When sprite character output is ON (SDS = 1), the sprite character outputs to output B and output C can be  
controlled independently. (Output A is controlled only with the SDS bit.)  
• Output-B sprite character output control  
Screen output control 1B (Command 5-01): Bit SOB  
SOB  
Output-B sprite character output  
OFF*1  
ON*2  
0
1
• Output-C sprite character output control  
Screen output control 1C (Command 5-02): Bit SOC  
SOC  
Output-C sprite character output  
OFF*1  
ON*2  
0
1
*1: When the lower layer has display output, that portion appear transparent.  
(The lower layer cannot be displayed.)  
*2: Enabled only when screen background color output is ON (SDS = 1).  
45  
MB90097  
■ CONTROL FUNCTIONS  
1. Serial Command Control  
The MB90097 executes serial command/data transfer using the chip select (CS), serial clock (SCLK), and serial  
data input (SIN) pins. The data transfer direction (MSB-first or LSB-first transfer) is selected under control of the  
serial data input direction select (SDR) pin. The data length is 16 bits. If the CS pin goes HIGH during transfer  
with data less than 16 bits, command transfer is not guaranteed. Keeping the CS pin LOW allows multiple items  
of command data to be transferred continuously. (It is however recommended to set the CS pin to the HIGH  
level at intervals of tens of words for word synchronization.)  
The SCLK clock frequency is 4 MHz at maximum. Set it such that: VRAM write cycle (a minimum of 16 clock  
pulses) > input horizontal sync pulse width. If this condition is not satisfied, VRAM write may fail.)  
(1) MSB-first signal input timing  
SDR  
CS  
(Fixed at High)  
SCLK  
SIN  
DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0  
DF  
(2) LSB-first signal input timing  
SDR  
(Fixed at Low)  
CS  
SCLK  
SIN  
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF  
D0  
46  
MB90097  
2. Dot Clock Control  
For the dot clock, you can select internal generation by the LC oscillator circuit or external input.  
For the external input, you can select dot clock frequency direct input or frequency-doubled input.  
Set bits DC2 to DC0 of command 11-2 (dot clock control 1) to select dot clock control.  
• Dot clock selection control  
Dot clock control 1 (Command 11-2: Bits DC2 to DC0)  
DC2 DC1 DC0  
Dot clock control  
LC oscillation  
0
0
0
0
1
0
0
1
External input (dot clock)  
External input (2 × dot clock)  
Setting prohibited  
1
Else  
(1) Dot clock LC oscillation  
Connect the relevant pins to external “L” and “C” to form an LC oscillator circuit.  
External input of a horizontal sync signal is used to internally perform oscillation stop control, enabling horizontal  
display synchronization.  
Note: The horizontal synchronization operation edge must be the trailing edge.  
Set the horizontal synchronization operation edge (bit HE) of I/O pin control (command 13-0) to 0.)  
MB90097  
XD  
EXD  
L
C
C
47  
MB90097  
(2) External dot clock input  
The MB90097 inputs a dot clock signal to the EXD pin.  
Note: The input horizontal cycle must be synchronized in integer multiples of the input clock cycle.  
The input clock signal must be a continuous signal without being intermitted.  
MB90097  
XD  
EXD  
Open  
Dot clock  
(3) External “2 ×” (frequency-doubled) dot clock input  
Input the 2 × (frequency-doubled) dot clock signal to the EXD pin.  
Note: The input horizontal cycle must be synchronized in integer multiples of the input clock cycle.  
The horizontal synchronization operation edge must be the trailing edge.  
(Set the horizontal synchronization operation edge (bit HE) of I/O pin control (command 13-0) to 0.)  
The input clock signal must be a continuous signal without being intermitted.  
MB90097  
XD  
EXD  
Open  
2 ×  
Dot clock  
48  
MB90097  
3. Sync Signal Input  
3. 1 Vertical Synchronization Detection  
Vertical synchronization is detected by sensing the level of the vertical sync signal at the leading or trailing edge  
of the horizontal sync pulse to detect the transition. The vertical display position on the screen depends on the  
vertical synchronization detection position.  
Use I/O pin control (command 13-0) to select operation control.  
• Selecting a vertical synchronization detection edge • Selecting a vertical synchronization detection  
HSYNC edge  
Vertical synchronization detection  
HSYNC edge  
Vertical synchronization  
detection edge  
VHE  
VVE  
Detect vertical synchronization at the  
leading edge of HSYNC.  
0
1
Detect the leading edge of VSYNC.  
Detect the trailing edge of VSYNC.  
0
1
Detect vertical synchronization at the  
trailing edge of HSYNC.  
• Sync signal input logic control  
SIX  
0
Sync signal input logic  
The HSYNC and VSYNC pins are active low inputs.  
The HSYNC and VSYNC pins are active high inputs.  
1
• Principle of operation of detecting vertical synchronization  
(Example with sync signal input logic SIX = 0)  
(1) Detecting the leading edge of the vertical sync pulse at the leading edge of the horizontal sync pulse  
(VVE = 0, VHE = 0)  
VSYNC input  
HSYNC input  
Internally detected VSYNC  
1H pulse generated  
Synchronization detected position  
49  
MB90097  
(2) Detecting the leading edge of the vertical sync pulse at the trailing edge of the horizontal sync pulse  
(VVE = 0, VHE = 1)  
VSYNC input  
HSYNC input  
Internally detected VSYNC  
1H pulse generated  
Synchronization detected position  
(3) Detecting the trailing edge of the vertical sync pulse at the leading edge of the horizontal sync pulse  
(VVE = 1, VHE = 0)  
VSYNC input  
HSYNC input  
Internally detected VSYNC  
Synchronization detected position  
(4) Detecting the trailing edge of the vertical sync pulse at the trailing edge of the horizontal sync pulse  
(VVE = 1, VHE = 1)  
VSYNC input  
HSYNC input  
Internally detected VSYNC  
Synchronization detected position  
50  
MB90097  
3. 2 Operation in Horizontal Synchronization  
(1) Operation with dot clock LC oscillation  
The sync pulse of the input horizontal sync signal is used to control the oscillation and stop of the dot clock,  
enabling display horizontal synchronization.  
Bit HE (horizontal synchronization operation edge) of I/O pin control (command 13-0) must be set to “0”.  
• Operation example of horizontal synchronization  
LC oscillation  
dot clock input  
(EXD pin)  
HSYNC input  
Internal HSYNC  
Internal dot clock  
Clock stop period  
8 to 12 clock  
Horizontal synchronization position  
(Reference display position)  
51  
MB90097  
(2) Operation with external dot clock input  
You can select horizontal sync leading-edge or trailing-edge operation.  
• Horizontal synchronization operation edge selection  
I/O pin control (Command 13-0): Bit HE  
HE Horizontal synchronization operation edge  
0
1
Trailing-edge operation  
Leading-edge operation  
• Examples of horizontal synchronization operations  
(a) Horizontal syznc trailing-edge operation (HE = 0)  
Dot clock input  
HSYNC input  
Internal HSYNC  
Internal dot clock  
Clock stop period  
8 to 12 clock  
Horizontal synchronization position  
(Reference display position)  
(b) Horizontal sync leading-edge operation (HE = 1)  
Dot clock input  
HSYNC input  
Internal HSYNC  
Internal dot clock  
Clock stop period  
8 to 12 clock  
About 16 clock  
Horizontal synchronization position  
(Reference display position)  
52  
MB90097  
3. 3 Vertical Blanking Control  
Vertical blanking control is used to internally generate the vertical blanking interval for display signal output  
control.  
Display singnal output is stopped during the vertical blanking interval.  
Vertical blanking control results in either of the following two operations depending on the setting of bit VVE  
(vertical synchronization detection edge selection control) of I/O pin control (command 13-0).  
(1) Operation of vertical sync leading-edge detection  
VSYNC input  
About 17H  
Vertical blanking interval  
(2) Operation of vertical sync trailing-edge detection  
VSYNC input  
About 14H  
Vertical blanking interval  
53  
MB90097  
3. 4 Horizontal Blanking Control  
Horizontal blanking control is used to generate the horizontal blanking interval for display signal output control.  
Display signal output is stopped during the horizontal blanking interval.  
Horizontal blanking control can be set for the back porch or front porch by command control.  
Horizontal blanking control results in either of the following two operations depending on the setting of bit HE  
(horizontal synchronization operation edge selection control) of I/O pin control (command 13-0).  
(1) When the horizontal synchronization operation edge is the trailing edge (bit HE = 0)  
HSYNC input  
Front porch  
Back porch  
Horizontal blanking interval  
(2) When the horizontal synchronization operation edge is the leading edge (bit HE = 1)  
HSYNC input  
Front porch  
Back porch  
Horizontal blanking interval  
• Horizontal blanking (back porch) control  
Horizontal blanking control 1 (Command 13-1): Bits BB5 to BB0  
Setting between 0 and 126 dots in 2-dot units.  
• Horizontal blanking (front porch) control  
Horizontal blanking control 2 (Command 13-2): Bits BF8 to BF0  
Setting between 0 and 1022 dots in 2-dot units.  
Notes: 1. The back porch must be shorter than the front porch. Do not make any other setting.  
2. The actual horizontal blanking interval is offset from the set value by several tens of dots in the positive  
direction.  
54  
MB90097  
4. Display Signal Output  
4. 1 Three-Channel Output Control  
(1) Display control bits and control ranges  
The following chart summarizes the relationships among display control and three-channel output control bits.  
A-channel output  
B-channel output  
C-channel output  
DSP  
LDS  
Display output control  
Line character output control  
OA2 to OA0,  
MO1, MO0  
OB2 to OB0,  
MO1, MO0  
OC2 to OC0,  
MO1, MO0  
Character  
MM1, MM0  
LM1, LM0  
Character background control  
Line background control  
Character  
background  
BLB  
BLC  
Line background  
BGB  
SOB  
BGC  
SOC  
UDS  
SDS  
Screen background output control  
Sprite character output control  
Screen background  
Sprite character  
• If character display of a character is turned OFF by bits OA2-OA0, OB2-OB0, OC2-OC0, or MO1, MO0, the  
character (including its trimming and character background) is displayed transparent, including the  
corresponding portion of the lower layer (line and screen backgrounds).  
• If line background display is turned OFF by bit BLB, the line background and the corresponding portion of the  
screen background display layer are displayed transparent.  
• If line background display is turned OFF by bit BLC, the line background and the corresponding portion of the  
screen background display layer are displayed transparent.  
• If screen background display is turned OFF by bit BGB, the screen background display layer is displayed  
transparent.  
• If screen background display is turned OFF by bit BGC, the screen background display layer is displayed  
transparent.  
• If sprite character display is turned OFF by bit SCB, the sprite character (including its trimming) and the  
corresponding portions of all lower layers are displayed transparent.  
• If sprite character display is turned OFF by bit SCC, the sprite character (including its trimming) and the  
corresponding portions of all lower layers are displayed transparent.  
55  
MB90097  
(2) Output-A/B/C control  
The character attributes (character, trimming, and character background) of each character can be displayed  
by three-channel (A/B/C) output control.  
Commands 5-00 to 5-02 are used for output control for each screen; command 2 is used for output control for  
each character.  
When trimming dots for a character are displayed protruding to the area for an adjacent character, the output  
of the trimming dots is controlled by the character output control of that adjacent character. Three-channel output  
control for each character serves as output control within the character area (12 × 18 dots for normal-sized  
characters).  
If there are trimming dots to the left of the leftmost character on a line, they cannot be controlled by three-channel  
output control. In this case, place a blank character at the left end of the line and set characters to be displayed  
to the right.  
When trimming dots are displayed to the right of the rightmost character on a line, the three-channel output  
control of the trimming dots depends on the character output control of the rightmost character.  
• Output-A character control  
Screen output control 1A (Command 5-00):Bits OA2 to OA0  
Settable, selected from among eight types.  
• Output-B character control  
Screen output control 1B (Command 5-01): Bits OB2 to OB0  
Settable, selected from among eight types.  
• Output-C character control  
Screen output control 1C (Command 5-02): Bits OC2 to OC0  
Settable, selected from among eight types.  
• Character output control  
Character data setting 2 (Command 2): Bits MO1 and MO0  
Settable, selected from among four types for each character.  
Output-A/B/C character control  
Character output control  
Output (Pin output)  
OA2  
/
OB2  
/
OA1  
/
OB1  
/
OA0  
/
OB0  
/
MO1  
MO0  
Output-A (BLKA pin output)  
/
Output-B (BLKB pin output)  
/
OC2  
OC1  
OC0  
Output-C (BLKC pin output)  
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
×
×
×
×
All display OFF  
0
0
0
0
0
1
All display ON  
: Display ON  
× : Display OFF  
(Continued)  
56  
MB90097  
(Continued)  
Output-A/B/C character control  
Character output control  
Output (Pin output)  
OA2  
/
OB2  
/
OA1  
/
OB1  
/
OA0  
/
OB0  
/
MO1  
MO0  
Output-A (BLKA pin output)  
/
Output-B (BLKB pin output)  
/
OC2  
OC1  
OC0  
Output-C (BLKC pin output)  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
×
Display ON for only characters with  
MO0 = 1  
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
×
×
×
Display ON for only characters with  
MO1 = 1  
×
Display ON for only characters with  
MO0 = 1 or MO1 = 1  
Display ON for only characters with  
MO0 = 0  
×
×
Display ON for only characters with  
MO1 = 0  
×
×
Display ON for only characters with  
MO0 = 0 or MO1 = 0  
×
×
×
: Display ON  
× : Display OFF  
57  
MB90097  
4. 2 Display Signal Output Timings  
Display signals are output as shown below.  
• Output channel-A display period signal: BLKA pin  
• Output channel-B display period signal: BLKB pin  
• Output channel-C display period signal: BLKC pin  
• Color code signals: VC3 to VC0 pin  
• Display signal output example  
Displayed character  
Display line  
Trimming color  
Trimming color  
Display color  
Screen  
background background  
Character  
Character  
color  
Character  
background  
color  
Screen  
background  
color  
color  
color  
VC3-0 output  
(Color code)  
(4)  
(3) (2)  
(1)  
(2) (3)  
(4)  
BLKA output  
HIGH level  
BLKB output  
BLKC output  
LOW level  
Notes: The settings for the above display are as follows:  
• Output A: All items are output (with screen background output).  
• Output B: Only character attributes are output.  
• Output C: Output OFF  
• Color settings: Character color code: 1  
Trimming color code: 2  
Character background color code: 3  
Screen background color code: 4  
58  
MB90097  
■ CONTENTS OF MB90097-001 (STANDARD PRODUCT) FRONT ROM  
59  
MB90097  
60  
MB90097  
■ ORDERING INFORMATION  
Part number  
Package  
Remarks  
20-pin plastic SSOP  
(FPT-20P-M03)  
MB90097-PFV  
61  
MB90097  
■ PACKAGE DIMENSION  
20-pin plastic SSOP  
(FPT-20P-M03)  
* : These dimensions do not include resin protrusion.  
1.25–+00..1200  
*
6.50±0.10(.256±.004)  
(Mounting height)  
.049+–..000048  
0.10(.004)  
INDEX  
*
4.40±0.10 6.40±0.20  
(.173±.004) (.252±.008)  
5.40(.213)  
NOM  
"A"  
0.22–+00..0150  
0.15–+00..0025  
Details of "A" part  
0.10±0.10(.004±.004)  
0.65±0.12  
(.0256±.0047)  
.009–+..000024  
.006–+..000012  
(STAND OFF)  
0
10°  
0.50±0.20  
(.020±.008)  
5.85(.230)REF  
C
1994 FUJITSU LIMITED F20012S-2C-4  
Dimensions in mm (inches).  
62  
MB90097  
FUJITSU LIMITED  
For further information please contact:  
Japan  
FUJITSU LIMITED  
Corporate Global Business Support Division  
Electronic Devices  
KAWASAKI PLANT, 4-1-1, Kamikodanaka  
Nakahara-ku, Kawasaki-shi  
Kanagawa 211-8588, Japan  
Tel: (044) 754-3763  
All Rights Reserved.  
The contents of this document are subject to change without  
notice. Customers are advised to consult with FUJITSU sales  
representatives before ordering.  
Fax: (044) 754-3329  
http://www.fujitsu.co.jp/  
The information and circuit diagrams in this document are  
presented as examples of semiconductor device applications,  
and are not intended to be incorporated in devices for actual use.  
Also, FUJITSU is unable to assume responsibility for  
infringement of any patent rights or other rights of third parties  
arising from the use of this information or circuit diagrams.  
North and South America  
FUJITSU MICROELECTRONICS, INC.  
Semiconductor Division  
3545 North First Street  
San Jose, CA 95134-1804, USA  
Tel: (408) 922-9000  
Fax: (408) 922-9179  
FUJITSU semiconductor devices are intended for use in  
standard applications (computers, office automation and other  
office equipment, industrial, communications, and measurement  
equipment, personal or household devices, etc.).  
CAUTION:  
Customers considering the use of our products in special  
applications where failure or abnormal operation may directly  
affect human lives or cause physical injury or property damage,  
or where extremely high levels of reliability are demanded (such  
as aerospace systems, atomic energy controls, sea floor  
repeaters, vehicle operating controls, medical devices for life  
support, etc.) are requested to consult with FUJITSU sales  
representatives before such use. The company will not be  
responsible for damages arising from such use without prior  
approval.  
Customer Response Center  
Mon. - Fri.: 7 am - 5 pm (PST)  
Tel: (800) 866-8608  
Fax: (408) 922-9179  
http://www.fujitsumicro.com/  
Europe  
FUJITSU MIKROELEKTRONIK GmbH  
Am Siebenstein 6-10  
D-63303 Dreieich-Buchschlag  
Germany  
Tel: (06103) 690-0  
Fax: (06103) 690-122  
Any semiconductor devices have an inherent chance of  
failure. You must protect against injury, damage or loss from  
such failures by incorporating safety design measures into your  
facility and equipment such as redundancy, fire protection, and  
prevention of over-current levels and other abnormal operating  
conditions.  
http://www.fujitsu-ede.com/  
Asia Pacific  
FUJITSU MICROELECTRONICS ASIA PTE LTD  
#05-08, 151 Lorong Chuan  
New Tech Park  
Singapore 556741  
Tel: (65) 281-0770  
If any products described in this document represent goods or  
technologies subject to certain restrictions on export under the  
Foreign Exchange and Foreign Trade Law of Japan, the prior  
authorization by Japanese government will be required for  
export of those products from Japan.  
Fax: (65) 281-0220  
http://www.fmap.com.sg/  
F9906  
FUJITSU LIMITED Printed in Japan  

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