MC9S08FL16CBM_技术文档

Freescale Semiconductor

Data Sheet: Product Preview

Document Number: MC9S08FL16

Rev. 0 Draft B, 10/2008

MC9S08FL16

MC9S08FL16 Series

Covers: MC9S08FL16 and

MC9S08FL8

32-Pin SDIP

32-Pin LQFP

• Illegal address detection with reset

• Flash block protection

Features:

8-Bit S08 Central Processor Unit (CPU)

Development Support

• Up to 20 MHz CPU at 4.5 V to 5.5 V across

• Single-wire background debug interface

temperature range of 0 °C to 85 °C

• Breakpoint capability to allow single breakpoint

setting during in-circuit debugging (plus two more

breakpoints). On-chip in-circuit emulator (ICE)

debug module containing two comparators and

nine trigger modes.

• HC08 instruction set with added BGND instruction

• Support for up to 32 interrupt/reset sources

On-Chip Memory

• Up to 16 KB flash read/program/erase over full

Peripherals

operating voltage and temperature

• Up to 1024-byte random-access memory (RAM)

• Security circuitry to prevent unauthorized access

to RAM and flash contents

• IPC — Interrupt Priority Controller to provide

hardware based nested interrupt mechanism

• ADC — 12-channel, 8-bit resolution; 2.5 μs

conversion time; automatic compare function;

1.7 mV/°C temperature sensor; internal bandgap

reference channel; operation in stop; optional

hardware trigger; fully functional from 4.5V to

5.5 V

• TPM — One 4-channel and one 2-channel

timer/pulse-width modulators (TPM) modules;

selectable input capture, output compare, or

buffered edge- or center-aligned PWM on each

channel

Power-Saving Modes

• Two low power stop modes; reduced power wait

mode

• Allows clocks to remain enabled to specific

peripherals in stop3 mode

Clock Source Options

• Oscillator (XOSC) — Loop-control Pierce

oscillator; Crystal or ceramic resonator range of

31.25 kHz to 39.0625 kHz or 16 MHz to 20 MHz

• Internal Clock Source (ICS) — Internal clock

source module containing a

• MTIM16 — One 16-bit modulo timer with optional

prescaler

• SCI — One serial communications interface

frequency-locked-loop (FLL) controlled by internal

or external reference; precision trimming of

internal reference allows 0.2% resolution and 2%

deviation over temperature and voltage; supports

bus frequencies up to 10 MHz

module with optional 13-bit break; LIN extensions

Input/Output

• 30 GPIOs including 1 output only pin and 1 input

only pin

System Protection

Package Options

• 32-pin SDIP

• Watchdog computer operating properly (COP)

reset with option to run from dedicated 1 kHz

internal clock source or bus clock

• 32-pin LQFP

• Low-voltage detection with reset or interrupt;

selectable trip points

• Illegal opcode detection with reset

This document contains information on a product under development. Freescale reserves the

right to change or discontinue this product without notice.

Table of Contents

1

2

3

4

5

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

System Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . 4

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 10

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2 Parameter Classification . . . . . . . . . . . . . . . . . . 10

5.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 10

5.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . 11

5.5 ESD Protection and Latch-Up Immunity . . . . . . 12

5.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12

5.7 Supply Current Characteristics . . . . . . . . . . . . . 16

5.8 External Oscillator (XOSC) Characteristics . . . . 17

5.9 Internal Clock Source (ICS) Characteristics. . . . 18

5.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 19

5.10.1Control Timing . . . . . . . . . . . . . . . . . . . . . 20

5.10.2TPM Module Timing . . . . . . . . . . . . . . . . 21

5.11 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . 22

5.12 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . 24

5.13 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . 25

5.13.1Conducted Transient Susceptibility . . . . . 25

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . 26

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . 27

6

7

Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.

Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

http://freescale.com/

The following revision history table summarizes changes contained in this document.

Rev

Date

Description of Changes

Initial created by Kenny and edited by Ping.

Added information of MTIM16, IPC, and 4 ADC channels

0

1

Sep 11, 2008

Oct 17, 2008

Related Documentation

Find the most current versions of all documents at: http://www.freescale.com

Reference Manual (MC9S08FL16RM)

Contains extensive product information including modes of operation, memory,

resets and interrupts, register definition, port pins, CPU, and all module

information.

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

2

Freescale Semiconductor

MCU Block Diagram

1

MCU Block Diagram

The block diagram, Figure 1, shows the structure of MC9S08FL16 series MCU.

PTA0/ADP0

16-bit Modulo Timer

TCLK

HCS08 CORE

PTA1/ADP1

(MTIM16)

PTA2/ADP2

BDC

CPU

PTA3/ADP3

2-CH TIMER/PWM

TPM2CH[1:0]

MODULE (TPM2)

PTA4/BKGD/MS

PTA5/IRQ/TCLK/RESET

PTA6/TPM2CH0

PTA7/TPM2CH1

HCS08 SYSTEM CONTROL

RESETS AND INTERRUPTS

MODES OF OPERATION

POWER MANAGEMENT

RESET

IRQ

COP

IRQ

LVD

Interrupt Priority Controller

(IPC)

PTB0/RxD/ADP4

PTB1/TxD/ADP5

PTB2/ADP6

ON-CHIP ICE AND

DEBUG MODUE (DBG)

TxD

RxD

Serial Communications

Interface (SCI)

PTB3/ADP7

USER FLASH

PTB4/TPM1CH0

PTB5/TPM1CH1

PTB6/XTAL

MC9S08FL16 — 16,384 BYTES

MC9S08FL8 — 8,192 BYTES

4-CH TIMER/PWM

TPM2CH[3:0]

MODULE (TPM1)

USER RAM

MC9S08FL16 — 1,024 BYTES

MC9S08FL8 — 768 BYTES

PTB7/EXTAL

PTC0/ADC8

PTC1/ADP9

PTC2/ADP10

PTC3/ADP11

PTC4

20-MHz INTERNAL CLOCK

SOURCE (ICS)

EXTAL

XTAL

External Oscillator Source

(XOSC)

V

PTC5

DD

SS

VOLTAGE REGULATOR

PTC6

PTC7

V

REFH

REFL

DDAD

SSAD

12-CH 8-BIT

ANALOG-TO-DIGITAL

CONVERTER(ADC)

ADP[11:0]

PTD0

PTD1

PTD2/TPM1CH2

PTD3/TPM1CH3

PTD4

NOTE

1. PTA4 is output only when used as port pin.

2. PTA5 is input only when used as port pin.

PTD5

Figure 1. MC9S08FL16 Series Block Diagram

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

Freescale Semiconductor

3

System Clock Distribution

2

System Clock Distribution

MC9S08FL16 series use ICS module as clock sources. The ICS module can use internal or external clock

source as reference to provide up to 20 MHz CPU clock. The output of ICS module includes,

•

ICSERCLK — ICS external clock reference provides EXTAL signal to ADC as external reference

clock.

ICSFFCLK — ICS fixed frequency clock reference (around 32.768 kHz) provides fixed lock

signal to TPMs.

ICSOUT — ICS CPU clock provides double of bus clock which is basic clock reference of

peripherals.

ICSLCLK — Alternate BDC clock provides debug signal to BDC module.

The TCLK pin is an extra external clock source. When TCLK is enabled, it can provide alternate clock

source to TPMs and MTIM16. The on-chip 1 kHz clock can provide clock source of COP module.

TCLK

1-kHz

COP

TPM1

TPM2

MTIM16

ADC

ICSERCLK

ICSFFCLK

ICSOUT

FIXED CLOCK (XCLK)

ICS

BUS CLOCK

÷2

ICSLCLK

XOSC

IPC

CPU

SCI

BDC

FLASH

RAM

EXTAL XTAL

Figure 2. System Clock Distribution Diagram

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

4

Freescale Semiconductor

Pin Assignments

3

Pin Assignments

This section shows the pin assignments for the MC9S08FL16 series devices.

PTC6

PTC5

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

PTC7

PTC4

2

PTA0/ADP0

PTD5

PTA5/IRQ/TCLK/RESET

3

PTD2/TPM1CH2

4

PTA1/ADP1

PTA2/ADP2

PTA3/ADP3

PTA6/TPM2CH0

PTA7/TPM2CH1

PTB0/RxD/ADP4

PTB1/TxD/ADP5

PTB2/ADP6

PTD4

PTA4/BKGD/MS

5

PTD0

6

PTD1

7

V_DD

8

V_SS

9

PTB7/EXTAL

10

PTB6/XTAL

11

PTB5/TPM2CH1

12

PTD3/TPM1CH3

13

PTB3/ADP7

PTC0/ADP8

PTC1/ADP9

PTB4/TPM1CH0

14

PTC3/ADP11

15

PTC2/ADP10

16

Figure 3. MC9S08FL16 Series 32-Pin SDIP Package

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

Freescale Semiconductor

5

Pin Assignments

PTA4/BKGD/MS

PTD0

PTA1/ADP1

1

24

23

22

21

20

19

18

PTA2/ADP2

2

3

4

5

6

7

8

PTD1

PTA3/ADP3

V_DD

PTA6/TPM2CH0

PTA7/TPM2CH1

PTB0/RxD/ADP4

PTB1/TxD/ADP5

PTB2/ADP6

V_SS

PTB7/EXTAL

PTB6/XTAL

PTB5/TPM1CH1

17

Figure 4. MC9S08FL16 Series 32-Pin LQFP Package

Table 3-1. Pin Availability by Package Pin-Count

Pin Number

<-- Lowest Priority --> Highest

32-SDIP

32-LQFP

Port Pin I/O

Alt 1

I/O

Alt 2

I/O

Alt 3

I/O

1

2

29

30

31

32

1

PTC5

PTC4

PTA5

PTD2

PTA4

PTD0

PTD1

I/O

O

I/O

I

3

IRQ

TCLK

TPM1CH2

BKGD

I

RESET

MS

I

4

5

O

6

2

I/O

7

3

8

4

V_DD

V_SS

I

9

5

10

11

12

6

PTB7

PTB6

PTB5

I/O

EXTAL

XTAL

I

7

O

8

TPM1CH1 I/O

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

6

Freescale Semiconductor

Pin Assignments

Table 3-1. Pin Availability by Package Pin-Count

Pin Number

<-- Lowest Priority --> Highest

32-SDIP

32-LQFP

Port Pin I/O

Alt 1

I/O

Alt 2

I/O

Alt 3

I/O

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

9

PTD3

PTB4

PTC3

PTC2

PTC1

PTC0

PTB3

PTD4

PTB2

PTB1

PTB0

PTA7

PTA6

PTA3

PTA2

PTA1

PTD5

PTA0

PTC7

PTC6

I/O

TPM1CH3 I/O

TPM1CH0 I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

ADP11

ADP10

ADP9

ADP8

ADP7

I

ACMP–

ACMP+

I

I/O

I

ADP6

TxD

O

I

ADP5

ADP4

I

RxD

TPM2CH1 I/O

TPM2CH0 I/O

I

ADP3

ADP2

ADP1

I

I/O

I

ADP0

NOTE

When an alternative function is first enabled, it is possible to get a spurious

edge to the module. User software should clear out any associated flags

before interrupts are enabled. Table 3-1 illustrates the priority if multiple

modules are enabled. The highest priority module will have control over the

pin. Selecting a higher priority pin function with a lower priority function

already enabled can cause spurious edges to the lower priority module.

Disable all modules that share a pin before enabling another module.

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

Freescale Semiconductor

7

Memory Map

4

Memory Map

Figure 5 shows the memory map for the MC9S08FL16 series. On-chip memory in the MC9S08FL16

series of MCUs consist of RAM, flash program memory for nonvolatile data storage, plus I/O and

control/status registers. The registers are divided into two groups:

•

Direct-page registers (0x0000 through 0x003F)

High-page registers (0x1800 through 0x187F)

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

8

Freescale Semiconductor

Memory Map

$0000

DIRECT PAGE REGISTERS

RAM 768 BYTES

DIRECT PAGE REGISTERS

RAM 1024 BYTES

$003F

$0040

$003F

$0040

$033F

$0340

$043F

$0440

UNIMPLEMENTED

$17FF

$1800

$17FF

$1800

HIGH PAGE REGISTERS

$187F

$1880

$187F

$1880

UNIMPLEMENTED

$BFFF

$C000

FLASH

16384 BYTES

$DFFF

$E000

FLASH

8192 BYTES

$FFFF

MC9S08FL8

MC9S08FL16

Figure 5. MC9S08FL16 Series Memory Map

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

Freescale Semiconductor

9

Electrical Characteristics

5

Electrical Characteristics

5.1

Introduction

This section contains electrical and timing specifications for the MC9S08FL16 series of microcontrollers available at the time

of publication.

5.2

Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better

understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:

Table 2. Parameter Classifications

Those parameters are guaranteed during production testing on each individual device.

P

C

Those parameters are achieved by the design characterization by measuring a statistically relevant

sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical devices

under typical conditions unless otherwise noted. All values shown in the typical column are within this

category.

T

Those parameters are derived mainly from simulations.

D

NOTE

The classification is shown in the column labeled “C” in the parameter

tables where appropriate.

5.3

Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the

limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating

conditions, refer to the remaining tables in this section.

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised

that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this

high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for

instance, either V or V ) or the programmable pullup resistor associated with the pin is enabled.

SS

DD

Table 3. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Supply voltage

V_DD

I_DD

V_In

–0.3 to 5.5

120

V

mA

V

Maximum current into V_DD

Digital input voltage

–0.3 to V_DD+ 0.3

Instantaneous maximum current

I_D

±25

mA

Single pin limit (applies to all port pins)^{1, 2, 3}

Storage temperature range

T_stg

–55 to 150

°C

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

10

Freescale Semiconductor

Electrical Characteristics

Input must be current limited to the value specified. To determine the value of the required

1

current-limiting resistor, calculate resistance values for positive (V_DD) and negative (V_SS) clamp

voltages, then use the larger of the two resistance values.

2

3

All functional non-supply pins, except for PTA5 are internally clamped to V_SSand V_DD

.

Power supply must maintain regulation within operating V_DDrange during instantaneous and

operating maximum current conditions. If positive injection current (V_In> V_DD) is greater than

I_DD, the injection current may flow out of V_DDand could result in external power supply going

out of regulation. Ensure external V_DDload will shunt current greater than maximum injection

current. This will be the greatest risk when the MCU is not consuming power. Examples are: if

no system clock is present, or if the clock rate is very low (which would reduce overall power

consumption).

5.4

Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power

dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and

it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine

I/O

the difference between actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of

SS

DD

unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very small.

SS

DD

Table 4. Thermal Characteristics

Symbol

Rating

Value

Unit

Operating temperature range

(packaged)

T_Lto T_H

0 to 85

T_A

°C

Maximum junction temperature

T_JM

TBD

Thermal resistance

Single-layer board

32-pin SDIP

32-pin LQFP

TBD

66

θ_JA

°C/W

Thermal resistance

Four-layer board

32-pin LQFP

TBD

47

θ_JA

The average chip-junction temperature (T ) in °C can be obtained from:

J

T = T + (P × θ )

JA

Eqn. 1

J

A

D

where:

T = Ambient temperature, °C

A

θ

= Package thermal resistance, junction-to-ambient, °C/W

JA

P = P + P

D

int

I/O

P

= I × V , Watts — chip internal power

= Power dissipation on input and output pins — user determined

int

I/O

DD DD

For most applications, P << P and can be neglected. An approximate relationship between P and T (if P is neglected)

I/O

int

D

J

I/O

is:

P = K ÷ (T + 273°C)

Eqn. 2

D

J

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

Freescale Semiconductor

11

Electrical Characteristics

Solving Equation 1 and Equation 2 for K gives:

2

K = P × (T + 273°C) + θ × (P )

Eqn. 3

D

A

JA

D

where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium)

D

for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively

A

D

J

for any value of T .

A

5.5

ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,

normal handling precautions must be taken to avoid exposure to static discharge. Qualification tests are performed to ensure

that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.

All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During

the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the

charge device model (CDM).

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete

DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot

temperature, unless instructed otherwise in the device specification.

Table 5. ESD and Latch-up Test Conditions

Model

Description

Series resistance

Symbol

Value

Unit

R1

1500

Ω

pF

—

Human

Body

Storage capacitance

C

100

3

Number of pulses per pin

—

Series resistance

R1

0

Ω

pF

—

V

Machine

Latch-up

Storage capacitance

C

200

3

Number of pulses per pin

Minimum input voltage limit

Maximum input voltage limit

—

–2.5

7.5

V

Table 6. ESD and Latch-Up Protection Characteristics

1

No.

1

Symbol

V_HBM

V_MM

Min

±2000

±200

±500

±100

Max

—

Unit

V

Rating

Human body model (HBM)

Machine model (MM)

2

—

V

V_CDM

I_LAT

3

Charge device model (CDM)

Latch-up current at T_A= 85°C

—

V

4

—

mA

1

Parameter is achieved by design characterization on a small sample size from typical devices

under typical conditions unless otherwise noted.

5.6

DC Characteristics

This section includes information about power supply requirements and I/O pin characteristics.

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

12

Freescale Semiconductor

Electrical Characteristics

Table 7. DC Characteristics

Num

C

Characteristic

Symbol

Condition

Min.

Typical¹

Max.

Unit

1

P Operating Voltage

4.5

5.5

V

All I/O pins,

low-drive strength

C

I_Load= –2 mA

_Load= –10 mA

—

V_DD– 1.5

—

V

Output high

voltage

2

V_OH

All I/O pins,

high-drive strength

P

I

V_DD– 1.5

Output high

current

D

C

P

D

P

C

Max total I_OHfor all ports I_OHT

All I/O pins,

—

100

mA

V

3

4

I_Load= 2 mA

I_Load= 10 mA

—

1.5

low-drive strength

Output low

voltage

V_OL

All I/O pins,

high-drive strength

—

1.5

Output low

current

5

6

7

8

Max total I_OLfor all ports

all digital inputs

I_OLT

V_IH

V_IL

100

mA

V

Input high

voltage

0.65 x V_DD

—

Input low

voltage

all digital inputs

0.35 x V_DD

—

Input

hysteresis

all digital inputs V_hys

—

0.06 x V_DD

mV

Input

P leakage

current

all input only pins

|I_In|

9

V_In= V_DDor V_SS

—

0.1

1

μA

(Per pin)

Hi-Z

(off-state)

leakage

current

all input/output

10

P

|I_OZ

|

V_In= V_DDor V_SS

μA

kΩ

(per pin)

all digital inputs, when

enabled (all I/O pins other R_PU,

Pullup,

11a P Pulldown

resistors

17.5

—

52.5

than

R_PD

—

PTA5/IRQ/TCLK/RESET

R_PU,

R_PD

Pullup,

11b C Pulldown

resistors

(PTA5/IRQ/TCLK/RESET)

—

(Note²)

Single pin limit

–0.2

–5

—

0.2

5

mA

DCinjection

12 C current ^{3, 4,}

I_IC

V_IN< V_SS, V_IN> V_DD

Total MCU limit, includes

sum of all stressed pins

5

13 C Input Capacitance, all pins

14 C RAM retention voltage

15 C POR re-arm voltage⁶

16 D POR re-arm time

C_In

—

0.6

1.4

—

8

pF

V

V_RAM

V_POR

t_POR

1.0

2.0

—

0.9

10

V

μs

V_DDfalling

V_DDrising

17 C Low-voltage detection threshold

18 C Low-voltage warning threshold

V_LVD

V_LVW

—

TBD

—

V

V_DDfalling

V_DDrising

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

Freescale Semiconductor

13

Electrical Characteristics

Table 7. DC Characteristics (continued)

Num

C

Characteristic

Symbol

Condition

Min.

Typical¹

Max.

Unit

Low-voltage inhibit reset/recover

hysteresis

20 C Bandgap Voltage Reference⁷

19

C

V_hys

V_BG

—

80

—

mV

V

TBD

1

2

Typical values are measured at 25°C. Characterized, not tested

The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when

measured externally on the pin.

3

4

All functional non-supply pins, except for PTA5 are internally clamped to V_SSand V_DD

.

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate

resistance values for positive and negative clamp voltages, then use the larger of the two values.

5

Power supply must maintain regulation within operating V_DDrange during instantaneous and operating maximum current

conditions. If the positive injection current (V_In> V_DD) is greater than I_DD, the injection current may flow out of V_DDand could

result in external power supply going out of regulation. Ensure that external V_DDload will shunt current greater than maximum

injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is

present, or if clock rate is very low (which would reduce overall power consumption).

6

7

Maximum is highest voltage that POR is guaranteed.

Factory trimmed at V_DD= 5.0 V, Temp = 25 °C

TBD

Figure 6. Pullup and Pulldown Typical Resistor Values (V = 5.0 V)

DD

TBD

Figure 7. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

14

Freescale Semiconductor

Electrical Characteristics

TBD

Figure 8. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)

TBD

Figure 9. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)

TBD

Figure 10. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

Freescale Semiconductor

15

Electrical Characteristics

5.7

Supply Current Characteristics

This section includes information about power supply current in various operating modes.

Table 8. Supply Current Characteristics

Parameter

V_DD

(V)

Bus

Freq

Temp

(°C)

Typical¹

Num

C

Symbol

Max

Unit

P

C

10 MHz

1 MHz

10 MHz

1 MHz

20 MHz

1 MHz

—

TBD

—

Run supply current

FEI mode, all modules on

1

R_IDD

5

mA

0 to 85°C

Run supply current

FEI mode, all modules off

2

3

R_IDD

mA

Wait mode supply current

FEI mode, all modules off

W_IDD

μA

4

5

6

7

8

Stop2 mode supply current

S2_IDD

S3_IDD

5

μA

nA

μA

0 to 85°C

25°C

Stop3 mode supply current

no clocks active

C

—

TBD

—

ADC adder to stop3

ICS adder to stop3

EREFSTEN = 1

25°C

LVD adder to stop3

25°C

1

Data in Typical column was characterized at 5.0 V, 25°C or is typical recommended value.

TBD

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

16

Freescale Semiconductor

Electrical Characteristics

Figure 11. Typical Run I for FBE and FEI, I vs. V

DD

(ADC off, All Other Modules Enabled)

5.8

External Oscillator (XOSC) Characteristics

Refer to Figure 12 and Figure 13 for crystal or resonator circuits.

Table 9. XOSC and ICS Specifications (Temperature Range = 0 to 85°C Ambient)

Num

C

Characteristic

Symbol

Min.

Typical¹Max. Unit

Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)

Low range (RANGE = 0)

High range (RANGE = 1), high gain (HGO = 1)

High range (RANGE = 1), low power (HGO = 0)

f_lo

f_hi

32

1

—

38.4

16

8

kHz

MHz

1

C

Load capacitors

Low range (RANGE=0), low power (HGO=0)

Other oscillator settings

See Note ²

See Note ³

C_1,C₂

2

3

D

Feedback resistor

Low range, low power (RANGE=0, HGO=0)²

Low range, high gain (RANGE=0, HGO=1)

High range (RANGE=1, HGO=X)

—

10

1

—

R_F

MΩ

kΩ

Series resistor —

Low range, low power (RANGE = 0, HGO = 0)²

—

100

0

—

Low range, high gain (RANGE = 0, HGO = 1)

High range, low power (RANGE = 1, HGO = 0)

High range, high gain (RANGE = 1, HGO = 1)

R_S

4

D

≥ 8 MHz

4 MHz

1 MHz

—

0

10

20

Crystal start-up time ⁴

Low range, low power

Low range, high gain

High range, low power

High range, high gain

t

—

600

400

5

—

CSTL

5

6

C

D

ms

t

CSTH

15

Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)

FEE mode

f_extal

0.03125

0

—

20

MHz

FBE or FBELP mode

1

2

3

4

Data in Typical column was characterized at 5.0 V, 25°C or is typical recommended value.

Load capacitors (C_1,C₂), feedback resistor (R_F) and series resistor (R_S) are incorporated internally when RANGE = HGO = 0.

See crystal or resonator manufacturer’s recommendation.

Proper PC board layout procedures must be followed to achieve specifications.

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

Freescale Semiconductor

17

Electrical Characteristics

XOSC

EXTAL

XTAL

R_S

R_F

Crystal or Resonator

C₁

C₂

Figure 12. Typical Crystal or Resonator Circuit

5.9

Internal Clock Source (ICS) Characteristics

Table 10. ICS Frequency Specifications (Temperature Range = 0 to 85°C Ambient)

Num

C

Characteristic

Symbol

Min. Typical¹Max.

Unit

Average internal reference frequency — factory trimmed

at V_DD= 3.6 V and temperature = 25°C

f_{int_ft}

1

P

—

32.768

—

kHz

Internal reference frequency — user trimmed

Internal reference start-up time

f_{int_ut}

t_IRST

f_{dco_u}

2

3

4

P

T

P

31.25

—

60

—

39.06

100

30

kHz

μs

DCO output frequency range — trimmed²

24

MHz

DCO output frequency²

Reference = 32768 Hz and DMX32 = 1

f_{dco_DMX32}

Δf_{dco_res_t}

Δf_{dco_t}

5

6

7

8

P

C

—

TBD

±0.1

±0.2

—

±0.2

±0.4

±2

MHz

%f_dco

Resolution of trimmed DCO output frequency at fixed voltage and

temperature (using FTRIM)

Resolution of trimmed DCO output frequency at fixed voltage and

temperature (not using FTRIM)

Total deviation of trimmed DCO output frequency over voltage

and temperature

+ 0.5

–1.0

Total deviation of trimmed DCO output frequency over fixed

voltage and temperature range of 0°C to 70 °C

Δf_{dco_t}

t_Acquire

C_Jitter

%f_dco

ms

9

C

—

±0.5

—

±1

1

FLL acquisition time³

10

Long term jitter of DCO output clock (averaged over 2-ms

interval)⁴

%f_dco

11

0.02

0.2

1

Data in Typical column was characterized at 5.0 V, 25°C or is typical recommended value.

The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.

2

3

This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing

from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,

this specification assumes it is already running.

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

18

Freescale Semiconductor

Electrical Characteristics

4

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_Bus

.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the FLL circuitry via V_DDand V_SSand variation in crystal oscillator frequency increase the C_Jitterpercentage for a

given interval.

1.00%

0.50%

0.00%

-60

-40

-20

0

20

40

60

80

100

120

-0.50%

-1.00%

-1.50%

-2.00%

TBD

Temperature

Figure 13. Deviation of DCO Output from Trimmed Frequency (20 MHz, 5.0 V)

5.10 AC Characteristics

This section describes timing characteristics for each peripheral system.

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

Freescale Semiconductor

19

Electrical Characteristics

5.10.1 Control Timing

Table 11. Control Timing

Num

C

D

Rating

Symbol

f_Bus

t_LPO

t_extrst

t_rstdrv

Min

Typical¹

Max

20

Unit

MHz

μs

Bus frequency (t_cyc= 1/f_Bus

)

1

2

3

4

dc

700

—

Internal low power oscillator period

1300

—

External reset pulse width²

Reset low drive

100

ns

34 x t_cyc

—

ns

BKGD/MS setup time after issuing background debug

force reset to enter user or BDM modes

t_MSSU

t_MSH

5

6

D

500

100

—

ns

BKGD/MS hold time after issuing background debug

force reset to enter user or BDM modes ³

μs

IRQ pulse width

Asynchronous path²

Synchronous path⁴

t_{ILIH, IHIL}

t

100

1.5 x t_cyc

—

ns

7

D

8

D

Keyboard interrupt pulse width

Asynchronous path²

t_{ILIH, IHIL}

t

100

1.5 x t_cyc

—

Synchronous path⁴

Port rise and fall time —

Low output drive (PTxDS = 0) (load = 50 pF)⁵

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

t

_Rise, t_Fall

ns

—

16

23

—

9

C

Port rise and fall time —

High output drive (PTxDS = 1) (load = 50 pF)⁵

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

t_Rise, t_Fall

—

5

9

—

1

2

3

Typical values are based on characterization data at V_DD= 5.0V, 25°C unless otherwise stated.

This is the shortest pulse that is guaranteed to be recognized as a reset pin request.

To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t_MSHafter V_DD

rises above V_LVD

.

4

5

This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.

Timing is shown with respect to 20% V_DDand 80% V_DDlevels. Temperature range 0°C to 85°C.

t_extrst

RESET PIN

Figure 14. Reset Timing

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

20

Freescale Semiconductor

Electrical Characteristics

t_IHIL

KBIPx

IRQ/KBIPx

t_ILIH

Figure 15. IRQ/KBIPx Timing

5.10.2 TPM Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the

optional external source to the timer counter. These synchronizers operate from the current bus rate clock.

Table 12. TPM Input Timing

No.

C

Function

Symbol

Min

Max

Unit

1

2

3

4

5

D

External clock frequency

External clock period

f_TCLK

t_TCLK

t_clkh

0

f_Bus/4

—

Hz

t_cyc

4

External clock high time

External clock low time

Input capture pulse width

1.5

—

t_clkl

—

t_ICPW

—

t_TCLK

t_clkh

TCLK

t_clkl

Figure 16. Timer External Clock

t_ICPW

TPMCHn

t_ICPW

Figure 17. Timer Input Capture Pulse

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

Freescale Semiconductor

21

Electrical Characteristics

5.11 ADC Characteristics

Table 13. 12-bit ADC Operating Conditions

Characteristic

Conditions

Symb

Min

Typical¹

Max

Unit

Comment

Supply voltage

Absolute

Delta to V_DD(V_DD-V_DDAD

V_DDAD

ΔV_DDAD

ΔV_SSAD

4.5

—

0

5.5

V

—

2

)

–100

+100

mV

2

Ground voltage

Delta to V_SS(V_SS-V_SSAD

)

0

Ref Voltage

High

—

V_REFH

V_ADIN

C_ADIN

1.8

V_REFL

—

V_DDAD

—

V_DDAD

V_REFH

5.5

V

—

Input Voltage

—

Input

Capacitance

4.5

pF

Input

Resistance

—

R_ADIN

—

5

7

kΩ

—

Analog Source

Resistance

8 bit mode (all valid f_ADCK

)

R_AS

—

10

External to MCU

ADC

Conversion

Clock Freq.

High Speed (ADLPC=0)

Low Power (ADLPC=1)

0.4

—

8.0

4.0

f_ADCK

MHz

—

1

2

Typical values assume V_DDAD= 5.0 V, Temp = 25 °C, f_ADCK=1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

DC potential difference.

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

22

Freescale Semiconductor

Electrical Characteristics

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

Z_ADIN

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

Z_AS

leakage

due to

input

ADC SAR

ENGINE

R_AS

R_ADIN

protection

+

V_ADIN

–

C_AS

V_AS

+

–

R_ADIN

INPUT PIN

C_ADIN

Figure 18. ADC Input Impedance Equivalency Diagram

Table 14. 12-bit ADC Characteristics (V

= V

, V

= V

)

SSAD

REFH

Min.

DDAD REFL

C

Characteristic

Conditions

Symbol

Typical¹

Max.

Unit

Comment

Supply Current

ADLPC=1

ADLSMP=1

ADCO=1

T

—

I_DDAD

—

120

—

μA

—

Supply Current

ADLPC=1

ADLSMP=0

ADCO=1

T

P

I_DDAD

202

288

—

1

μA

Supply Current

ADLPC=0

ADLSMP=1

ADCO=1

I_DDAD

Supply Current

ADLPC=0

ADLSMP=0

ADCO=1

I_DDAD

0.532

mA

—

P

C

ADC

Asynchronous

Clock Source

High Speed (ADLPC=0)

Low Power (ADLPC=1)

2

3.3

2

5

t_ADACK=

1/f_ADACK

f_ADACK

MHz

1.25

3.3

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

Freescale Semiconductor

23

Electrical Characteristics

Table 14. 12-bit ADC Characteristics (V

= V

, V

= V

) (continued)

SSAD

REFH

DDAD REFL

C

Characteristic

Conditions

Short Sample

Symbol

Min.

Typical¹

Max.

Unit

Comment

Conversion

Time(Including (ADLSMP=0)

sample time)

See ADC

chapter in the

QE8

Reference

Manual for

conversion

time

P

—

20

—

ADCK

cycles

t_ADC

Long Sample

C

P

C

40

3.5

(ADLSMP=1)

Short Sample

(ADLSMP=0)

Sample Time

ADCK

cycles

variances

t_ADS

Long Sample

(ADLSMP=1)

23.5

Total

Unadjusted

Error

Includes

quantization

T

8 bit mode

E_TUE

—

±0.5

—

LSB²

Differential

Non-Linearity

T

D

8 bit mode³

8 bit mode

DNL

INL

E_ZS

E_FS

E_Q

—

±0.3

±0.5

±0.1

±0.5

±1.0

—

LSB²

—

Integral

Non-Linearity

Zero-Scale

Error

V_ADIN

V_SSAD

=

Full-Scale

Error

V_ADIN=

V_DDAD

Quantization

Error

—

Input Leakage

Error

Padleakage³

* R_AS

E_IL

—

0°C to 25°C

—

1.646

1.769

—

Temp Sensor

Slope

D

m

mV/°C

25°C to 85°C

Temp Sensor

Voltage

25°C

V_TEMP25

—

701.2

—

mV

1

Typical values assume V_DDAD= 5.0 V, Temp = 25 °C, f_ADCK= 1.0 MHz unless otherwise stated. Typical values are for reference

only and are not tested in production.

2

3

1 LSB = (V_REFH– V_REFL)/2^N

Based on input pad leakage current. Refer to pad electricals.

5.12 Flash Specifications

This section provides details about program/erase times and program-erase endurance for the flash memory.

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

24

Freescale Semiconductor

Electrical Characteristics

Program and erase operations do not require any special power sources other than the normal V supply. For more detailed

DD

information about program/erase operations, see the Memory section.

Table 15. Flash Characteristics

C

Characteristic

Symbol

Min

Typical

Max

Unit

Supply voltage for program/erase

0°C to 85°C

D

—

V_prog/erase

V_Read

f_FCLK

4.5

150

5

5.5

V

D

P

Supply voltage for read operation

Internal FCLK frequency¹

Internal FCLK period (1/FCLK)

Byte program time (random location)²

Byte program time (burst mode)²

Page erase time²

Mass erase time²

Byte program current³

Page erase current³

—

V

—

200

6.67

kHz

μs

t_Fcyc

—

t_prog

9

t_Fcyc

mA

t_Burst

4

4000

20,000

4

t_Page

t_Mass

RI_DDBP

RI_DDPE

—

6

Program/erase endurance⁴

T_Lto T_H= 0°C to + 85°C

T = 25°C

C

—

10,000

100

—

cycles

years

Data retention⁵

t_{D_ret}

10

1

2

The frequency of this clock is controlled by a software setting.

These values are hardware state machine controlled. User code does not need to count cycles. This information supplied

for calculating approximate time to program and erase.

3

4

The program and erase currents are additional to the standard run I_DD. These values are measured at room temperatures

with V_DD= 5.0 V, bus frequency = 4.0 MHz.

Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how

Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile

Memory.

5

Typical data retention values are based on intrinsic capability of the technology measured at high temperature and

de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,

please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.

5.13 EMC Performance

Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board

design and layout, circuit topology choices, location and characteristics of external components as well as MCU software

operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such

as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC

performance.

5.13.1 Conducted Transient Susceptibility

Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The

measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC

test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient

susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

Freescale Semiconductor

25

Ordering Information

61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is

greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 16.

Table 16. Conducted Susceptibility, EFT/B

Amplitude¹

f_OSC/f_BUS

Parameter

Symbol

Conditions

Result

Unit

(Min)

A

B

C

D

2.3

V_DD= 5V

T_A= +25^oC

package type

32 LQFP

8 MHz

crystal

8 MHz bus

4.0

Conducted susceptibility, electrical

fast transient/burst (EFT/B)

V_{CS_EFT}

kV

>4.0

1

Data based on qualification test results. Not tested in production.

The susceptibility performance classification is described in Table 17.

Table 17. Susceptibility Performance Classification

Performance Criteria

Result

A

No failure

The MCU performs as designed during and after exposure.

Self-recovering The MCU does not perform as designed during exposure. The MCU returns

B

C

D

failure

automatically to normal operation after exposure is removed.

The MCU does not perform as designed during exposure. The MCU does not return to

normal operation until exposure is removed and the RESET pin is asserted.

Soft failure

The MCU does not perform as designed during exposure. The MCU does not return to

normal operation until exposure is removed and the power to the MCU is cycled.

Hard failure

Damage

The MCU does not perform as designed during and after exposure. The MCU cannot

be returned to proper operation due to physical damage or other permanent

performance degradation.

E

6

Ordering Information

This section contains ordering information for MC9S08FL16 series devices. See below for an example of the device numbering

system.

Table 18. Device Numbering System

Memory

Device Number¹

Available Packages²

FLASH

RAM

32 SDIP

32 LQFP

MC9S08FL16

MC9S08FL8

16K

1024

32 SDIP

32 LQFP

8K

768

1

2

See the reference manual, MC9S08FL16 Series Reference Manual, for a complete

description of modules included on each device.

See Table 19 for package information.

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

26

Freescale Semiconductor

Package Information

Example of the device numbering system:

MC S08

FL 16

C

XX

9

Status

(MC = Fully Qualified)

Package designator (see Table 19)

Temperature range

(C = 0°C to 85°C)

Memory

(9 = Flash-based)

Core

Approximate flash size in Kbytes

Family

7

Package Information

Table 19. Package Descriptions

Pin Count

Package Type

Abbreviation

Designator

Case No.

Document No.

32

Low Quad Flat Package

LQFP

SDIP

LC

873A-03

1376-02

98ASH70029A

98ASA99330D

Shrink Dual In-line Package

TBD

7.1

Mechanical Drawings

The following pages are mechanical drawings for the packages described in Table 19.

MC9S08FL16 Series Data Sheet, Rev. 0 Draft B

Freescale Semiconductor

27

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Document Number: MC9S08FL16

Rev. 0 Draft B

10/2008


型号：	MC9S08FL16CBM
厂家：	Freescale
描述：	MC9S08FL16CBM 外围集成电路光电二极管微控制器 PC 时钟
文件：	总35页 (文件大小：1175K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC9S08FL16CBM [FREESCALE]

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