MC9S08FL8_技术文档

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MC9S08FL16

Rev. 2, 7/2009

MC9S08FL16

MC9S08FL16 Series

Covers: MC9S08FL16 and

MC9S08FL8

32-Pin SDIP

1376-02

32-Pin LQFP

873A-03

• Illegal address detection with reset

• Flash block protection

Features:

8-Bit S08 Central Processor Unit (CPU)

Development Support

• Up to 20 MHz CPU at 4.5 V to 5.5 V across

• Single-wire background debug interface

temperature range of –40 °C to 85 °C

• Breakpoint capability to allow single breakpoint

setting during in-circuit debugging (plus two more

breakpoints).

• HC08 instruction set with added BGND instruction

• Support for up to 32 interrupt/reset sources

• On-chip in-circuit emulator (ICE) debug module

containing two comparators and nine trigger

modes.

On-Chip Memory

• Up to 16 KB flash read/program/erase over full

operating voltage and temperature

Peripherals

• Up to 1024-byte random-access memory (RAM)

• Security circuitry to prevent unauthorized access

to RAM and flash contents

• IPC — Interrupt priority controller to provide

hardware based nested interrupt mechanism

• ADC — 12-channel, 8-bit resolution; 2.5 μs

conversion time; automatic compare function;

1.7 mV/°C temperature sensor; internal bandgap

reference channel; operation in stop; optional

hardware trigger; fully functional from 4.5 V to

5.5 V

Power-Saving Modes

• Two low power stop modes; reduced power wait

mode

• Allows clocks to remain enabled to specific

peripherals in stop3 mode

• TPM — One 4-channel and one 2-channel

timer/pulse-width modulators (TPM) modules;

selectable input capture, output compare, or

buffered edge- or center-aligned PWM on each

channel

Clock Source Options

• Oscillator (XOSC) — Loop-control Pierce

oscillator; crystal or ceramic resonator range of

31.25 kHz to 39.0625 kHz or 1 MHz to 16 MHz

• Internal Clock Source (ICS) — Internal clock

source module containing a

• MTIM16 — One 16-bit modulo timer with optional

prescaler

frequency-locked-loop (FLL) controlled by internal

or external reference; precision trimming of

internal reference allows 0.2% resolution and 2%

deviation over temperature and voltage; supports

bus frequencies up to 10 MHz

• SCI — One serial communications interface

module with optional 13-bit break; LIN extensions

Input/Output

• 30 GPIOs including 1 output-only pin and 1

input-only pin

System Protection

• Watchdog computer operating properly (COP)

reset with option to run from dedicated 1 kHz

internal clock source or bus clock

• Low-voltage detectionwith reset or interrupt;

selectable trip points

Package Options

• 32-pin SDIP

• 32-pin LQFP

• Illegal opcode detection with reset

This document contains information on a product under development. Freescale reserves the

right to change or discontinue this product without notice.

Table of Contents

1

2

3

4

5

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

System Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . 4

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9

5.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 9

5.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . 10

5.5 ESD Protection and Latch-Up Immunity . . . . . . 11

5.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12

5.7 Supply Current Characteristics . . . . . . . . . . . . . 17

5.8 External Oscillator (XOSC) and ICS

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.9 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 21

5.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . 22

5.9.2 TPM Module Timing . . . . . . . . . . . . . . . . 23

5.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . 24

5.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . 26

5.12 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . 27

5.12.1Radiated Emissions. . . . . . . . . . . . . . . . . 27

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . 27

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . 28

6

7

Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web will

be the most current. Your printed copy may be an earlier revision. To verify you have the latest information

available, refer to:

http://freescale.com/

The following revision history table summarizes changes contained in this document.

Rev

Date

Description of Changes

1

2

March 18, 2009

July 20, 2009

Initial public release.

Updated Section 5.12, “EMC Performance.” and corrected Figure 1 and Table 1.

Corrected default trim value to 31.25 kHz.

Related Documentation

Find the most current versions of all documents at: http://www.freescale.com

Reference Manual (MC9S08FL16RM)

Contains extensive product information including modes of operation, memory,

resets and interrupts, register definition, port pins, CPU, and all module

information.

MC9S08FL16 Series Data Sheet, Rev. 2

2

Freescale Semiconductor

MCU Block Diagram

1

MCU Block Diagram

The block diagram, Figure 1, shows the structure of MC9S08FL16 series MCU.

PTA0/ADP0

16-BIT MODULO TIMER

TCLK

HCS08 CORE

PTA1/ADP1

(MTIM16)

PTA2/ADP2

BDC

CPU

PTA3/ADP3

2-CH TIMER/PWM

TPM2CH[1:0]

MODULE (TPM2)

PTA4/BKGD/MS

PTA5/IRQ/TCLK/RESET

PTA6/TPM2CH0

PTA7/TPM2CH1

HCS08 SYSTEM CONTROL

RESETS AND INTERRUPTS

MODES OF OPERATION

POWER MANAGEMENT

RESET

IRQ

COP

IRQ

LVD

INTERRUPT PRIORITY

CONTROLLER (IPC)

PTB0/RxD/ADP4

PTB1/TxD/ADP5

PTB2/ADP6

ON-CHIP ICE AND

DEBUG MODUE (DBG)

TxD

RxD

SERIAL COMMUNICATIONS

INTERFACE (SCI)

PTB3/ADP7

USER FLASH

PTB4/TPM1CH0

PTB5/TPM1CH1

PTB6/XTAL

MC9S08FL16 — 16,384 BYTES

MC9S08FL8 — 8,192 BYTES

4-CH TIMER/PWM

TPM1CH[3:0]

MODULE (TPM1)

USER RAM

MC9S08FL16 — 1,024 BYTES

MC9S08FL8 — 768 BYTES

PTB7/EXTAL

PTC0/ADP8

PTC1/ADP9

PTC2/ADP10

PTC3/ADP11

PTC4

20 MHz INTERNAL CLOCK

SOURCE (ICS)

EXTAL

XTAL

EXTERNAL OSCILLATOR

SOURCE (XOSC)

V

PTC5

DD

SS

VOLTAGE REGULATOR

PTC6

PTC7

V

REFH

REFL

DDA

12-CH 8-BIT

ANALOG-TO-DIGITAL

CONVERTER (ADC)

ADP[11:0]

SSA

PTD0

PTD1

PTD2/TPM1CH2

PTD3/TPM1CH3

PTD4

NOTE

1. PTA4 is output only when used as port pin.

2. PTA5 is input only when used as port pin.

PTD5

Figure 1. MC9S08FL16 Series Block Diagram

MC9S08FL16 Series Data Sheet, Rev. 2

Freescale Semiconductor

3

System Clock Distribution

2

System Clock Distribution

MC9S08FL16 series use ICS module as clock sources. The ICS module can use internal or external clock

source as reference to provide up to 20 MHz CPU clock. The output of ICS module includes,

•

OSCOUT — XOSC output provides external reference clock to ADC.

ICSFFCLK — ICS fixed frequency clock reference (around 32.768 kHz) provides double of the

fixed lock signal to TPMs and MTIM16.

•

ICSOUT — ICS CPU clock provides double of the bus clock which is basic clock reference of

peripherals.

•

ICSLCLK — Alternate BDC clock provides debug signal to BDC module.

The TCLK pin is an extra external clock source. When TCLK is enabled, it can provide alternate clock

source to TPMs and MTIM16. The on-chip 1 kHz clock provides clock source of COP module.

TCLK

1 kHz

COP

TPM1

TPM2

MTIM16

ADC

OSCOUT

ICSFFCLK

ICSOUT

FIXED CLOCK (XCLK)

÷2

ICS

BUS CLOCK

÷2

ICSLCLK

XOSC

IPC

CPU

SCI

BDC

FLASH

RAM

EXTAL XTAL

Figure 2. System Clock Distribution Diagram

MC9S08FL16 Series Data Sheet, Rev. 2

4

Freescale Semiconductor

Pin Assignments

3

Pin Assignments

This section shows the pin assignments for the MC9S08FL16 series devices.

PTC6

PTC5

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

PTC7

PTC4

PTA5/IRQ/TCLK/RESET

PTD2/TPM1CH2

PTA4/BKGD/MS

PTD0

2

PTA0/ADP0

PTD5

3

4

PTA1/ADP1

PTA2/ADP2

PTA3/ADP3

PTA6/TPM2CH0

PTA7/TPM2CH1

PTB0/RxD/ADP4

PTB1/TxD/ADP5

PTB2/ADP6

PTD4

5

6

PTD1

7

V_DD

8

V_SS

9

PTB7/EXTAL

10

11

12

13

14

15

16

PTB6/XTAL

PTB5/TPM2CH1

PTD3/TPM1CH3

PTB4/TPM1CH0

PTC3/ADP11

PTB3/ADP7

PTC0/ADP8

PTC1/ADP9

PTC2/ADP10

Figure 3. MC9S08FL16 Series 32-Pin SDIP Package

MC9S08FL16 Series Data Sheet, Rev. 2

Freescale Semiconductor

5

Pin Assignments

PTA4/BKGD/MS

PTD0

PTA1/ADP1

1

24

23

22

21

20

19

18

PTA2/ADP2

2

3

4

5

6

7

8

PTD1

PTA3/ADP3

V_DD

PTA6/TPM2CH0

PTA7/TPM2CH1

PTB0/RxD/ADP4

PTB1/TxD/ADP5

PTB2/ADP6

V_SS

PTB7/EXTAL

PTB6/XTAL

PTB5/TPM1CH1

17

Figure 4. MC9S08FL16 Series 32-Pin LQFP Package

Table 1. Pin Availability by Package Pin-Count

Pin Number

<-- Lowest Priority --> Highest

32-SDIP

32-LQFP

Port Pin I/O

Alt 1

I/O

Alt 2

I/O

Alt 3

I/O

1

2

29

30

31

32

1

PTC5

PTC4

PTA5

PTD2

PTA4

PTD0

PTD1

I/O

I

3

IRQ

I

TCLK

I

RESET

MS

I

4

I/O

O

TPM1CH2 I/O

BKGD

5

I

6

2

I/O

7

3

8

4

V_DD

V_SS

I

9

5

10

11

12

13

14

15

6

PTB7

PTB6

PTB5

PTD3

PTB4

PTC3

I/O

EXTAL

XTAL

I

7

O

8

TPM1CH1 I/O

TPM1CH3 I/O

TPM1CH0 I/O

9

10

11

ADP11

I

MC9S08FL16 Series Data Sheet, Rev. 2

6

Freescale Semiconductor

Pin Assignments

Table 1. Pin Availability by Package Pin-Count (continued)

Pin Number <-- Lowest Priority --> Highest

32-SDIP

32-LQFP

Port Pin I/O

Alt 1

I/O

Alt 2

I/O

Alt 3

I/O

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

PTC2

PTC1

PTC0

PTB3

PTD4

PTB2

PTB1

PTB0

PTA7

PTA6

PTA3

PTA2

PTA1

PTD5

PTA0

PTC7

PTC6

I/O

ADP10

ADP9

ADP8

ADP7

I

ADP6

TxD

I

I/O

I

ADP5

ADP4

I

RxD

TPM2CH1 I/O

TPM2CH0 I/O

ADP3

ADP2

ADP1

I

ADP0

I

NOTE

When an alternative function is first enabled, it is possible to get a spurious

edge to the module. User software must clear out any associated flags before

interrupts are enabled. Table 1 illustrates the priority if multiple modules are

enabled. The highest priority module will have control over the pin.

Selecting a higher priority pin function with a lower priority function

already enabled can cause spurious edges to the lower priority module.

Disable all modules that share a pin before enabling another module.

MC9S08FL16 Series Data Sheet, Rev. 2

Freescale Semiconductor

7

Memory Map

4

Memory Map

Figure 5 shows the memory map for the MC9S08FL16 series. On-chip memory in the MC9S08FL16

series of MCUs consists of RAM, flash program memory for nonvolatile data storage, plus I/O and

control/status registers. The registers are divided into two groups:

•

Direct-page registers (0x0000 through 0x003F)

High-page registers (0x1800 through 0x187F)

$0000

DIRECT PAGE REGISTERS

RAM 768 BYTES

DIRECT PAGE REGISTERS

RAM 1024 BYTES

$003F

$0040

$003F

$0040

$033F

$0340

$043F

$0440

UNIMPLEMENTED

$17FF

$1800

$17FF

$1800

HIGH PAGE REGISTERS

$187F

$1880

$187F

$1880

UNIMPLEMENTED

$BFFF

$C000

FLASH

16384 BYTES

$DFFF

$E000

FLASH

8192 BYTES

$FFFF

MC9S08FL8

MC9S08FL16

Figure 5. MC9S08FL16 Series Memory Map

MC9S08FL16 Series Data Sheet, Rev. 2

8

Freescale Semiconductor

Electrical Characteristics

5

Electrical Characteristics

5.1

Introduction

This section contains electrical and timing specifications for the MC9S08FL16 series of microcontrollers

available at the time of publication.

5.2

Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the

customer a better understanding, the following classification is used and the parameters are tagged

accordingly in the tables where appropriate:

Table 2. Parameter Classifications

Those parameters are guaranteed during production testing on each individual device.

P

C

Those parameters are achieved by the design characterization by measuring a statistically relevant

sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical devices

under typical conditions unless otherwise noted. All values shown in the typical column are within this

category.

T

Those parameters are derived mainly from simulations.

D

NOTE

The classification is shown in the column labeled “C” in the parameter

tables where appropriate.

5.3

Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not

guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent

damage to the device. For functional operating conditions, refer to the remaining tables in this section.

This device contains circuitry protecting against damage due to high static voltage or electrical fields;

however, it is advised that normal precautions be taken to avoid application of any voltages higher than

maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused

inputs are tied to an appropriate logic voltage level (for instance, either V or V ) or the programmable

SS

DD

pullup resistor associated with the pin is enabled.

MC9S08FL16 Series Data Sheet, Rev. 2

Freescale Semiconductor

9

Electrical Characteristics

Table 3. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Supply voltage

V_DD

I_DD

V_In

–0.3 to 5.8

120

V

mA

V

Maximum current into V_DD

Digital input voltage

–0.3 to V_DD+ 0.3

Instantaneous maximum current

I_D

±25

mA

Single pin limit (applies to all port pins)^{1, 2, 3}

Storage temperature range

T_stg

–55 to 150

°C

1

Input must be current limited to the value specified. To determine the value of the required

current-limiting resistor, calculate resistance values for positive (V_DD) and negative (V_SS) clamp

voltages, then use the larger of the two resistance values.

2

3

All functional non-supply pins, except for PTA5 are internally clamped to V_SSand V_DD

.

Power supply must maintain regulation within operating V_DDrange during instantaneous and

operating maximum current conditions. If positive injection current (V_In> V_DD) is greater than

I_DD, the injection current may flow out of V_DDand could result in external power supply going

out of regulation. Ensure external V_DDload will shunt current greater than maximum injection

current. This will be the greatest risk when the MCU is not consuming power. Examples are: if

no system clock is present, or if the clock rate is very low (which would reduce overall power

consumption).

5.4

Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package

thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in

on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the

MCU design. To take P into account in power calculations, determine the difference between actual pin

I/O

voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of unusually high

SS

DD

pin current (heavy loads), the difference between pin voltage and V or V will be very small.

SS

Table 4. Thermal Characteristics

DD

Rating

Symbol

Value

Unit

Operating temperature range

(packaged)

T_Lto T_H

–40 to 85

T_A

°C

Thermal resistance

Single-layer board

32-pin SDIP

32-pin LQFP

60

85

θ_JA

°C/W

Thermal resistance

Four-layer board

32-pin SDIP

32-pin LQFP

35

56

θ_JA

The average chip-junction temperature (T ) in °C can be obtained from:

J

MC9S08FL16 Series Data Sheet, Rev. 2

10

Freescale Semiconductor

Electrical Characteristics

T = T + (P × θ )

JA

Eqn. 1

J

A

D

where:

T = Ambient temperature, °C

A

θ

= Package thermal resistance, junction-to-ambient, °C/W

JA

P = P + P

D

int

I/O

P = I × V , Watts — chip internal power

int

DD

P

= Power dissipation on input and output pins — user determined

I/O

For most applications, P far much smaller than P and can be neglected. An approximate relationship

I/O

int

between P and T (if P is neglected) is:

D

J

I/O

P = K ÷ (T + 273 °C)

Eqn. 2

D

J

Solving Equation 1 and Equation 2 for K gives:

2

K = P × (T + 273 °C) + θ × (P )

Eqn. 3

D

A

JA

D

where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring

P (at equilibrium) for an known T . Using this value of K, the values of P and T can be obtained by

D

A

D

J

solving Equation 1 and Equation 2 iteratively for any value of T .

A

5.5

ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early

CMOS circuits, normal handling precautions must be taken to avoid exposure to static discharge.

Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels

of static without suffering any permanent damage.

During the device qualification, ESD stresses were performed for the human body model (HBM) and the

charge device model (CDM).

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification. Complete DC parametric and functional testing is performed per the applicable device

specification at room temperature followed by hot temperature, unless instructed otherwise in the device

specification.

Table 5. ESD and Latch-Up Test Conditions

Model

Description

Series resistance

Symbol

Value

1500

100

3

Unit

Ω

R1

C

Human

body

Storage capacitance

pF

—

V

Number of pulses per pin

Minimum input voltage limit

Maximum input voltage limit

—

–2.5

7.5

Latch-up

V

MC9S08FL16 Series Data Sheet, Rev. 2

Freescale Semiconductor

11

Electrical Characteristics

Table 6. ESD and Latch-Up Protection Characteristics

1

No.

1

Symbol

V_HBM

V_CDM

I_LAT

Min

±2000

±500

±100

Max

—

Unit

V

Rating

Human body model (HBM)

Charge device model (CDM)

Latch-up current at T_A= 85 °C

2

—

V

3

—

mA

1

Parameter is achieved by design characterization on a small sample size from typical devices

under typical conditions unless otherwise noted.

5.6

DC Characteristics

This section includes information about power supply requirements and I/O pin characteristics.

Table 7. DC Characteristics

Num C

Characteristic

Symbol

Condition

Min.

Typical¹

Max.

Unit

1

P Operating voltage

—

4.5

—

5.5

V

All I/O pins,

low-drive strength

C

P

D

C

P

D

P

C

I_Load= –2 mA

V_DD– 1.5

—

Output high

voltage

2

V_OH

V

mA

V

All I/O pins,

high-drive strength

I_Load= –10 mA

V_DD– 1.5

Output high

current

Max total I_OHfor all ports I_OHT

All I/O pins,

—

100

3

4

I_Load= 2 mA

—

1.5

low-drive strength

Output low

voltage

V_OL

All I/O pins,

high-drive strength

I_Load= 10 mA

—

1.5

Output low

current

5

6

7

8

Max total I_OLfor all ports

All digital inputs

I_OLT

V_IH

V_IL

—

100

mA

V

Input high

voltage

0.65 × V_DD

—

Input low

voltage

All digital inputs

0.35 × V_DD

—

V

Input

hysteresis

All digital inputs V_hys

0.06 × V_DD

mV

Input

P leakage

current

All input only pins

|I_In|

9

V_In= V_DDor V_SS

—

0.1

1

μA

(per pin)

Hi-Z

(off-state)

leakage

All input/output

10

P

|I_OZ

|

V_In= V_DDor V_SS

(per pin)

current

All digital inputs, when

enabled (all I/O pins other R_PU,

Pullup,

11a C pulldown

resistors

—

17.5

36.5

52.5

kΩ

than

R_PD

PTA5/IRQ/TCLK/RESET)

Pullup,

11b C pulldown

resistors

R_PU,

R_PD

(PTA5/IRQ/TCLK/RESET)

(Note²)

MC9S08FL16 Series Data Sheet, Rev. 2

12

Freescale Semiconductor

Electrical Characteristics

Table 7. DC Characteristics (continued)

Num C

Characteristic

Single pin limit

Symbol

Condition

Min.

Typical¹

Max.

Unit

–0.2

—

0.2

mA

DCinjection

12 C current ^{3, 4,}

I_IC

V_IN< V_SS, V_IN> V_DD

Total MCU limit, includes

sum of all stressed pins

5

–5

—

5

mA

13 C Input capacitance, all pins

14 C RAM retention voltage

15 C POR re-arm voltage⁶

16 D POR re-arm time

C_In

—

0.6

1.4

—

8

pF

V

V_RAM

V_POR

t_POR

1.0

2.0

—

0.9

10

V

μs

Low-voltage detection threshold —

high range

P

C

P

V_LVD1

V_LVD0

V_LVW3

V_LVW2

V_LVW1

V_LVW0

—

V

V_DDfalling

V_DDrising

3.9

4.0

4.1

4.2

17

Low-voltage detection threshold —

low range

V_DDfalling

V_DDrising

2.48

2.54

2.56

2.62

2.64

2.70

Low-voltage warning threshold —

high range 1

V_DDfalling

V_DDrising

4.5

4.6

4.7

4.8

18

Low-voltage warning threshold —

high range 0

V_DDfalling

V_DDrising

4.2

4.3

4.4

4.5

Low-voltage warning threshold

low range 1

V_DDfalling

V_DDrising

2.84

2.90

2.92

2.98

3.00

3.06

19

20

Low-voltage warning threshold —

low range 0

C

V_DDfalling

V_DDrising

2.66

2.72

2.74

2.80

2.82

2.88

Low-voltage inhibit reset/recover

hysteresis

21 C Bandgap voltage reference⁷

V_hys

V_BG

—

100

—

mV

V

1.21

1

2

Typical values are measured at 25 °C. Characterized, not tested.

The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when

measured externally on the pin.

3

4

All functional non-supply pins, except for PTA5 are internally clamped to V_SSand V_DD

.

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate

resistance values for positive and negative clamp voltages, then use the larger of the two values.

5

Power supply must maintain regulation within operating V_DDrange during instantaneous and operating maximum current

conditions. If the positive injection current (V_In> V_DD) is greater than I_DD, the injection current may flow out of V_DDand could

result in external power supply going out of regulation. Ensure that external V_DDload will shunt current greater than maximum

injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is

present, or if clock rate is very low (which would reduce overall power consumption).

6

7

Maximum is highest voltage that POR is guaranteed.

Factory trimmed at V_DD= 5.0 V, Temp = 25 °C

MC9S08FL16 Series Data Sheet, Rev. 2

Freescale Semiconductor

13

Electrical Characteristics

Typical I_OHvs. V_DD-V_OHV_DD= 5 V (High Drive)

50.000

45.000

40.000

35.000

30.000

25.000

20.000

15.000

10.000

5.000

-40C

0C

25C

55C

85C

0.000

0

0.3

0.5

0.8

1

1.3

2

V

Figure 6. Typical I Vs V –V (V = 5.0 V) (High Drive)

OH

DD OH

DD

MC9S08FL16 Series Data Sheet, Rev. 2

14

Freescale Semiconductor

Electrical Characteristics

Typical I_OHvs. V_DD-V_OHV_DD= 5V (Low Drive)

10.000

9.000

8.000

7.000

6.000

5.000

4.000

3.000

2.000

1.000

0.000

-40C

0C

25C

55C

85C

0

0.3

0.5

0.8

1

1.3

2

V

Figure 7. Typical I Vs V –V (V = 5.0 V) (Low Drive)

OH

DD OH

DD

MC9S08FL16 Series Data Sheet, Rev. 2

Freescale Semiconductor

15

Electrical Characteristics

Typical I_OLvs. V_OLV_DD= 5 V (High Drive)

50.000

45.000

40.000

35.000

30.000

25.000

20.000

15.000

10.000

5.000

-40C

0C

25C

55C

85C

0.000

0

0.3

0.5

0.8

1

1.3

2

V

Figure 8. Typical I Vs V (V = 5.0 V) (High Drive)

OH

OL

DD

MC9S08FL16 Series Data Sheet, Rev. 2

16

Freescale Semiconductor

Electrical Characteristics

Typical I_OLvs. V_OLV_DD= 5V (Low Drive)

14.000

12.000

10.000

8.000

6.000

4.000

2.000

0.000

-40C

0C

25C

55C

85C

0

0.3

0.5

0.8

1

1.3

2

V

Figure 9. Typical I Vs V (V = 5.0 V) (Low Drive)

OH

OL

DD

5.7

Supply Current Characteristics

This section includes information about power supply current in various operating modes.

MC9S08FL16 Series Data Sheet, Rev. 2

Freescale Semiconductor

17

Electrical Characteristics

Table 8. Supply Current Characteristics

Parameter

V_DD

(V)

Bus

Freq

Typical¹

Num

C

Symbol

Max

Unit

Temp

5.66

5.75

5.80

–40 °C

25 °C

85 °C

P

10 MHz

1 MHz

10 MHz

1 MHz

—

Run supply current

FEI mode, all modules off

1

RI_DD

5

mA

1.61

1.65

1.78

–40 °C

25 °C

85 °C

P

C

—

2.79

2.86

2.88

–40 °C

25 °C

85 °C

Wait mode supply current

FEI mode, all modules off

2

3

WI_DD

μA

1.05

1.06

–40 °C

25 °C

85 °C

C

Stop2 mode supply current

S2I_DD

S3I_DD

—

5

1.06

1.17

—

μA

–40 to 85 °C

25 °C

Stop3 mode supply current

no clocks active

4

5

6

ADC adder to stop3

163.88

1.25

ICS adder to stop3

EREFSTEN = 1

—

25 °C

LVD adder to stop3

—

161.3

25 °C

1

Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.

MC9S08FL16 Series Data Sheet, Rev. 2

18

Freescale Semiconductor

Electrical Characteristics

5.8

External Oscillator (XOSC) and ICS Characteristics

Refer to Figure 11 for crystal or resonator circuits.

Table 9. XOSC and ICS Specifications (Temperature Range = –40 to 85 °C Ambient)

Num

C

Characteristic

Symbol

Min

Typical¹

Max

Unit

Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)

Low range (RANGE = 0)

High range (RANGE = 1) FEE or FBE mode²

High range (RANGE = 1), high gain (HGO = 1), FBELP

mode

f_lo

f_hi

32

1

—

38.4

5

16

8

kHz

MHz

1

C

1

High range (RANGE = 1), low power (HGO = 0), FBELP

mode

C₁

C₂

See Note³

2

3

D Load capacitors

Feedback resistor

Low range (32 kHz to 38.4 kHz)

D

R_F

R_S

10

1

MΩ

High range (1 MHz to 16 MHz)

Series resistor — Low range

4

5

D

Low gain (HGO = 0)

High gain (HGO = 1)

—

0

100

—

kΩ

Series resistor — High range

Low Gain (HGO = 0)

High Gain (HGO = 1)

≥ 8 MHz

R_S

kΩ

—

0

4 MHz

1 MHz

10

20

Crystal startup time^{4, 5}

Low range, low power

Low range, high power

High range, low power

High range, high power

—

200

400

5

—

t

CSTL

6

C

ms

t

CSTH

15

t_IRST

7

8

T Internal reference start-up time

—

60

100

μs

Square wave input clock frequency (EREFS = 0, ERCLKEN

= 1)

f_extal

D

0.03125

0

—

5

20

MHz

FEE or FBE mode²

FBELP mode

f_{int_t}

9

P Average internal reference frequency — trimmed

—

31.25

—

kHz

DCO output frequency range — trimmed⁶

P

f_{dco_t}

10

16

20

MHz

Low range (DRS = 00)

Total deviation of DCO output from trimmed frequency⁴

Over full voltage and temperature range

Over fixed voltage and temperature range of 0 to 70°C

Δf_{dco_t}

%f_dco

ms

11

12

C

—

–1.0 to 0.5

± 2

± 1

±0.5

FLL acquisition time^4,7

t_Acquire

1

MC9S08FL16 Series Data Sheet, Rev. 2

Freescale Semiconductor

19

Electrical Characteristics

Table 9. XOSC and ICS Specifications (Temperature Range = –40 to 85 °C Ambient) (continued)

Num

C

Characteristic

Symbol

Min

Typical¹

Max

Unit

Long term jitter of DCO output clock (averaged over 2 ms

interval) ⁸

C_Jitter

%f_dco

13

C

—

0.02

0.2

1

2

Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.

When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of

31.25 kHz to 39.0625 kHz.

3

4

5

6

7

See crystal or resonator manufacturer’s recommendation.

This parameter is characterized and not tested on each device.

Proper PC board layout procedures must be followed to achieve specifications.

The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.

This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, DMX32

bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If

a crystal/resonator is being used as the reference, this specification assumes it is already running.

8

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_Bus

.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the FLL circuitry via V_DDand V_SSand variation in crystal oscillator frequency increase the C_Jitterpercentage for

a given interval.

XOSC

EXTAL

XTAL

R_S

R_F

Crystal or Resonator

C₁

C₂

Figure 10. Typical Crystal or Resonator Circuit

MC9S08FL16 Series Data Sheet, Rev. 2

20

Freescale Semiconductor

Electrical Characteristics

1.00%

0.50%

0.00%

-0.50%

-1.00%

-1.50%

-2.00%

-60

-40

-20

0

20

40

60

80

100

120

TBD

Temperature

Figure 11. Deviation of DCO Output from Trimmed Frequency (20 MHz, 5.0 V)

5.9

AC Characteristics

This section describes timing characteristics for each peripheral system.

MC9S08FL16 Series Data Sheet, Rev. 2

Freescale Semiconductor

21

Electrical Characteristics

5.9.1

Control Timing

Table 10. Control Timing

Num

C

D

Rating

Symbol

f_Bus

t_LPO

t_extrst

t_rstdrv

Min

Typical¹

Max

10

Unit

MHz

μs

Bus frequency (t_cyc= 1/f_Bus

)

1

2

3

4

dc

700

—

Internal low power oscillator period

1300

—

External reset pulse width²

Reset low drive

100

ns

34 × t_cyc

—

ns

BKGD/MS setup time after issuing background debug

force reset to enter user or BDM modes

t_MSSU

t_MSH

5

6

D

500

100

—

ns

BKGD/MS hold time after issuing background debug

force reset to enter user or BDM modes³

μs

IRQ pulse width

Asynchronous path²

Synchronous path⁴

t_{ILIH, IHIL}

t

100

1.5 × t_cyc

—

ns

7

D

Keyboard interrupt pulse width

Asynchronous path²

8

D

100

1.5 × t_cyc

—

t_{ILIH, IHIL}

t

ns

Synchronous path⁴

Port rise and fall time —

Low output drive (PTxDS = 0) (load = 50 pF)⁵

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

t

_Rise, t_Fall

—

16

23

—

9

C

Port rise and fall time —

High output drive (PTxDS = 1) (load = 50 pF)⁵

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

t_Rise, t_Fall

ns

—

5

9

—

1

Typical values are based on characterization data at V_DD= 5.0 V, 25 °C unless otherwise stated.

This is the shortest pulse that is guaranteed to be recognized as a reset pin request.

2

3

To enter BDM mode following a POR, BKGD/MS must be held low during the power-up and for a hold time of t_MSHafter V_DD

rises above V_LVD

.

4

5

This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.

Timing is shown with respect to 20% V_DDand 80% V_DDlevels. Temperature range –40 °C to 85 °C.

t_extrst

RESET PIN

Figure 12. Reset Timing

MC9S08FL16 Series Data Sheet, Rev. 2

22

Freescale Semiconductor

Electrical Characteristics

t_IHIL

KBIPx

IRQ/KBIPx

t_ILIH

Figure 13. IRQ/KBIPx Timing

5.9.2

TPM Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that

can be used as the optional external source to the timer counter. These synchronizers operate from the

current bus rate clock.

Table 11. TPM Input Timing

No.

C

Function

Symbol

Min

Max

Unit

1

2

3

4

5

D

External clock frequency

External clock period

f_TCLK

t_TCLK

t_clkh

0

f_Bus/4

—

Hz

t_cyc

4

External clock high time

External clock low time

Input capture pulse width

1.5

—

t_clkl

—

t_ICPW

—

t_TCLK

t_clkh

TCLK

t_clkl

Figure 14. Timer External Clock

t_ICPW

TPMCHn

t_ICPW

Figure 15. Timer Input Capture Pulse

MC9S08FL16 Series Data Sheet, Rev. 2

Freescale Semiconductor

23

Electrical Characteristics

5.10 ADC Characteristics

Table 12. 8-Bit ADC Operating Conditions

Characteristic

Conditions

Symb

Min

Typical¹

Max

Unit

Comment

Absolute

Delta to V_DD(V_DD– V_DDA

V_DDA

ΔV_DDA

ΔV_SSA

V_ADIN

4.5

—

0

5.5

100

V

mV

V

Supply voltage

2

)

–100

V_REFL

2

Ground voltage Delta to V_SS(V_SS– V_SSA

)

0

100

Input voltage

—

V_REFH

Input

capacitance

—

C_ADIN

R_ADIN

R_AS

—

4.5

3

5.5

5

pF

kΩ

Input resistance

—

Analog source

resistance

8-bit mode (all valid f_ADCK

)

—

10

External to MCU

High speed (ADLPC = 0)

Low power (ADLPC = 1)

0.4

—

8.0

4.0

ADC conversion

clock frequency

f_ADCK

MHz

1

Typical values assume V_DDA= 5.0 V, Temp = 25 °C, f_ADCK= 1.0 MHz unless otherwise stated. Typical values are for reference

only and are not tested in production.

2

DC potential difference.

SIMPLIFIED

INPUT PIN EQUIVALENT

Z_ADIN

CIRCUIT

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

Z_AS

leakage

due to

ADC SAR

ENGINE

input

protection

R_AS

R_ADIN

+

V_ADIN

–

C_AS

V_AS

+

–

R_ADIN

INPUT PIN

C_ADIN

Figure 16. ADC Input Impedance Equivalency Diagram

MC9S08FL16 Series Data Sheet, Rev. 2

24

Freescale Semiconductor

Electrical Characteristics

Table 13. 8-Bit ADC Characteristics (V

= V

, V

= V

)

SSA

REFH

Min

DDA

REFL

C

Characteristic

Conditions

Symb

Typ¹

Max

Unit

Comment

Supply Current

ADLPC=1

ADLSMP=1

ADCO=1

T

I_DDA

—

133

—

1

μA

Supply Current

ADLPC=1

ADLSMP=0

ADCO=1

T

P

I_DDA

218

327

μA

Supply Current

ADLPC=0

ADLSMP=1

ADCO=1

Supply Current

ADLPC=0

ADLSMP=0

ADCO=1

0.582

mA

C

P

Supply Current Stop, Reset, Module Off

I_DDA

—

2

0.011

3.3

1

5

μA

ADC

Asynchronous

Clock Source

High Speed (ADLPC = 0)

Low Power (ADLPC = 1)

Short Sample (ADLSMP = 0)

Long Sample (ADLSMP = 1)

t_ADACK

1/f_ADACK

=

f_ADACK

MHz

1.25

—

2

3.3

—

Conversion

Time(Including

sample time)

20

40

ADCK

cycles

P

t_ADC

See reference

manual for

conversion

—

Short Sample (ADLSMP = 0)

Long Sample (ADLSMP = 1)

–40°C– 25°C

—

3.5

—

ADCK

cycles

time variances

Sample Time

t_ADS

23.5

3.266

3.638

Temp Sensor

Slope

D

m

mV/°C

25°C– 125°C

Temp Sensor

Voltage

25 °C

V_TEMP25

—

1.396

—

mV

Total

Includes

quantization

LSB²

E_TUE

P

Unadjusted

Error

8-bit mode

±0.5

±1.0

Differential

Non-Linearity

LSB²

P

T

P

T

8-bit mode³

8-bit mode

DNL

INL

—

±0.3

±0.5

Integral

Non-Linearity

Zero-Scale

Error

E_ZS

V_ADIN= V_SSA

V_ADIN= V_DDA

Full-Scale

Error

E_FS

MC9S08FL16 Series Data Sheet, Rev. 2

Freescale Semiconductor

25

Electrical Characteristics

Table 13. 8-Bit ADC Characteristics (V

= V

, V

= V

) (continued)

SSA

REFH

DDA

REFL

C

Characteristic

Conditions

8-bit mode

Symb

Min

Typ¹

Max

±0.5

Unit

Comment

Quantization

Error

LSB²

E_Q

E_IL

D

—

Pad leakage²

* R_AS

Input Leakage

Error

LSB²

D

8-bit mode

—

±0.1

±1

1

2

Typical values assume V_DDA= 5.0 V, Temp = 25 °C, f_ADCK= 1.0 MHz unless otherwise stated. Typical values are for reference

only and are not tested in production.

Based on input pad leakage current. Refer to pad electricals.

5.11 Flash Specifications

This section provides details about program/erase times and program-erase endurance for the flash

memory.

Program and erase operations do not require any special power sources other than the normal V supply.

DD

For more detailed information about program/erase operations, see the Memory section.

Table 14. Flash Characteristics

C

Characteristic

Symbol

Min

Typical

Max

Unit

Supply voltage for program/erase

–40 °C to 85 °C

D

—

V_prog/erase

V_Read

f_FCLK

4.5

150

5

5.5

V

D

P

Supply voltage for read operation

Internal FCLK frequency¹

Internal FCLK period (1/FCLK)

Byte program time (random location)²

Byte program time (burst mode)²

Page erase time²

Mass erase time²

Byte program current³

Page erase current³

—

V

—

200

6.67

kHz

μs

t_Fcyc

—

t_prog

9

t_Fcyc

mA

t_Burst

4

4000

20,000

4

t_Page

t_Mass

RI_DDBP

RI_DDPE

—

6

Program/erase endurance⁴

T_Lto T_H= –40 °C to 85 °C

T = 25 °C

C

—

5

10,000

100

—

cycles

years

Data retention⁵

t_{D_ret}

1

2

The frequency of this clock is controlled by a software setting.

These values are hardware state machine controlled. User code does not need to count cycles. This information supplied

for calculating approximate time to program and erase.

3

4

The program and erase currents are additional to the standard run I_DD. These values are measured at room temperatures

with V_DD= 5.0 V, bus frequency = 4.0 MHz.

Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how

Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile

Memory.

MC9S08FL16 Series Data Sheet, Rev. 2

26

Freescale Semiconductor

Ordering Information

Typical data retention values are based on intrinsic capability of the technology measured at high temperature and

5

de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,

please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.

5.12 EMC Performance

Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the

MCU resides. Board design and layout, circuit topology choices, location and characteristics of external

components as well as MCU software operation all play a significant role in EMC performance. The

system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263,

AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.

5.12.1 Radiated Emissions

Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell

method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed

with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test

software. The radiated emissions from the microcontroller are measured in a TEM cell in two package

orientations (the North and East).

The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal

to the reported emissions levels.

Table 15. Radiated Emissions, Electric Field

Level¹

Parameter

Symbol

Conditions

Frequency

f_OSC/f_BUS

Unit

(Max)

Radiated emissions,

electric field

V_{RE_TEM}

V_DD= 5.0 V

T_A= 25 ^οC

package type

32-pin LQFP

0.15 – 50 MHz

50 – 150 MHz

150 – 500 MHz

500 – 1000 MHz

IEC Level

4 MHz crystal

19 MHz bus

9

5

2

1

N

1

dBμV

—

SAE Level

1

Data based on qualification test results.

6

Ordering Information

This section contains ordering information for MC9S08FL16 series devices. See below for an example of

the device numbering system.

Table 16. Device Numbering System

Memory

Device Number¹

Available Packages²

FLASH

RAM

MC9S08FL16

MC9S08FL8

16 KB

8 KB

1024

768

32 SDIP

32 LQFP

MC9S08FL16 Series Data Sheet, Rev. 2

Freescale Semiconductor

27

Package Information

1

2

See the reference manual, MC9S08FL16 Series Reference Manual, for a complete

description of modules included on each device.

See Table 17 for package information.

Example of the device numbering system:

FL 16

C

XX

9

MC S08

Status

(MC = Fully Qualified)

Package designator (see Table 17)

Temperature range

(C =–40 °C to 85 °C)

Memory

(9 = Flash-based)

Core

Approximate flash size in KB

Family

7

Package Information

Table 17. Package Descriptions

Pin Count

Package Type

Abbreviation

Designator

Case No.

Document No.

32

Low Quad Flat Package

LQFP

SDIP

LC

873A-03

1376-02

98ASH70029A

98ASA99330D

Shrink Dual In-line Package

BM

7.1

Mechanical Drawings

The following pages are mechanical drawings for the packages described in Table 17.

MC9S08FL16 Series Data Sheet, Rev. 2

28

Freescale Semiconductor

How to Reach Us:

Home Page:

www.freescale.com

Web Support:

http://www.freescale.com/support

USA/Europe or Locations Not Listed:

Freescale Semiconductor, Inc.

Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284

1-800-521-6274 or +1-480-768-2130

www.freescale.com/support

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

www.freescale.com/support

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064

Japan

0120 191014 or +81 3 5437 9125

support.japan@freescale.com

Information in this document is provided solely to enable system and

software implementers to use Freescale Semiconductor products. There are

no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits or integrated circuits based on the

information in this document.

Asia/Pacific:

Freescale Semiconductor China Ltd.

Exchange Building 23F

No. 118 Jianguo Road

Chaoyang District

Freescale Semiconductor reserves the right to make changes without further

notice to any products herein. Freescale Semiconductor makes no warranty,

representation or guarantee regarding the suitability of its products for any

particular purpose, nor does Freescale Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or

incidental damages. “Typical” parameters that may be provided in Freescale

Semiconductor data sheets and/or specifications can and do vary in different

applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer

application by customer’s technical experts. Freescale Semiconductor does

not convey any license under its patent rights nor the rights of others.

Freescale Semiconductor products are not designed, intended, or authorized

for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other

application in which the failure of the Freescale Semiconductor product could

create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended

or unauthorized application, Buyer shall indemnify and hold Freescale

Semiconductor and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized

use, even if such claim alleges that Freescale Semiconductor was negligent

regarding the design or manufacture of the part.

Beijing 100022

China

+86 10 5879 8000

support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

1-800-441-2447 or +1-303-675-2140

Fax: +1-303-675-2150

LDCForFreescaleSemiconductor@hibbertgroup.com

Freescale™ and the Freescale logo are trademarks of

Freescale Semiconductor, Inc. All other product or service names

are the property of their respective owners.

MC9S08FL16

Rev. 2

7/2009


型号：	MC9S08FL8
厂家：	Freescale
描述：	8-Bit S08 Central Processor Unit (CPU) 8位S08的中央处理单元（CPU）的
文件：	总34页 (文件大小：627K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC9S08FL8 [FREESCALE]

相关型号：

MC9S08FL8CBM

MC9S08FL8CLC

MC9S08FL8CLC

MC9S08GB32

MC9S08GB32

MC9S08GB32A

MC9S08GB32ACFUE

MC9S08GB32ACFUE

MC9S08GB32ACFUER

MC9S08GB32CB

MC9S08GB32CFB

MC9S08GB32CFD