MC9S08FL8CBM [FREESCALE]
MC9S08FL8CBM;型号: | MC9S08FL8CBM |
厂家: | Freescale |
描述: | MC9S08FL8CBM |
文件: | 总35页 (文件大小:1180K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08FL16
Rev. 3, 11/2010
MC9S08FL16
MC9S08FL16 Series
Covers: MC9S08FL16 and
MC9S08FL8
32-Pin SDIP
1376-02
32-Pin LQFP
873A-03
• Illegal address detection with reset
• Flash block protection
Features:
8-Bit S08 Central Processor Unit (CPU)
Development Support
• Up to 20 MHz CPU at 4.5 V to 5.5 V across
• Single-wire background debug interface
temperature range of –40 °C to 85 °C
• Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints).
• HC08 instruction set with added BGND instruction
• Support for up to 32 interrupt/reset sources
• On-chip in-circuit emulator (ICE) debug module
containing two comparators and nine trigger
modes.
On-Chip Memory
• Up to 16 KB flash read/program/erase over full
operating voltage and temperature
Peripherals
• Up to 1024-byte random-access memory (RAM)
• Security circuitry to prevent unauthorized access
to RAM and flash contents
• IPC — Interrupt priority controller to provide
hardware based nested interrupt mechanism
• ADC — 12-channel, 8-bit resolution; 2.5 s
conversion time; automatic compare function;
1.7 mV/C temperature sensor; internal bandgap
reference channel; operation in stop; optional
hardware trigger; fully functional from 4.5 V to
5.5 V
Power-Saving Modes
• Two low power stop modes; reduced power wait
mode
• Allows clocks to remain enabled to specific
peripherals in stop3 mode
• TPM — One 4-channel and one 2-channel
timer/pulse-width modulators (TPM) modules;
selectable input capture, output compare, or
buffered edge- or center-aligned PWM on each
channel
Clock Source Options
• Oscillator (XOSC) — Loop-control Pierce
oscillator; crystal or ceramic resonator range of
31.25 kHz to 39.0625 kHz or 1 MHz to 16 MHz
• Internal Clock Source (ICS) — Internal clock
source module containing a
• MTIM16 — One 16-bit modulo timer with optional
prescaler
frequency-locked-loop (FLL) controlled by internal
or external reference; precision trimming of
internal reference allows 0.2% resolution and 2%
deviation over temperature and voltage; supports
bus frequencies up to 10 MHz
• SCI — One serial communications interface
module with optional 13-bit break; LIN extensions
Input/Output
• 30 GPIOs including 1 output-only pin and 1
input-only pin
System Protection
• Watchdog computer operating properly (COP)
reset with option to run from dedicated 1 kHz
internal clock source or bus clock
• Low-voltage detectionwith reset or interrupt;
selectable trip points
Package Options
• 32-pin SDIP
• 32-pin LQFP
• Illegal opcode detection with reset
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
Table of Contents
1
2
3
4
5
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
System Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . 4
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9
5.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 9
5.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . 10
5.5 ESD Protection and Latch-Up Immunity . . . . . . 11
5.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12
5.7 Supply Current Characteristics . . . . . . . . . . . . . 17
5.8 External Oscillator (XOSC) and ICS
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.9 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 21
5.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . 22
5.9.2 TPM Module Timing . . . . . . . . . . . . . . . . 23
5.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . 24
5.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . 26
5.12 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . 27
5.12.1Radiated Emissions. . . . . . . . . . . . . . . . . 27
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . 28
6
7
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
Date
Description of Changes
1
2
March 18, 2009
July 20, 2009
Initial public release.
Updated Section 5.12, “EMC Performance.” and corrected Figure 1 and Table 1.
Corrected default trim value to 31.25 kHz.
3
Nov. 29, 2010
Updated Table 7.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08FL16RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08FL16 Series Data Sheet, Rev. 3
2
Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
The block diagram, Figure 1, shows the structure of MC9S08FL16 series MCU.
PTA0/ADP0
16-BIT MODULO TIMER
TCLK
HCS08 CORE
PTA1/ADP1
(MTIM16)
PTA2/ADP2
BDC
CPU
PTA3/ADP3
2-CH TIMER/PWM
TPM2CH[1:0]
MODULE (TPM2)
PTA4/BKGD/MS
PTA5/IRQ/TCLK/RESET
PTA6/TPM2CH0
PTA7/TPM2CH1
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RESET
IRQ
COP
IRQ
LVD
INTERRUPT PRIORITY
CONTROLLER (IPC)
PTB0/RxD/ADP4
PTB1/TxD/ADP5
PTB2/ADP6
ON-CHIP ICE AND
DEBUG MODUE (DBG)
TxD
RxD
SERIAL COMMUNICATIONS
INTERFACE (SCI)
PTB3/ADP7
USER FLASH
PTB4/TPM1CH0
PTB5/TPM1CH1
PTB6/XTAL
MC9S08FL16 — 16,384 BYTES
MC9S08FL8 — 8,192 BYTES
4-CH TIMER/PWM
TPM1CH[3:0]
MODULE (TPM1)
USER RAM
MC9S08FL16 — 1,024 BYTES
MC9S08FL8 — 768 BYTES
PTB7/EXTAL
PTC0/ADP8
PTC1/ADP9
PTC2/ADP10
PTC3/ADP11
PTC4
20 MHz INTERNAL CLOCK
SOURCE (ICS)
EXTAL
XTAL
EXTERNAL OSCILLATOR
SOURCE (XOSC)
V
V
PTC5
DD
SS
VOLTAGE REGULATOR
PTC6
PTC7
V
V
V
V
REFH
REFL
DDA
12-CH 8-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
ADP[11:0]
SSA
PTD0
PTD1
PTD2/TPM1CH2
PTD3/TPM1CH3
PTD4
NOTE
1. PTA4 is output only when used as port pin.
2. PTA5 is input only when used as port pin.
PTD5
Figure 1. MC9S08FL16 Series Block Diagram
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
3
System Clock Distribution
2
System Clock Distribution
MC9S08FL16 series use ICS module as clock sources. The ICS module can use internal or external clock
source as reference to provide up to 20 MHz CPU clock. The output of ICS module includes,
•
•
OSCOUT — XOSC output provides external reference clock to ADC.
ICSFFCLK — ICS fixed frequency clock reference (around 32.768 kHz) provides double of the
fixed lock signal to TPMs and MTIM16.
•
ICSOUT — ICS CPU clock provides double of the bus clock which is basic clock reference of
peripherals.
•
ICSLCLK — Alternate BDC clock provides debug signal to BDC module.
The TCLK pin is an extra external clock source. When TCLK is enabled, it can provide alternate clock
source to TPMs and MTIM16. The on-chip 1 kHz clock provides clock source of COP module.
TCLK
1 kHz
COP
TPM1
TPM2
MTIM16
ADC
OSCOUT
ICSFFCLK
ICSOUT
FIXED CLOCK (XCLK)
2
ICS
BUS CLOCK
2
ICSLCLK
XOSC
IPC
CPU
SCI
BDC
FLASH
RAM
EXTAL XTAL
Figure 2. System Clock Distribution Diagram
MC9S08FL16 Series Data Sheet, Rev. 3
4
Freescale Semiconductor
Pin Assignments
3
Pin Assignments
This section shows the pin assignments for the MC9S08FL16 series devices.
PTC6
PTC5
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
PTC7
PTC4
PTA5/IRQ/TCLK/RESET
PTD2/TPM1CH2
PTA4/BKGD/MS
PTD0
2
PTA0/ADP0
PTD5
3
4
PTA1/ADP1
PTA2/ADP2
PTA3/ADP3
PTA6/TPM2CH0
PTA7/TPM2CH1
PTB0/RxD/ADP4
PTB1/TxD/ADP5
PTB2/ADP6
PTD4
5
6
PTD1
7
VDD
8
VSS
9
PTB7/EXTAL
10
11
12
13
14
15
16
PTB6/XTAL
PTB5/TPM2CH1
PTD3/TPM1CH3
PTB4/TPM1CH0
PTC3/ADP11
PTB3/ADP7
PTC0/ADP8
PTC1/ADP9
PTC2/ADP10
Figure 3. MC9S08FL16 Series 32-Pin SDIP Package
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
5
Pin Assignments
PTA4/BKGD/MS
PTD0
PTA1/ADP1
1
24
23
22
21
20
19
18
PTA2/ADP2
2
3
4
5
6
7
8
PTD1
PTA3/ADP3
VDD
PTA6/TPM2CH0
PTA7/TPM2CH1
PTB0/RxD/ADP4
PTB1/TxD/ADP5
PTB2/ADP6
VSS
PTB7/EXTAL
PTB6/XTAL
PTB5/TPM1CH1
17
Figure 4. MC9S08FL16 Series 32-Pin LQFP Package
Table 1. Pin Availability by Package Pin-Count
Pin Number
<-- Lowest Priority --> Highest
32-SDIP
32-LQFP
Port Pin I/O
Alt 1
I/O
Alt 2
I/O
Alt 3
I/O
1
2
29
30
31
32
1
PTC5
PTC4
PTA5
PTD2
PTA4
PTD0
PTD1
I/O
I/O
I
3
IRQ
I
TCLK
I
RESET
MS
I
I
4
I/O
O
TPM1CH2 I/O
BKGD
5
I
6
2
I/O
I/O
7
3
8
4
VDD
VSS
I
I
9
5
10
11
12
13
14
15
6
PTB7
PTB6
PTB5
PTD3
PTB4
PTC3
I/O
I/O
I/O
I/O
I/O
I/O
EXTAL
XTAL
I
7
O
8
TPM1CH1 I/O
TPM1CH3 I/O
TPM1CH0 I/O
9
10
11
ADP11
I
MC9S08FL16 Series Data Sheet, Rev. 3
6
Freescale Semiconductor
Pin Assignments
Table 1. Pin Availability by Package Pin-Count (continued)
Pin Number <-- Lowest Priority --> Highest
32-SDIP
32-LQFP
Port Pin I/O
Alt 1
I/O
Alt 2
I/O
Alt 3
I/O
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PTC2
PTC1
PTC0
PTB3
PTD4
PTB2
PTB1
PTB0
PTA7
PTA6
PTA3
PTA2
PTA1
PTD5
PTA0
PTC7
PTC6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ADP10
ADP9
ADP8
ADP7
I
I
I
I
ADP6
TxD
I
I/O
I
ADP5
ADP4
I
I
RxD
TPM2CH1 I/O
TPM2CH0 I/O
ADP3
ADP2
ADP1
I
I
I
ADP0
I
NOTE
When an alternative function is first enabled, it is possible to get a spurious
edge to the module. User software must clear out any associated flags before
interrupts are enabled. Table 1 illustrates the priority if multiple modules are
enabled. The highest priority module will have control over the pin.
Selecting a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority module.
Disable all modules that share a pin before enabling another module.
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
7
Memory Map
4
Memory Map
Figure 5 shows the memory map for the MC9S08FL16 series. On-chip memory in the MC9S08FL16
series of MCUs consists of RAM, flash program memory for nonvolatile data storage, plus I/O and
control/status registers. The registers are divided into two groups:
•
•
Direct-page registers (0x0000 through 0x003F)
High-page registers (0x1800 through 0x187F)
$0000
$0000
DIRECT PAGE REGISTERS
RAM 768 BYTES
DIRECT PAGE REGISTERS
RAM 1024 BYTES
$003F
$0040
$003F
$0040
$033F
$0340
$043F
$0440
UNIMPLEMENTED
UNIMPLEMENTED
$17FF
$1800
$17FF
$1800
HIGH PAGE REGISTERS
HIGH PAGE REGISTERS
$187F
$1880
$187F
$1880
UNIMPLEMENTED
UNIMPLEMENTED
$BFFF
$C000
FLASH
16384 BYTES
$DFFF
$E000
FLASH
8192 BYTES
$FFFF
$FFFF
MC9S08FL8
MC9S08FL16
Figure 5. MC9S08FL16 Series Memory Map
MC9S08FL16 Series Data Sheet, Rev. 3
8
Freescale Semiconductor
Electrical Characteristics
5
Electrical Characteristics
5.1
Introduction
This section contains electrical and timing specifications for the MC9S08FL16 series of microcontrollers
available at the time of publication.
5.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 2. Parameter Classifications
Those parameters are guaranteed during production testing on each individual device.
P
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
Those parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
5.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either V or V ) or the programmable
SS
DD
pullup resistor associated with the pin is enabled.
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
9
Electrical Characteristics
Table 3. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
IDD
VIn
–0.3 to 5.8
120
V
mA
V
Maximum current into VDD
Digital input voltage
–0.3 to VDD + 0.3
Instantaneous maximum current
ID
25
mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range
Tstg
–55 to 150
C
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
3
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
5.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the
MCU design. To take P into account in power calculations, determine the difference between actual pin
I/O
voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of unusually high
SS
DD
pin current (heavy loads), the difference between pin voltage and V or V will be very small.
SS
Table 4. Thermal Characteristics
DD
Rating
Symbol
Value
Unit
Operating temperature range
(packaged)
TL to TH
–40 to 85
TA
C
Thermal resistance
Single-layer board
32-pin SDIP
32-pin LQFP
60
85
JA
C/W
C/W
Thermal resistance
Four-layer board
32-pin SDIP
32-pin LQFP
35
56
JA
The average chip-junction temperature (T ) in C can be obtained from:
J
MC9S08FL16 Series Data Sheet, Rev. 3
10
Freescale Semiconductor
Electrical Characteristics
T = T + (P )
JA
Eqn. 1
J
A
D
where:
T = Ambient temperature, C
A
= Package thermal resistance, junction-to-ambient, C/W
JA
P = P P
D
int
I/O
P = I V , Watts — chip internal power
int
DD
DD
P
= Power dissipation on input and output pins — user determined
I/O
For most applications, P far much smaller than P and can be neglected. An approximate relationship
I/O
int
between P and T (if P is neglected) is:
D
J
I/O
P = K (T + 273 C)
Eqn. 2
D
J
Solving Equation 1 and Equation 2 for K gives:
2
K = P (T + 273 C) + (P )
Eqn. 3
D
A
JA
D
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
P (at equilibrium) for an known T . Using this value of K, the values of P and T can be obtained by
D
A
D
J
solving Equation 1 and Equation 2 iteratively for any value of T .
A
5.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions must be taken to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
During the device qualification, ESD stresses were performed for the human body model (HBM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless instructed otherwise in the device
specification.
Table 5. ESD and Latch-Up Test Conditions
Model
Description
Series resistance
Symbol
Value
1500
100
3
Unit
R1
C
Human
body
Storage capacitance
pF
—
V
Number of pulses per pin
Minimum input voltage limit
Maximum input voltage limit
—
—
—
–2.5
7.5
Latch-up
V
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
11
Electrical Characteristics
Table 6. ESD and Latch-Up Protection Characteristics
1
No.
1
Symbol
VHBM
VCDM
ILAT
Min
2000
500
100
Max
—
Unit
V
Rating
Human body model (HBM)
Charge device model (CDM)
Latch-up current at TA = 85 C
2
—
V
3
—
mA
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
5.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 7. DC Characteristics
Num
C
Characteristic
Symbol
Condition
Min.
Typical1
Max.
Unit
1
P Operating voltage
—
—
4.5
—
5.5
V
All I/O pins,
low-drive strength
C
ILoad = –2 mA
VDD – 1.5
—
—
—
—
—
—
—
—
—
—
—
Output high
voltage
2
VOH
V
mA
V
All I/O pins,
high-drive strength
P
ILoad = –10 mA
VDD – 1.5
Output high
current
D
C
P
D
P
P
C
Max total IOH for all ports IOHT
All I/O pins,
—
—
100
3
4
ILoad = 2 mA
—
1.5
low-drive strength
Output low
voltage
VOL
All I/O pins,
high-drive strength
ILoad = 10 mA
—
—
1.5
Output low
current
5
6
7
8
Max total IOL for all ports
All digital inputs
IOLT
VIH
VIL
—
—
—
—
100
mA
V
Input high
voltage
0.65 VDD
—
—
Input low
voltage
All digital inputs
0.35 VDD
—
V
Input
hysteresis
All digital inputs Vhys
0.06 VDD
mV
Input
P leakage
current
All input only pins
|IIn|
9
VIn = VDD or VSS
—
—
0.1
0.1
1
1
A
A
(per pin)
Hi-Z
(off-state)
leakage
All input/output
10
P
|IOZ
|
VIn = VDD or VSS
(per pin)
current
All digital inputs, when
enabled (all I/O pins other RPU,
than RPD
Pullup,
11a C pulldown
resistors
—
—
17.5
17.5
36.5
36.5
52.5
52.5
k
k
PTA5/IRQ/TCLK/RESET)
Pullup,
11b C pulldown
resistors
RPU,
(PTA5/IRQ/TCLK/RESET) RPD
(Note2)
MC9S08FL16 Series Data Sheet, Rev. 3
12
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num
C
Characteristic
Single pin limit
Symbol
Condition
Min.
Typical1
Max.
Unit
–0.2
—
0.2
mA
DCinjection
12 C current 3, 4,
IIC
VIN < VSS, VIN > VDD
Total MCU limit, includes
sum of all stressed pins
5
–5
—
5
mA
13 C Input capacitance, all pins
14 C RAM retention voltage
15 C POR re-arm voltage6
16 D POR re-arm time
CIn
—
—
—
—
—
—
—
0.6
1.4
—
8
pF
V
VRAM
VPOR
tPOR
1.0
2.0
—
0.9
10
V
s
Low-voltage detection threshold —
high range
7
17
P
C
VLVD1
—
—
—
V
V
V
VDD falling
VDD rising
3.9
4.0
4.0
4.1
4.1
4.2
Low-voltage warning threshold —
high range 1
VLVW3
VDD falling
VDD rising
4.5
4.6
4.6
4.7
4.7
4.8
18
19
Low-voltage warning threshold —
high range 0
7
P
C
VLVW2
VDD falling
VDD rising
4.2
4.3
4.3
4.4
4.4
4.5
Low-voltage inhibit reset/recover
hysteresis
20 C Bandgap voltage reference8
Vhys
VBG
—
—
—
—
100
—
—
mV
V
1.21
1
2
Typical values are measured at 25 C. Characterized, not tested.
The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when
measured externally on the pin.
3
4
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD
.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
5
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
6
7
Maximum is highest voltage that POR is guaranteed.
When VDD is in between the minimun of this parameter and 4.5 V, the CPU, RAM, LVD and flash are full functional, but the
performance of other modules may be reduced.
8
Factory trimmed at VDD = 5.0 V, Temp = 25 C
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
13
Electrical Characteristics
Typical IOH vs. VDD-VOH VDD = 5 V (High Drive)
50.000
45.000
40.000
35.000
30.000
25.000
20.000
15.000
10.000
5.000
-40C
0C
25C
55C
85C
0.000
0
0.3
0.5
0.8
1
1.3
2
V
Figure 6. Typical I Vs V –V (V = 5.0 V) (High Drive)
OH
DD OH
DD
MC9S08FL16 Series Data Sheet, Rev. 3
14
Freescale Semiconductor
Electrical Characteristics
Typical IOH vs. VDD-VOH VDD = 5V (Low Drive)
10.000
9.000
8.000
7.000
6.000
5.000
4.000
3.000
2.000
1.000
0.000
-40C
0C
25C
55C
85C
0
0.3
0.5
0.8
1
1.3
2
V
Figure 7. Typical I Vs V –V (V = 5.0 V) (Low Drive)
OH
DD OH
DD
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
15
Electrical Characteristics
Typical IOL vs. VOL VDD = 5 V (High Drive)
50.000
45.000
40.000
35.000
30.000
25.000
20.000
15.000
10.000
5.000
-40C
0C
25C
55C
85C
0.000
0
0.3
0.5
0.8
1
1.3
2
V
Figure 8. Typical I Vs V (V = 5.0 V) (High Drive)
OH
OL
DD
MC9S08FL16 Series Data Sheet, Rev. 3
16
Freescale Semiconductor
Electrical Characteristics
Typical IOL vs. VOL VDD = 5V (Low Drive)
14.000
12.000
10.000
8.000
6.000
4.000
2.000
0.000
-40C
0C
25C
55C
85C
0
0.3
0.5
0.8
1
1.3
2
V
Figure 9. Typical I Vs V (V = 5.0 V) (Low Drive)
OH
OL
DD
5.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
17
Electrical Characteristics
Table 8. Supply Current Characteristics
Parameter
VDD
(V)
Bus
Freq
Typical1
Num
C
Symbol
Max
Unit
Temp
5.66
5.75
5.80
–40 C
25 C
85 C
P
10 MHz
1 MHz
10 MHz
1 MHz
—
Run supply current
FEI mode, all modules off
1
RIDD
5
5
mA
1.61
1.65
1.78
–40 C
25 C
85 C
P
C
C
—
—
—
2.79
2.86
2.88
–40 C
25 C
85 C
Wait mode supply current
FEI mode, all modules off
2
3
WIDD
A
1.05
1.06
1.06
–40 C
25 C
85 C
C
C
C
C
C
Stop2 mode supply current
S2IDD
S3IDD
—
—
—
—
—
—
5
5
5
5
5
1.06
1.17
—
—
—
—
—
A
A
A
A
A
–40 to 85 C
–40 to 85 C
25 C
Stop3 mode supply current
no clocks active
4
5
6
ADC adder to stop3
163.88
1.25
ICS adder to stop3
EREFSTEN = 1
—
25 C
LVD adder to stop3
—
161.3
25 C
1
Data in Typical column was characterized at 5.0 V, 25 C or is typical recommended value.
MC9S08FL16 Series Data Sheet, Rev. 3
18
Freescale Semiconductor
Electrical Characteristics
5.8
External Oscillator (XOSC) and ICS Characteristics
Refer to Figure 11 for crystal or resonator circuits.
Table 9. XOSC and ICS Specifications (Temperature Range = –40 to 85 C Ambient)
Num
C
Characteristic
Symbol
Min
Typical1
Max
Unit
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
High range (RANGE = 1) FEE or FBE mode2
High range (RANGE = 1), high gain (HGO = 1), FBELP
mode
flo
fhi
fhi
fhi
32
1
1
—
—
—
—
38.4
5
16
8
kHz
MHz
MHz
MHz
1
C
1
High range (RANGE = 1), low power (HGO = 0), FBELP
mode
C1
C2
See Note3
2
3
D Load capacitors
Feedback resistor
Low range (32 kHz to 38.4 kHz)
D
RF
RS
10
1
M
M
High range (1 MHz to 16 MHz)
Series resistor — Low range
4
5
D
D
Low gain (HGO = 0)
High gain (HGO = 1)
—
—
0
100
—
—
k
Series resistor — High range
Low Gain (HGO = 0)
High Gain (HGO = 1)
8 MHz
RS
k
—
—
—
0
0
0
0
4 MHz
1 MHz
10
20
Crystal startup time4, 5
Low range, low power
Low range, high power
High range, low power
High range, high power
—
—
—
—
200
400
5
—
—
—
—
t
CSTL
6
C
ms
t
CSTH
15
tIRST
7
8
T Internal reference start-up time
—
60
100
s
Square wave input clock frequency (EREFS = 0, ERCLKEN
= 1)
fextal
D
0.03125
0
—
—
5
20
MHz
MHz
FEE or FBE mode2
FBELP mode
fint_t
9
P Average internal reference frequency — trimmed
—
31.25
—
—
kHz
DCO output frequency range — trimmed6
P
fdco_t
10
16
20
MHz
Low range (DRS = 00)
Total deviation of DCO output from trimmed frequency4
Over full voltage and temperature range
Over fixed voltage and temperature range of 0 to 70C
fdco_t
%fdco
ms
11
12
C
C
—
–1.0 to 0.5
2
1
0.5
FLL acquisition time4,7
tAcquire
1
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
19
Electrical Characteristics
Table 9. XOSC and ICS Specifications (Temperature Range = –40 to 85 C Ambient) (continued)
Num
C
Characteristic
Symbol
Min
Typical1
Max
Unit
Long term jitter of DCO output clock (averaged over 2 ms
interval) 8
CJitter
%fdco
13
C
—
0.02
0.2
1
2
Data in Typical column was characterized at 5.0 V, 25 C or is typical recommended value.
When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of
31.25 kHz to 39.0625 kHz.
3
4
5
6
7
See crystal or resonator manufacturer’s recommendation.
This parameter is characterized and not tested on each device.
Proper PC board layout procedures must be followed to achieve specifications.
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, DMX32
bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If
a crystal/resonator is being used as the reference, this specification assumes it is already running.
8
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for
a given interval.
XOSC
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 10. Typical Crystal or Resonator Circuit
MC9S08FL16 Series Data Sheet, Rev. 3
20
Freescale Semiconductor
Electrical Characteristics
1.00%
0.50%
0.00%
-0.50%
-1.00%
-1.50%
-2.00%
-60
-40
-20
0
20
40
60
80
100
120
Temperature
Figure 11. Deviation of DCO Output from Trimmed Frequency (20 MHz, 5.0 V)
5.9
AC Characteristics
This section describes timing characteristics for each peripheral system.
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
21
Electrical Characteristics
5.9.1
Control Timing
Table 10. Control Timing
Num
C
D
D
D
D
Rating
Symbol
fBus
tLPO
textrst
trstdrv
Min
Typical1
Max
10
Unit
MHz
s
Bus frequency (tcyc = 1/fBus
)
1
2
3
4
dc
700
—
—
—
—
Internal low power oscillator period
1300
—
External reset pulse width2
Reset low drive
100
ns
34 tcyc
—
ns
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
tMSH
5
6
D
D
500
100
—
—
—
—
ns
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes3
s
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, IHIL
t
100
1.5 tcyc
—
—
—
—
ns
7
D
Keyboard interrupt pulse width
Asynchronous path2
8
D
100
1.5 tcyc
—
—
—
—
tILIH, IHIL
t
ns
ns
Synchronous path4
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t
Rise, tFall
—
—
16
23
—
—
9
C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
ns
—
—
5
9
—
—
1
Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
2
3
To enter BDM mode following a POR, BKGD/MS must be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD
.
4
5
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 C to 85 C.
textrst
RESET PIN
Figure 12. Reset Timing
MC9S08FL16 Series Data Sheet, Rev. 3
22
Freescale Semiconductor
Electrical Characteristics
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 13. IRQ/KBIPx Timing
5.9.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 11. TPM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
2
3
4
5
D
D
D
D
D
External clock frequency
External clock period
fTCLK
tTCLK
tclkh
0
fBus/4
—
Hz
tcyc
tcyc
tcyc
tcyc
4
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
tclkl
—
tICPW
—
tTCLK
tclkh
TCLK
tclkl
Figure 14. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 15. Timer Input Capture Pulse
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
23
Electrical Characteristics
5.10 ADC Characteristics
Table 12. 8-Bit ADC Operating Conditions
Characteristic
Conditions
Symb
Min
Typical1
Max
Unit
Comment
Absolute
Delta to VDD (VDD – VDDA
VDDA
VDDA
VSSA
VADIN
4.5
—
0
5.5
100
V
mV
mV
V
Supply voltage
2
)
–100
–100
VREFL
2
Ground voltage Delta to VSS (VSS – VSSA
)
0
100
Input voltage
—
—
VREFH
Input
capacitance
—
CADIN
RADIN
RAS
—
—
—
4.5
3
5.5
5
pF
k
k
Input resistance
—
Analog source
resistance
8-bit mode (all valid fADCK
)
—
10
External to MCU
High speed (ADLPC = 0)
Low power (ADLPC = 1)
0.4
0.4
—
—
8.0
4.0
ADC conversion
clock frequency
fADCK
MHz
1
Typical values assume VDDA = 5.0 V, Temp = 25 C, fADCK= 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
DC potential difference.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
ADC SAR
ENGINE
input
protection
RAS
RADIN
+
VADIN
–
CAS
VAS
+
–
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 16. ADC Input Impedance Equivalency Diagram
MC9S08FL16 Series Data Sheet, Rev. 3
24
Freescale Semiconductor
Electrical Characteristics
Table 13. 8-Bit ADC Characteristics (V
= V
, V
= V
)
SSA
REFH
Min
DDA
REFL
C
Characteristic
Conditions
Symb
Typ1
Max
Unit
Comment
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
T
IDDA
—
—
—
—
133
—
—
—
1
A
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
T
T
P
IDDA
IDDA
IDDA
218
327
A
A
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
0.582
mA
C
P
Supply Current Stop, Reset, Module Off
IDDA
—
2
0.011
3.3
1
5
A
ADC
Asynchronous
Clock Source
High Speed (ADLPC = 0)
Low Power (ADLPC = 1)
Short Sample (ADLSMP = 0)
Long Sample (ADLSMP = 1)
tADACK
1/fADACK
=
fADACK
MHz
1.25
—
2
3.3
—
Conversion
Time(Including
sample time)
20
40
ADCK
cycles
P
P
tADC
See reference
manual for
conversion
—
—
Short Sample (ADLSMP = 0)
Long Sample (ADLSMP = 1)
–40C– 25C
—
—
—
—
3.5
—
—
—
—
ADCK
cycles
time variances
Sample Time
tADS
23.5
3.266
3.638
Temp Sensor
Slope
D
D
m
mV/C
25C– 125C
Temp Sensor
Voltage
25 C
VTEMP25
—
—
1.396
—
mV
Total
Includes
quantization
LSB2
ETUE
P
Unadjusted
Error
8-bit mode
0.5
1.0
Differential
Non-Linearity
LSB2
LSB2
LSB2
LSB2
P
T
P
T
8-bit mode3
8-bit mode
8-bit mode
8-bit mode
DNL
INL
—
—
—
—
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
Integral
Non-Linearity
Zero-Scale
Error
EZS
VADIN = VSSA
VADIN = VDDA
Full-Scale
Error
EFS
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
25
Electrical Characteristics
Table 13. 8-Bit ADC Characteristics (V
= V
, V
= V
) (continued)
SSA
REFH
DDA
REFL
C
Characteristic
Conditions
8-bit mode
Symb
Min
Typ1
Max
0.5
Unit
Comment
Quantization
Error
LSB2
EQ
EIL
D
—
—
Pad leakage2
* RAS
Input Leakage
Error
LSB2
D
8-bit mode
—
0.1
1
1
2
Typical values assume VDDA = 5.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
Based on input pad leakage current. Refer to pad electricals.
5.11 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash
memory.
Program and erase operations do not require any special power sources other than the normal V supply.
DD
For more detailed information about program/erase operations, see the Memory section.
Table 14. Flash Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
Supply voltage for program/erase
–40 C to 85 C
D
—
Vprog/erase
VRead
fFCLK
4.5
4.5
150
5
5.5
5.5
V
D
D
D
P
P
P
P
Supply voltage for read operation
Internal FCLK frequency1
Internal FCLK period (1/FCLK)
Byte program time (random location)2
Byte program time (burst mode)2
Page erase time2
Mass erase time2
Byte program current3
Page erase current3
—
V
—
200
6.67
kHz
s
tFcyc
—
tprog
9
tFcyc
tFcyc
tFcyc
tFcyc
mA
mA
tBurst
4
4000
20,000
4
tPage
tMass
RIDDBP
RIDDPE
—
—
—
—
6
Program/erase endurance4
TL to TH = –40 C to 85 C
T = 25 C
C
C
—
5
10,000
100
—
—
cycles
years
Data retention5
tD_ret
1
2
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
3
4
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 5.0 V, bus frequency = 4.0 MHz.
Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
MC9S08FL16 Series Data Sheet, Rev. 3
26
Freescale Semiconductor
Ordering Information
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
5
de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
5.12 EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external
components as well as MCU software operation all play a significant role in EMC performance. The
system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263,
AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
5.12.1 Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell
method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed
with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test
software. The radiated emissions from the microcontroller are measured in a TEM cell in two package
orientations (the North and East).
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal
to the reported emissions levels.
Table 15. Radiated Emissions, Electric Field
Level1
Parameter
Symbol
Conditions
Frequency
fOSC/fBUS
Unit
(Max)
Radiated emissions,
electric field
VRE_TEM
VDD = 5.0 V
TA = 25 C
package type
32-pin LQFP
0.15 – 50 MHz
50 – 150 MHz
150 – 500 MHz
500 – 1000 MHz
IEC Level
4 MHz crystal
19 MHz bus
9
5
2
1
N
1
dBV
—
—
SAE Level
1
Data based on qualification test results.
6
Ordering Information
This section contains ordering information for MC9S08FL16 series devices. See below for an example of
the device numbering system.
Table 16. Device Numbering System
Memory
Device Number1
Available Packages2
FLASH
RAM
MC9S08FL16
MC9S08FL8
16 KB
8 KB
1024
768
32 SDIP
32 LQFP
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
27
Package Information
1
2
See the reference manual, MC9S08FL16 Series Reference Manual, for a complete
description of modules included on each device.
See Table 17 for package information.
Example of the device numbering system:
FL 16
C
XX
9
MC S08
Status
(MC = Fully Qualified)
Package designator (see Table 17)
Temperature range
(C =–40 C to 85 C)
Memory
(9 = Flash-based)
Core
Approximate flash size in KB
Family
7
Package Information
Table 17. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
32
32
Low Quad Flat Package
LQFP
SDIP
LC
873A-03
1376-02
98ASH70029A
98ASA99330D
Shrink Dual In-line Package
BM
7.1
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 17.
MC9S08FL16 Series Data Sheet, Rev. 3
28
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MC9S08FL16
Rev. 3
11/2010
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