MC33290D/R2 [FREESCALE]

ISO K Line Serial Link Interface; ISO K线串行接口
MC33290D/R2
型号: MC33290D/R2
厂家: Freescale    Freescale
描述:

ISO K Line Serial Link Interface
ISO K线串行接口

文件: 总12页 (文件大小:788K)
中文:  中文翻译
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Document Number: MC33290  
Rev 8.0, 8/2008  
Freescale Semiconductor  
Technical Data  
ISO K Line Serial Link Interface  
33290  
The 33290 is a serial link bus interface device designed to provide  
bi-directional half-duplex communication interfacing in automotive  
diagnostic applications. It is designed to interface between the  
vehicle’s on-board microcontroller and systems off-board the vehicle  
via the special ISO K line. The 33290 is designed to meet the  
Diagnostic Systems ISO9141 specification. The device’s K line bus  
driver’s output is fully protected against bus shorts and  
overtemperature conditions.  
ISO9141 PHYSICAL INTERFACE  
The 33290 derives its robustness to temperature and voltage  
extremes by being built on a SMARTMOS process, incorporating  
CMOS logic, bipolar/MOS analog circuitry, and DMOS power FETs.  
Although the 33290 was principally designed for automotive  
applications, it is suited for other serial communication applications.  
It is parametrically specified over an ambient temperature range of  
-40ºC TA 125ºC and 8.0 V VBB 18 V supply. The economical  
SO-8 surface-mount plastic package makes the 33290 very cost  
effective.  
D SUFFIX  
EF SUFFIX (PB-FREE)  
98ASB42564B  
8-PIN SOICN  
ORDERING INFORMATION  
Temperature  
Features  
Device  
Package  
• Operates Over Wide Supply Voltage of 8.0 to 18V  
• Operating Temperature of -40 to 125°C  
• Interfaces Directly to Standard CMOS Microprocessors  
• ISO K Line Pin Protected Against Shorts to Ground  
• Thermal Shutdown with Hysteresis  
Range (T )  
A
MC33290D/R2  
-40 to 125°C  
8-SOICN  
MCZ33290EF/R2  
• ISO K Line Pin Capable of High Currents  
• ISO K Line Can Be Driven with up to 10 nF of Parasitic  
Capacitance  
• 8.0 kV ESD Protection Attainable with Few Additional Components  
• Standby Mode: No VBat Current Drain with VDD at 5.0 V  
• Low Current Drain During Operation with VDD at 5.0 V  
• Pb-Free Packaging Designated by Suffix Code EF  
+V  
BAT  
V
DD  
33290  
VBB  
VDD  
VDD  
MCU  
ISO K-Line  
D
ISO  
CEN  
RX  
x
SCIR D  
x
T D  
x
SCIT D  
x
TX  
R D  
x
GND  
Figure 1. 33290 Simplified Application Diagram  
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as  
may be required, to permit improvements in the design of its products.  
© Freescale Semiconductor, Inc., 2006-2008. All rights reserved.  
INTERNAL BLOCK DIAGRAM  
INTERNAL BLOCK DIAGRAM  
VBB  
1
3.0 kΩ  
50 V  
20 V  
RX  
200 Ω  
6
10 V  
10 V  
ISO  
4
RHys  
Master  
Bias  
CEN  
40 V  
8
125 kΩ  
VDD  
Thermal  
Shutdown  
GND  
3
7
TX  
5
125 kΩ  
2.0 kΩ  
10 V  
10 V  
Figure 2. 33290 Simplified Block Diagram  
33290  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
2
PIN CONNECTIONS  
PIN CONNECTIONS  
1
8
VBB  
NC  
CEN  
VDD  
RX  
2
7
3
6
GND  
ISO  
4
5
TX  
Figure 3. 33290 Pin Connections  
Table 1. 33290 Pin Definitions  
Pin Number  
Pin Name  
Definition  
1
VBB  
Battery power through external resistor and diode.  
Not to be connected. (1)  
2
NC  
3
4
5
6
7
8
GND  
ISO  
TX  
Common signal and power return.  
Bus connection.  
Logic level input for data to be transmitted on the bus.  
Logic output of data received on the bus.  
Logic power source input.  
RX  
VDD  
CEN  
Chip enable. Logic “1” for active state. Logic “0” for sleep state.  
Notes  
1. NC pins should not have any connections made to them. NC pins are not guaranteed to be open circuits.  
33290  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
3
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
Table 2. Maximum Ratings  
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or  
permanent damage to the device.  
Rating  
Symbol  
Value  
Unit  
VDD DC Supply Voltage  
VDD  
VBB(LD)  
VISO  
-0.3 to 7.0  
V
V
V
A
V
VBB Load Dump Peak Voltage  
45  
40  
ISO Pin Load Dump Peak Voltage (2)  
ISO Short Circuit Current Limit  
IISO(LIM)  
1.0  
ESD Voltage (3)  
Human Body Model (4)  
Machine Model (4)  
VESD1  
VESD2  
±2000  
±200  
ISO Clamp Energy (5)  
Eclamp  
Tstg  
TC  
10  
mJ  
°C  
°C  
°C  
W
Storage Temperature  
-55 to +150  
-40 to +125  
-40 to +150  
Operating Case Temperature  
Operating Junction Temperature  
TJ  
Power Dissipation  
PD  
TA = 25°C  
0.8  
(7)  
Peak Package Reflow Temperature During Reflow (6)  
,
TPPRT  
RθJA  
Note 7.  
°C  
Thermal Resistance  
Junction-to-Ambient  
°C/W  
150  
Notes  
2. Device will survive double battery jump start conditions in typical applications for 10 minutes duration, but is not guaranteed to remain  
within specified parametric limits during this duration.  
3. ESD data available upon request.  
4. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in  
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).  
5. Nonrepetitive clamping capability at 25°C.  
6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may  
cause malfunction or permanent damage to the device.  
7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow  
Temperature and Moisture Sensitivity Levels (MSL),  
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.  
MC33xxxD enter 33xxx), and review parametrics.  
33290  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
4
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics  
Characteristics noted under conditions of 4.75 V VDD 5.25 V, 8.0 V VBB 18 V, -40°C TC 125°C, unless otherwise  
noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
POWER AND CONTROL  
VDD Sleep State Current  
IDD(SS)  
IDD(Q)  
IBB(SS)  
IBB(Q)  
mA  
mA  
µA  
mA  
V
0.1  
1.0  
50  
Tx = 0.8 VDD, CEN = 0.3 VDD  
VDD Quiescent Operating Current  
Tx = 0.2 VDD, CEN = 0.7 VDD  
VBB Sleep State Current  
VBB = 16 V, Tx = 0.8 VDD, CEN = 0.3 VDD  
VBB Quiescent Operating Current  
1.0  
TX = 0.2 VDD, CEN = 0.7 VDD  
Chip Enable  
Input High-Voltage Threshold (8)  
Input Low-Voltage Threshold (9)  
VIH(CEN)  
VIL(CEN)  
0.7 VDD  
0.3 VDD  
Chip Enable Pull-Down Current (10)  
TX Input Low-Voltage Threshold  
RISO = 510 Ω (11)  
IPD(CEN)  
VIL(Tx)  
2.0  
40  
µA  
V
0.3 x VDD  
TX Input High-Voltage Threshold  
VIH(Tx)  
V
0.7 x VDD  
-40  
RISO = 510 Ω (12)  
TX Pull-Up Current (13)  
IPU(Tx)  
-2.0  
µA  
V
RX Output Low-Voltage Threshold  
VOL(Rx)  
0.2 VDD  
RISO = 510 Ω, TX = 0.2 VDD, Rx Sinking 1.0 mA  
RX Output High-Voltage Threshold  
VOH(Rx)  
V
0.8 VDD  
150  
RISO = 510 Ω, TX = 0.8 VDD, RX Sourcing 250 µA  
Thermal Shutdown (14)  
TLIM  
170  
°C  
Notes  
8. When IBB transitions to >100 µA.  
9. When IBB transitions to <100 µA.  
10. Enable pin has an internal current pull-down. Pull-down current is measured with CEN pin at 0.3 VDD  
11. Measured by ramping TX down from 0.7 VDD and noting TX value at which ISO falls below 0.2 VBB  
12. Measured by ramping TX up from 0.3 VDD and noting the value at which ISO rises above 0.9 VBB  
13. Tx pin has internal current pull-up. Pull-up current is measured with TX pin at 0.7 VDD  
.
.
.
.
14. Thermal Shutdown performance (TLIM) is guaranteed by design but not production tested.  
33290  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
5
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics (Continued)  
Characteristics noted under conditions of 4.75 V VDD 5.25 V, 8.0 V VBB 18 V, -40°C TC 125°C, unless otherwise  
noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
ISO I/O  
Input Low Voltage Threshold  
VIL(ISO)  
V
V
(15)  
(16)  
0.4 x VBB  
RISO = 0 Ω, TX = 0.8 VDD  
Input High Voltage Threshold  
VIH(ISO)  
0.7 x VBB  
RISO = 0 Ω, TX = 0.8 VDD  
Input Hysteresis (17)  
VHys(ISO)  
IPU(ISO)  
0.05 x VBB  
0.1 x VBB  
V
Internal Pull-Up Current  
µA  
R
ISO = ∞ Ω, TX = 0.8 VDD, VISO = 9.0 V, VBB = 18 V  
-5.0  
50  
-140  
Short Circuit Current Limit (18)  
ISC(ISO)  
mA  
1000  
RISO = 0 Ω, TX = 0.4 VDD, VISO = VBB  
Output Low Voltage  
VOL(ISO)  
V
V
RISO = 510 Ω, TX = 0.2 VDD  
0.1 x VBB  
Output High Voltage  
VOH(ISO)  
RISO = ∞ Ω, TX = 0.8 VDD  
0.95 x VBB  
Notes  
15. ISO ramped from 0.8 VBB to 0.4 VBB, Monitor RX, Value of ISO voltage at which RX transitions to 0.3 VDD  
16. ISO ramped from 0.4 VBB to 0.8 VBB, Monitor RX, Value of ISO voltage at which RX transitions to 0.7 VDD  
.
.
17. Input Hysteresis, VHys(ISO) = VIH(ISO) - VIL(ISO)  
18. ISO has internal current limiting.  
.
33290  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
6
ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 4. Dynamic Electrical Characteristics  
Characteristics noted under conditions of 4.75 V VDD 5.25 V, 8.0 V VBB 18 V, -40°C TC 125°C, unless otherwise  
noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
Fall Time (19)  
tfall(ISO)  
µs  
2.0  
RISO = 510 Ω to VBB, CISO = 10 nF to Ground  
ISO Propagation Delay (20)  
tPD(ISO)  
µs  
2.0  
2.0  
High to Low: RISO = 510 Ω, CISO = 500 pF (21)  
Low to High: RISO = 510 Ω, CISO = 500 pF (22)  
Notes  
19. Time required ISO voltage to transition from 0.8 VBB to 0.2 VBB  
.
20. Changes in the value of CISO affect the rise and fall time but have minimal effect on Propagation Delay.  
21. Step TX voltage from 0.2 VDD to 0.8 VDD. Time measured from VIH(ISO) until VISO reaches 0.3 VBB  
.
22. Step TX voltage from 0.8 VDD to 0.2 VDD. Time measured from VIL(ISO) until VISO reaches 0.7 VBB  
.
33290  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
7
ELECTRICAL CHARACTERISTICS  
ELECTRICAL PERFORMANCE CURVES  
ELECTRICAL PERFORMANCE CURVES  
1.2  
0.6  
VOH  
VIH; VDD = 5.25 V, VBB  
18 V  
VIH; VDD = 4.75 V, VBB  
8.0 V  
=
=
1.0  
0.8  
0.6  
0.4  
0.2  
0
0.575  
0.55  
0.525  
0.5  
VDD = 4.75 V, VBB = 8.0 V  
and  
VDD = 5.25 V, VBB = 18 V  
VIL; VDD = 5.25 V, VBB  
18 V  
=
VIL; VDD = 4.75 V, VBB  
8.0 V  
=
VOL  
0.475  
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
TA, AMBIENT TEMPERATURE (°C)  
TA, AMBIENT TEMPERATURE (°C)  
Figure 6. ISO Fall Time vs. Temperature  
Figure 4. ISO Input Threshold/VBB vs. Temperature  
0.95  
0.7  
0.6  
0.5  
0.4  
VDD = 5.25 V, VBB = 18 V  
VDD = 4.75 V, VBB = 8.0 V  
PdH-L  
0.9  
VDD = 5.25 V, VBB = 18 V  
0.85  
0.8  
0.75  
V
DD = 4.75 V, VBB = 8.0 V  
0.3  
0.2  
0.7  
VDD = 5.25 V, VBB = 18 V  
PdL-H  
DD = 4.75 V, VBB = 8.0 V  
100  
TA, AMBIENT TEMPERATURE (°C)  
V
0.65  
-50  
0
50  
150  
-50  
0
50  
100  
150  
TA, AMBIENT TEMPERATURE (°C)  
Figure 5. ISO Output/VBB vs. Temperature  
Figure 7. ISO Propagation Delay vs. Temperature  
33290  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
8
TYPICAL APPLICATIONS  
INTRODUCTION  
TYPICAL APPLICATIONS  
INTRODUCTION  
The 33290 is a serial link bus interface device conforming  
to the ISO 9141 physical bus specification. The device was  
designed for automotive environment usage compliant with  
On-Board Diagnostic (OBD) requirements set forth by the  
California Air Resources Board (CARB) using the ISO K line.  
The device does not incorporate an ISO L line. It provides bi-  
directional half-duplex communications interfacing from a  
microcontroller to the communication bus. The 33290  
incorporates circuitry to interface the digital translations from  
5.0 V microcontroller logic levels to battery level logic and  
from battery level logic to 5.0 V logic levels. The 33290 is built  
using Freescale Semiconductor’s SMARTMOS process and  
is packaged in an 8-pin plastic SOIC.  
FUNCTIONAL DESCRIPTION  
The 33290 transforms 5.0 V microcontroller logic signals  
to battery level logic signals and visa versa. The maximum  
data rate is set by the fall time and the rise time. The fall time  
is set by the output driver. The rise time is set by the bus  
capacitance and the pull-up resistors on the bus. The fall time  
of the 33290 allows data rates up to 150 kbps using a 30  
percent maximum bit time transition value. The serial link  
interface will remain fully functional over a battery voltage  
range of 6.0 to 18 V. The device is parametrically specified  
over a dynamic VBB voltage range of 8.0 to 18 V.  
passive pull-up to VDD, while the CEN input has an internal  
passive pull-down to ground.  
A pull-up to battery is internally provided as well as an  
active data pull-down. The internal active pull-down is  
current-limit-protected against shorts to battery and further  
protected by thermal shutdown. Typical applications have  
reverse battery protection by the incorporation of an external  
510 Ω pull-up resistor and diode to battery.  
Reverse battery protection of the device is provided by  
using a reverse battery blocking diode (“D” in the Simplified  
Application Diagram on page 1). Battery line transient  
protection of the device is provided for by using a 45 V zener  
and a 500 Ω resistor connected to the VBB source as shown  
in the same diagram. Device ESD protection from the  
communication lines exiting the module is through the use of  
the capacitor connected to the VBB device pin and the  
capacitor used in conjunction with the 27 V zener connected  
to the ISO pin.  
Required input levels from the microcontroller are ratio-  
metric with the VDD voltage normally used to power the  
microcontroller. This enhances the 33290’s ability to remain  
in harmony with the RX and TX control input signals of the  
microcontroller. The RX and TX control inputs are compatible  
with standard 5.0 V CMOS circuitry. For fault-tolerant  
purposes the TX input from the microcontroller has an internal  
33290  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
9
PACKAGING  
PACKAGE DIMENSIONS  
PACKAGING  
PACKAGE DIMENSIONS  
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.  
D SUFFIX  
EF SUFFIX (PB-FREE)  
8-PIN  
PLASTIC PACKAGE  
98ASB42564B  
REV. U  
33290  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
10  
REVISION HISTORY  
REVISION HISTORY  
REVISION  
DATE  
DESCRIPTION OF CHANGES  
• Implemented Revision History page  
7/2006  
6.0  
• Converted to Freescale format and updated to the prevailing for and style  
• Added Pb-free suffix EF  
• Removed MC33290EG/R2 and replaced with MCZ33290EG/R2 in the Ordering  
Information block  
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter  
from Maximum Ratings on page 4. Added note with instructions to obtain this information  
from www.freescale.com.  
10/2006  
8/2008  
7.0  
8.0  
• Corrected the Document header information.  
• Updated to the current Freescale form and style.  
33290  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
11  
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MC33290  
Rev 8.0  
8/2008  

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