MC33291 [MOTOROLA]
Eight Output Switch with Serial Peripheral Interface I/O; 八个输出开关，串行外设接口I / O
| 型号： | MC33291 |
| 厂家： | 
MOTOROLA |
| 描述： | Eight Output Switch with Serial Peripheral Interface I/O |
| 文件： | 总24页 (文件大小：634K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33291/D
Rev 2, 11/2002
SEMICONDUCTOR TECHNICAL DATA
33291
Eight Output Switch with Serial
Peripheral Interface I/O
The 33291 device is an eight output, low side power switch with 8-bit serial
input control. The 33291 is a versatile circuit designed for automotive applica-
tions, but is well suited for other environments. The 33291 incorporates
SMARTMOS technology, with CMOS logic, bipolar/MOS analog circuitry,
and DMOS power MOSFETs. The 33291 interfaces directly with a microcon-
troller to control various inductive or incandescent loads.
EIGHT OUTPUT SWITCH
(SPI I/O)
Package Options
The circuit’s innovative monitoring and protection features include: Very
Low Standby Current, SPI Cascade Fault Reporting Capability, Internal 53 V
Clamp on Each Output, Output Specific Diagnostics, Independent Shutdown
of Outputs.
The device is parametrically specified over an ambient temperature range
of -40°C ≤ TA ≤ 125°C and 9.0 V ≤ VPWR ≤ 16 V supply.
DW SUFFIX
PLASTIC PACKAGE
CASE 751E
Features:
• Designed to Operate Over Wide Supply Voltages of 5.5 to 26.5 V
• Interfaces to Microprocessor Using 8-Bit SPI I/O Protocol up to 3.0 MHz
• 1.0 A Peak Current Outputs with Maximum RDS(on) of 1.6 Ω at TJ - 150°C
SOICW (16+4+4)
• Outputs Current Limited to Accommodate In-rush Currents Associated
ORDERING INFORMATION
Temperature
with Switching Incandescent Loads
Device
Package
• Output Voltages Clamped to 53 V During Inductive Switching
• Maximum Sleep Current (IPWR) of 25 µA
• Maximum of 4.0 mA IDD During Operation
Range TA
MC33291DW
SOIC-24
SOIC-24
-40°C to 125°C
-40°C to 125°C
MC33291DWR2
33291 Simplified Application Schematic
+V
BAT
SFPD
V
V
PWR
DD
Output 0
Output 1
SFPD
Output 2
Output 3
Updrain
DMOS
Output
Switches
and
CS
CMOS
Serial
CMOS
Input
Micro-
SCLK
Shift
Logic
controller
Output 4
Output 5
Output 6
Registers
and
Sense
Circuits
SI
Latches
RST
SO
Output 7
GND
This device contains 1266 active transistors.
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© Motorola, Inc. 2002
Freescale Semiconductor, Inc.
V
21
PWR
Output 0
24
Over
Voltage
Regulator
Bias
Voltage
53 V
+
V
DD
GE
OT
SF
OF
16
OVD
Gate
V
RB
SFPD
RST
DD
Control
Outputs 1 to 7
10 µA
15
To Gates
1 to 7
2
SFPD
SFL
CS
SCLK
SI
SO
CSI
CSBI
11 - 14
23
25 µA
22
+
Open
Load
SPI
Interface
Logic
Detect
CS
10 µA
Fault Timers
lLimit
10
+
R
S
Short
Circuit
Detect
–
SCLK
+
10 µA
10 µA
3
SI
Grounds 5-8
17-20
Over
Temperature
Detect
4
9
SO
Serial D/O
Line Driver
From Detectors 1 to 7
Figure 1. 33291 Simplified Block Diagram
FAULT OPERATION
Serial Output (SO) Pin Reports
Over Voltage
Over voltage condition reported
Fault reported by Serial Output (SO) pin
SO pin reports short to battery/supply or over current condition
Over Temperature
Over Current
Output ON, Open Load Fault Not reported
Output OFF, Open Load Fault SO pin reports output OFF open load condition
Device Shutdowns
Over Voltage
Total device shutdown at VPWR = 28 to 36 V. All outputs are latched off while the SPI register is reset (cleared).
Outputs can be turned back on with a new SPI command after VPWR has decayed below 26.5 V.
Over Temperature
Over Current
Only the output experiencing an over temperature condition turns OFF.
Only the output experiencing an over current shuts down at 1.0 to 3.0 A after a 70 to 250 µs delay, with SFPD pin
grounded. All other outputs will continue to operate in a current limit mode, with no shutdown, if the SFPD pin is at
5.0 V (so long as the individual outputs are not experiencing thermal limit conditions).
33291
2
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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1
24
23
22
21
20
19
18
17
16
15
14
13
OP 7
OP 6
SCLK
SI
GND
GND
GND
GND
SO
OP 0
OP 1
RST
VPWR
GND
GND
GND
GND
VDD
2
3
4
5
6
7
8
9
10
11
12
CS
OP 5
OP 4
SFPD
OP 2
OP 3
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Description
Output 7. This pin provides connection to drain of output MOSFET number seven.
Output 6. This pin provides connection to drain of output MOSFET number six.
System Clock. This pin clocks the internal Shift registers of the 33291.
1
OP7
2
OP6
3
SCLK
Serial Input. This pin is for the input of serial instruction data. SI information is read on the falling edge
4
SI
of SCLK.
Ground. This pin provides connection to IC Power Ground and functions as part of heat sinking path.
Ground. This pin provides connection to IC Power Ground and functions as part of heat sinking path.
Ground. This pin provides connection to IC Power Ground and functions as part of heat sinking path.
Ground. This pin provides connection to IC Power Ground and functions as part of heat sinking path.
Serial Output. This pin is the tri-stateable output from the Shift register.
5
6
7
8
9
GND
GND
GND
GND
SO
Chip Select. Whenever this pin is in a logic low state, data can be transferred from the MCU to the 33291
10
CS
through the SI pin and from the 33291 to the MCU through the SO pin.
Output 5. This pin provides connection to drain of output MOSFET number five.
Output 4. This pin provides connection to drain of output MOSFET number four.
Output 3. This pin provides connection to drain of output MOSFET number three.
Output 2. This pin provides connection to drain of output MOSFET number two.
11
12
13
14
OP5
OP4
OP3
OP2
Short Fault Protect Disable. This pin is used to prevent the outputs from latching-OFF because of an
15
SFPD
VDD
over current condition.
Logic Supply.
16
17
18
19
20
21
Ground. This pin provides connection to IC Power Ground and functions as part of heat sinking path.
Ground. This pin provides connection to IC Power Ground and functions as part of heat sinking path.
Ground. This pin provides connection to IC Power Ground and functions as part of heat sinking path.
Ground. This pin provides connection to IC Power Ground and functions as part of heat sinking path.
Output MOSFET Gate Drive Supply.
GND
GND
GND
GND
VPWR
RESET. This pin is active low. It is used to clear the SPI Shift register, thereby setting all output switches
OFF.
22
RST
Output 1. This pin provides connection to drain of output MOSFET number one.
Output 0. This pin provides connection to drain of output MOSFET number zero.
23
24
OP1
OP0
33291
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MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Power Supply Voltage
V
Normal Operation (Steady-State)
Transient Conditions (Note 1)
VPWR(SUS)
VPWR(PK)
- 1.5 to 26.5
- 13 to 60
Logic Supply Voltage (Note 2)
Input Pin Voltage (Note 3)
VDD
VIN
- 0.3 to 7.0
- 0.3 to 7.0
V
V
V
Output Clamp Voltage (Note 4)
VOUT(OFF)
5.0 mA ≤ Iout ≤ 0.5 A
45 to 65
Output Self-Limit Current
IOUT(LIM)
1.0 to 3.0
500
A
mA
V
Continuous Per Output Current (Note 5)
IOUT(CONT)
ESD Voltage (Note 6)
Human Body Model (Note 7)
Machine Model (Note 8)
VESD1
VESD2
2000
200
Output Clamp Energy (Note 9)
Recommended Frequency of SPI Operation
Storage Temperature
ECLAMP
fSPI
50
mJ
3.0
MHz
TSTG
TC
- 55 to 150
- 40 to 125
- 40 to 150
2.0
°C
°C
°C
W
Operating Case Temperature
Operating Junction Temperature
Power Dissipation (TA = 25° C) (Note 10)
TJ
PD
Soldering Temperature (Note 11)
TSOLDER
RθJA
260
°C
Thermal Resistance (Junction-to-Ambient)
Case 751E-04 Package
°C/W
All Outputs ON (Note 12)
Single Output ON (Note 13)
45
60
Notes:
1. Transient capability with external 100 Ω resistor in series with VP pin and supply.
2. Exceeding these limits may cause a malfunction or permanent damage to the device.
3. Exceeding the limits on SCLK, SI, CS, SFPD, or RST pins may cause permanent damage to the device.
4. With output OFF.
5. Continuous output current rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient temperature will
require maximum output current computation using package RθJA
6. ESD data available upon request.
.
7. ESD1 testing is performed in accordance with the Human Body Model (CZap = 200 pF, RZap = 1500 Ω).
8. ESD2 testing is performed in accordance with the Machine Model (CZap = 200pF, RZap = 0 Ω).
9. Maximum output clamp energy capability at 150°C junction temperature using a single non-repetitive pulse method.
10. Maximum power dissipation at indicated junction temperature with no heat sink used.
11. Lead soldering temperature limit is for 10 seconds maximum duration; not designed for immersion soldering; exceeding these limits may
cause malfunction or permanent damage to the device.Contact Motorola Sales Office for device immersion soldering time/temperature limits.
12. Thermal resistance from Junction-to-Ambient with all outputs ON and dissipating equal power.
13. Thermal resistance from Junction -to-Ambient with a single output ON.
33291
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical
values noted reflect the approximate value with VBat = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
Power Input
Supply Voltage Range
Quasi-Functional (Note 14)
Fully Operational
V
VPWR(QF)
VPWR(FO)
VPWR(ON)
IPWR(ON)
5.5
9.0
—
—
9.0
26.5
Supply Current (All Outputs ON, IOUT = 0.5 A)
—
—
1.0
1.0
2.0
2.5
V
Sleep State Supply Current at RST ≤ 0.2 VDD and/or VDD < 0.5 V
µA
Sleep State Output Leakage Current (Per Output, RST = 0)
Over voltage Shutdown
IPWR(SS)
VOV
VOV(HYS)
VDD
—
28
1.0
32
2.5
36
µA
V
Over voltage Shutdown Hysteresis (Note 15)
Logic Supply Voltage
0.2
4.5
0.8
—
1.5
5.5
V
V
Logic Supply Current (Note 16)
RST ≥ 0.7 VDD
IDD
—
—
1.0
—
4.0
25
mA
µA
RST ≤ 0.5 V
Logic Supply Under Voltage Lockout Threshold (Note 17)
Notes:
VDD(UVLO)
2.5
—
3.5
V
14. SPI inputs and outputs operational; Fault status reporting may not be fully operational within this voltage range. Outputs remain operational
somewhat below this VPWR range, but RDS(on) will increase, causing power dissipation to increase. Outputs will re-establish their instructed
state following a VPWR interruption as long as VDD remains non-interrupted.
15. This parameter is guaranteed by design, but it is not production tested.
16. Measured with the RST pin held at a logic high state; outputs can be OFF or ON or in any combination thereof.
17. Device incorporates a power-ON reset function; for VDD less than the Under Voltage Lockout Threshold voltage, all data registers are reset
and all outputs are disabled.
33291
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical
values noted reflect the approximate value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
Power Output
Ω
RDS(ON)
Drain-to-Source ON Resistance (IOUT = 0.5 A, TJ - 25°C)
—
—
—
—
0.6
0.55
2.0
1.2
1.0
VPWR = 5.5 V
VPWR = 9.0 V
VPWR = 13 V
Ω
RDS(ON)
Drain-to-Source ON Resistance (IOUT = 0.5 A, TJ - 150°C)
—
—
—
—
1.2
1.0
3.0
1.6
1.2
V
PWR = 5.5 V
VPWR = 9.0 V
VPWR = 13 V
Output Self-Limiting Current
IOUT(LIM)
A
V
Outputs Programmed ON, VOUT = 0.6 VDD
1.0
2.0
3.0
Output Fault Detect Threshold (Note 18)
Output Programmed OFF
VOUTth(F)
2.5
30
3.0
50
3.5
µA
Output OFF Open Load Detect Current (Note 19)
Output Programmed OFF, VOUT = 0.6 VDD
IOCO
100
V
Output Clamp Voltage
VOK
2.0 mA < IOUT < 200 mA
45
53
0
65
25
µA
Output Leakage Current (VDD < 2.0 V) (Note 20)
IOUT(LKG)
-25
°C
°C
Over Temperature Shutdown (Outputs OFF) (Note 21)
TLIM
155
—
180
10
—
Over Temperature Shutdown Hysteresis (Note 21)
Notes:
TLIM(HYS)
20
18. Output Fault Detect Threshold with outputs programmed OFF. Output fault detect thresholds are the same for output opens and shorts.
19. Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open
load condition when the specific output is commanded to be OFF.
20. Output leakage current measured with the output OFF and at 16 V.
21. This parameter is guaranteed by design, but it is not production tested.
33291
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical
values noted reflect the approximate value with VBAT = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
Digital Interface
Input Logic High Voltage (Note 22)
VIH
VIL
0.7
0
—
—
1.0
0.2
500
20
VDD
VDD
mV
µA
µA
µA
µA
µA
V
Input Logic Low Voltage (Note 22)
Input Logic Threshold Hysteresis (SCLK, RST, and SFPD) (Note 23)
SI Pull-Up Current (SI = 0 V)
VI(Hvs)
ISI
50
0
100
10
10
10
25
10
CS Pull-Up Current (CS = 0 V)
ICSB
ISCLK
IRST
ISFPD
VSOH
0
20
SCLK Pull-Down Current (SCLK = 5.0 V)
RST Pull-Down Current (RST = 5.0 V)
SFPD Pull-Down Current (SFPD = 5.0 V)
SO High State Output Voltage (IOH = 1.0 mA)
0
20
5.0
5.0
50
25
VDD -0.4 V VDD -0.2 V
—
SO Low State Output Voltage (IOL = -1.6 mA)
VSOL
ISOT
CIN
—
-10
—
0.2
0
0.4
10
12
20
V
SO Tri-State Leakage Current (CS = 0.7 VDD, 0 V < VSO < VDD
Input Capacitance (0 V < VDD < 5.5 V) (Note 24)
SO Tn-State Capacitance (0 V < VDD < 5.5 V) (Note 25)
Notes:
)
µA
pF
pF
—
—
CSOT
—
22. Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, RST, and SFPD inputs.
23. Hysteresis is characterized, but it is not production tested.
24. Input capacitance of SI CS, SCLK, RST, and SFPD for 0 V < VDD < 5.5 V. This parameter is guaranteed by design, but it is not production
tested.
25. Tri-state capacitance of SO for 0 V < VDD < 5.5 V. This parameter is guaranteed by design, but it is not production tested.
VIH
RST
0.2 VDD
VIL
VIH
VIL
tw(RST)
CS
0.2 VDD
tw(SCLKH)
tlead
0.7 VDD
tr
tlag
VIH
VIL
SCLK
SI
0.2 VDD
tw(SCLKL)
tSI(hold)
tSI(su)
tf
0.7 VDD
VIH
VIL
Don't Care
Valid
Don't Care
Valid
Don't Care
0.2 VDD
Figure 2. Input Timing Switch Characteristics
33291
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.
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Power Output Timing
Output Rise Time (VPWR = 13 V, RL = 26 Ω) (Note 26)
Output Fall Time (VPWR = 13 V, RL = 26 Ω) (Note 26)
tr
0.4
0.4
1.0
1.0
5.0
5.0
15
20
20
50
50
µs
µs
µs
µs
µs
tf
Output Turn ON Delay Time (VPWR = 13 V, RL = 26 Ω) (Note 27)
Output Turn-OFF Delay Time (VPWR = 13 V, RL = 26 Ω) (Note 28)
tDLY(ON)
tDLY(OFF)
tDLY(SF)
15
Output Short Fault Disable Report Delay (Note 29)
SFPD = 0.2 x VDD
70
70
150
150
250
250
Output OFF Fault Report Delay (Note 30)
SFPD = 0.2 x VDD
tDLY(OFF)
µs
Notes:
26. Output Rise and Fall time respectively measured across a 26 Ω resistive load at 10 to 90 percent, and 90 to 10 percent voltage points.
27. Output Turn ON Delay time measured from 50 percent rising edge of CS to 90 percent of Output OFF voltage (VPWR) with RL = 26 Ω resistive
load.
28. Output Turn OFF Delay time measured from 50 percent rising edge of CS to 10 percent of Output OFF voltage (VPWR) with RL = 26 Ω resistive
load.
29. Propagation time of Short Fault Disable Report measured from 50 percent rising edge of CS to 10 percent Output OFF voltage (VPWR), VPWR
= 6.0 V and SFPD = 2.0 x VDD
.
30. Output OFF Fault Report Delay measured from 50 percent rising edge of CS to 10 percent rising edge of Output OFF voltage (VPWR).
33291
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.
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Digital Interface Timing
Required Low State Duration for Reset (VIL < 0.2 VDD) (Note 31)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required for Setup Time)
SI to Falling Edge of SCLK (Required for Setup Time)
Falling Edge of SCLK to SI (Required for Hold Time)
SO Rise Time (CL = 200 pF)
tW(RST)
tLEAD
—
—
—
—
—
—
—
—
—
—
—
50
50
50
25
25
25
25
—
—
—
—
167
167
167
83
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tLAG
tSI(SU)
tSI(HOLD)
tR(SO)
tF(SO)
83
50
SO Fall Time (CL = 200 pF)
50
SI, CS, SCLK, Incoming Signal Rise Time (Note 32)
SI, CS, SCLK, Incoming Signal Fall Time (Note 32)
Time from Falling Edge of CS to SO Low Impedance (Note 33)
Time from Rising Edge of CS to SO High Impedance (Note 34)
tR(SI)
50
tF(SI)
50
tSO(EN)
tSO(DIS)
tVALID
110
110
Time from Rising Edge of SCLK to SO Data Valid (Note 35)
0.2 VDD < SO > 0.8 VDD, CL = 200 pF
—
65
105
Notes:
31. RST Low duration measured with outputs enabled and going to OFF or disabled condition.
32. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
33. Time required for output status data to be available for use at the SO pin.
34. Time required for output status data to be terminated at the SO pin.
35. Time required to obtain valid data out from SO following the rise of SCLK. See (Note 4).
33291
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Electrical Performance Curves
tr (SI)
tf (SI)
< 50 ns
< 50 ns
0.2 V
V
= 5.0 V
DD
5.0 V
0.7 VDD
50%
SCLK
DD
0
V0H
t
dly(lh)
0.7 VDD
33291
Under
Test
SCLK
SO
0.2 VDD
SO
V0L
V0H
(Low-to-High)
tr (SO)
tf (SO)
C
= 200 pF
t
L
valid
SO
(High-to-Low)
0.7 VDD
0.2 VDD
V0L
t
dly(hl)
SO (Low-to-High) is for an output with internal conditions such that the
low-to-high transition of CS causes the SO output to switch from high
to low.
CL represents the total capacitance of the test fixture and probe.
Figure 3. Valid Data Delay Time and
Valid Time Test Circuit
Figure 5. Valid Data Delay Time and
Valid Time Waveforms
t
t
f(SI)
r(SI)
< 50 ns
90%
< 50 ns
0.7 V
CS
SO
V
= 5.0 V
V
= 2.5 V
Pull-Up
DD
5.0 V
0
DD
10%
0.2 V
DD
t
t
R = 1.0 kΩ
SO(en)
90%
SO(dis)
L
V
Tri-State
33291
(High-to-Low)
Under
Test
CS
SO
10%
tSO(dis)
V0H
C
= 20 pF
L
t
t
SO(en)
10%
SO(dis)
90%
SO
(Low-to-High)
V
Tri-State
1. SO (high-to-low) waveform is for SO output with internal conditions such that
SO output is low except when an output is disabled as a result of detecting a
circuit fault with CS in a High Logic state, e.g. open load.
CL represents the total capacitance of the test fixture and probe.
2. SO (low-to-high) waveform is for SO output with internal conditions such that
SO output is high except when an output is disabled as a result of detecting a
circuit fault with CS in a High Logic state, e.g. shortened load.
Figure 4. Enable and Disable Time Test Circuit
Figure 6. Enable and Disable Time Waveforms
33291
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t
t
f(SI)
r(SI)
< 50 ns
< 50 ns
90%
5.0 V
V
= 5.0 V
V
= 14 V
PWR
DD
50%
CS
10%
0
t
dly(off)
R = 26 Ω
L
14 V
Output Voltage
Waveform 1
33291
10%
Under
Test
Output
V
CS
OL
C
L
14 V
Output Voltage
Waveform 2
90%
V
OL
t
dly(on)
1. tdly(ON) and tdly(OFF) are turn-ON and turn-OFF propagation delay times.
2. Turn-OFF is an output programmed from an ON to an OFF state.
3. Turn-ON is an output programmed from and OFF to an ON state.
CL represents the total capacitance of the test fixture and probe.
Figure 7. Switching Time Test Circuit
Figure 9. Turn-On/Off Waveforms
t
t
f(SI)
r(SI)
V
= 5.0 V
V
= 11 V
PWR
DD
< 50 ns
50%
< 50 ns
5.0 V
0
90%
10%
CS
I
= 2.0 A
L
Output Voltage
Waveform
(Output ON)
V
= 11 V
off
33291
50%
Under
Test
Output
CS
V
I
= 5.0 V
ON
t
dly(off)
C = 20 pF
L
O(CL)
0
50%
Output Current
Waveform
1. t
is the output fault unlatch disable propagation delay time required to
pdly(off)
correctly report an output fault after CS rises. It represents an output command-
ed ON while having an existing output short (over current) to supply.
2. The SFPD pin < 0.2 V
C represents the total capacitance of the test fixture and probe.
L
Figure 8. Output Fault Unlatch Disable
Delay Test Circuit
Figure 10. Output Fault Unlatch Disable
Delay Waveforms
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33291 was conceived, specified, designed, and
management functions. The 33291 directly interfaces to an
developed for automotive applications. It is an eight output low
side power switch having 8-bit serial control. The 33291
incorporates SMARTMOS technology having effective 1.5 µ
CMOS logic, bipolar/MOS analog circuitry, and independent
state of the art double diffused MOS (DMOS) power output
transistors. Many benefits are realized as a direct result of using
this mixed technology. A simplified block diagram delineates
33291 in Figure 1.
MCU, operating at system clock serial frequencies in excess
of 3.0 MHz. It uses a Synchronous Peripheral Interface (SPI) for
control and diagnostic readout. Figure 11 illustrates the basic
SPI configuration between an MCU and one 33291.
MC68HCXX
33291
Microcontroller
MOSI
MISO
SI
Where bipolar devices require considerable control current
for their operation, structured MOS devices, since they are
voltage controlled, require only transient gate charging current
affording a significant decrease in power consumption. The
CMOS capability of the SMARTMOS process allows
significant amounts of logic to be economically incorporated
into the monolithic design. Additionally, the bipolar/MOS analog
circuits embedded within the updrain power DMOS output
transistors monitor and provide fast, independent protection
control functions for each individual output. All outputs have
internal 45 V at 0.5 A independent output voltage clamps to
provide fast inductive turn-off and transient protection.
Shift Register
Shift Register
SO
SCLK
Receive
Buffer
To
Logic
RST
CS
Parallel
Ports
Figure 11. SPI Interface with Microcontroller
The 33291 uses high efficiency updrain power DMOS output
transistors exhibiting very low room temperature drain-to-
The circuit can also be used in a variety of other applications
in the computer, telecommunications, and industrial fields. It is
parametrically specified over an input battery /supply range of
9.0 to 16 V but is designed to operate over a considerably wider
range of 5.5 to 26.5 V. The design incorporates the use of Logic
Level MOSFETs as output devices. These MOSFETs are
sufficiently turned ON with a gate voltage of less than 5.0 V thus
eliminating the need for an internal charge pump. Each output
is identically sized and independent in operation. The efficiency
of each output transistor, at room temperature provides as little
as 9.0 V supply (VPWR), the maximum RDS(on) of an output
source ON resistance values (RDS(on) ≤ 1.0 Ω at 13 V VPWR
)
and dense CMOS control logic. Operational bias currents of
less than 2.0 mA (1.0 mA typical) with any combination of
outputs ON are the result of using this mixed technology and
would not be possible with bipolar structures. To accomplish a
comparable functional feature set using a bipolar structure
approach would result in a device requiring hundreds of
milliamperes of internal bias and control current. This would
represent a very large amount of power to be consumed by the
device itself and not available for load use.
All inputs are compatible with 5.0 V CMOS logic levels,
incorporating negative or inverted logic. Whenever an input is
programmed to a logic low state (<1.0 V) the corresponding low
side switched output being controlled will be active low and
turned ON. Conversely, whenever an input is programmed to a
logic high state (>3.0 V), the output being controlled will be high
and turned OFF.
During operation, the 33291 functions as an eight output
serial switch serving as a microcontroller (MCU) bus expander
and buffer with fault management and fault reporting features.
In doing so, the device directly relieves the MCU of the fault
management functions.
The 33291 directly relieves the MCU of the fault
33291
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SCLK
Parallel Port
CS
SO
SCLK
SI
CS
SO
SCLK
SI
CS
SO
SCLK
SI
CS
SO
SCLK
SI
MISO
IRQ
MC68XX
Microcontroller
SPI
33291
8 Outputs
33291
8 Outputs
33291
8 Outputs
33291
8 Outputs
MOSI
Figure 12. 33291 SPI System Daisy Chain
One main advantage of the 33291 is the serial port. When
coupled to an MCU, it receives ON/OFF commands from the
MCU and in return transmits the drain status of the device’s
output switches. Many devices can be daisy-chained together,
forming a larger system, illustrated in Figure 12.
Note: In this example, only one dedicated MCU parallel port (aside
from the required SPI) is required for chip select to control 32 possible
loads.
to the other in an orderly manner. The master MCU supplies the
system clock signal (top MCU designated the master); the lower
MCU being the slave. It is possible to have a system with more
than one master; however, not at the same time. Only when the
master is not communicating can a slave assume the
mastership and communicate. MCU master control is switched
through the use of the slave select (SS) pin of the MCUs. A
master will become a slave when it detects a logic low state on
its SS pin.
Multiple 33291 devices can also be controlled in a parallel input
fashion using SPI, illustrated in Figure 13. This figure shows a
possible 24 loads being controlled by only three dedicated
parallel MCU ports used for chip select.
These basic examples make the 33291 very attractive for
applications where a large number of loads require efficient
control. To this end, the popular Synchronous Serial Peripheral
Interface (SPI) protocol is incorporated to communicate
efficiently with the MCU.
33291
MOSI
SCLK
SPI System Attributes
SI
SCLK
8 Outputs
8 Outputs
The SPI system is flexible enough to communicate directly
with numerous standard peripherals and MCUs available from
Motorola and other semiconductor manufacturers. SPI reduces
the number of pins necessary for input/output (I/O) on the
33291. It also offers an easy means of expanding the I/O
function using few MCU pins. The SPI system of
CS
MC68XX
Microcontroller
SPI
33291
SI
SCLK
communication consists of the MCU transmitting, in return it
receives one data-bit of information per system clock cycle.
A0
Parallel
Ports
A1
A2
CS
Data-bits of information are simultaneously transmitted by
one pin, Microcontroller Out Serial In (MOSI), and received by
another pin, Microcontroller In Serial Out (MISO), of the MCU.
33291
Some features of SPI are:
8 Outputs
SI
• Full duplex, three-wire synchronous data transfer
• Each microcontroller can be a master or a slave
• Provides write collision flag protection
SCLK
CS
• Provides end of message interrupt flag
• Four I/Os associated with SPI (MOSI, MISO, SCLK, SS)
Figure 13. Parallel Input SPI Control
Drawbacks to SPI are:
• An MCU is required for efficient operational control
• In contrast to parallel input control it Is slower at
performing pulse width modulating (PWM) functions.
Figure 14 illustrates a basic method of controlling multiple
33291 devices using two MCUs. A system can have only one
master MCU at any given instant of time and one or more slave
MCUs. Master control of the system must pass from one MCU
33291
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MC68XX
Microcontroller
SPI
(Master)
33291
CS
SCLK
B0
B1
A0
A1
A2
Parallel
Ports
8 Outputs
8 Outputs
8 Outputs
8-Bit
SO
SI
SCLK
MISO
MOSI
8-Bit
VDD
33291
SS
CS
SCLK
8-Bit
MC68XX
SO
SI
Microcontroller
SPI
(Alternate Master)
Parallel
B0
B1
A0
A1
A2
Ports
33291
CS
SCLK
MISO
MOSI
SCLK
8-Bit
8-Bit
SO
SI
VDD
SS
Figure 14. Multiple MCU SPI Control
33291
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FUNCTIONAL PIN DESCRIPTION
SO Pin
CS Pin
The 33291 receives its MCU communication through the CS
The serial output (SO) pin is the tri-stateable output from the
Shift register. The SO pin remains in a high impedance state
until the CS pin goes to a logic low state. The SO data reports
the drain status, either high or low relative to the previous
command word. The SO pin changes state on the rising edge
of SCLK and reads out on the falling edge of SCLK. When an
output is OFF and not faulted, the corresponding SO data-bit is
a high state. When an output is ON, and there is no fault, the
corresponding data-bit on the SO pin will be a low logic state.
The SI/SO shifting of data follows a first-in-first-out (FIFO)
protocol with both input and output words transferring the MSB
first. Referring to Figure 16, the DO bit is the MSB
pin. Whenever this pin is in a logic low state, data can be
transferred from the MCU to the 33291 by way of the SI pin and
from the 33291 to the MCU through the SO pin. Clocked-in data
from the MCU is transferred from the 33291 Shift register and
latched into the power outputs on the rising edge of the CS
signal. On the falling edge of the CS signal, drain status
information is transferred from the power outputs then loaded
into the Shift register of the device. The CS pin also controls the
output driver of the serial output (SO) pin. Whenever the CS pin
goes to a logic low state, the SO pin output driver is enabled
allowing information to be transferred from the 33291 to the
MCU. To avoid data corruption or the generation of spurious
data, it is essential the high-to-low transition of the CS signal
occur only when SCLK is in a logic low state.
corresponding to Output 7 relative to the previous command
word. The SO pin is not affected by the status of the Reset pin.
RST Pin
SCLK Pin
The 33291 reset (RST) pin is active low. It is used to clear the
SPI Shift register. In doing so, all output switches are set at
OFF. The device situated in the same system with an MCU, the
MCU retains the Reset pin of the device in a logic low state.
Retention ensures all outputs to be OFF until both the VDD and
The system clock (SCLK) pin clocks the internal shift
registers of the 33291. The serial input (SI) pin accepts data into
the Input Shift register on the falling edge of the SCLK signal
while the serial output (SO) pin shifts data information out of the
SO line driver on the rising edge of the SCLK signal. False
clocking of the Shift register must be avoided to guarantee
validity of data. It is essential the SCLK pin be in a logic low
state whenever the chip select bar (CS) pin makes any
transition. For this reason, it is recommended, though not
absolutely necessary, the SCLK pin be kept in a low logic state
as long as the device is not accessed (CS in logic high state).
When CS is in a logic high state, signals at the SCLK and SI
pins are ignored and SO is tri-stated (high impedance). See the
Data Transfer Timing diagram in Figure 16.
VPWR pin voltages are adequate for predictable operation.
Retention of the device Reset pin takes place only upon initial
system power up. After the 33291 is reset, the MCU is ready to
assert system control with all output switches initially OFF.
If the VPWR pin of the 33291 experiences a low voltage,
following normal operation, the MCU should pull the Reset pin
low to shutdown the outputs and clear the input data register.
The Reset pin is active low and has an internal pull-down
incorporated, insuring operational predictability should the
external pull-down of the MCU open circuit. The internal pull-
down is only 25 µA, affording safe and easy interfacing to the
MCU. The Reset pin of the 33291 should be pulled to a logic low
state for a duration of at least 250 ns, ensuring reliable a reset.
SI Pin
This pin is for the input of serial instruction (SI) data. SI is
read on the falling edge of SCLK. A logic high state present on
this pin when the SCLK signal rises will program a specific
output OFF. In turn, the pin turns OFF the specific output on the
rising edge of the CS signal. Conversely, a logic low state
present on the SI pin will program the output ON, In turn, the pin
turns ON the specific output on the rising edge of the CS signal.
VDD
+
RDLY
20 µA
Reset
To program the eight outputs of the 33291 ON or OFF, an 8-
bit serial stream of data is required to be synchronously entered
into the SI pin starting with Output 7, followed by Output 6,
Output 5, and so on, to Output 0. Referring to Figure 16, the DO
bit is the most significant bit (MSB) corresponding to Output 7.
For each rise of the SCLK signal, with CS held in a logic low
state, a data-bit instruction (ON or OFF) is synchronously
loaded into the Shift register per the data-bit SI state. The Shift
register is full after eight bits of information have been entered.
To preserve data integrity, care should be taken to not transition
SI as SCLK transitions from a low-to-high logic state.
MCU
Reset
CDLY
33291L
Figure 15. Power ON Reset
A simple power ON reset delay of the system can be
programmed through the use of an RC network comprised of a
shunt capacitor from the Reset pin to Ground and a resistor to
VDD, illustrated in Figure 15. Care should be exercised ensuring
proper discharge of the capacitor. Careful attention eliminates
adverse delay of the Reset and damage of the MCU if it pulls
the Reset line low, thereby accomplishing initialization for turn
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ON delay. It may be easier to incorporate delay into the
Paralleling of Outputs
software program and use a parallel port pin of the MCU to
control the 33291 Reset pin.
Using MOSFETs as output switches permits connecting any
combination of outputs together. RDS(on) of MOSFETs have an
inherent positive temperature coefficient providing balanced
current sharing between outputs without destructive operation
(bipolar outputs could not be paralleled in this fashion as
thermal run-away would likely occur). The device can even be
operated with all outputs tied together. This mode of operation
may be desirable in the event the application requires lower
power dissipation, or the added capability of switching higher
currents.
SFPD Pin
The Short Fault Protect Disable (SFPD) pin is used to
prevent the outputs from latching-off due to an over current
condition. This feature provides control of incandescent lamp
loads where in-rush currents exceed the device’s analog
current limits. Essentially the SFPD pin determines whether the
33291 output(s) will instantly shutdown upon sensing an output
short or remain ON in a current limiting mode of operation until
the output short is removed or thermal shutdown is reached. If
the SFPD pin is tied to VDD = 5.0 V the 33291 output(s) will
remain ON in a current limited mode of operation upon
encountering a load short to supply or over current condition.
When the SFPD pin is grounded, a short circuit will immediately
shut down only the output affected. Other outputs not having a
fault condition will operate normally. The short circuit operation
is addressed in more detail later.
Performance of parallel operation results in a corresponding
decrease in RDS(on) while the Output OFF Open Load Detect
Currents and the Output Current Limits increase
correspondingly (by a factor of eight if all outputs are
paralleled). Less than 125 mΩ RDS(on) at 25°C with current
limiting of eight to 24 A will result if all outputs are paralleled
together. There will be no change in the over voltage detect or
the OFF output threshold voltage range. The advantage of
paralleling outputs within the same 33291 affords the existence
of minimal RDS(on) and output clamp voltage variation between
Power Consumption
outputs.
The 33291 has extremely low power consumption in both the
operating and standby modes. In the standby, or Sleep mode,
with VDD ≤ 2.0 V, the current consumed by the VPWR pin is less
Typically, the variation of RDS(on) between outputs of the
same device is less than 0.5 percent. The variation in clamp
voltages, potentially affecting dynamic current sharing, is less
than five percent. Paralleling outputs from two or more different
devices is possible, but it is not recommended. There is no
guarantee the RDS(on) and clamp voltage of the two devices will
than 25 µA. In the operating mode, the current drawn by the
VDD pin is less than 4.0 mA (1.0 mA typical) while the current
drawn at the VPWR pin is 2.0 mA maximum (1.0 mA typical).
During normal operation, turning outputs ON increases IPWR by
match. System level thermal design analysis and verification
should be conducted whenever paralleling outputs; particularly
where different devices are involved.
only 20 µA per output. Each output experiencing a soft short
(over current conditions just under the current limit), adds 0.5
mA to the IPWR current.
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Figure 16. Data Transfer Timing
33291
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FAULT LOGIC OPERATION
Introduction
The shutdown following an Over Temperature condition is
independent of the system clock and other logic signal. Each
independent output shuts down at 155°C to 185°C. When an
output shuts down due to an Over Temperature Fault, no other
outputs are affected. The MCU recognizes the fault since the
output was commanded to be ON and the status word indicates
it is OFF. A maximum hysteresis of 20°C ensures an adequate
time delay between output turn OFF and recovery. This avoids
a very rapid turn ON and turn OFF of the device around the
Over Temperature threshold. When the temperature falls below
the recovery level for the Over Temperature Fault, the device
will turn on only if the Command Word during the next write
cycle indicates the output should be turned ON.
The MCU can perform a parity check of the fault logic
operation by comparing the command 8-bit word to the status
8-bit word. Assume after system reset, the MCU first sends an
8-bit command word to the 33291. This word is called
Command Word 1. Each output to be turned ON will have its
corresponding data bit low. Refer to the data transfer timing
illustration in Figure 16.
As Command Word 1 is being written into the Shift register
of the 33291, a status word is being simultaneously written and
received by the MCU. However, the word being received by the
MCU is the status of the previous write word to the 33291,
Status Word 0. If the command word of the MCU is written a
second time (Command Word 2 = Command Word 1), the word
received by the MCU, Status Word 2, is the status of Command
Word 1. The timing diagram illustrated in Figure 16 depicts this
operation. Status Word 2 is then compared with Command
Word 1. The MCU will Exclusive OR Status Word 2 with
Command Word 1 to determine if the two words are identical. If
the two words are identical, faults do not exist. The timing
between the two write words must be greater than 100 µs to
receive proper drain status. The system data bus integrity may
be tested by writing two like words to the 33291 within a few
microseconds of each other.
Over Voltage Fault
An Over Voltage condition on the VPWR pin causes the 33291
to shut down all outputs until the over voltage condition is
removed and the device is re-programmed by the SPI. The over
voltage threshold on the VPWR pin is specified as 28 V to 36 V
with 1.0 V typical hysteresis. Following the over voltage
condition, the next write cycle sends the SO pin the
hexadecimal word $FF (all ones) indicating all outputs are
turned off. In this way, potentially dangerous timing problems
are avoided and the MCU reset routine ensures an orderly
startup of the loads. The 33291 does not detect an over voltage
on the VDD pin. Other external circuitry, such as the Motorola
33161 Universal Voltage Monitor, is necessary to accomplish
this function.
Initial System Setup Timing
The MCU can monitor two kinds of faults:
1. Communication errors on the data bus
2. Actual faults of the output loads
Output OFF Open Load Fault
An Output OFF Open Load Fault is the detection and
reporting of an open load when the corresponding output is
disabled (input in a logic high state). To understand the
operation of the Open Load Fault detect circuit, see Figure 17.
The Output OFF Open Load Fault is detected by comparing the
drain voltage of the specific MOSFET output to an internally
generated reference. Each output has one dedicated
comparator for this purpose.
After initial system start up or reset, the MCU will write one
word to the 33291. If the word is repeated within approximately
five microseconds of the first word, the word received by the
MCU, at the end of the repeated word, serves as a confirmation
of data bus integrity (1). At start up, the 33291 will take 25 to 100
µs before a repeat of the first word should be repeated at least
100 µs later to verify the status of the outputs.
The SO of the 33291 will indicate any one of four faults. The
four possible faults are:
1. Over Temperature
2. Output OFF Open Fault
3. Short Fault (over current)
4. VPWR Over Voltage Fault.
33291
VPWR
Low = Fault
RL
MOSFET OFF
+
–
Output
All of these faults, with the exception of the Over Voltage Fault,
are output specific. Over Temperature Detect, Output OFF
Open Detect, and Output Short Detect are dedicated to each
output separately such that the outputs are independent in
operation. A VPWR Over Voltage Detect is a global nature
causing all outputs to be turned OFF.
50 µA
VThres
2.5 to 3.5 V
Over Temperature Fault
Figure 17. Output OFF Open Load Fault
Patent pending Over Temperature Detect and shutdown
circuits are specifically incorporated for each individual output.
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An Output OFF Open Load Fault is indicates when the output
3. The output thermal limit of the device is sensed, and
when attained, causes only the specific faulted output to
be latched OFF, allowing all remaining outputs to operate
normally.
voltage is less than the Output Threshold Voltage (VThres) of 0.6
to 0.8 x VDD. Since the 33291 outputs function as switches,
during normal operation, each MOSFET output should either be
completely turned ON or OFF. By design, the threshold voltage
was selected to be between the ON and OFF voltage of the
MOSFET. During normal operation, the ON state VDS voltage of
the MOSFET is less than the threshold voltage and the OFF
state VDS voltage is greater than the threshold voltage. This
Each of the three protection mechanisms are incorporated in
their output providing robust independent output operation.
The analog current limit circuit is always active, monitoring
the output drain current. An over current condition causes the
gate control circuitry to reduce the gate-to-source voltage
imposed on the output MOSFET, re-establishing the load
current in compliance with current limit (1.0 to 3.0 A) range.
Time required for the current limit circuitry to act is less than
20 µs. Therefore, currents higher than 1.0 to 3.0 A will never be
seen for more than 20 µs (a typical duration is 10 µs). If the
current of an output attempts to exceed the predetermined limit
of 1.0 to 3.0 A (2.0 A nominal), the VDS voltage will exceed the
design approach provides using the same threshold
comparator for Output Open Load Detect in the OFF state and
Short Circuit Detect in the ON state. See Figure 18 for an
understanding of the Short Circuit Detect circuit. With
V
DD = 5.0 V, an OFF state output voltage of less than 3.0 V will
be detected as an Output OFF Open Load Fault while voltages
greater than 4.0 V will not be detected as a fault.
The 33291 has an internal pull-down current source of
50 µA, illustrated in Figure 17 between the MOSFET drain and
ground. This current source prevents the output from floating up
to VPWR if there is an open load or internal wire bond failure. The
internal comparator compares the drain voltage with a
reference voltage, VThres (0.6 to 0.8 x VDD). If the output voltage
is less than this reference voltage, the 33291 will declare the
condition to be an open load fault.
VThres voltage and the over current comparator will be tripped,
illustrated in Figure 18.
33291
VPWR
High = Fault
RL
MOSFET ON
During steady-state operation, the minimum load resistance
(RL) required to prevent false fault reporting during normal
operation can be located using the following equation:
+
–
Output
Digital
V
–
Therefore, the load resistance necessary to prevent false open
+
Analog
ref
load fault reporting is (using Ohm’s Law) equal to 92 kΩ or less.
During output switching, especially with capacitive loads, a
false output OFF Open Load Fault may be triggered. To prevent
this false fault from being reported an internal fault filter in the
range of 25 to 100 µs is incorporated. The duration in which a
false fault may be reported is a function of the load impedance
(RL,CL,LL), RDS(on), and COUT of the MOSFET as well as the
supply voltage (VPWR). The rising edge of CS triggers a built-in
fault delay timer which must time-out (25 or 100 µs) before the
fault comparator is enabled to detect at faulted threshold. The
circuit automatically returns to normal operation once the
condition causing the Open Load Fault is removed.
VThres
2.5 to 3.5 V
Figure 18. Short Circuit Detect and
Analog Current Limiting Circuit
The status of SFPD determines whether the 33291 will shut
down immediately, or continue to operate in an analog current
limited mode until either the short circuit (over current) condition
is removed or thermal shutdown is reached.
Shorted Load Fault
A short load, or over current fault can be caused by any
output being shorted directly to supply, or an output
experiencing a current greater than the current limit.
Grounding the SFPD pin enables the short fault protection
shutdown circuitry. Consider a load short (output short to
supply) occurring on an output before, during, and after output
turn ON. When the CS signal rises to the high logic state, the
corresponding output is turned ON, activating a delay timer.
The duration of the delay timer is 70 to 250 µs. If the short circuit
takes place before the output is turned ON, the delay
experienced is the entire 70 µs to 250 µs followed by shutdown.
If the short occurs during the delay time, the shutdown still
occurs after the delay time has elapsed. However, if the short
circuit occurs after the delay time, shutdown is immediate
(within 20 µs after sensing). The purpose of the delay timer is to
prevent false faults from being reported when switching
capacitive loads.
There are three safety circuits progressively in operation
during load short conditions providing system protection. They
are:
1. The output current of the device is monitored in an
analog fashion using a SENSEFET approach and
current limited.
2. The output current of the device is sensed by monitoring
the MOSFET drain voltage.
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If the SFPD pin is at 5.0 V, or VDD, an output will not be
Sometimes both a delay period greater than 70 to 250 µs
(current limiting of the output) followed by an immediate over
current shutdown is necessary. This can be accomplished by
programming the SFPD pin to 5.0 V for the extended delay
period, allowing the outputs to remain ON in a current limited
mode, then grounding it to accomplish the immediate shutdown
after a period of time. Additional external circuitry is required to
implement this type of function. An MCU parallel output port can
be devoted to controlling the SFPD voltage during and after the
delay period, is often a much better method. In either case, care
should be taken to execute the SFPD start-up routine every
time start-up or reset occurs.
disabled when an over current is detected. The specific output
will, within 5.0 to 10 µs of encountering the short circuit, go into
an analog current limited mode. This feature is especially useful
when switching incandescent lamp loads, where high in-rush
currents experienced during startup last for 10 to 20
milliseconds.
Each output of the 33291 has its own over current shutdown
circuitry. Over temperature, and the over voltage faults are not
affected by the SFPD pin’s state.
Both load current sensing and output voltage sensing are
incorporated for Short Fault detection with actual detection
occurring slightly after the onset of current limit. The current
limit circuitry incorporates a SENSEFET approach to
measure the total drain current. This calls for the current
through a small number of cells in the power MOSFET to be
measured and the result multiplied by a constant, giving the
total current. Wherein output shutdown circuitry measures the
drain-to-source voltage, shutting down the output if its threshold
(VThres) is exceeded.
Under Voltage Shutdown
An under voltage VDD condition will result in the global
shutdown of all outputs. The under voltage threshold is between
2.5 V and 3.5 V. When VDD goes below the threshold, all
outputs are turned OFF, thereby resetting the Serial Output
Data register to indicate the same.
An under voltage condition at the VPWR pin will not cause
output shutdown and reset. When VPWR is between 5.5 V and
Short fault detection is accomplished by sensing the output
voltage and comparing it to VThres. The lowest VThres requires
9.0 V, the outputs will operate per the command word.
However, the status as reported by the SO pin may not be
accurate below 9.0 V VPWR. Proper operation at VPWR voltages
a voltage of 2.5 V to be sensed. For an enabled output, with
V
DD = 5.0 ± 0.5 V, an output voltage in excess of 3.5 V will be
below 5.5 V are not be guaranteed.
detected as a short, or over current condition, while voltages
less than 2.5 V will not be detected as shorts.
Deciphering Fault Type
Over Current Recovery
The 33291 SO pin can be used to determine what kind of
system fault has occurred. With eight outputs having open load,
over current, over temperature, and over voltage faults; a total
of 25 different faults are possible. The SO status word received
by the MCU will be compared with the word sent to the 33291
during the previous write cycle. For a specific output, if the SO
bit compares with the corresponding SI bit of the previous word;
the output is operating normal with no fault. Only when the SO
bit and previous word SI bit differ is there a fault indicated. If the
two words are not the same, the MCU should be programmed
to determine which output or outputs are faulted.
If the SFPD pin is in a high logic state, the circuit returns to
normal operation automatically after the short circuit is removed
(unless thermal shutdown has occurred).
If the SFPD pin is grounded and over current shutdown
occurs, removing the short circuit will result in the output
remaining OFF until the next write cycle. If the short circuit is not
removed, the output will turn ON for the delay time (70 to 250
µs) and then turn OFF for every write cycle commanding a turn
ON.
If, for a specific output, the initial SI command bit were logic
high, the output would be programmed to be off; if, upon the
next command word being entered, a logic low came back on
SO, for that specific output’s corresponding bit, an output-off
open-load fault would be indicated. The resulting SO bit, for that
specific output, would be different from that entered during the
previous word for that SI bit, indicating the fault. The eight
output-off open-load faults are therefore most easily detected.
SFPD Pin Voltage Selection
Since the voltage condition of the SFPD pin controls the
activation of the short fault protection (i.e., shutdown) mode
equally for all eight outputs, the load having the longest duration
of in-rush current determines what voltage (state) the SFPD pin
should be. Usually if at least one load is, an incandescent lamp
for example, the in-rush current on that input will be
milliseconds in duration. Therefore, setting SFPD at 5.0 V will
prevent shutdown of the output due to the in-rush current. The
system relies only on the over temperature shutdown to protect
the outputs and the loads. The 33291 was designed to switch
GE194 incandescent lamps, or equivalents, with the SFPD pin
in a grounded state. Considerably larger lamps can be switched
with the SFPD pin held in a high logic state.
If for a specific output, the initial SI command bit were a logic
low, calling for the output to be programmed on; upon the next
word command being entered, the corresponding bit came
back with a logic high on SO, an output over current fault would
be indicated. An over current fault is always reported by the SO
output and is independent of the logic state existing on the
SFPD pin. When the SFPD pin is in a logic high state, an over
current condition will be reported on the SO pin. However,
33291
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limiting output current is in effect and the output is permitted to
operate if the over current condition does not drive output into
an over temperature fault. An over temperature fault will
shutdown the specific output effected for the duration of the
over temperature condition.
transistors from avalanching by causing the transient energy to
be dissipated in the linear mode. See Figure 19. The total
energy clamped (EJ) can be calculated by multiplying the
current area under the current curve (IA) times the clamp
voltage (VCL) times the duration the clamp is active (t).
Over current and over temperature faults are often related.
Turning the effected output switches OFF and waiting for some
time to allow the output to cool down should make these types
of faults go away. Soft over current faults can sometimes be
determined over hard short faults and over temperature faults
by observing the time required for the device to recover.
However, in general over current and over temperature faults
can not be differentiated in normal application usage.
Characterization of the output clamps, using a single pulse
non-repetitive method at 0.5 A, indicate the maximum energy to
be 50 mJ at 150°C junction temperature per output. See Figure
19.
Drain-to-Source Clamp
Voltage (VCL = 65 V)
An advantage of the synchronous serial output is multiple
faults can be detected with only one (SO) pin being used for
fault status reporting.
Drain Voltage
Drain Current
If VPWR experiences an over voltage condition, all outputs
(ID = 0.5A)
Clamp Energy
(EJ = IA x VCL x t)
will immediately be turned OFF and remain latched off. A new
command word is required to turn the outputs back on following
an over voltage condition.
VPWR
Output Voltage Clamping
Drain-to-Source ON
Voltage (VDS(on)
)
Current
Area (I )
Each output of the 33291 incorporates an internal voltage
clamp to provide fast turn-off and transient protection of the
output. Each clamp independently limits the drain to source
voltage to 53 V at drain currents of 0.5 A and keeps the output
A
Time
GND
Figure 19. Output Voltage Clamping
THERMAL CHARACTERIZATION
The battery voltage in the thermal model represents the
ambient temperature the device and PC board are subjected to.
The IPWR current source represents the total power dissipation
and is calculated by totalling the power dissipation of each
individual output transistor. This is easily accomplished by
knowing RDS(on) and load current of the individual outputs.
Thermal Model
Logic functions take up a very small area of the die and
generate negligible power. In contrast, the output transistors
take up most of the die area and are the primary contributors of
power generation. The thermal model illustrated in Figure 20
was developed for the 33291 mounted on a typical PC board.
The model is accurate for both steady state and transient
thermal conditions. The components RD0 through RD7 represent
the steady state thermal resistance of the silicon die for
transistor outputs 0 through 7, while CD0 through CD7 represent
the corresponding thermal capacitance of the silicone die
translator outputs and plastic. The device area and die
thickness determine the values of these specific components.
Very satisfactory steady state and transient results are
experienced with this thermal model. Tests indicate the model
accuracy to have less than 10 percent error. Output interaction
with an adjacent output is believed to be the main contributor to
the thermal inaccuracy. Tests indicate little or no detectable
thermal affects caused by distant output transistors isolated by
one or more other outputs. Tests were conducted with the
device mounted on a typical PC board placed horizontally in a
33 cubic inch still air enclosure. The PC board was made of FR4
material measuring 2.5 by 2.5 inches, having double sided
circuit traces of 1.0 ounce copper soldered to each device pin.
The board temperature was measured with thermal couple
soldered to the board surface one inch away from the center of
the device. The ambient temperature of the enclosure was
measured with a second thermal couple located over the center
of one inch distance from device.
The thermal impedance of the package from the internal
mounting flag to the outside environment is represented by the
terms Rpkg and Cpkg. The steady state thermal resistance of
leads and the PC board make up the steady state package
thermal resistance, Rpkg. The thermal capacitance of the
package is made up of the combined capacitance of the flag
and the PC board. The mode compound was not modeled as a
specific component but it is factored into the other overall
component values.
33291
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Thermal Performance
(34°C/W with all outputs dissipating equal power 0 and the
thermal resistance from junction-to-PC board (Rjunction-board) to
be 30°C/W (board temperature, measure one inch from device
center). The junction-to-heatsink lead resistance was found
again to approximate 10°C/W. Devoting additional PC board
metal around the heatsinking pins for this package improved
the Rpkg from 33° to 31°C/W.
Figure 20 illustrates the worst case thermal component
parameters values for the 33291 in the 20-pin plastic power DIP
and the SOP-24 wide body surface mount package. Pins 5, 6,
15, and 16 of the power DIP package are connected directly to
the lead frame flag. The parameter values indicated take into
account adjacent output combinations. The characterization
was conducted over power dissipation levels of 0.7 to 17 W.
The junction-to-ambient temperature thermal resistance was
found to be 37°C/W with a single output active (31°C/W with all
outputs dissipating equal power) and in conjunction with this,
The total power dissipation available is dependent on the
number of outputs enabled at any one time. At 25°C the RDS(on)
in 450 mΩ with a coefficient of 6500 ppm/°C. For the junction
temperature to remain below 150°C, the maximum available
power dissipation must decrease as the ambient temperature
increases. Figures 21 and 22 depict the per output limit of
current at ambient temperatures necessary when one, four, or
eight outputs are enable ON. Figure 23 illustrates how the
the thermal resistance from junction to PC board (Rjunction-board
)
was found to be 27°C/W (board temperature, measure one inch
from device center). Additionally, the thermal resistance from
junction-to-heatsink lead was found to approximate 10°C/W.
Devoting additional PC board metal around the heatsinking
pins improved Rpkg from 30° to 28° C/W.
RDS(on) output value is affected by junction temperature.
The SOP-24 package has pins 5, 6, 7, 8, 17, 18, 19 and 20of
the package connected directly to the lead frame flag.
Characterization was conducted in the same manner as with
the DIP package. The junction-to-ambient temperature
resistance was found to be 40°C/W with a single output active
Junction Temperature Node
V
- T (C°)
D
D
(Volts represent Die Surface Temperature)
Output 0
Output 1
Output 2
Output 6
R
Output 7
C
C
C
C
C
d7
R
R
R
d2
R
d0
d1
d2
d6
d0
d1
d6
d7
Flag Temperature Node
I
(Steady State or Transient)
PWR
(1.0 A = 1.0 W of Device Power Dissipation)
R
= R
+R
C
= C + C
flag PC Board
pkg
leads
PC Board
pkg
Ambient Temperature Node
= T (C°)
Rdx
(Ω)*
Cdx
(F)*
Rpkg
(Ω)*
Cpkg
(F)*
V
A
A
Package
(1.0 V = 1°C Ambient Temperature)
20 Pin Dip
SOP-24L
7.0
0.002
30
0.2
7.0
0.002
33
0.15
* Ω = °C/W, F = W s/°C, I
= W, and V = °C
A
PWR
Figure 20. Thermal Model (Electrical Equivalent)
33291
22
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3.0
2.5
2.0
1.5
1.0
1.0
VPWR = 13 V
1 Output ON (37°C/W)
RDS(on)@150°C=0.8Ω
TJ =150°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
V
DD = 5.0 V
I
OUT = 0.5 A
4 Outputs ON (32°C/W)
8 Outputs ON (31°C/W)
0.5
0
-50 -25
0
25
50 75 100 125 150
-50 -25
0
25
50 75 100 125 150
TA, Ambient Temperature (C°)
TJ Junction Temperature (°C)
Figure 21. Maximum DIP Package Steady State
Output Current vs. Ambient Temperature
Figure 23. Maximum Output ON Resistance vs. Junction
Temperature
2.5
1 Output ON (40°C/W)
RDS(on)@150°C=0.8Ω
2.0
TJ =150°C
4 Outputs ON (35°C/W)
1.5
1.0
8 Outputs ON (34°C/W)
0.5
0
-50 -25
0
25
50 75 100 125 150
TA Ambient Temperature (C°)
Figure 22. Maximum SOP Package Steady State Output
Current vs. Ambient Temperature
33291
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PACKAGE DIMENSIONS
DW SUFFIX
PLASTIC PACKAGE
CASE 751E-04
SOP (16+4+4)L
-A-
NOTES:
24
13
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
-B- 12X P
4. MAXIMUM MOLDPROTRUSION0.15 (0.006)
PER SIDE.
M
M
0.010 (0.25)
B
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
1
12
24X D
J
F
MILLIMETERS
MAX
INCHES
M
S
S
0.010 (0.25) T A
B
DIM MIN
MIN MAX
A
B
C
D
F
15.25 15.54 0.601 0.612
7.40
2.35
0.35
0.41
7.60 0.292 0.299
2.65 0.093 0.104
0.49 0.014 0.019
0.90 0.016 0.035
R X 45
°
G
J
1.27 BSC
0.050 BSC
0.32 0.009 0.013
0.29 0.005 0.011
0.23
C
K
K
M
P
R
0.13
-T-
0
8
0
°
8
°
°
°
M
10.05 10.55 0.395 0.415
0.25 0.75 0.010 0.029
SEATING
PLANE
22X G
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MC33291/D
相关型号：
MC33291DW/R2
1A BUF OR INV BASED PRPHL DRVR, PDSO24, 7.50 X 15.40 MM, 1.27 PITCH, LEAD FREE, MS-013AD, SOIC-24
NXP
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