DSP56362P_技术文档

Document Number: DSP56366

Rev. 3.1, 1/2007

Freescale Semiconductor

Data Sheet: Technical Data

DSP56366

24-Bit Audio Digital Signal Processor

Contents

1 Overview

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

2 Signal/Connection Descriptions. . . . . . . . . 2-1

3 Specifications. . . . . . . . . . . . . . . . . . . . . . . . 3-1

4 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

5 Design Considerations . . . . . . . . . . . . . . . . 5-1

6 Ordering Information . . . . . . . . . . . . . . . . . . 6-1

A Power Consumption Benchmark . . . . . . . . A-1

The DSP56366 supports digital audio applications

requiring sound field processing, acoustic equalization,

and other digital audio algorithms. The DSP56366 uses

the high performance, single-clock-per-cycle DSP56300

core family of programmable CMOS digital signal

processors (DSPs) combined with the audio signal

processing capability of the Freescale Symphony™ DSP

family, as shown in Figure 1-1. This design provides a

two-fold performance increase over Freescale’s popular

56000 Symphony family of DSPs while retaining code

compatibility. Significant architectural enhancements

include a barrel shifter, 24-bit addressing, instruction

cache, and direct memory access (DMA). The

DSP56366 offers 120 million instructions per second

(MIPS) using an internal 120 MHz clock at 3.3 V.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Overview

Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

Used to indicate a signal that is active when pulled low (For example, the RESET pin is active

when low.)

“asserted”

Means that a high true (active high) signal is high or that a low true (active low) signal is low

Means that a high true (active high) signal is low or that a low true (active low) signal is high

“deasserted”

Examples:

Signal/Symbol

Logic State

Signal State

Voltage*

True

False

True

Asserted

Deasserted

Asserted

V_IL/ V_OL

V_IH/ V_OH

V_IL/ V_OL

False

Deasserted

Note: *Values for V_IL, V_OL, V_IH, and V_OHare defined by individual product specifications.

4

8

2

16

5

1

6

MEMORY EXPANSION AREA

PROGRAM

RAM/INSTR.

CACHE

3K x 24

PROGRAM ROM

40K x 24

DAX

(SPDIF Tx.)

INTER-

HOST

INTER-

FACE

SHI

INTER-

FACE

ESAI

INTER-

FACE

TRIPLE

TIMER

X MEMORY

RAM

13K X 24

Y MEMORY

RAM

7K X 24

ROM

FACE

ROM

32K x 24

8K x 24

ESAI_1

Bootstrap ROM

192 x 24

PERIPHERAL

EXPANSION AREA

ADDRESS

GENERATION

UNIT

YAB

EXTERNAL

ADDRESS

BUS

SWITCH

18

XAB

PAB

DAB

ADDRESS

SIX CHANNELS

DMA UNIT

24-BIT

DSP56300

Core

DRAM &

SRAM BUS

INTERFACE

&

10

CONTROL

I - CACHE

DDB

YDB

XDB

PDB

GDB

EXTERNAL

DATA BUS

SWITCH

24

INTERNAL

DATA

BUS

SWITCH

DATA

POWER

MNGMNT

PLL

DATA ALU

24X24 56 56-BIT MAC

TWO 56-BIT

ACCUMULATORS

BARREL SHIFTER

+

->

PROGRAM

DECODE

CONTROLLER

PROGRAM

ADDRESS

GENERATOR

PROGRAM

INTERRUPT

CONTROLLER

4

JTAG

CLOCK

GENERATOR

OnCE™

24 BITS BUS

EXTAL

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

PINIT/NMI

Figure 1-1 DSP56366 Block Diagram

DSP56366 Technical Data, Rev. 3.1

1-2

Freescale Semiconductor

Overview

1.1

Features

1.1.1

DSP56300 Modular Chassis

•

120 Million Instructions Per Second (MIPS) with an 120 MHz clock at 3.3V.

Object Code Compatible with the 56K core.

Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic

support.

•

Program Control with position independent code support and instruction cache support.

Six-channel DMA controller.

PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors

i

(1 to 16) and power saving clock divider (2 : i=0 to 7). Reduces clock noise.

•

Internal address tracing support and OnCE™ for Hardware/Software debugging.

JTAG port.

Very low-power CMOS design, fully static design with operating frequencies down to DC.

STOP and WAIT low-power standby modes.

1.1.2

On-chip Memory Configuration

•

7Kx24 Bit Y-Data RAM and 8Kx24 Bit Y-Data ROM.

13Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM.

40Kx24 Bit Program ROM.

3Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 1K of Program RAM may be used as

Instruction Cache or for Program ROM patching.

•

2Kx24 Bit from Y Data RAM and 5Kx24 Bit from X Data RAM can be switched to Program RAM

resulting in up to 10Kx24 Bit of Program RAM.

1.1.3

Off-chip Memory Expansion

•

External Memory Expansion Port.

Off-chip expansion up to two 16M x 24-bit word of Data memory.

Off-chip expansion up to 16M x 24-bit word of Program memory.

Simultaneous glueless interface to SRAM and DRAM.

1.1.4

Peripheral Modules

2

•

Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I S, Sony,

AC97, network and other programmable protocols.

2

•

Serial Audio Interface I(ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I S,

Sony, AC97, network and other programmable protocols

The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT support HCKR and

HCKT (high frequency clocks)

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

1-3

Overview

2

•

Serial Host Interface (SHI): SPI and I C protocols, multi master capability, 10-word receive FIFO,

support for 8, 16 and 24-bit words.

•

Byte-wide parallel Host Interface (HDI08) with DMA support.

Triple Timer module (TEC).

Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF, IEC958,

CP-340 and AES/EBU digital audio formats.

•

Pins of unused peripherals (except SHI) may be programmed as GPIO lines.

1.1.5

Packaging

•

144-pin plastic LQFP package.

1.2

Documentation

Table 1-1 lists the documents that provide a complete description of the DSP56366 and are required to

design properly with the part. Documentation is available from a local Freescale distributor, a Freescale

semiconductor sales office, a Freescale Literature Distribution Center, or through the Freescale DSP home

page on the Internet (the source for the latest information).

Table 1-1 DSP56366 Documentation

Document Name

Description

Order Number

DSP56300 Family Manual

Detailed description of the 56300-family architecture and

the 24-bit core processor and instruction set

DSP56300FM

DSP56366 User’s Manual

Detailed description of memory, peripherals, and

interfaces

DSP56366UM

DSP56366 Product Brief

Brief description of the chip

DSP56366P

DSP56366

DSP56366 Technical Data Sheet

(this document)

Electrical and timing specifications; pin and package

descriptions

IBIS Model

Input Output Buffer Information Specification.

For software or simulation

models, contact sales or

go to www.freescale.com.

DSP56366 Technical Data, Rev. 3.1

1-4

Freescale Semiconductor

2 Signal/Connection Descriptions

2.1

Signal Groupings

The input and output signals of the DSP56366 are organized into functional groups, which are listed in

Table 2-1 and illustrated in Figure 2-1.

The DSP56366 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special

notice for this feature is added to the signal descriptions of those inputs.

Table 2-1 DSP56366 Functional Signal Groupings

Number of

Signals

Detailed

Description

Functional Group

Power (V_CC

)

20

18

3

Table 2-2

Table 2-3

Table 2-4

Table 2-5

Table 2-6

Table 2-7

Table 2-8

Table 2-9

Table 2-10

Table 2-11

Table 2-12

Table 2-13

Table 2-14

Table 2-15

Ground (GND)

Clock and PLL

Address bus

Data bus

18

24

10

5

Port A¹

Bus control

Interrupt and mode control

HDI08

Port B²

16

5

SHI

ESAI

Port C³

Port E⁴

Port D⁵

12

6

ESAI_1

Digital audio transmitter (DAX)

Timer

2

1

JTAG/OnCE Port

4

1

2

3

4

5

Port A is the external memory interface port, including the external address bus, data bus, and control signals.

Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals.

Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.

Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.

Port D signals are the GPIO port signals which are multiplexed with the DAX signals.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

2-1

OnCE™ ON-CHIP EMULATION/

PORT A ADDRESS BUS

JTAG PORT

TDI

DSP56366

A0-A17

VCCA (3)

TCK

TDO

GNDA (4)

TMS

PORT A DATA BUS

PARALLEL HOST PORT (HDI08)

D0-D23

VCCD (4)

HAD(7:0) [PB0-PB7]

HAS/HA0 [PB8]

Port B

GNDD (4)

HA8/HA1 [PB9]

PORT A BUS CONTROL

HA9/HA2 [PB10]

HRW/HRD [PB11]

HDS/HWR [PB12]

HCS/HA10 [PB13]

HOREQ/HTRQ [PB14]

AA0-AA2/RAS0-RAS2

CAS

RD

WR

TA

HACK/HRRQ [PB15]

VCCH

BR

GNDH

BG

BB

SERIAL AUDIO INTERFACE (ESAI)

SCKT[PC3]

VCCC (2)

GNDC (2)

FST [PC4]

Port C

HCKT [PC5]

INTERRUPT AND

MODE CONTROL

SCKR [PC0]

FSR [PC1]

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

HCKR [PC2]

SDO0[PC11] / SDO0_1[PE11]

SDO1[PC10] / SDO1_1[PE10]

SDO2/SDI3[PC9] / SDO2_1/SDI3_1[PE9]

SDO3/SDI2[PC8] / SDO3_1/SDI2_1[PE8]

SDO4/SDI1 [PC7]

PLL AND CLOCK

SDO5/SDI0 [PC6]

EXTAL

PINIT/NMI

PCAP

SERIAL AUDIO INTERFACE(ESAI_1)

SCKT_1[PE3]

FS T_1[PE4]

VCCP

GNDP

Port E

SCKR_1[PE0]

FSR_1[PE1]

QUIET POWER

VCCQH (3)

SDO4_1/SDI1_1[PE7]

SDO5_1/SDI0_1[PE6]

VCCS (2)

VCCQL (4)

GNDQ (4)

GNDS (2)

SPDIF TRANSMITTER (DAX)

Port D

SERIAL HOST INTERFACE (SHI)

MOSI/HA0

ADO [PD1]

ACI [PD0]

SS/HA2

MISO/SDA

TIMER 0

TIO0 [TIO0]

SCK/SCL

HREQ

Figure 2-1 Signals Identified by Functional Group

DSP56366 Technical Data, Rev. 3.1

2-2

Freescale Semiconductor

2.2

Power

Table 2-2 Power Inputs

Description

Power Name

V_CCP

PLL Power—V_CCPis V_CCdedicated for PLL use. The voltage should be well-regulated and the input

should be provided with an extremely low impedance path to the V_CCpower rail. There is one V_CCPinput.

V_CCQL(4)

Quiet Core (Low) Power—V_CCQLis an isolated power for the internal processing logic. This input must

be tied externally to all other chip power inputs. The user must provide adequate external decoupling

capacitors. There are four V_CCQLinputs.

V_CCQH(3)

V_CCA(3)

V_CCD(4)

V_CCC(2)

V_CCH

Quiet External (High) Power—V_CCQHis a quiet power source for I/O lines. This input must be tied

externally to all other chip power inputs. The user must provide adequate decoupling capacitors. There are

three V_CCQHinputs.

Address Bus Power—V_CCAis an isolated power for sections of the address bus I/O drivers. This input

must be tied externally to all other chip power inputs. The user must provide adequate external decoupling

capacitors. There are three V_CCAinputs.

Data Bus Power—V_CCDis an isolated power for sections of the data bus I/O drivers. This input must be

tied externally to all other chip power inputs. The user must provide adequate external decoupling

capacitors. There are four V_CCDinputs.

Bus Control Power—V_CCCis an isolated power for the bus control I/O drivers. This input must be tied

externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

There are two V_CCCinputs.

Host Power—V_CCHis an isolated power for the HDI08 I/O drivers. This input must be tied externally to all

other chip power inputs. The user must provide adequate external decoupling capacitors. There is one

V_CCHinput.

V_CCS(2)

SHI, ESAI, ESAI_1, DAX and Timer Power —V_CCSis an isolated power for the SHI, ESAI, ESAI_1, DAX

and Timer. This input must be tied externally to all other chip power inputs. The user must provide

adequate external decoupling capacitors. There are two V_CCSinputs.

2.3

Ground

Table 2-3 Grounds

Description

Ground Name

GND_P

PLL Ground—GND_Pis a ground dedicated for PLL use. The connection should be provided with an

extremely low-impedance path to ground. V_CCPshould be bypassed to GND_Pby a 0.47 μF capacitor

located as close as possible to the chip package. There is one GND_Pconnection.

GND_Q(4)

GND_A(4)

Quiet Ground—GND_Qis an isolated ground for the internal processing logic. This connection must be

tied externally to all other chip ground connections. The user must provide adequate external decoupling

capacitors. There are four GND_Qconnections.

Address Bus Ground—GND_Ais an isolated ground for sections of the address bus I/O drivers. This

connection must be tied externally to all other chip ground connections. The user must provide adequate

external decoupling capacitors. There are four GND_Aconnections.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

2-3

Table 2-3 Grounds (continued)

Description

Ground Name

GND_D(4)

Data Bus Ground—GND_Dis an isolated ground for sections of the data bus I/O drivers. This connection

must be tied externally to all other chip ground connections. The user must provide adequate external

decoupling capacitors. There are four GND_Dconnections.

GND_C(2)

GND_H

Bus Control Ground—GND_Cis an isolated ground for the bus control I/O drivers. This connection must

be tied externally to all other chip ground connections. The user must provide adequate external

decoupling capacitors. There are two GND_Cconnections.

Host Ground—GND_his an isolated ground for the HD08 I/O drivers. This connection must be tied

externally to all other chip ground connections. The user must provide adequate external decoupling

capacitors. There is one GND_Hconnection.

GND_S(2)

SHI, ESAI, ESAI_1, DAX and Timer Ground—GND_Sis an isolated ground for the SHI, ESAI, ESAI_1,

DAX and Timer. This connection must be tied externally to all other chip ground connections. The user

must provide adequate external decoupling capacitors. There are two GND_Sconnections.

2.4

Clock and PLL

Table 2-4 Clock and PLL Signals

State

during

Reset

Signal

Name

Type

Signal Description

EXTAL

Input

External Clock Input—An external clock source must be connected to EXTAL in order

to supply the clock to the internal clock generator and PLL.

This input cannot tolerate 5 V.

PCAP

Input

PLL Capacitor—PCAP is an input connecting an off-chip capacitor to the PLL filter.

Connect one capacitor terminal to PCAP and the other terminal to V_CCP

.

If the PLL is not used, PCAP may be tied to V_CC, GND, or left floating.

PINIT/NMI

PLL Initial/Nonmaskable Interrupt—During assertion of RESET, the value of

PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,

determining whether the PLL is enabled or disabled. After RESET de assertion and

during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a

negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized

to internal system clock.

This input cannot tolerate 5 V.

2.5

External Memory Expansion Port (Port A)

When the DSP56366 enters a low-power standby mode (stop or wait), it releases bus mastership and

tri-states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0–AA2/RAS2, RD, WR, BB, CAS.

DSP56366 Technical Data, Rev. 3.1

2-4

Freescale Semiconductor

2.5.1

External Address Bus

Table 2-5 External Address Bus Signals

State

during

Reset

Signal

Name

Type

Signal Description

A0–A17

Output

Tri-stated Address Bus—When the DSP is the bus master, A0–A17 are active-high outputs

that specify the address for external program and data memory accesses.

Otherwise, the signals are tri-stated. To minimize power dissipation, A0–A17 do not

change state when external memory spaces are not being accessed.

2.5.2

External Data Bus

Table 2-6 External Data Bus Signals

State

during

Reset

Signal

Name

Type

Signal Description

D0–D23

Input/Output

Tri-stated Data Bus—When the DSP is the bus master, D0–D23 are active-high,

bidirectional input/outputs that provide the bidirectional data bus for external

program and data memory accesses. Otherwise, D0–D23 are tri-stated.

2.5.3

External Bus Control

Table 2-7 External Bus Control Signals

State during

Reset

Signal Name

Type

Signal Description

AA0–AA2/

RAS0–RAS2

Output

Tri-stated

Address Attribute or Row Address Strobe—When defined as AA, these

signals can be used as chip selects or additional address lines. When defined

as RAS, these signals can be used as RAS for DRAM interface. These signals

are tri-statable outputs with programmable polarity.

CAS

Output

Column Address Strobe— When the DSP is the bus master, CAS is an

active-low output used by DRAM to strobe the column address. Otherwise, if the

bus mastership enable (BME) bit in the DRAM control register is cleared, the

signal is tri-stated.

RD

Output

Tri-stated

Read Enable—When the DSP is the bus master, RD is an active-low output

that is asserted to read external memory on the data bus (D0-D23). Otherwise,

RD is tri-stated.

WR

Write Enable—When the DSP is the bus master, WR is an active-low output

that is asserted to write external memory on the data bus (D0-D23). Otherwise,

WR is tri-stated.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

2-5

Table 2-7 External Bus Control Signals (continued)

State during

Signal Description

Reset

Signal Name

Type

TA

Input

Ignored Input Transfer Acknowledge—If the DSP is the bus master and there is no external

bus activity, or the DSP is not the bus master, the TA input is ignored. The TA

input is a data transfer acknowledge (DTACK) function that can extend an

external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be

added to the wait states inserted by the BCR by keeping TA deasserted. In

typical operation, TA is deasserted at the start of a bus cycle, is asserted to

enable completion of the bus cycle, and is deasserted before the next bus cycle.

The current bus cycle completes one clock period after TA is asserted

synchronous to the internal system clock. The number of wait states is

determined by the TA input or by the bus control register (BCR), whichever is

longer. The BCR can be used to set the minimum number of wait states in

external bus cycles.

In order to use the TA functionality, the BCR must be programmed to at least

one wait state. A zero wait state access cannot be extended by TA deassertion,

otherwise improper operation may result. TA can operate synchronously or

asynchronously, depending on the setting of the TAS bit in the operating mode

register (OMR).

TA functionality may not be used while performing DRAM type accesses,

otherwise improper operation may result.

BR

Output

Bus Request—BR is an active-low output, never tri-stated. BR is asserted

when the DSP requests bus mastership. BR is deasserted when the DSP no

longer needs the bus. BR may be asserted or deasserted independent of

whether the DSP56366 is a bus master or a bus slave. Bus “parking” allows BR

to be deasserted even though the DSP56366 is the bus master. (See the

description of bus “parking” in the BB signal description.) The bus request hold

(BRH) bit in the BCR allows BR to be asserted under software control even

though the DSP does not need the bus. BR is typically sent to an external bus

arbitrator that controls the priority, parking, and tenure of each master on the

same external bus. BR is only affected by DSP requests for the external bus,

never for the internal bus. During hardware reset, BR is deasserted and the

arbitration is reset to the bus slave state.

(deasserted)

DSP56366 Technical Data, Rev. 3.1

2-6

Freescale Semiconductor

Table 2-7 External Bus Control Signals (continued)

State during

Signal Description

Reset

Signal Name

Type

BG

Input

Ignored Input Bus Grant—BG is an active-low input. BG is asserted by an external bus

arbitration circuit when the DSP56366 becomes the next bus master. When BG

is asserted, the DSP56366 must wait until BB is deasserted before taking bus

mastership. When BG is deasserted, bus mastership is typically given up at the

end of the current bus cycle. This may occur in the middle of an instruction that

requires more than one external bus cycle for execution.

For proper BG operation, the asynchronous bus arbitration enable bit (ABE) in

the OMR register must be set.

BB

Input/Output

Input

Bus Busy—BB is a bidirectional active-low input/output. BB indicates that the

bus is active. Only after BB is deasserted can the pending bus master become

the bus master (and then assert the signal again). The bus master may keep

BB asserted after ceasing bus activity regardless of whether BR is asserted or

deasserted. This is called “bus parking” and allows the current bus master to

reuse the bus without rearbitration until another device requires the bus. The

deassertion of BB is done by an “active pull-up” method (i.e., BB is driven high

and then released and held high by an external pull-up resistor).

For proper BB operation, the asynchronous bus arbitration enable bit (ABE) in

the OMR register must be set.

BB requires an external pull-up resistor.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

2-7

2.6

Interrupt and Mode Control

The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.

After RESET is deasserted, these inputs are hardware interrupt request lines.

Table 2-8 Interrupt and Mode Control

State

Signal Name

Type

during

Reset

Signal Description

MODA/IRQA

Input

Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low

Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the

initial chip operating mode during hardware reset and becomes a level-sensitive or

negative-edge-triggered, maskable interrupt request input during normal instruction

processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating

modes, latched into the OMR when the RESET signal is deasserted. If the processor is

in the stop standby state and the MODA/IRQA pin is pulled to GND, the processor will

exit the stop state.

This input is 5 V tolerant.

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

Input

Mode Select B/External Interrupt Request B—MODB/IRQB is an active-low

Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects the

initial chip operating mode during hardware reset and becomes a level-sensitive or

negative-edge-triggered, maskable interrupt request input during normal instruction

processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating

modes, latched into OMR when the RESET signal is deasserted.

This input is 5 V tolerant.

Mode Select C/External Interrupt Request C—MODC/IRQC is an active-low

Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC selects the

initial chip operating mode during hardware reset and becomes a level-sensitive or

negative-edge-triggered, maskable interrupt request input during normal instruction

processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating

modes, latched into OMR when the RESET signal is deasserted.

This input is 5 V tolerant.

Mode Select D/External Interrupt Request D—MODD/IRQD is an active-low

Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD selects the

initial chip operating mode during hardware reset and becomes a level-sensitive or

negative-edge-triggered, maskable interrupt request input during normal instruction

processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating

modes, latched into OMR when the RESET signal is deasserted.

This input is 5 V tolerant.

Reset—RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed

in the Reset state and the internal phase generator is reset. The Schmitt-trigger input

allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When

the RESET signal is deasserted, the initial chip operating mode is latched from the

MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during

power up. A stable EXTAL signal must be supplied while RESET is being asserted.

This input is 5 V tolerant.

DSP56366 Technical Data, Rev. 3.1

2-8

Freescale Semiconductor

2.7

Parallel Host Interface (HDI08)

The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The

HDI08 supports a variety of standard buses and can be directly connected to a number of industry standard

microcomputers, microprocessors, DSPs, and DMA hardware.

Table 2-9 Host Interface

State during

Signal Name

Type

Signal Description

Reset

H0–H7

Input/

GPIO

Host Data—When HDI08 is programmed to interface a nonmultiplexed host

output

disconnected bus and the HI function is selected, these signals are lines 0–7 of the

bidirectional, tri-state data bus.

HAD0–HAD7

PB0–PB7

Input/

output

GPIO

Host Address/Data—When HDI08 is programmed to interface a

disconnected multiplexed host bus and the HI function is selected, these signals are lines

0–7 of the address/data bidirectional, multiplexed, tri-state bus.

Input, output, or

disconnected

GPIO

Port B 0–7—When the HDI08 is configured as GPIO, these signals are

disconnected individually programmable as input, output, or internally disconnected.

The default state after reset for these signals is GPIO disconnected.

These inputs are 5 V tolerant.

HA0

Input

GPIO

Host Address Input 0—When the HDI08 is programmed to interface a

disconnected nonmultiplexed host bus and the HI function is selected, this signal is line 0

of the host address input bus.

HAS/HAS

GPIO

Host Address Strobe—When HDI08 is programmed to interface a

disconnected multiplexed host bus and the HI function is selected, this signal is the host

address strobe (HAS) Schmitt-trigger input. The polarity of the address

strobe is programmable, but is configured active-low (HAS) following reset.

PB8

Input, output, or

disconnected

GPIO

Port B 8—When the HDI08 is configured as GPIO, this signal is individually

disconnected programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant.

HA1

HA8

PB9

Input

GPIO

Host Address Input 1—When the HDI08 is programmed to interface a

disconnected nonmultiplexed host bus and the HI function is selected, this signal is line 1

of the host address (HA1) input bus.

GPIO

Host Address 8—When HDI08 is programmed to interface a multiplexed

disconnected host bus and the HI function is selected, this signal is line 8 of the host

address (HA8) input bus.

Input, output, or

disconnected

GPIO

Port B 9—When the HDI08 is configured as GPIO, this signal is individually

disconnected programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

2-9

Table 2-9 Host Interface (continued)

State during

Signal Name

Type

Signal Description

Reset

HA2

Input

GPIO

Host Address Input 2—When the HDI08 is programmed to interface a

disconnected non-multiplexed host bus and the HI function is selected, this signal is line 2

of the host address (HA2) input bus.

HA9

Input

GPIO

Host Address 9—When HDI08 is programmed to interface a multiplexed

disconnected host bus and the HI function is selected, this signal is line 9 of the host

address (HA9) input bus.

PB10

Input, Output, or

Disconnected

GPIO

Port B 10—When the HDI08 is configured as GPIO, this signal is

disconnected individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant.

HRW

Input

GPIO

Host Read/Write—When HDI08 is programmed to interface a

disconnected single-data-strobe host bus and the HI function is selected, this signal is the

Host Read/Write (HRW) input.

HRD/

HRD

GPIO

Host Read Data—When HDI08 is programmed to interface a

disconnected double-data-strobe host bus and the HI function is selected, this signal is the

host read data strobe (HRD) Schmitt-trigger input. The polarity of the data

strobe is programmable, but is configured as active-low (HRD) after reset.

PB11

Input, Output, or

Disconnected

GPIO

Port B 11—When the HDI08 is configured as GPIO, this signal is

disconnected individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant.

HDS/

HDS

Input

GPIO

Host Data Strobe—When HDI08 is programmed to interface a

disconnected single-data-strobe host bus and the HI function is selected, this signal is the

host data strobe (HDS) Schmitt-trigger input. The polarity of the data strobe

is programmable, but is configured as active-low (HDS) following reset.

HWR/

HWR

GPIO

Host Write Data—When HDI08 is programmed to interface a

disconnected double-data-strobe host bus and the HI function is selected, this signal is the

host write data strobe (HWR) Schmitt-trigger input. The polarity of the data

strobe is programmable, but is configured as active-low (HWR) following

reset.

PB12

HCS

Input, output, or

disconnected

GPIO

Port B 12—When the HDI08 is configured as GPIO, this signal is

disconnected individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant.

Input

GPIO

Host Chip Select—When HDI08 is programmed to interface a

disconnected nonmultiplexed host bus and the HI function is selected, this signal is the

host chip select (HCS) input. The polarity of the chip select is

programmable, but is configured active-low (HCS) after reset.

DSP56366 Technical Data, Rev. 3.1

2-10

Freescale Semiconductor

Table 2-9 Host Interface (continued)

State during

Signal Name

Type

Signal Description

Reset

HA10

Input

GPIO

Host Address 10—When HDI08 is programmed to interface a multiplexed

disconnected host bus and the HI function is selected, this signal is line 10 of the host

address (HA10) input bus.

PB13

Input, output, or

disconnected

GPIO

Port B 13—When the HDI08 is configured as GPIO, this signal is

disconnected individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant.

HOREQ/

HOREQ

Output

GPIO

Host Request—When HDI08 is programmed to interface a single host

disconnected request host bus and the HI function is selected, this signal is the host

request (HOREQ) output. The polarity of the host request is programmable,

but is configured as active-low (HOREQ) following reset. The host request

may be programmed as a driven or open-drain output.

HTRQ/

HTRQ

GPIO

Transmit Host Request—When HDI08 is programmed to interface a

disconnected double host request host bus and the HI function is selected, this signal is

the transmit host request (HTRQ) output. The polarity of the host request is

programmable, but is configured as active-low (HTRQ) following reset. The

host request may be programmed as a driven or open-drain output.

PB14

Input, output, or

disconnected

GPIO

Port B 14—When the HDI08 is configured as GPIO, this signal is

disconnected individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant.

HACK/

HACK

Input

GPIO

Host Acknowledge—When HDI08 is programmed to interface a single

disconnected host request host bus and the HI function is selected, this signal is the host

acknowledge (HACK) Schmitt-trigger input. The polarity of the host

acknowledge is programmable, but is configured as active-low (HACK) after

reset.

HRRQ/

HRRQ

Output

GPIO

Receive Host Request—When HDI08 is programmed to interface a double

disconnected host request host bus and the HI function is selected, this signal is the

receive host request (HRRQ) output. The polarity of the host request is

programmable, but is configured as active-low (HRRQ) after reset. The host

request may be programmed as a driven or open-drain output.

PB15

Input, output, or

disconnected

GPIO

Port B 15—When the HDI08 is configured as GPIO, this signal is

disconnected individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

2-11

2.8

Serial Host Interface

2

The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I C mode.

Table 2-10 Serial Host Interface Signals

Signal

Name

State during

Reset

Signal Type

Signal Description

SCK

Input or

output

Tri-stated

SPI Serial Clock—The SCK signal is an output when the SPI is configured as a

master and a Schmitt-trigger input when the SPI is configured as a slave. When the

SPI is configured as a master, the SCK signal is derived from the internal SHI clock

generator. When the SPI is configured as a slave, the SCK signal is an input, and

the clock signal from the external master synchronizes the data transfer. The SCK

signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal

is not asserted. In both the master and slave SPI devices, data is shifted on one

edge of the SCK signal and is sampled on the opposite edge where data is stable.

Edge polarity is determined by the SPI transfer protocol.

SCL

Input or

output

Tri-stated

I²C Serial Clock—SCL carries the clock for I²C bus transactions in the I²C mode.

SCL is a Schmitt-trigger input when configured as a slave and an open-drain output

when configured as a master. SCL should be connected to V_CCthrough a pull-up

resistor.

This signal is tri-stated during hardware, software, and individual reset. Thus, there

is no need for an external pull-up in this state.

This input is 5 V tolerant.

MISO

SDA

Input or

output

Tri-stated

SPI Master-In-Slave-Out—When the SPI is configured as a master, MISO is the

master data input line. The MISO signal is used in conjunction with the MOSI signal

for transmitting and receiving serial data. This signal is a Schmitt-trigger input when

configured for the SPI Master mode, an output when configured for the SPI Slave

mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted.

An external pull-up resistor is not required for SPI operation.

Input or

open-drain

output

I²C Data and Acknowledge—In I²C mode, SDA is a Schmitt-trigger input when

receiving and an open-drain output when transmitting. SDA should be connected to

V

_CCthrough a pull-up resistor. SDA carries the data for I²C transactions. The data

in SDA must be stable during the high period of SCL. The data in SDA is only

allowed to change when SCL is low. When the bus is free, SDA is high. The SDA

line is only allowed to change during the time SCL is high in the case of start and

stop events. A high-to-low transition of the SDA line while SCL is high is a unique

situation, and is defined as the start event. A low-to-high transition of SDA while

SCL is high is a unique situation defined as the stop event.

This signal is tri-stated during hardware, software, and individual reset. Thus, there

is no need for an external pull-up in this state.

This input is 5 V tolerant.

MOSI

Input or

output

Tri-stated

SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI is the

master data output line. The MOSI signal is used in conjunction with the MISO

signal for transmitting and receiving serial data. MOSI is the slave data input line

when the SPI is configured as a slave. This signal is a Schmitt-trigger input when

configured for the SPI Slave mode.

DSP56366 Technical Data, Rev. 3.1

2-12

Freescale Semiconductor

Table 2-10 Serial Host Interface Signals (continued)

Signal

Name

State during

Signal Type

Signal Description

Reset

HA0

Input

I²C Slave Address 0—This signal uses a Schmitt-trigger input when configured for

the I²C mode. When configured for I²C slave mode, the HA0 signal is used to form

the slave device address. HA0 is ignored when configured for the I²C master mode.

This signal is tri-stated during hardware, software, and individual reset. Thus, there

is no need for an external pull-up in this state.

This input is 5 V tolerant.

SS

Input

Tri-stated

SPI Slave Select—This signal is an active low Schmitt-trigger input when

configured for the SPI mode. When configured for the SPI Slave mode, this signal

is used to enable the SPI slave for transfer. When configured for the SPI master

mode, this signal should be kept deasserted (pulled high). If it is asserted while

configured as SPI master, a bus error condition is flagged. If SS is deasserted, the

SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance

state.

HA2

Input

I²C Slave Address 2—This signal uses a Schmitt-trigger input when configured for

the I²C mode. When configured for the I²C Slave mode, the HA2 signal is used to

form the slave device address. HA2 is ignored in the I²C master mode.

This signal is tri-stated during hardware, software, and individual reset. Thus, there

is no need for an external pull-up in this state.

This input is 5 V tolerant.

HREQ

Input or

Output

Tri-stated

Host Request—This signal is an active low Schmitt-trigger input when configured

for the master mode but an active low output when configured for the slave mode.

When configured for the slave mode, HREQ is asserted to indicate that the SHI is

ready for the next data word transfer and deasserted at the first clock pulse of the

new data word transfer. When configured for the master mode, HREQ is an input.

When asserted by the external slave device, it will trigger the start of the data word

transfer by the master. After finishing the data word transfer, the master will await

the next assertion of HREQ to proceed to the next transfer.

This signal is tri-stated during hardware, software, personal reset, or when the

HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external pull-up

in this state.

This input is 5 V tolerant.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

2-13

2.9

Enhanced Serial Audio Interface

Table 2-11 Enhanced Serial Audio Interface Signals

Signal

Name

State during

Reset

Signal Type

Signal Description

HCKR

Input or output

GPIO

High Frequency Clock for Receiver—When programmed as an input, this

disconnected signal provides a high frequency clock source for the ESAI receiver as an

alternate to the DSP core clock. When programmed as an output, this signal

can serve as a high-frequency sample clock (e.g., for external digital to analog

converters [DACs]) or as an additional system clock.

PC2

Input, output, or

disconnected

GPIO

Port C 2—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

HCKT

Input or output

GPIO

High Frequency Clock for Transmitter—When programmed as an input,

disconnected this signal provides a high frequency clock source for the ESAI transmitter as

an alternate to the DSP core clock. When programmed as an output, this

signal can serve as a high frequency sample clock (e.g., for external DACs)

or as an additional system clock.

PC5

FSR

Input, output, or

disconnected

GPIO

Port C 5—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Input or output

GPIO

Frame Sync for Receiver—This is the receiver frame sync input/output

disconnected signal. In the asynchronous mode (SYN=0), the FSR pin operates as the

frame sync input or output used by all the enabled receivers. In the

synchronous mode (SYN=1), it operates as either the serial flag 1 pin

(TEBE=0), or as the transmitter external buffer enable control (TEBE=1,

RFSD=1).

When this pin is configured as serial flag pin, its direction is determined by the

RFSD bit in the RCCR register. When configured as the output flag OF1, this

pin will reflect the value of the OF1 bit in the SAICR register, and the data in

the OF1 bit will show up at the pin synchronized to the frame sync in normal

mode or the slot in network mode. When configured as the input flag IF1, the

data value at the pin will be stored in the IF1 bit in the SAISR register,

synchronized by the frame sync in normal mode or the slot in network mode.

PC1

Input, output, or

disconnected

GPIO

Port C 1—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

DSP56366 Technical Data, Rev. 3.1

2-14

Freescale Semiconductor

Table 2-11 Enhanced Serial Audio Interface Signals (continued)

State during

Signal

Name

Signal Type

Signal Description

Reset

FST

Input or output

GPIO

Frame Sync for Transmitter—This is the transmitter frame sync input/output

disconnected signal. For synchronous mode, this signal is the frame sync for both

transmitters and receivers. For asynchronous mode, FST is the frame sync for

the transmitters only. The direction is determined by the transmitter frame

sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR).

PC4

Input, output, or

disconnected

Port C 4—When the ESAI is configured as GPIO, this signal is individually

programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SCKR

Input or output

GPIO

Receiver Serial Clock—SCKR provides the receiver serial bit clock for the

disconnected ESAI. The SCKR operates as a clock input or output used by all the enabled

receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the

synchronous mode (SYN=1).

When this pin is configured as serial flag pin, its direction is determined by the

RCKD bit in the RCCR register. When configured as the output flag OF0, this

pin will reflect the value of the OF0 bit in the SAICR register, and the data in

the OF0 bit will show up at the pin synchronized to the frame sync in normal

mode or the slot in network mode. When configured as the input flag IF0, the

data value at the pin will be stored in the IF0 bit in the SAISR register,

synchronized by the frame sync in normal mode or the slot in network mode.

PC0

Input, output, or

disconnected

GPIO

Port C 0—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SCKT

PC3

Input or output

GPIO

Transmitter Serial Clock—This signal provides the serial bit rate clock for the

disconnected ESAI. SCKT is a clock input or output used by all enabled transmitters and

receivers in synchronous mode, or by all enabled transmitters in

asynchronous mode.

Input, output, or

disconnected

GPIO

Port C 3—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO5

SDI0

Output

Input

GPIO

Serial Data Output 5—When programmed as a transmitter, SDO5 is used to

disconnected transmit data from the TX5 serial transmit shift register.

GPIO

Serial Data Input 0—When programmed as a receiver, SDI0 is used to

disconnected receive serial data into the RX0 serial receive shift register.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

2-15

Table 2-11 Enhanced Serial Audio Interface Signals (continued)

State during

Signal

Name

Signal Type

Signal Description

Reset

PC6

Input, output, or

disconnected

GPIO

Port C 6—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO4

SDI1

PC7

Output

Input

GPIO

Serial Data Output 4—When programmed as a transmitter, SDO4 is used to

disconnected transmit data from the TX4 serial transmit shift register.

GPIO

Serial Data Input 1—When programmed as a receiver, SDI1 is used to

disconnected receive serial data into the RX1 serial receive shift register.

Input, output, or

disconnected

GPIO

Port C 7—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO3/SD

O3_1

Output

Input

GPIO

Serial Data Output 3—When programmed as a transmitter, SDO3 is used to

disconnected transmit data from the TX3 serial transmit shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 3.

SDI2/

GPIO

Serial Data Input 2—When programmed as a receiver, SDI2 is used to

SDI2_1

disconnected receive serial data into the RX2 serial receive shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input 2.

PC8/PE8 Input, output, or

disconnected

GPIO

Port C 8—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

When enabled for ESAI_1 GPIO, this is the Port E 8 signal.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO2/

SDO2_1

Output

Input

GPIO

Serial Data Output 2—When programmed as a transmitter, SDO2 is used to

disconnected transmit data from the TX2 serial transmit shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 2.

SDI3/SDI3

_1

GPIO

Serial Data Input 3—When programmed as a receiver, SDI3 is used to

disconnected receive serial data into the RX3 serial receive shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input 3.

PC9/PE9 Input, output, or

disconnected

GPIO

Port C 9—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

When enabled for ESAI_1 GPIO, this is the Port E 9 signal.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

DSP56366 Technical Data, Rev. 3.1

2-16

Freescale Semiconductor

Table 2-11 Enhanced Serial Audio Interface Signals (continued)

State during

Signal

Name

Signal Type

Signal Description

Reset

SDO1/

Output

GPIO

Serial Data Output 1—SDO1 is used to transmit data from the TX1 serial

SDO1_1

disconnected transmit shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 1.

PC10/

PE10

Input, output, or

disconnected

GPIO

Port C 10—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

When enabled for ESAI_1 GPIO, this is the Port E 10 signal.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO0/SD

O0_1

Output

GPIO

disconnected transmit shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 0.

Serial Data Output 0—SDO0 is used to transmit data from the TX0 serial

PC11/

PE11

Input, output, or

disconnected

GPIO

Port C 11—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

When enabled for ESAI_1 GPIO, this is the Port E 11 signal.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

2-17

2.10 Enhanced Serial Audio Interface_1

Table 2-12 Enhanced Serial Audio Interface_1 Signals

Signal

Name

State during

Signal Type

Signal Description

Reset

FSR_1

Input or output

GPIO

Frame Sync for Receiver_1—This is the receiver frame sync input/output

disconnected signal. In the asynchronous mode (SYN=0), the FSR pin operates as the

frame sync input or output used by all the enabled receivers. In the

synchronous mode (SYN=1), it operates as either the serial flag 1 pin

(TEBE=0), or as the transmitter external buffer enable control (TEBE=1,

RFSD=1).

When this pin is configured as serial flag pin, its direction is determined by

the RFSD bit in the RCCR register. When configured as the output flag OF1,

this pin will reflect the value of the OF1 bit in the SAICR register, and the

data in the OF1 bit will show up at the pin synchronized to the frame sync in

normal mode or the slot in network mode. When configured as the input flag

IF1, the data value at the pin will be stored in the IF1 bit in the SAISR

register, synchronized by the frame sync in normal mode or the slot in

network mode.

PE1

Input, output, or

disconnected

GPIO

Port E 1—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input cannot tolerate 5 V.

FST_1

Input or output

GPIO

Frame Sync for Transmitter_1—This is the transmitter frame sync

disconnected input/output signal. For synchronous mode, this signal is the frame sync for

both transmitters and receivers. For asynchronous mode, FST is the frame

sync for the transmitters only. The direction is determined by the transmitter

frame sync direction (TFSD) bit in the ESAI transmit clock control register

(TCCR).

PE4

Input, output, or

disconnected

GPIO

Port E 4—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input cannot tolerate 5 V.

SCKR_1

Input or output

GPIO

Receiver Serial Clock_1—SCKR provides the receiver serial bit clock for

disconnected the ESAI. The SCKR operates as a clock input or output used by all the

enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin

in the synchronous mode (SYN=1).

When this pin is configured as serial flag pin, its direction is determined by

the RCKD bit in the RCCR register. When configured as the output flag OF0,

this pin will reflect the value of the OF0 bit in the SAICR register, and the

data in the OF0 bit will show up at the pin synchronized to the frame sync in

normal mode or the slot in network mode. When configured as the input flag

IF0, the data value at the pin will be stored in the IF0 bit in the SAISR

register, synchronized by the frame sync in normal mode or the slot in

network mode.

DSP56366 Technical Data, Rev. 3.1

2-18

Freescale Semiconductor

Table 2-12 Enhanced Serial Audio Interface_1 Signals

Signal

Name

State during

Signal Description

Reset

Signal Type

PE0

Input, output, or

disconnected

GPIO

Port E 0—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input cannot tolerate 5 V.

SCKT_1

PE3

Input or output

GPIO

Transmitter Serial Clock_1—This signal provides the serial bit rate clock

disconnected for the ESAI. SCKT is a clock input or output used by all enabled

transmitters and receivers in synchronous mode, or by all enabled

transmitters in asynchronous mode.

Input, output, or

disconnected

GPIO

Port E 3—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input cannot tolerate 5 V.

SDO5_1

SDI0_1

PE6

Output

Input

GPIO

Serial Data Output 5_1—When programmed as a transmitter, SDO5 is

disconnected used to transmit data from the TX5 serial transmit shift register.

GPIO

Serial Data Input 0_1—When programmed as a receiver, SDI0 is used to

disconnected receive serial data into the RX0 serial receive shift register.

Input, output, or

disconnected

GPIO

Port E 6—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input cannot tolerate 5 V.

SDO4_1

SDI1_1

PE7

Output

Input

GPIO

Serial Data Output 4_1—When programmed as a transmitter, SDO4 is

disconnected used to transmit data from the TX4 serial transmit shift register.

GPIO

Serial Data Input 1_1—When programmed as a receiver, SDI1 is used to

disconnected receive serial data into the RX1 serial receive shift register.

Input, output, or

disconnected

GPIO

Port E 7—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

2-19

2.11 SPDIF Transmitter Digital Audio Interface

Table 2-13 Digital Audio Interface (DAX) Signals

Signal

Name

State During

Reset

Type

Signal Description

ACI

Input

GPIO

Audio Clock Input—This is the DAX clock input. When programmed to use

Disconnected an external clock, this input supplies the DAX clock. The external clock

frequency must be 256, 384, or 512 times the audio sampling frequency

(256 × Fs, 384 × Fs or 512 × Fs, respectively).

PD0

Input, output, or

disconnected

GPIO

Port D 0—When the DAX is configured as GPIO, this signal is individually

Disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

ADO

PD1

Output

GPIO

Digital Audio Data Output—This signal is an audio and non-audio output

Disconnected in the form of AES/EBU, CP340 and IEC958 data in a biphase mark format.

Input, output, or

disconnected

GPIO

Port D 1—When the DAX is configured as GPIO, this signal is individually

Disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

2.12 Timer

Table 2-14 Timer Signal

Signal

Name

State during

Signal Description

Reset

Type

Input or Output

TIO0

Input

Timer 0 Schmitt-Trigger Input/Output—When timer 0 functions as an

external event counter or in measurement mode, TIO0 is used as input.

When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0

is used as output.

The default mode after reset is GPIO input. This can be changed to output or

configured as a timer input/output through the timer 0 control/status register

(TCSR0). If TIO0 is not being used, it is recommended to either define it as

GPIO output immediately at the beginning of operation or leave it defined as

GPIO input but connected to Vcc through a pull-up resistor in order to ensure

a stable logic level at this input.

This input is 5 V tolerant.

DSP56366 Technical Data, Rev. 3.1

2-20

Freescale Semiconductor

2.13 JTAG/OnCE Interface

Table 2-15 JTAG/OnCE Interface

Signal

Name

Signal

Type

State during

Reset

Signal Description

TCK

Input

Test Clock—TCK is a test clock input signal used to synchronize the JTAG test

logic. It has an internal pull-up resistor.

This input is 5 V tolerant.

TDI

Input

Test Data Input—TDI is a test data serial input signal used for test instructions and

data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor.

This input is 5 V tolerant.

TDO

TMS

Output

Input

Tri-stated

Input

Test Data Output—TDO is a test data serial output signal used for test instructions

and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR

controller states. TDO changes on the falling edge of TCK.

Test Mode Select—TMS is an input signal used to sequence the test controller’s

state machine. TMS is sampled on the rising edge of TCK and has an internal

pull-up resistor.

This input is 5 V tolerant.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

2-21

NOTES

DSP56366 Technical Data, Rev. 3.1

2-22

Freescale Semiconductor

3 Specifications

3.1

Introduction

The DSP56366 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs

and outputs. The DSP56366 specifications are preliminary and are from design simulations, and may not

be fully tested or guaranteed. Finalized specifications will be published after full characterization and

device qualifications are complete.

3.2

Maximum Ratings

CAUTION

This device contains circuitry protecting against damage due to high static

voltage or electrical fields. However, normal precautions should be taken to

avoid exceeding maximum voltage ratings. Reliability of operation is

enhanced if unused inputs are pulled to an appropriate logic voltage level

(e.g., either GND or V ). The suggested value for a pullup or pulldown

CC

resistor is 10 kΩ.

NOTE

In the calculation of timing requirements, adding a maximum value of one

specification to a minimum value of another specification does not yield a

reasonable sum. A maximum specification is calculated using a worst case

variation of process parameter values in one direction. The minimum

specification is calculated using the worst case for the same parameters in

the opposite direction. Therefore, a “maximum” value for a specification

will never occur in the same device that has a “minimum” value for another

specification; adding a maximum to a minimum represents a condition that

can never exist.

Table 3-1 Maximum Ratings

Rating¹

Symbol

V_CC

V_IN

Value^{1, 2}

−0.3 to +4.0

Unit

V

Supply Voltage

All input voltages excluding “5 V tolerant” inputs³

All “5 V tolerant” input voltages³

GND -0.3 to V_CC+ 0.3

GND − 0.3 to V_CC+ 3.95

10

V

V_IN5

I

V

Current drain per pin excluding V_CCand GND

mA

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-1

Table 3-1 Maximum Ratings (continued)

Rating¹

Operating temperature range

Storage temperature

Symbol

T_J

Value^{1, 2}

Unit

°C

−40 to +110

−55 to +125

T_STG

°C

1

GND = 0 V, V_CC= 3.3 V 0.16 V, T_J= –40°C to +110°C, C_L= 50 pF

2

Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the maximum rating may affect device reliability or cause permanent damage to the device.

CAUTION: All “5 V Tolerant” input voltages must not be more than 3.95 V greater than the supply voltage; this restriction

applies to “power on”, as well as during normal operation. In any case, the input voltages cannot be more than 5.75 V. “5 V

Tolerant” inputs are inputs that tolerate 5 V.

3

3.3

Thermal Characteristics

Table 3-2 Thermal Characteristics

Characteristic

Symbol

R_θJAor θ_JA

R_θJCor θ_JC

Ψ_JT

LQFP Value

Unit

°C/W

Junction-to-ambient thermal resistance^{1, 2}Natural Convection

Junction-to-case thermal resistance³

37

7

Thermal characterization parameter⁴Natural Convection

2.0

1

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is

written as Psi-JT.

2

3

4

DSP56366 Technical Data, Rev. 3.1

3-2

Freescale Semiconductor

3.4

DC Electrical Characteristics

1

Table 3-3 DC Electrical Characteristics

Characteristics

Symbol

Min

Typ

Max

Unit

V

3.14

3.3

3.46

V

Supply voltage

CC

Input high voltage

V

• D(0:23), BG, BB, TA, ESAI_1_{(except SDO4_1)}

• MOD²/IRQ², RESET, PINIT/NMI and all

V_IH

2.0

—

V

V_CC+ 3.95

IHP

JTAG/ESAI/Timer/HDI08/DAX/ESAI_1_{(only SDO4_1)}/SHI_(SPI

mode)

• SHI_{(I2C mode)}

• EXTAL³

V

1.5

—

V

_CC+ 3.95

IHP

IHX

0.8 × V_CC

V_CC

Input low voltage

V

• D(0:23), BG, BB, TA, ESAI_1_{(except SDO4_1)}

• MOD²/IRQ², RESET, PINIT/NMI and all

V_IL

–0.3

—

0.8

V_ILP

JTAG/ESAI/Timer/HDI08/DAX/ESAI_1_{(only SDO4_1)}/SHI_(SPI

mode)

• SHI_{(I2C mode)}

• EXTAL³

V_ILP

V_ILX

–0.3

—

0.3 x V_CC

0.2 x V_CC

Input leakage current

I_IN

–10

—

10

μA

V

High impedance (off-state) input current (@ 2.4 V / 0.4 V)

I_TSI

Output high voltage

• TTL (I_OH= –0.4 mA)^4,5

• CMOS (I_OH= –10 μA)⁴

V_OH

2.4

—

V_CC– 0.01

Output low voltage

V

• TTL (I_OL= 3.0 mA, open-drain pins I_OL= 6.7 mA)^4,5

• CMOS (I_OL= 10 μA)⁴

V_OL

—

0.4

0.01

Internal supply current⁶at internal clock of 120MHz

• In Normal mode

mA

I_CCI

I_CCW

I_CCS

—

116

7.3

1

200

25

• In Wait mode

• In Stop mode⁷

10

PLL supply current

Input capacitance⁴

—

1

2.5

10

mA

pF

C_IN

—

1

V_CC= 3.3 V .16 V; T_J= – 40°C to +110°C, C_L= 50 pF

Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC,and MODD/IRQD pins.

Driving EXTAL to the low V_IHXor the high V_ILXvalue may cause additional power consumption (DC current). To minimize

2

3

power consumption, the minimum V_IHXshould be no lower than 0.9 × V_CCand the maximum V_ILXshould be no higher than

0.1 × V_CC

.

4

5

Periodically sampled and not 100% tested.

This characteristic does not apply to PCAP.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-3

6

7

Appendix A, "Power Consumption Benchmark" provides a formula to compute the estimated current requirements

in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are

based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the

measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with

V_CC= 3.3 V at

T_J= 110°C. Maximum internal supply current is measured with V_CC= 3.46 V at T_J= 110°C.

In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to

float).

3.5

AC Electrical Characteristics

The timing waveforms shown in the AC electrical characteristics section are tested with a V maximum

IL

of 0.3 V and a V minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels

IH

shown in Note 3 of the previous table. AC timing specifications, which are referenced to a device input

signal, are measured in production with respect to the 50% point of the respective input signal’s transition.

DSP56366 output levels are measured with the production test machine V and V reference levels set

OL

OH

at 0.4 V and 2.4 V, respectively.

NOTE

Although the minimum value for the frequency of EXTAL is 0 MHz, the

device AC test conditions are 15 MHz and rated speed.

3.6

Internal Clocks

Table 3-4 Internal Clocks

Expression^{1, 2}

Characteristics

Symbol

Min

Typ

Max

Internal operation frequency with PLL

enabled

f

—

(Ef × MF)/(PDF × DF)

—

Internal operation frequency with PLL

disabled

f

—

Ef/2

—

Internal clock high period

• With PLL disabled

T_H

—

ET_C

—

• With PLL enabled and MF ≤ 4

0.49 × ET_C× PDF ×

0.51 × ET_C× PDF ×

DF/MF

• With PLL enabled and MF > 4

0.47 × ET_C× PDF ×

—

0.53 × ET_C× PDF ×

DF/MF

Internal clock low period

• With PLL disabled

T_L

—

ET_C

—

• With PLL enabled and MF ≤ 4

0.49 × ET_C× PDF ×

0.51 × ET_C× PDF ×

DF/MF

• With PLL enabled and MF > 4

0.47 × ET_C× PDF ×

—

0.53 × ET_C× PDF ×

DF/MF

Internal clock cycle time with PLL

enabled

T_C

—

ET_C× PDF × DF/MF

—

DSP56366 Technical Data, Rev. 3.1

3-4

Freescale Semiconductor

Table 3-4 Internal Clocks

Expression^{1, 2}

Typ

Characteristics

Symbol

Min

Max

Internal clock cycle time with PLL

disabled

T_C

—

2 × ET_C

—

Instruction cycle time

I_CYC

—

T_C

—

1

DF = Division Factor

Ef = External frequency

ET_C= External clock cycle

MF = Multiplication Factor

PDF = Predivision Factor

T_C= internal clock cycle

2

See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL.

3.7

EXTERNAL CLOCK OPERATION

The DSP56366 system clock is an externally supplied square wave voltage source connected to EXTAL

(See Figure 3-1).

V_IHC

Midpoint

EXTAL

ETH

ETL

V_ILC

2

3

4

ETC

Notes The midpoint is 0.5 (V_IHC+ V_ILC).

Figure 3-1 External Clock Timing

Table 3-5 Clock Operation

No.

Characteristics

Symbol

Min

Max

1

Frequency of EXTAL (EXTAL Pin Frequency)

Ef

0

120.0

The rise and fall time of this external clock should be 3 ns maximum.

2

3

EXTAL input high^{1, 2}

• With PLL disabled (46.7%–53.3% duty cycle³)

• With PLL enabled (42.5%–57.5% duty cycle³)

ET_H

ET_L

3.89 ns

3.54 ns

∞

157.0 μs

EXTAL input low^{1, 2}

• With PLL disabled (46.7%–53.3% duty cycle³)

• With PLL enabled (42.5%–57.5% duty cycle³)

3.89 ns

3.54 ns

∞

157.0 μs

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-5

Table 3-5 Clock Operation (continued)

Characteristics

No.

Symbol

Min

Max

4

EXTAL cycle time²

• With PLL disabled

• With PLL enabled

ET_C

8.33 ns

∞

273.1 μs

4, 2

7

Instruction cycle time = I_CYC= T_C

• With PLL disabled

I_CYC

16.66 ns

8.33 ns

∞

• With PLL enabled

8.53 μs

1

2

3

Measured at 50% of the input transition.

The maximum value for PLL enabled is given for minimum V_COand maximum MF.

The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time

required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock

frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time

requirements are met.

4

The maximum value for PLL enabled is given for minimum VCO and maximum DF.

3.8

Phase Lock Loop (PLL) Characteristics

Table 3-6 PLL Characteristics

Characteristics

Min

Max

Unit

MHz

pF

V_COfrequency when PLL enabled (MF × E_f× 2/PDF)

30

240

1

PLL external capacitor (PCAP pin to V_CCP) (C_PCAP

)

• @ MF ≤ 4

(MF × 580) − 100

MF × 830

(MF × 780) − 140

MF × 1470

• @ MF > 4

1

C_PCAPis the value of the PLL capacitor (connected between the PCAP pin and V_CCP). The recommended value in pF

for C_PCAPcan be computed from one of the following equations:

(MF x 680)-120, for MF ≤ 4 or MF x 1100, for MF > 4.

3.9

Reset, Stop, Mode Select, and Interrupt Timing

1

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing

No.

8

Characteristics

Expression

Min

Max

Unit

Delay from RESET assertion to all pins at reset value²

—

26.0

ns

9

Required RESET duration³

• Power on, external clock generator, PLL disabled

• Power on, external clock generator, PLL enabled

• During normal operation

50 × ET_C

1000 × ET_C

2.5 × T_C

416.7

8.3

—

ns

μs

ns

20.8

10 Delay from asynchronous RESET deassertion to first

external address output (internal reset deassertion)⁴

• Minimum

• Maximum

3.25 × T_C+ 2.0

29.1

—

ns

20.25 T_C+ 7.50

176.2

13 Mode select setup time

30.0

—

ns

DSP56366 Technical Data, Rev. 3.1

3-6

Freescale Semiconductor

1

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing (continued)

No.

Characteristics

Expression

Min

0.0

5.5

Max

—

Unit

ns

14 Mode select hold time

15 Minimum edge-triggered interrupt request assertion width

16 Minimum edge-triggered interrupt request deassertion width

—

ns

—

ns

17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

external memory access address out valid

• Caused by first interrupt instruction fetch

4.25 × T_C+ 2.0

7.25 × T_C+ 2.0

37.4

62.4

—

ns

• Caused by first interrupt instruction execution

18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

general-purpose transfer output valid caused by first interrupt

instruction execution

10 × T_C+ 5.0

88.3

—

ns

19 Delay from address output valid caused by first interrupt

instruction execute to interrupt request deassertion for level

sensitive fast interrupts⁵

3.75 × T_C+ WS × T_C– 10.94

3.25 × T_C+ WS × T_C– 10.94

—

Note⁶

Note 6

ns

20 Delay from RD assertion to interrupt request deassertion for

level sensitive fast interrupts⁵

—

ns

21 Delay from WR assertion to interrupt request deassertion for

level sensitive fast interrupts⁵

• DRAM for all WS

• SRAM WS = 1

• SRAM WS = 2, 3

• SRAM WS ≥ 4

(WS + 3.5) × T_C– 10.94

(WS + 3) × T_C– 10.94

(WS + 2.5) × T_C– 10.94

—

Note 6

24 Duration for IRQA assertion to recover from Stop state

4.9

—

25 Delay from IRQA assertion to fetch of first instruction (when

exiting Stop)^{2, 7}

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is enabled (OMR Bit 6 = 0)

PLC × ET_C× PDF + (128 K −

PLC/2) × T_C

—

ms

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is not enabled (OMR Bit 6 = 1)

PLC × ET_C× PDF + (23.75 ±

0.5) × T_C

• PLL is active during Stop (PCTL Bit 17 = 1) (Implies No

Stop Delay)

(8.25 ± 0.5) × T_C

64.6

72.9

26 Duration of level sensitive IRQA assertion to ensure interrupt

service (when exiting Stop)^{2, 7}

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is enabled (OMR Bit 6 = 0)

PLC × ET_C× PDF + (128K −

PLC/2) × T_C

—

ms

ns

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop PLC × ET_C× PDF + (20.5 ± 0.5)

delay is not enabled (OMR Bit 6 = 1)

× T_C

• PLL is active during Stop (PCTL Bit 17 = 1) (implies no

Stop delay)

5.5 × T_C

45.8

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-7

1

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing (continued)

No.

Characteristics

Expression

Min

Max

Unit

27 Interrupt Requests Rate

• HDI08, ESAI, ESAI_1, SHI, DAX, Timer

• DMA

12T_C

8T_C

—

100.0

66.7

ns

• IRQ, NMI (edge trigger)

• IRQ (level trigger)

8T_C

66.7

12T_C

100.0

28 DMA Requests Rate

• Data read from HDI08, ESAI, ESAI_1, SHI, DAX

• Data write to HDI08, ESAI, ESAI_1, SHI, DAX

• Timer

6T_C

7T_C

2T_C

3T_C

—

50.0

58.0

16.7

25.0

ns

• IRQ, NMI (edge trigger)

—

ns

29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

external memory (DMA source) access address out valid

4.25 × T_C+ 2.0

37.4

—

1

2

3

V_CC= 3.3 V 0.16 V; T_J= –40°C to + 110°C, C_L= 50 pF

Periodically sampled and not 100% tested.

RESET duration is measured during the time in which RESET is asserted, V_CCis valid, and the EXTAL input is active and

valid. When the V_CCis valid, but the other “required RESET duration” conditions (as specified above) have not been yet met,

the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs

should minimize this state to the shortest possible duration.

4

5

If PLL does not lose lock.

When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to

prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended

when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.

WS = number of wait states (measured in clock cycles, number of T_C). Use expression to compute maximum value.

This timing depends on several settings:

6

7

For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined

by the PCTL Bit 17 and OMR Bit 6 settings.

For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked.

The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in

parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs: the stop delay

counter completes count or PLL lock procedure completion.

PLC value for PLL disable is 0.

The maximum value for ET_Cis 4096 (maximum MF) divided by the desired internal frequency (i.e., for 120 MHz it is 4096/120

MHz = 34.1 μs). During the stabilization period, T_C, T_H, and T_Lwill not be constant, and their width may vary, so timing may

vary as well.

DSP56366 Technical Data, Rev. 3.1

3-8

Freescale Semiconductor

V_IH

RESET

9

10

8

All Pins

A0–A17

Reset Value

First Fetch

AA0460

Figure 3-2 Reset Timing

First Interrupt Instruction

Execution/Fetch

A0–A17

RD

20

WR

21

19

17

IRQA, IRQB,

IRQC, IRQD,

NMI

a) First Interrupt Instruction Execution

General

Purpose

I/O

18

IRQA, IRQB,

IRQC, IRQD,

NMI

b) General Purpose I/O

Figure 3-3 External Fast Interrupt Timing

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-9

IRQA, IRQB,

IRQC, IRQD,

NMI

15

16

IRQA, IRQB,

IRQC, IRQD,

NMI

AA0463

Figure 3-4 External Interrupt Timing (Negative Edge-Triggered)

V_IH

RESET

13

14

IRQA, IRQB,

IRQD, NMI

V_IH

V_IL

V_IH

V_IL

MODA, MODB,

MODC, MODD,

PINIT

AA0465

Figure 3-5 Operating Mode Select Timing

24

IRQA

25

First Instruction Fetch

A0–A17

AA0466

Figure 3-6 Recovery from Stop State Using IRQA

DSP56366 Technical Data, Rev. 3.1

3-10

Freescale Semiconductor

26

IRQA

25

A0–A17

First IRQA Interrupt Instruction Fetch

AA0467

Figure 3-7 Recovery from Stop State Using IRQA Interrupt Service

DMA Source Address

A0–A17

RD

WR

29

IRQA, IRQB,

IRQC, IRQD,

NMI

First Interrupt Instruction Execution

AA1104

Figure 3-8 External Memory Access (DMA Source) Timing

3.10 External Memory Expansion Port (Port A)

3.10.1 SRAM Timing

1

Table 3-8 SRAM Read and Write Accesses

No.

Characteristics

Symbol

Expression²

Min

Max

Unit

100 Address valid and AA assertion pulse width

t_RC, t_WC

(WS + 1) × T_C− 4.0

[1 ≤ WS ≤ 3]

12.0

—

ns

(WS + 2) × T_C− 4.0

[4 ≤ WS ≤ 7]

46.0

87.0

—

ns

(WS + 3) × T_C− 4.0

[WS ≥ 8]

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-11

1

Table 3-8 SRAM Read and Write Accesses (continued)

No.

Characteristics

Symbol

Expression²

Min

Max

Unit

101 Address and AA valid to WR assertion

t_AS

0.25 × T_C− 2.0

0.1

—

ns

[WS = 1]

1.25 × T_C− 2.0

[WS ≥ 4]

8.4

—

ns

102 WR assertion pulse width

t_WP

1.5 × T_C− 4.0 [WS = 1]

8.5

—

ns

All frequencies:

WS × T_C− 4.0

[2 ≤ WS ≤ 3]

12.7

(WS − 0.5) × T_C− 4.0

[WS ≥ 4]

25.2

0.1

—

ns

103 WR deassertion to address not valid

t_WR

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

8.4

2.25 × T_C− 2.0

[WS ≥ 8]

16.7

6.4

All frequencies:

1.25 × T_C− 4.0

[4 ≤ WS ≤ 7]

2.25 × T_C− 4.0

[WS ≥ 8]

14.7

—

ns

104 Address and AA valid to input data valid

105 RD assertion to input data valid

t_AA, t_AC

(WS + 0.75) × T_C− 7.0

[WS ≥ 1]

7.6

3.4

t_OE

(WS + 0.25) × T_C− 7.0

[WS ≥ 1]

—

106 RD deassertion to data not valid (data hold time)

107 Address valid to WR deassertion³

t_OHZ

t_AW

0.0

—

ns

(WS + 0.75) × T_C− 4.0

[WS ≥ 1]

10.6

108 Data valid to WR deassertion (data setup time)

t_DS(t_DW

)

(WS − 0.25) × T_C− 3.0

[WS ≥ 1]

3.2

—

ns

DSP56366 Technical Data, Rev. 3.1

3-12

Freescale Semiconductor

1

Table 3-8 SRAM Read and Write Accesses (continued)

No.

Characteristics

Symbol

Expression²

Min

Max

Unit

109 Data hold time from WR deassertion

t_DH

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

0.1

—

ns

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

8.4

16.7

2.5

0.0

—

ns

2.25 × T_C− 2.0

[WS ≥ 8]

110 WR assertion to data active

—

0.75 × T_C− 3.7

—

[WS = 1]

0.25 × T_C− 3.7

[2 ≤ WS ≤ 3]

—

−0.25 × T_C− 3.7

[WS ≥ 4]

—

111 WR deassertion to data high impedance

112 Previous RD deassertion to data active (write)

113 RD deassertion time

0.25 × T_C+ 0.2

[1 ≤ WS ≤ 3]

2.3

10.6

18.9

—

ns

1.25 × T_C+ 0.2

[4 ≤ WS ≤ 7]

—

2.25 × T_C+ 0.2

[WS ≥ 8]

—

1.25 × T_C− 4.0

[1 ≤ WS ≤ 3]

6.4

14.7

23.1

2.2

10.6

18.9

ns

2.25 × T_C− 4.0

[4 ≤ WS ≤ 7]

—

3.25 × T_C− 4.0

[WS ≥ 8]

—

0.75 × T_C− 4.0

[1 ≤ WS ≤ 3]

—

ns

1.75 × T_C− 4.0

[4 ≤ WS ≤ 7]

—

2.75 × T_C− 4.0

[WS ≥ 8]

—

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-13

1

Table 3-8 SRAM Read and Write Accesses (continued)

No.

Characteristics

Symbol

Expression²

Min

Max

Unit

114 WR deassertion time

0.5 × T_C− 4.0

0.2

—

ns

[WS = 1]

T_C− 2.0

[2 ≤ WS ≤ 3]

6.3

—

ns

2.5 × T_C− 4.0

[4 ≤ WS ≤ 7]

16.8

25.2

3.5 × T_C− 4.0

[WS ≥ 8]

115 Address valid to RD assertion

116 RD assertion pulse width

0.5 × T_C− 4.0

0.2

6.4

0.1

—

ns

(WS + 0.25) × T_C−4.0

117 RD deassertion to address not valid

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

8.4

—

ns

2.25 × T_C− 2.0

[WS ≥ 8]

16.7

118 TA setup before RD or WR deassertion⁴

119 TA hold after RD or WR deassertion

0.25 × T_C+ 2.0

4.1

0.0

—

ns

1

2

3

4

All timings for 100 MHz are measured from 0.5 · Vcc to .05 · Vcc

WS is the number of wait states specified in the BCR.

Timings 100, 107 are guaranteed by design, not tested.

In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active

DSP56366 Technical Data, Rev. 3.1

3-14

Freescale Semiconductor

100

A0–A17

AA0–AA2

117

106

113

116

RD

115

105

WR

104

119

118

TA

Data

In

D0–D23

AA0468

Figure 3-9 SRAM Read Access

100

107

A0–A17

AA0–AA2

101

102

103

WR

114

RD

TA

118

119

108

109

Data

Out

D0–D23

Figure 3-10 SRAM Write Access

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-15

3.10.2 DRAM Timing

The selection guides provided in Figure 3-11 and Figure 3-14 should be used for primary selection only.

Final selection should be based on the timing provided in the following tables. As an example, the selection

guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode DRAM.

However, by using the information in the appropriate table, a designer may choose to evaluate whether

fewer wait states might be used by determining which timing prevents operation at 100 MHz, running the

chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available), and control

factors such as capacitive and resistive load to improve overall system performance.

DRAM Type

Notes This figure should be use for primary selection. For

exact and detailed timings see the following tables.

(tRAC ns)

100

80

70

60

50

Chip Frequency

(MHz)

120

40

66

80

100

1 Wait States

2 Wait States

3 Wait States

4 Wait States

AA0472

Figure 3-11 DRAM Page Mode Wait States Selection Guide

DSP56366 Technical Data, Rev. 3.1

3-16

Freescale Semiconductor

1, 2, 3

Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)

20 MHz⁴30 MHz⁴

No.

Characteristics

Symbol

Expression

Unit

Min

Max

Min

Max

131 Page mode cycle time for two consecutive

accesses of the same direction

t_PC

2 × T_C

100.0

62.5

—

66.7

41.7

—

ns

Page mode cycle time for mixed (read and

write) accesses

1.25 × T_C

—

132 CAS assertion to data valid (read)

t_CAC

t_AA

T_C− 7.5

—

42.5

67.5

—

25.8

42.5

—

ns

133 Column address valid to data valid (read)

1.5 × T_C− 7.5

134 CAS deassertion to data not valid (read hold

time)

t_OFF

0.0

135 Last CAS assertion to RAS deassertion

t_RSH

0.75 × T_C− 4.0

2 × T_C− 4.0

33.5

96.0

—

21.0

62.7

—

ns

136 Previous CAS deassertion to RAS

deassertion

t_RHCP

137 CAS assertion pulse width

t_CAS

t_CRP

0.75 × T_C− 4.0

33.5

—

21.0

—

ns

138 Last CAS deassertion to RAS deassertion⁵

• BRW[1:0] = 00

1.75 × T_C− 6.0

3.25 × T_C− 6.0

4.25 × T_C− 6.0

6.25 × T_C– 6.0

81.5

156.5

206.5

306.5

—

52.3

102.2

135.5

202.1

—

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

139 CAS deassertion pulse width

t_CP

0.5 × T_C− 4.0

0.75 × T_C− 4.0

2 × T_C− 4.0

21.0

33.5

96.0

—

12.7

21.0

62.7

—

ns

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

t_ASC

t_CAH

t_RAL

142 Last column address valid to RAS

deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

t_RCS

t_RCH

t_WCH

t_WP

0.75 × T_C− 3.8

0.25 × T_C− 3.7

0.5 × T_C− 4.2

1.5 × T_C− 4.5

1.75 × T_C− 4.3

0.25 × T_C− 4.0

33.7

8.8

—

21.2

4.6

—

ns

20.8

70.5

83.2

8.5

12.5

45.5

54.0

4.3

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (Write)

t_RWL

t_CWL

t_DS

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-17

1, 2, 3

Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)

20 MHz⁴

(continued)

30 MHz⁴

No.

Characteristics

Symbol

Expression

Unit

Min

33.5

45.7

71.0

—

Max

—

Min

21.0

29.0

46.0

—

Max

—

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t_DH

t_WCS

t_ROH

t_GA

0.75 × T_C− 4.0

T_C− 4.3

ns

—

1.5 × T_C− 4.0

T_C− 7.5

—

42.5

—

25.8

—

154 RD deassertion to data not valid⁶

155 WR assertion to data active

t_GZ

0.0

0.75 × T_C− 0.3

0.25 × T_C

37.2

—

24.7

—

156 WR deassertion to data high impedance

12.5

8.3

1

2

3

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t_PCequals 2 × T_Cfor

read-after-read or write-after-write sequences).

Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See Figure 3-14.).

BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page

access.

4

5

6

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

1, 2, 3, 4

Table 3-10 DRAM Page Mode Timings, Two Wait States

66 MHz

80 MHz

No.

Characteristics

Symbol

Expression⁵

Unit

Min

Max

Min

Max

131 Page mode cycle time for two consecutive

accesses of the same direction

t_PC

2 × T_C

45.4

41.1

—

37.5

34.4

—

ns

Page mode cycle time for mixed (read and write)

accesses

1.25 × T_C

—

132 CAS assertion to data valid (read)

t_CAC

1.5 × T_C− 7.5

1.5 × T_C− 6.5

—

15.2

—

ns

12.3

133 Column address valid to data valid (read)

t_AA

2.5 × T_C− 7.5

2.5 × T_C− 6.5

—

30.4

—

ns

24.8

134 CAS deassertion to data not valid (read hold

time)

t_OFF

0.0

—

0.0

—

ns

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

t_RSH

t_RHCP

t_CAS

1.75 × T_C− 4.0

3.25 × T_C− 4.0

1.5 × T_C− 4.0

22.5

45.2

18.7

—

17.9

36.6

14.8

—

ns

DSP56366 Technical Data, Rev. 3.1

3-18

Freescale Semiconductor

1, 2, 3, 4

Table 3-10 DRAM Page Mode Timings, Two Wait States

(continued)

66 MHz 80 MHz

No.

Characteristics

Symbol

Expression⁵

Unit

Min

Max

Min

Max

138 Last CAS deassertion to RAS deassertion⁶

• BRW[1:0] = 00

t_CRP

ns

2.0 × T_C− 6.0

3.5 × T_C− 6.0

4.5 × T_C− 6.0

6.5 × T_C− 6.0

24.4

47.2

62.4

92.8

—

19.0

37.8

50.3

75.3

—

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

139 CAS deassertion pulse width

t_CP

t_ASC

t_CAH

t_RAL

t_RCS

t_RCH

t_WCH

t_WP

1.25 × T_C− 4.0

T_C− 4.0

14.9

11.2

22.5

41.5

15.1

3.9

—

11.6

8.5

—

ns

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

1.75 × T_C− 4.0

3 × T_C− 4.0

17.9

33.5

11.8

2.6

1.25 × T_C− 3.8

0.5 × T_C− 3.7

1.5 × T_C− 4.2

2.5 × T_C− 4.5

2.75 × T_C− 4.3

2.5 × T_C− 4.3

18.5

33.5

33.4

33.6

14.6

26.8

27.0

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

t_RWL

t_CWL

t_DS

0.25 × T_C− 3.7

0.25 × T_C− 3.0

0.1

—

0.1

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t_DH

t_WCS

t_ROH

t_GA

1.75 × T_C− 4.0

T_C− 4.3

22.5

10.9

33.9

—

17.9

8.2

—

ns

2.5 × T_C− 4.0

27.3

1.75 × T_C− 7.5

1.75 × T_C− 6.5

—

19.0

—

15.4

154 RD deassertion to data not valid⁷

155 WR assertion to data active

t_GZ

0.0

11.1

—

0.0

9.1

—

ns

0.75 × T_C− 0.3

0.25 × T_C

156 WR deassertion to data high impedance

3.8

3.1

1

2

3

4

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for DSP56366.

There are no DRAMs fast enough to fit to two wait states Page mode @ 100MHz (See Figure 3-11)

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-19

5

6

7

All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t_PCequals 3 × T_Cfor

read-after-read or write-after-write sequences).

BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page

access.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ.

1, 2, 3

Table 3-11 DRAM Page Mode Timings, Three Wait States

No.

Characteristics

Symbol

Expression⁴

Min Max Unit

131 Page mode cycle time for two consecutive accesses of the same

direction

t_PC

2 × T_C

40.0

—

ns

Page mode cycle time for mixed (read and write) accesses

1.25 × T_C

2 × T_C− 7.0

3 × T_C− 7.0

35.0

—

13.0

23.0

—

132 CAS assertion to data valid (read)

t_CAC

t_AA

ns

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

—

t_OFF

t_RSH

t_RHCP

t_CAS

t_CRP

0.0

2.5 × T_C− 4.0 21.0

4.5 × T_C− 4.0 41.0

—

2 × T_C− 4.0

16.0

—

138 Last CAS deassertion to RAS assertion⁵

• BRW[1:0] = 00

2.25 × T_C− 6.0

3.75 × T_C− 6.0

—

• BRW[1:0] = 01

• BRW[1:0] = 10

4.75 × T_C− 6.0 41.5

6.75 × T_C− 6.0 61.5

• BRW[1:0] = 11

139 CAS deassertion pulse width

t_CP

t_ASC

t_CAH

t_RAL

t_RCS

t_RCH

t_WCH

t_WP

1.5 × T_C− 4.0 11.0

—

ns

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

T_C− 4.0

2.5 × T_C− 4.0 21.0

4 × T_C− 4.0 36.0

6.0

1.25 × T_C− 4.0 8.5

0.75 × T_C− 4.0 3.5

2.25 × T_C− 4.2 18.3

3.5 × T_C− 4.5 30.5

3.75 × T_C− 4.3 33.2

3.25 × T_C− 4.3 28.2

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

t_RWL

t_CWL

t_DS

0.5 × T_C− 4.0

1.0

DSP56366 Technical Data, Rev. 3.1

3-20

Freescale Semiconductor

1, 2, 3

Table 3-11 DRAM Page Mode Timings, Three Wait States

(continued)

Expression⁴

Min Max Unit

No.

Characteristics

Symbol

t_DH

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

2.5 × T_C− 4.0 21.0

1.25 × T_C− 4.3 8.2

3.5 × T_C− 4.0 31.0

—

ns

t_WCS

t_ROH

t_GA

—

2.5 × T_C− 7.0

—

18.0

—

154 RD deassertion to data not valid⁶

155 WR assertion to data active

t_GZ

0.0

0.75 × T_C− 0.3 7.2

0.25 × T_C

—

156 WR deassertion to data high impedance

—

2.5

1

2

3

4

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for DSP56366.

All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t_PCequals 4 × T_Cfor

read-after-read or write-after-write sequences).

BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of

page-access.

5

6

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

1, 2, 3

Table 3-12 DRAM Page Mode Timings, Four Wait States

No.

Characteristics

Symbol

Expression⁴

Min Max Unit

131 Page mode cycle time for two consecutive accesses of the same

direction.

t_PC

5 × T_C

41.7

—

ns

Page mode cycle time for mixed (read and write) accesses

4.5 × T_C

37.5

—

15.9

24.2

—

132 CAS assertion to data valid (read)

t_CAC

t_AA

2.75 × T_C− 7.0

3.75 × T_C− 7.0

ns

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

—

t_OFF

t_RSH

t_RHCP

t_CAS

t_CRP

0.0

3.5 × T_C− 4.0

6 × T_C− 4.0

25.2

46.0

16.8

—

2.5 × T_C− 4.0

—

138 Last CAS deassertion to RAS assertion⁵

• BRW[1:0] = 00

2.75 × T_C− 6.0

4.25 × T_C− 6.0

—

• BRW[1:0] = 01

• BRW[1:0] = 10

5.25 × T_C− 6.0 37.7

7.25 × T_C− 6.0 54.4

• BRW[1:0] = 11

139 CAS deassertion pulse width

t_CP

2 × T_C− 4.0

12.7

—

ns

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-21

1, 2, 3

Table 3-12 DRAM Page Mode Timings, Four Wait States

(continued)

No.

Characteristics

Symbol

t_ASC

t_CAH

t_RAL

t_RCS

t_RCH

t_WCH

t_WP

Expression⁴

T_C− 4.0

Min Max Unit

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

4.3

25.2

37.7

6.4

—

ns

3.5 × T_C− 4.0

5 × T_C− 4.0

1.25 × T_C− 4.0

—

6.4

—

3.25 × T_C− 4.2 22.9

—

4.5 × T_C− 4.5

4.75 × T_C− 4.3

33.0

35.3

—

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

—

3.75 × T_C− 4.3 26.9

—

0.5 × T_C− 4.0

3.5 × T_C− 4.0

1.25 × T_C− 4.3

4.5 × T_C− 4.0

3.25 × T_C− 7.0

0.2

25.2

6.1

33.5

—

t_DH

—

t_WCS

t_ROH

t_GA

—

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

—

20.1

—

154 RD deassertion to data not valid⁶

155 WR assertion to data active

t_GZ

0.0

5.9

—

0.75 × T_C− 0.3

0.25 × T_C

—

156 WR deassertion to data high impedance

2.1

1

2

3

4

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for DSP56366.

All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t_PCequals 3 × T_Cfor

read-after-read or write-after-write sequences).

BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page

access.

5

6

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

DSP56366 Technical Data, Rev. 3.1

3-22

Freescale Semiconductor

RAS

CAS

136

131

135

137

139

141

138

140

151

142

Column

Address

Last Column

Address

Column

Address

Row

Add

A0–A17

144

143

147

145

WR

RD

146

148

155

149

156

150

D0–D23

Data Out

AA0473

Figure 3-12 DRAM Page Mode Write Accesses

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-23

RAS

CAS

136

135

131

137

140

139

141

138

142

Last Column

Address

Row

Add

Column

Address

Column

Address

A0–A17

WR

143

132

133

153

152

RD

134

154

D0–D23

Data In

AA0474

Figure 3-13 DRAM Page Mode Read Accesses

DSP56366 Technical Data, Rev. 3.1

3-24

Freescale Semiconductor

DRAM Type

(tRAC ns)

Notes This figure should be use for primary selection. For exact

and detailed timings see the following tables.

100

80

70

60

50

Chip Frequency

(MHz)

120

40

66

80

100

4 Wait States

8 Wait States

11 Wait States

15 Wait States

AA0475

Figure 3-14 DRAM Out-of-Page Wait States Selection Guide

1, 2

Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

20 MHz⁴

30 MHz⁴

No.

Characteristics³

Symbol

Expression

Unit

Min

250.0

—

Max

—

Min

166.7

—

Max

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

t_RC

t_RAC

t_CAC

t_AA

5 × T_C

—

ns

2.75 × T_C− 7.5

1.25 × T_C− 7.5

1.5 × T_C− 7.5

130.0

55.0

67.5

—

84.2

34.2

42.5

—

161 CAS deassertion to data not valid (read hold

time)

t_OFF

0.0

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t_RP

1.75 × T_C− 4.0 83.5

3.25 × T_C− 4.0 158.5

1.75 × T_C− 4.0 83.5

—

54.3

104.3

54.3

—

ns

t_RAS

t_RSH

164 CAS assertion to RAS deassertion

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-25

1, 2

Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

(continued)

30 MHz⁴

20 MHz⁴

No.

Characteristics³

Symbol

Expression

Unit

Min

Max

Min

87.7

37.7

48.0

39.7

71.0

54.3

37.7

4.3

Max

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

2.75 × T_C− 4.0 133.5

1.25 × T_C− 4.0 58.5

—

77.0

64.5

—

52.0

43.7

—

ns

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

1.5 × T_C± 2

73.0

60.5

1.25 × T_C± 2

2.25 × T_C− 4.0 108.5

1.75 × T_C− 4.0 83.5

1.25 × T_C− 4.0 58.5

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

178 CAS deassertion to WR assertion

179 RAS deassertion to WR assertion

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t_ASR

t_RAH

t_ASC

t_CAH

t_AR

0.25 × T_C− 4.0

8.5

1.75 × T_C− 4.0 83.5

3.25 × T_C− 4.0 158.5

54.3

104.3

62.7

46.2

21.3

4.6

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

2 × T_C− 4.0

96.0

71.2

1.5 × T_C− 3.8

0.75 × T_C− 3.7 33.8

0.25 × T_C− 3.7

1.5 × T_C− 4.2

3 × T_C− 4.2

8.8

70.8

145.8

45.8

95.8

145.5

154.0

137.4

71.0

54.3

104.3

95.7

12.7

37.7

4.5 × T_C− 4.5 220.5

4.75 × T_C− 4.3 233.2

4.25 × T_C− 4.3 208.2

2.25 × T_C− 4.0 108.5

1.75 × T_C− 4.0 83.5

3.25 × T_C− 4.0 158.5

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

t_DH

t_DHR

t_WCS

t_CSR

t_RPC

3 × T_C− 4.3

145.7

21.0

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

0.5 × T_C− 4.0

1.25 × T_C− 4.0 58.5

DSP56366 Technical Data, Rev. 3.1

3-26

Freescale Semiconductor

1, 2

Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

(continued)

30 MHz⁴

20 MHz⁴

No.

Characteristics³

Symbol

Expression

Unit

Min

Max

Min

146.0

—

Max

191 RD assertion to RAS deassertion

192 RD assertion to data valid

t_ROH

t_GA

4.5 × T_C− 4.0 221.0

—

192.5

—

125.8

—

ns

4 × T_C− 7.5

—

193 RD deassertion to data not valid³

194 WR assertion to data active

t_GZ

0.0

0.75 × T_C− 0.3 37.2

0.25 × T_C

—

24.7

—

195 WR deassertion to data high impedance

—

12.5

8.3

1

2

3

4

The number of wait states for out of page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (See Figure 3-17.).

1, 2

Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States

66 MHz

80 MHz

No.

Characteristics³

Symbol Expression⁴

Unit

Min

Max

Min

Max

157 Random read or write cycle time

158 RAS assertion to data valid (read)

t_RC

9 × T_C

136.4

—

112.5

—

ns

t_RAC

4.75 × T_C− 7.5

4.75 × T_C− 6.5

—

64.5

—

52.9

159 CAS assertion to data valid (read)

t_CAC

2.25 × T_C− 7.5

2.25 × T_C− 6.5

—

26.6

—

ns

21.6

160 Column address valid to data valid (read)

t_AA

3 × T_C− 7.5

3 × T_C− 6.5

—

40.0

—

31.0

161 CAS deassertion to data not valid (read hold

time)

t_OFF

0.0

—

0.0

—

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t_RP

3.25 × T_C− 4.0 45.2

5.75 × T_C− 4.0 83.1

3.25 × T_C− 4.0 45.2

4.75 × T_C− 4.0 68.0

2.25 × T_C− 4.0 30.1

—

36.6

67.9

36.6

55.5

24.1

29.3

19.9

—

ns

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

—

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

2.5 × T_C± 2

35.9

24.5

39.9

28.5

33.3

23.9

1.75 × T_C± 2

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-27

1, 2

Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States

(continued)

80 MHz

66 MHz

No.

Characteristics³

Symbol Expression⁴

Unit

Min

Max

—

Min

49.1

30.4

36.6

17.9

5.4

Max

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

t_CRP

t_CP

4.25 × T_C− 4.0 59.8

2.75 × T_C− 4.0 37.7

3.25 × T_C− 4.0 45.2

1.75 × T_C− 4.0 22.5

—

ns

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

178 CAS deassertion to WR⁵assertion

179 RAS deassertion to WR⁵assertion

t_ASR

t_RAH

t_ASC

t_CAH

t_AR

0.75 × T_C− 4.0

7.4

3.25 × T_C− 4.0 45.2

5.75 × T_C− 4.0 83.1

36.6

67.9

46.0

21.2

11.9

t_RAL

t_RCS

t_RCH

t_RRH

4 × T_C− 4.0

2 × T_C− 3.8

56.6

26.5

1.25 × T_C− 3.7 15.2

0.25 × T_C− 3.7

0.25 × T_C− 3.0

0.1

—

0.1

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t_WCH

t_WCR

t_WP

3 × T_C− 4.2

41.3

79.1

—

33.3

64.6

101.8

105.1

92.6

55.4

36.6

67.9

64.5

14.8

17.9

102.3

—

ns

5.5 × T_C− 4.2

8.5 × T_C− 4.5 124.3

8.75 × T_C− 4.3 128.3

7.75 × T_C− 4.3 113.1

4.75 × T_C− 4.0 68.0

3.25 × T_C− 4.0 45.2

5.75 × T_C− 4.0 83.1

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

192 RD assertion to data valid

t_RWL

t_CWL

t_DS

t_DH

t_DHR

t_WCS

t_CSR

t_RPC

t_ROH

t_GA

5.5 × T_C− 4.3

1.5 × T_C− 4.0

79.0

18.7

1.75 × T_C− 4.0 22.5

8.5 × T_C− 4.0 124.8

7.5 × T_C− 7.5

7.5 × T_C− 6.5

—

106.1

—

87.3

DSP56366 Technical Data, Rev. 3.1

3-28

Freescale Semiconductor

1, 2

Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States

(continued)

80 MHz

66 MHz

No.

Characteristics³

Symbol Expression⁴

Unit

Min

Max

—

Min

0.0

9.1

—

Max

193 RD deassertion to data not valid⁴

194 WR assertion to data active

t_GZ

0.0

—

ns

0.75 × T_C− 0.3 11.1

0.25 × T_C

—

195 WR deassertion to data high impedance

—

3.8

3.1

1

2

3

4

5

The number of wait states for out-of-page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

The asynchronous delays specified in the expressions are valid for DSP56366.

Either t_RCHor t_RRHmust be satisfied for read cycles.

.

1, 2

Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States

No.

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

Characteristics³

Random read or write cycle time

Symbol

t_RC

Expression⁴

12 × T_C

Min

Max

—

Unit

ns

120.0

—

RAS assertion to data valid (read)

CAS assertion to data valid (read)

Column address valid to data valid (read)

CAS deassertion to data not valid (read hold time)

RAS deassertion to RAS assertion

RAS assertion pulse width

t_RAC

t_CAC

t_AA

6.25 × T_C− 7.0

3.75 × T_C− 7.0

4.5 × T_C− 7.0

55.5

30.5

38.0

—

t_OFF

t_RP

0.0

4.25 × T_C− 4.0

7.75 × T_C− 4.0

5.25 × T_C− 4.0

6.25 × T_C− 4.0

3.75 × T_C− 4.0

2.5 × T_C± 4.0

1.75 × T_C± 4.0

5.75 × T_C− 4.0

4.25 × T_C− 4.0

1.75 × T_C− 4.0

0.75 × T_C− 4.0

38.5

73.5

48.5

58.5

33.5

21.0

13.5

53.5

38.5

13.5

3.5

—

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

—

CAS assertion to RAS deassertion

RAS assertion to CAS deassertion

CAS assertion pulse width

—

RAS assertion to CAS assertion

RAS assertion to column address valid

CAS deassertion to RAS assertion

CAS deassertion pulse width

29.0

21.5

—

Row address valid to RAS assertion

RAS assertion to row address not valid

Column address valid to CAS assertion

t_ASR

t_RAH

t_ASC

—

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-29

1, 2

Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States

(continued)

No.

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

Characteristics³

CAS assertion to column address not valid

RAS assertion to column address not valid

Column address valid to RAS deassertion

WR deassertion to CAS assertion

CAS deassertion to WR⁵assertion

RAS deassertion to WR⁵assertion

CAS assertion to WR deassertion

RAS assertion to WR deassertion

WR assertion pulse width

Symbol

t_CAH

t_AR

Expression⁴

Min

48.5

73.5

56.0

26.0

13.5

0.5

Max

Unit

ns

5.25 × T_C− 4.0

7.75 × T_C− 4.0

6 × T_C− 4.0

—

93.0

—

2.5

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

3.0 × T_C− 4.0

1.75 × T_C− 4.0

0.25 × T_C− 2.0

5 × T_C− 4.2

45.8

70.8

110.5

113.2

103.2

53.5

48.5

73.5

60.7

11.0

23.5

111.0

—

7.5 × T_C− 4.2

11.5 × T_C− 4.5

11.75 × T_C− 4.3

10.25 × T_C− 4.3

5.75 × T_C− 4.0

5.25 × T_C− 4.0

7.75 × T_C− 4.0

6.5 × T_C− 4.3

1.5 × T_C− 4.0

2.75 × T_C− 4.0

11.5 × T_C− 4.0

10 × T_C− 7.0

WR assertion to RAS deassertion

WR assertion to CAS deassertion

Data valid to CAS assertion (write)

CAS assertion to data not valid (write)

RAS assertion to data not valid (write)

WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

t_DH

t_DHR

t_WCS

t_CSR

t_RPC

t_ROH

t_GA

CAS assertion to RAS assertion (refresh)

RAS deassertion to CAS assertion (refresh)

RD assertion to RAS deassertion

RD assertion to data valid

RD deassertion to data not valid³

WR assertion to data active

t_GZ

0.0

0.75 × T_C− 0.3

0.25 × T_C

7.2

WR deassertion to data high impedance

—

1

2

3

4

5

The number of wait states for out-of-page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

The asynchronous delays specified in the expressions are valid for DSP56366.

Either t_RCHor t_RRHmust be satisfied for read cycles.

.

DSP56366 Technical Data, Rev. 3.1

3-30

Freescale Semiconductor

1, 2

Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States

No.

Characteristics³

Symbol

t_RC

Expression

16 × T_C

Min

Max

—

Unit

ns

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

161 CAS deassertion to data not valid (read hold time)

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

133.3

—

t_RAC

t_CAC

t_AA

8.25 × T_C− 5.7

4.75 × T_C− 5.7

5.5 × T_C− 5.7

0.0

63.0

33.9

40.1

—

t_OFF

t_RP

0.0

6.25 × T_C− 4.0

9.75 × T_C− 4.0

6.25 × T_C− 4.0

8.25 × T_C− 4.0

4.75 × T_C− 4.0

3.5 × T_C± 2

48.1

77.2

48.1

64.7

35.6

27.2

20.9

60.6

48.1

18.9

2.2

—

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

—

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

—

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

31.2

24.9

—

2.75 × T_C± 2

7.75 × T_C− 4.0

6.25 × T_C− 4.0

2.75 × T_C− 4.0

0.75 × T_C− 4.0

6.25 × T_C− 4.0

9.75 × T_C− 4.0

7 × T_C− 4.0

—

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

178 CAS deassertion to WR⁴assertion

179 RAS deassertion to WR⁵assertion

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t_ASR

t_RAH

t_ASC

t_CAH

t_AR

—

48.1

77.2

54.3

37.9

10.9

0.1

—

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

—

5 × T_C− 3.8

—

1.75 × T_C− 3.7

0.25 × T_C− 2.0

6 × T_C− 4.2

—

45.8

75.0

124.7

126.9

—

9.5 × T_C− 4.2

15.5 × T_C− 4.5

15.75 × T_C− 4.3

—

183 WR assertion to RAS deassertion

t_RWL

—

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-31

1, 2

Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States

(continued)

No.

Characteristics³

Symbol

t_CWL

t_DS

Expression

14.25 × T_C− 4.3

8.75 × T_C− 4.0

6.25 × T_C− 4.0

9.75 × T_C− 4.0

9.5 × T_C− 4.3

1.5 × T_C− 4.0

4.75 × T_C− 4.0

15.5 × T_C− 4.0

14 × T_C− 5.7

Min

114.4

68.9

48.1

77.2

74.9

8.5

Max

—

Unit

ns

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

—

t_DH

—

t_DHR

t_WCS

t_CSR

t_RPC

t_ROH

t_GA

—

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

192 RD assertion to data valid

—

35.6

125.2

—

111.0

—

193 RD deassertion to data not valid³

194 WR assertion to data active

t_GZ

0.0

0.75 × T_C− 0.3

0.25 × T_C

5.9

—

195 WR deassertion to data high impedance

—

2.1

1

2

3

4

The number of wait states for out-of-page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

Either t_RCHor t_RRHmust be satisfied for read cycles.

DSP56366 Technical Data, Rev. 3.1

3-32

Freescale Semiconductor

157

163

165

162

169

RAS

167

168

164

170

166

CAS

171

173

174

175

Row Address

172

Column Address

176

A0–A17

177

179

191

WR

RD

168

160

159

193

158

192

161

Data

In

D0–D23

AA0476

Figure 3-15 DRAM Out-of-Page Read Access

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-33

157

162

163

165

162

RAS

167

168

164

169

166

170

CAS

171

173

172

174

176

Row Address

Column Address

A0–A17

181

175

188

180

182

WR

RD

184

183

187

186

185

195

194

Data Out

D0–D23

AA0477

Figure 3-16 DRAM Out-of-Page Write Access

DSP56366 Technical Data, Rev. 3.1

3-34

Freescale Semiconductor

157

162

163

165

162

RAS

CAS

190

170

189

177

WR

AA0478

Figure 3-17 DRAM Refresh Access

3.10.3 Arbitration Timings

Table 3-17 Asynchronous Bus Arbitration timing

120 MHz

Min Max

No.

Characteristics

Expression

Unit

250

BB assertion window from BG input negation.

Delay from BB assertion to BG assertion

2 .5* Tc + 5

2 * Tc + 5

—

25.8

—

ns

251

21.7

Notes:

1. Bit 13 in the OMR register must be set to enter Asynchronous Arbitration mode

2. If Asynchronous Arbitration mode is active, none of the timings in Table 3-17 is required.

3. In order to guarantee timings 250, and 251, it is recommended to assert BG inputs to different 56300 devices (on the

same bus) in a non overlap manner as shown in Figure 3-18.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-35

BG1

BB

250

BG2

251

Figure 3-18 Asynchronous Bus Arbitration Timing

BG1

BG2

250+251

Figure 3-19 Asynchronous Bus Arbitration Timing

Background explanation for Asynchronous Bus Arbitration:

The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs.

These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a

result of this delay, a 56300 part may assume mastership and assert BB for some time after BG is negated.

This is the reason for timing 250.

Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is

exposed to other 56300 components which are potential masters on the same bus. If BG input is asserted

before that time, a situation of BG asserted, and BB negated, may cause another 56300 component to

assume mastership at the same time. Therefore some non-overlap period between one BG input active to

another BG input active is required. Timing 251 ensures that such a situation is avoided.

DSP56366 Technical Data, Rev. 3.1

3-36

Freescale Semiconductor

3.11 Parallel Host Interface (HDI08) Timing

1, 2

Table 3-18 Host Interface (HDI08) Timing

120 MHz

No.

Characteristics³

Expression

Unit

Min Max

317 Read data strobe assertion width⁴

HACK read assertion width

T_C+ 9.9

—

18.3

—

ns

318 Read data strobe deassertion width⁴

HACK read deassertion width

9.9

ns

319 Read data strobe deassertion width⁴after “Last Data Register” reads^5,6, or

between two consecutive CVR, ICR, or ISR reads⁷

2.5 × T_C+ 6.6

27.4

,

HACK deassertion width after “Last Data Register” reads^{5 6}

320 Write data strobe assertion width⁸

HACK write assertion width

—

13.2

27.4

—

ns

321 Write data strobe deassertion width⁸

HACK write deassertion width

2.5 × T_C+ 6.6

• after ICR, CVR and “Last Data Register” writes⁵

• after IVR writes, or

16.5

—

• after TXH:TXM writes (with HBE=0), or

• after TXL:TXM writes (with HBE=1)

—

9.9

0.0

9.9

—

ns

322 HAS assertion width

323 HAS deassertion to data strobe assertion⁹

324 Host data input setup time before write data strobe deassertion⁸

Host data input setup time before HACK write deassertion

325 Host data input hold time after write data strobe deassertion⁸

Host data input hold time after HACK write deassertion

—

3.3

—

ns

326 Read data strobe assertion to output data active from high impedance⁴

HACK read assertion to output data active from high impedance

327 Read data strobe assertion to output data valid⁴

HACK read assertion to output data valid

24.2

9.9

—

328 Read data strobe deassertion to output data high impedance⁴

HACK read deassertion to output data high impedance

—

329 Output data hold time after read data strobe deassertion⁴

Output data hold time after HACK read deassertion

3.3

330 HCS assertion to read data strobe deassertion⁴

331 HCS assertion to write data strobe deassertion⁸

332 HCS assertion to output data valid

T_C+9.9

—

18.2

9.9

—

ns

—

19.1

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-37

1, 2

Table 3-18 Host Interface (HDI08) Timing

Characteristics³

(continued)

Expression

120 MHz

No.

Unit

Min Max

333 HCS hold time after data strobe deassertion⁹

—

0.0

4.7

3.3

0

—

ns

334 Address (AD7–AD0) setup time before HAS deassertion (HMUX=1)

335 Address (AD7–AD0) hold time after HAS deassertion (HMUX=1)

336 A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before data

strobe assertion⁹

• Read

• Write

4.7

3.3

—

337 A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after data strobe

deassertion⁹

—

T_C

ns

338 Delay from read data strobe deassertion to host request assertion for “Last

8.3

16.7

—

, ,

Data Register” read^{4 5 10}

339 Delay from write data strobe deassertion to host request assertion for “Last

2 × T_C

—

, ,

Data Register” write^{5 8 10}

340 Delay from data strobe assertion to host request deassertion for “Last Data

19.1

300.0

, ,

Register” read or write (HROD = 0)^{5 9 10}

341 Delay from data strobe assertion to host request deassertion for “Last Data

—

, ,

,

Register” read or write (HROD = 1, open drain Host Request)^{5 9 10 11}

342 Delay from DMA HACK deassertion to HOREQ assertion

• For “Last Data Register” read⁵

• For “Last Data Register” write⁵

• For other cases

2 × T_C+ 19.1

35.8

—

1.5 × T_C+ 19.1 31.6

0.0

343 Delay from DMA HACK assertion to HOREQ deassertion

• HROD = 0⁵

—

20.2

ns

344 Delay from DMA HACK assertion to HOREQ deassertion for “Last Data

Register” read or write

300.0

,

• HROD = 1, open drain Host Request^{5 11}

1

2

3

4

5

6

See Host Port Usage Considerations in the DSP56366 User’s Manual.

In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.

V_CC= 3.3 V ± 0.16 V; T_J= –40°C to +110°C, C_L= 50 pF

The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.

The “last data register” is the register at address $7, which is the last location to be read or written in data transfers.

This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers

without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.

This timing is applicable only if two consecutive reads from one of these registers are executed.

The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.

The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single

data strobe mode.

7

8

9

¹⁰The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode.

¹¹In this calculation, the host request signal is pulled up by a 4.7 kΩ resistor in the open-drain mode.

DSP56366 Technical Data, Rev. 3.1

3-38

Freescale Semiconductor

317

318

HACK

328

327

326

329

HD7–HD0

HOREQ

AA1105

Figure 3-20 Host Interrupt Vector Register (IVR) Read Timing Diagram

HA0–HA2

336

337

333

330

HCS

317

HRD, HDS

318

319

328

332

327

329

326

341

HD0–HD7

338

340

HOREQ,

HRRQ,

HTRQ

AA0484

Figure 3-21 Read Timing Diagram, Non-Multiplexed Bus

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-39

HA0–HA2

337

333

336

331

HCS

320

HWR, HDS

321

325

324

HD0–HD7

340

339

341

HOREQ, HRRQ, HTRQ

AA0485

Figure 3-22 Write Timing Diagram, Non-Multiplexed Bus

DSP56366 Technical Data, Rev. 3.1

3-40

Freescale Semiconductor

HA8–HA10

336

337

322

HAS

323

317

HRD, HDS

334

318

319

335

327

328

329

HAD0–HAD7

Address

Data

326

338

340

341

HOREQ, HRRQ, HTRQ

AA0486

Figure 3-23 Read Timing Diagram, Multiplexed Bus

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-41

HA8–HA10

336

322

HAS

323

320

HWR, HDS

334

324

321

325

335

HAD0–HAD7

Data

340

Address

339

341

HOREQ, HRRQ, HTRQ

AA0487

Figure 3-24 Write Timing Diagram, Multiplexed Bus

HOREQ

(Output)

342

343

344

320

321

HACK

(Input)

TXH/M/L

Write

324

325

H0–H7

(Input)

Data

Valid

Figure 3-25 Host DMA Write Timing Diagram

DSP56366 Technical Data, Rev. 3.1

3-42

Freescale Semiconductor

HOREQ

(Output)

343

342

318

317

HACK

(Input)

RXH

Read

327

326

328

329

H0-H7

(Output)

Data

Valid

Figure 3-26 Host DMA Read Timing Diagram

3.12 Serial Host Interface SPI Protocol Timing

Table 3-19 Serial Host Interface SPI Protocol Timing

Filter

No.

Characteristics¹

Mode

Expression

Min

Max

Unit

Mode

Bypassed

Narrow

Wide

140 Tolerable spike width on clock or data in

141 Minimum serial clock cycle = t_SPICC(min)

142 Serial clock high period

—

0

50

100

—

ns

—

Master

Slave

Bypassed

Narrow

Wide

6×T_C+46

96

6×T_C+152

6×T_C+223

0.5×t_SPICC–10

2.5×T_C+12

2.5×T_C+102

2.5×T_C+189

202

273

38

Bypassed

Narrow

Wide

91

126.5

32.8

122.8

209.8

Bypassed

Narrow

Wide

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-43

Table 3-19 Serial Host Interface SPI Protocol Timing (continued)

Filter

No.

Characteristics¹

Mode

Expression

Min

Max

Unit

Mode

Bypassed

Narrow

Wide

143 Serial clock low period

Master

0.5×t_SPICC–10

2.5×T_C+12

2.5×T_C+102

2.5×T_C+189

—

38

91

—

ns

126.5

32.8

122.8

209.8

—

Slave

Bypassed

Narrow

Wide

—

144 Serial clock rise/fall time

Master

Slave

—

10

2000

—

146 SS assertion to first SCK edge

CPHA = 0

Bypassed

Narrow

Wide

3.5×T_C+15

0

44.2

0

—

0

—

CPHA = 1

Slave

Bypassed

Narrow

Wide

10

0

—

9

ns

0

147 Last SCK edge to SS not asserted

Bypassed

Narrow

Wide

12

102

189

0

189

148 Data input valid to SCK edge (data input

set-up time)

Master/Slave Bypassed

0

MAX{(20-T_C), 0}

MAX{(40-T_C), 0}

2.5×T_C+10

2.5×T_C+30

2.5×T_C+50

2

Narrow

Wide

11.7

31.7

30.8

50.8

70.8

2

149 SCK last sampling edge to data input not Master/Slave Bypassed

valid

Narrow

Wide

150 SS assertion to data out active

Slave

—

151 SS deassertion to data high impedance²

9

—

DSP56366 Technical Data, Rev. 3.1

3-44

Freescale Semiconductor

Table 3-19 Serial Host Interface SPI Protocol Timing (continued)

Filter

No.

Characteristics¹

Mode

Expression

Min

Max

Unit

Mode

152 SCK edge to data out valid

(data out delay time)

Master/Slave Bypassed

2×T_C+33

2×T_C+123

2×T_C+210

T_C+5

—

49.7

139.7

226.7

—

ns

Narrow

Wide

Master/Slave Bypassed

Narrow

—

153 SCK edge to data out not valid

(data out hold time)

13.3

63.3

114.3

—

T_C+55

—

Wide

T_C+106

T_C+33

—

154 SS assertion to data out valid

(CPHA = 0)

Slave

—

41.3

157 First SCK sampling edge to HREQ output

deassertion

Bypassed

Narrow

Wide

2.5×T_C+30

2.5×T_C+120

2.5×T_C+217

2.5×T_C+30

2.5×T_C+80

2.5×T_C+136

2.5×T_C+30

—

50.8

140.8

237.8

—

ns

—

158 Last SCK sampling edge to HREQ output

not deasserted (CPHA = 1)

Slave

Bypassed

Narrow

Wide

50.8

100.8

156.8

50.8

—

159 SS deassertion to HREQ output not

deasserted (CPHA = 0)

—

160 SS deassertion pulse width (CPHA = 0)

161 HREQ in assertion to first SCK edge

Slave

—

T_C+6

14.3

—

ns

Master

Bypassed

0.5 × t_SPICC

2.5×T_C+43

+

111.8

Narrow

Wide

—

0.5 ×t_SPICC

2.5×T_C+43

+

164.8

200.3

0

—

ns

0.5 ×t_SPICC

2.5×T_C+43

+

162 HREQ in deassertion to last SCK

sampling edge (HREQ in set-up time)

(CPHA = 1)

Master

0

163 First SCK edge to HREQ in not asserted

(HREQ in hold time)

—

0

—

ns

1

2

V_CC= 3.16 V 0.16 V; T_J= –40°C to +110°C, C_L= 50 pF

Periodically sampled, not 100% tested

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-45

SS

(Input)

143

141

142

143

144

SCK (CPOL = 0)

(Output)

142

SCK (CPOL = 1)

(Output)

148

149

148

149

MISO

(Input)

MSB

Valid

LSB

Valid

153

152

MSB

MOSI

(Output)

LSB

161

163

HREQ

(Input)

AA0271

Figure 3-27 SPI Master Timing (CPHA = 0)

DSP56366 Technical Data, Rev. 3.1

3-46

Freescale Semiconductor

SS

(Input)

143

142

141

142

143

144

SCK (CPOL = 0)

(Output)

144

SCK (CPOL = 1)

(Output)

148

149

MISO

(Input)

MSB

Valid

LSB

Valid

152

153

MOSI

(Output)

MSB

LSB

161

162

163

HREQ

(Input)

AA0272

Figure 3-28 SPI Master Timing (CPHA = 1)

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-47

SS

(Input)

143

141

147

142

144

160

SCK (CPOL = 0)

(Input)

146

142

144

143

SCK (CPOL = 1)

(Input)

154

152

153

151

LSB

150

MISO

(Output)

MSB

148

149

MSB

Valid

MOSI

(Input)

LSB

Valid

157

159

HREQ

(Output)

AA0273

Figure 3-29 SPI Slave Timing (CPHA = 0)

DSP56366 Technical Data, Rev. 3.1

3-48

Freescale Semiconductor

SS

(Input)

143

141

147

142

144

SCK (CPOL = 0)

(Input)

146

142

144

143

SCK (CPOL = 1)

(Input)

152

153

151

150

MISO

(Output)

MSB

LSB

148

149

MSB

Valid

LSB

Valid

MOSI

(Input)

157

158

HREQ

(Output)

AA0274

Figure 3-30 SPI Slave Timing (CPHA = 1)

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-49

2

3.13 Serial Host Interface (SHI) I C Protocol Timing

2

Table 3-20 SHI I C Protocol Timing

Standard

Fast Mode⁵

Min

Unit

Symbol/

Expression

Mode⁴

No.

Characteristics^1,2,3

Min

Max

Tolerable spike width on SCL or SDA

Filters bypassed

—

0

50

—

0

ns

Narrow filters enabled

Wide filters enabled

50

—

100

—

100

400

—

ns

171 SCL clock frequency

171 SCL clock cycle

F_SCL

T_SCL

—

kHz

μs

10

2.5

1.3

0.6

1.3

172 Bus free time

T_BUF

4.7

4.0

4.7

4.0

—

μs

173 Start condition set-up time

174 Start condition hold time

175 SCL low period

T_SU;STA

T_HD;STA

T_LOW

—

μs

—

μs

—

μs

176 SCL high period

T_HIGH

—

μs

177 SCL and SDA rise time

178 SCL and SDA fall time

179 Data set-up time

T

1000

300

—

20 + 0.1 × C_b

300

—

ns

R

T

—

20 + 0.1 × C_b

ns

F

T_SU;DAT

T_HD;DAT

F_DSP

250

0.0

100

0.0

ns

180 Data hold time

—

0.9

μs

181 DSP clock frequency

Filters bypassed

MHz

10.6

11.8

13.1

—

3.4

—

28.5

39.7

61.0

—

0.9

—

Narrow filters enabled

Wide filters enabled

182 SCL low to data out valid

183 Stop condition set-up time

T_VD;DAT

T_SU;STO

t_SU;RQI

μs

ns

4.0

0.6

184 HREQ in deassertion to last SCL edge

(HREQ in set-up time)

0.0

DSP56366 Technical Data, Rev. 3.1

3-50

Freescale Semiconductor

2

Table 3-20 SHI I C Protocol Timing (continued)

Standard

Fast Mode⁵

Min

Unit

Symbol/

Expression

Mode⁴

No.

Characteristics^1,2,3

Min

Max

186 First SCL sampling edge to HREQ output

deassertion

T_NG;RQO

ns

Filters bypassed

2 × T_C+ 30

2 × T_C+ 120

2 × T_C+ 208

T_AS;RQO

—

46.7

136.7

224.7

—

46.7

136.7

224.7

Narrow filters enabled

Wide filters enabled

187 Last SCL edge to HREQ output not

deasserted

ns

Filters bypassed

Narrow filters enabled

Wide filters enabled

2 × T_C+ 30

2 × T_C+ 80

2 × T_C+ 135

T_AS;RQI

46.7

96.7

—

46.7

96.7

—

151.6

188 HREQ in assertion to first SCL edge

Filters bypassed

ns

0.5 × T_I2_CCP

-

4440

4373

0.0

—

1041

999

958

0.0

—

0.5 × T_C- 21

Narrow filters enabled

Wide filters enabled

189 First SCL edge to HREQ in not asserted

(HREQ in hold time)

t_HO;RQI

1

2

3

4

5

V_CC= 3.16 V 0.16 V; T_J= –40°C to +110°C

Pull-up resistor: R_P(min) = 1.5 kOhm

Capacitive load: C_b(max) = 400 pF

It is recommended to enable the wide filters when operating in the I²C Standard Mode.

It is recommended to enable the narrow filters when operating in the I²C Fast Mode.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-51

3.13.1 Programming the Serial Clock

2

The programmed serial clock cycle, T

HCKR (SHI clock control register).

, is specified by the value of the HDM[7:0] and HRS bits of the

I CCP

2

The expression for T

is

I CCP

T

= [T × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]

C

2

I CCP

where

HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight

prescaler is operational. When HRS is set, the prescaler is bypassed.

HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256

(HDM[7:0] = $00 to $FF) may be selected.

2

In I C mode, the user may select a value for the programmed serial clock cycle from

6 × T if HDM[7:0] = 02 and HRS = 1

$

C

to

4096 × T

if HDM[7:0] =

$FF and HRS = 0

C

2

The programmed serial clock cycle (T

), SCL rise time (T ), and the filters selected should be chosen

I CCP

R

in order to achieve the desired SCL serial clock cycle (T ), as shown in Table 3-21.

SCL

Table 3-21 SCL Serial Clock Cycle (T

) generated as Master

SCL

2

Filters bypassed

T_{I CCP}+ 2.5 × T_C+ 45ns + T_R

2

Narrow filters enabled

Wide filters enabled

T_{I CCP}+ 2.5 × T_C+ 135ns + T_R

2

T_{I CCP}+ 2.5 × T_C+ 223ns + T_R

EXAMPLE:

For DSP clock frequency of 120 MHz (i.e. T = 8.33ns), operating in a standard mode I C environment

2

C

(F

= 100 kHz (i.e. T

= 10μs), T = 1000ns), with wide filters enabled:

SCL

R

T

= 10μs – 2.5 × 8.33ns – 223ns – 1000ns = 8756ns

2

I CCP

Choosing HRS = 0 gives

HDM[7:0] = 8756ns ⁄ (2 × 8.33ns × 8) – 1 = 64.67

Thus the HDM[7:0] value should be programmed to $41 (=65).

DSP56366 Technical Data, Rev. 3.1

3-52

Freescale Semiconductor

2

The resulting T

will be:

I CCP

T

= [T × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]

2

C

I CCP

T

= [8.33ns × 2 × (65 + 1) × (7 × (1 – 0) + 1)]

2

I CCP

T

= [8.33ns × 2 × 66 × 8] = 8796.48ns

2

I CCP

171

173

176

175

SCL

177

180

178

172

179

MSB

SDA

LSB

ACK

Stop

Start

174

188

186

182

183

187

189

184

HREQ

AA0275

2

Figure 3-31 I C Timing

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-53

3.14 Enhanced Serial Audio Interface Timing

Table 3-22 Enhanced Serial Audio Interface Timing

No.

Characteristics^{1, 2, 3}

Symbol

Expression

Min

Max

Condition⁴

Unit

430 Clock cycle⁵

t_SSICC

4 × T

33.3

25.0

27.2

—

i ck

x ck

ns

C

3 × T

C

TXC:max[3*tc; t454]

—

431 Clock high period

• For internal clock

• For external clock

ns

2 × T − 10.0

6.7

—

C

1.5 × T

12.5

C

432 Clock low period

• For internal clock

• For external clock

—

2 × T − 10.0

6.7

—

C

1.5 × T

12.5

C

433 RXC rising edge to FSR out (bl) high

434 RXC rising edge to FSR out (bl) low

435 RXC rising edge to FSR out (wr) high⁶

436 RXC rising edge to FSR out (wr) low⁶

437 RXC rising edge to FSR out (wl) high

438 RXC rising edge to FSR out (wl) low

—

37.0

22.0

x ck

ns

i ck a

—

37.0

22.0

x ck

i ck a

—

39.0

24.0

x ck

i ck a

—

39.0

24.0

x ck

i ck a

—

36.0

21.0

x ck

i ck a

—

37.0

22.0

x ck

i ck a

439 Data in setup time before RXC (SCK in

synchronous mode) falling edge

0.0

—

x ck

i ck

19.0

440 Data in hold time after RXC falling edge

5.0

3.0

—

x ck

i ck

441 FSR input (bl, wr) high before RXC

falling edge⁶

23.0

1.0

—

x ck

i ck a

442 FSR input (wl) high before RXC falling

edge

1.0

—

x ck

23.0

i ck a

443 FSR input hold time after RXC falling

edge

3.0

0.0

—

x ck

i ck a

DSP56366 Technical Data, Rev. 3.1

3-54

Freescale Semiconductor

Table 3-22 Enhanced Serial Audio Interface Timing (continued)

No.

Characteristics^{1, 2, 3}

Symbol

Expression

Min

Max

Condition⁴

Unit

444 Flags input setup before RXC falling

edge

—

0.0

—

x ck

ns

19.0

i ck s

445 Flags input hold time after RXC falling

edge

—

6.0

0.0

—

x ck

ns

i ck s

446 TXC rising edge to FST out (bl) high

447 TXC rising edge to FST out (bl) low

448 TXC rising edge to FST out (wr) high⁶

449 TXC rising edge to FST out (wr) low⁶

450 TXC rising edge to FST out (wl) high

451 TXC rising edge to FST out (wl) low

—

29.0

15.0

x ck

i ck

—

31.0

17.0

x ck

i ck

—

31.0

17.0

x ck

i ck

—

33.0

19.0

x ck

i ck

—

30.0

16.0

x ck

i ck

—

31.0

17.0

x ck

i ck

452 TXC rising edge to data out enable from

high impedance

—

31.0

17.0

x ck

i ck

453 TXC rising edge to transmitter #0 drive

enable assertion

—

34.0

20.0

x ck

i ck

454 TXC rising edge to data out valid

23 + 0.5 × T

—

27.2

21.0

x ck

i ck

C

21.0

455 TXC rising edge to data out high

impedance⁷

—

31.0

16.0

x ck

i ck

456 TXC rising edge to transmitter #0 drive

enable deassertion⁷

—

34.0

20.0

x ck

i ck

457 FST input (bl, wr) setup time before TXC

falling edge⁶

2.0

—

x ck

i ck

21.0

458 FST input (wl) to data out enable from

high impedance

—

27.0

—

ns

459 FST input (wl) to transmitter #0 drive

enable assertion

—

31.0

—

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-55

Table 3-22 Enhanced Serial Audio Interface Timing (continued)

No.

Characteristics^{1, 2, 3}

Symbol

Expression

Min

Max

Condition⁴

Unit

460 FST input (wl) setup time before TXC

falling edge

—

2.0

—

x ck

i ck

ns

21.0

461 FST input hold time after TXC falling

edge

—

4.0

0.0

—

x ck

i ck

ns

462 Flag output valid after TXC rising edge

—

32.0

18.0

x ck

i ck

463 HCKR/HCKT clock cycle

—

40.0

—

ns

464 HCKT input rising edge to TXC output

465 HCKR input rising edge to RXC output

27.5

—

1

2

V_CC= 3.16 V 0.16 V; T_J= –40°C to +110°C, C_L= 50 pF

i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(asynchronous implies that TXC and RXC are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that TXC and RXC are the same clock)

bl = bit length

wl = word length

wr = word length relative

3

4

TXC(SCKT pin) = transmit clock

RXC(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high frequency clock

HCKR(HCKR pin) = receive high frequency clock

5

6

For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync

signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one

before last bit clock of the first word in frame.

7

Periodically sampled and not 100% tested

DSP56366 Technical Data, Rev. 3.1

3-56

Freescale Semiconductor

430

431

432

TXC

(Input/Output)

446

447

FST (Bit)

Out

450

451

FST (Word)

Out

454

452

454

455

First Bit

Last Bit

459

Data Out

Transmitter

#0 Drive

Enable

457

453

456

461

460

FST (Bit) In

458

461

FST (Word) In

Flags Out

462

See Note

Notes In network mode, output flag transitions can occur at the start of each time slot within the

frame. In normal mode, the output flag state is asserted for the entire frame period.

AA0490

Figure 3-32 ESAI Transmitter Timing

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-57

430

431

432

RXC

(Input/Output)

433

434

FSR (Bit)

Out

437

438

FSR (Word)

Out

440

439

443

Last Bit

First Bit

Data In

441

FSR (Bit)

In

442

443

445

FSR (Word)

In

444

Flags In

AA0491

Figure 3-33 ESAI Receiver Timing

HCKT

463

SCKT(output)

464

Figure 3-34 ESAI HCKT Timing

DSP56366 Technical Data, Rev. 3.1

3-58

Freescale Semiconductor

HCKR

463

SCKR (output)

465

Figure 3-35 ESAI HCKR Timing

3.15 Digital Audio Transmitter Timing

Table 3-23 Digital Audio Transmitter Timing

120 MHz

No.

Characteristic

Expression

Unit

Min

—

Max

60

ACI frequency (see note)

1 / (2 x T_C)

2 × T_C

MHz

ns

220

221

222

223

ACI period

16.7

4.2

—

ACI high duration

ACI low duration

0.5 × T_C

1.5 × T_C

—

ns

—

ns

ACI rising edge to ADO valid

12.5

ns

Note: In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56366 internal

clock frequency. For example, if the DSP56366 is running at 120 MHz internally, the ACI frequency should be less than

60 MHz.

ACI

220

221

222

223

ADO

AA1280

Figure 3-36 Digital Audio Transmitter Timing

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-59

3.16 Timer Timing

Table 3-24 Timer Timing

Expression

120 MHz

No.

Characteristics

Unit

Min

18.7

Max

—

480

481

TIO Low

TIO High

2 × T_C+ 2.0

ns

—

Note: V_CC= 3.3 V ± 0.16 V; T_J= –40°C to +110°C, C_L= 50 pF

TIO

480

481

AA0492

Figure 3-37 TIO Timer Event Input Restrictions

3.17 GPIO Timing

Table 3-25 GPIO Timing

No.

Characteristics¹

Expression

Min

—

Max

32.8

—

Unit

490²EXTAL edge to GPIO out valid (GPIO out delay time)

ns

491

492

493

EXTAL edge to GPIO out not valid (GPIO out hold time)

GPIO In valid to EXTAL edge (GPIO in set-up time)

EXTAL edge to GPIO in not valid (GPIO in hold time)

4.8

10.2

1.8

54.5

—

494²Fetch to EXTAL edge before GPIO change

6.75 × T_C-1.8

—

495

496

GPIO out rise time

GPIO out fall time

—

13

—

13

1

2

V_CC= 3.3 V 0.16 V; T_J= –40°C to +110°C, C_L= 50 pF

Valid only when PLL enabled with multiplication factor equal to one.

DSP56366 Technical Data, Rev. 3.1

3-60

Freescale Semiconductor

EXTAL

(Input)

490

491

GPIO

(Output)

492

493

GPIO

(Input)

Valid

A0–A17

494

Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO

and R0 contains the address of GPIO data register.

GPIO

(Output)

495

496

Figure 3-38 GPIO Timing

3.18 JTAG Timing

1, 2

Table 3-26 JTAG Timing

All frequencies

No.

Characteristics

Unit

Min

Max

22.0

—

500 TCK frequency of operation (1/(T_C× 3); maximum 22 MHz)

501 TCK cycle time in Crystal mode

502 TCK clock pulse width measured at 1.5 V

503 TCK rise and fall times

0.0

45.0

20.0

0.0

MHz

ns

—

ns

3.0

—

ns

504 Boundary scan input data setup time

505 Boundary scan input data hold time

506 TCK low to output data valid

5.0

ns

24.0

0.0

—

ns

40.0

—

ns

507 TCK low to output high impedance

508 TMS, TDI data setup time

0.0

ns

5.0

ns

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-61

1, 2

Table 3-26 JTAG Timing

(continued)

All frequencies

No.

Characteristics

Unit

Min

Max

—

509 TMS, TDI data hold time

510 TCK low to TDO data valid

25.0

0.0

ns

44.0

511 TCK low to TDO high impedance

0.0

Notes: 1.

4.

1

V_CC= 3.3 V 0.16 V; T_J= –40°C to +110°C, C_L= 50 pF

All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

2

501

502

VM

502

VM

VIH

503

TCK

(Input)

VIL

503

AA0496

Figure 3-39 Test Clock Input Timing Diagram

VIH

TCK

(Input)

VIL

504

Input Data Valid

505

Data

Inputs

506

507

506

Data

Output Data Valid

Outputs

Data

Outputs

Data

Outputs

Output Data Valid

AA0497

Figure 3-40 Boundary Scan (JTAG) Timing Diagram

DSP56366 Technical Data, Rev. 3.1

3-62

Freescale Semiconductor

VIH

509

TCK

(Input)

VIL

508

Input Data Valid

TDI

TMS

(Input)

510

TDO

(Output)

Output Data Valid

511

TDO

(Output)

510

TDO

(Output)

Output Data Valid

AA0498

Figure 3-41 Test Access Port Timing Diagram

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-63

NOTES

DSP56366 Technical Data, Rev. 3.1

3-64

Freescale Semiconductor

4 Packaging

4.1

Pin-out and Package Information

This section provides information about the available package for this product, including diagrams of the

package pinouts and tables describing how the signals described in Section 2, “Signal/Connection

Descriptions” 1 are allocated for the package. The DSP56366 is available in a 144-pin LQFP package.

Table 4-1 and Table 4-2 show the pin/name assignments for the packages.

4.1.1

LQFP Package Description

Top view of the 144-pin LQFP package is shown in Figure 4-1 with its pin-outs. The package drawing is

shown in Figure 4-2.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

4-1

SCK/SCL

SS#/HA2

HREQ#

1

2

108

107

106

105

104

103

102

101

100

99

D6

D5

3

D4

D3

SDO0/SDO0_1

SDO1/SDO1_1

SDO2/SDI3/SDO2_1/SDI3_1

SDO3/SDI2/SDO3_1/SDI2_1

VCCS

4

5

GNDD

VCCD

D2

6

7

8

D1

D0

GNDS

9

SDO4/SDI1

SDO5/SDI0

FST

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

A17

A16

A15

GNDA

VCCQH

A14

A13

A12

VCCQL

GNDQ

A11

A10

GNDA

VCCA

A9

98

97

FSR

96

SCKT

95

SCKR

94

HCKT

93

HCKR

92

VCCQL

91

GNDQ

90

VCCQH

89

HDS/HWR

HRW/HRD

HACK/HRRQ

HOREQ/HTRQ

VCCS

88

87

86

85

84

A8

GNDS

83

A7

ADO

82

A6

ACI

81

GNDA

VCCA

A5

TIO0

80

HCS/HA10

HA9/HA2

HA8/HA1

HAS/HA0

HAD7

79

78

A4

77

A3

76

A2

75

GNDA

VCCA

A1

HAD6

HAD5

74

73

Figure 4-1 144-pin package

DSP56366 Technical Data, Rev. 3.1

4-2

Freescale Semiconductor

Table 4-1 Signal Identification by Name

Signal Name Pin No. Signal Name Pin No. Signal Name

Pin No.

9

Signal Name

Pin No.

4

A0

A1

72

73

D9

113

114

115

116

117

118

121

122

123

124

125

128

131

132

133

55

GNDS

SDO0/SDO0_1

D10

26

32

31

23

43

42

41

40

37

36

35

34

33

17

16

30

21

24

3

SDO1/SDO1_1

5

A2

76

D11

HA8/HA1

HA9/HA2

HACK/HRRQ

HAD0

SDO2/SDI3/SDO2_1/SDI3_1

6

A3

77

D12

SDO3/SDI2/SDO3_1/SDI2_1

SDO4/SDI1

SDO4_1/SDI1_1

SDO5/SDI0

SDO5_1/SDI0_1

SS#/HA2

TA#

7

A4

78

D13

10

A5

79

D14

138

11

A6

82

D15

HAD1

A7

83

D16

HAD2

48

A8

84

D17

HAD3

2

A9

85

D18

HAD4

62

A10

A11

A12

A13

A14

A15

A16

A17

AA0

AA1

AA2

ACI

ADO

BB#

BG#

BR#

CAS#

D0

88

D19

HAD5

TCK

141

140

139

29

89

D20

HAD6

TDI

92

D21

HAD7

TDO

93

D22

HAS/HA0

HCKR

TIO0

94

D23

TMS

142

74

97

EXTAL

FSR

HCKT

VCCA

98

13

HCS/HA10

HDS/HWR

HOREQ/HTRQ

HREQ#

VCCA

80

99

FSR_1

FST

59

VCCA

86

70

12

VCCC

57

69

FST_1

GNDA

GNDC

GNDD

GNDH

GNDP

GNDQ

50

VCCC

65

51

75

HRW/HRD

MODA/IRQA#

MODB/IRQB#

MODC/IRQC#

MODD/IRQD#

MISO/SDA

MOSI/HA0

PCAP

22

137

136

135

134

144

143

46

61

68

44

1

VCCD

103

111

119

129

38

28

81

VCCD

27

87

VCCD

64

96

VCCD

71

58

VCCH

63

66

VCCQH

VCCQL

VCCP

20

52

104

112

120

130

39

95

100

101

102

105

106

107

108

109

110

49

D1

PINIT/NMI#

RD#

18

D2

56

D3

RESET#

SCK/SCL

SCKR

91

D4

47

126

45

D5

19

15

60

14

53

D6

54

SCKR_1

SCKT

VCCS

8

D7

90

VCCS

25

D8

127

SCKT_1

WR#

67

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

4-3

Table 4-2 Signal Identification by Pin Number

Pin No.

1

Signal Name

SCK/SCL

SS#/HA2

HREQ#

Pin No.

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

Signal Name

HAD4

Pin No. Signal Name Pin No.

Signal Name

D7

73

74

A1

VCCA

GNDA

A2

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

2

VCCH

GNDH

HAD3

D8

3

75

VCCD

GNDD

D9

4

SDO0/SDO0_1

SDO1/SDO1_1

SDO2/SDI3/SDO2_1/SDI3_1

SDO3/SDI2/SDO3_1/SDI2_1

VCCS

76

5

HAD2

77

A3

6

HAD1

78

A4

D10

7

HAD0

79

A5

D11

8

RESET#

VCCP

PCAP

GND

80

VCCA

GNDA

A6

D12

9

GNDS

81

D13

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

SDO4/SDI1

SDO5/SDI0

FST

82

D14

83

A7

VCCD

GNDD

D15

SDO5_1/SDI0_1

VCCQH

FST_1

AA2

84

A8

FSR

85

A9

SCKT

86

VCCA

GNDA

A10

D16

SCKR

87

D17

HCKT

CAS#

88

D18

HCKR

SCKT_1

GNDQ

EXTAL

VCCQL

VCCC

GNDC

FSR_1

SCKR_1

PINIT/NMI#

TA#

89

A11

D19

VCCQL

90

GNDQ

VCCQL

A12

VCCQL

GNDQ

D20

GNDQ

91

VCCQH

92

HDS/HWR

HRW/HRD

HACK/HRRQ

HOREQ/HTRQ

VCCS

93

A13

VCCD

GNDD

D21

94

A14

95

VCCQH

GNDA

A15

96

D22

97

D23

GNDS

98

A16

MODD/IRQD#

MODC/IRQC#

MODB/IRQB#

MODA/IRQA#

SDO4_1/SDI1_1

TDO

ADO

BR#

99

A17

ACI

BB#

100

101

102

103

104

105

106

107

108

D0

TIO0

VCCC

GNDC

WR#

D1

HCS/HA10

HA9/HA2

HA8/HA1

HAS/HA0

HAD7

D2

VCCD

GNDD

D3

RD#

TDI

AA1

TCK

AA0

D4

TMS

HAD6

BG#

D5

MOSI/HA0

MISO/SDA

HAD5

A0

D6

DSP56366 Technical Data, Rev. 3.1

4-4

Freescale Semiconductor

4.1.2

LQFP Package Mechanical Drawing

CASE 918-03

Figure 4-2 DSP56366 144-pin LQFP Package

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

4-5

DSP56366 Technical Data, Rev. 3.1

4-6

Freescale Semiconductor

5 Design Considerations

5.1

Thermal Design Considerations

An estimation of the chip junction temperature, T , in °C can be obtained from the following equation:

J

T = T + (P × R

)

J

A

D

θJA

Where:

T

= ambient temperature °C

A

R

= package junction-to-ambient thermal resistance °C/W

= power dissipation in package W

qJA

D

P

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and

a case-to-ambient thermal resistance.

R

= R

+ R

θJA

θJC

θCA

Where:

R

= package junction-to-ambient thermal resistance °C/W

= package junction-to-case thermal resistance °C/W

= package case-to-ambient thermal resistance °C/W

θJA

θJC

θCA

R

is device-related and cannot be influenced by the user. The user controls the thermal environment to

θJC

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

θCA

the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB), or

otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This

model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through

the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where

the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the

device thermal performance may need the additional modeling capability of a system level thermal

simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which

the package is mounted. Again, if the estimations obtained from R

the thermal performance is adequate, a system level model may be appropriate.

do not satisfactorily answer whether

θJA

A complicating factor is the existence of three common ways for determining the junction-to-case thermal

resistance in plastic packages.

•

To minimize temperature variation across the surface, the thermal resistance is measured from the

junction to the outside surface of the package (case) closest to the chip mounting area when that

surface has a proper heat sink.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

5-1

•

To define a value approximately equal to a junction-to-board thermal resistance, the thermal

resistance is measured from the junction to where the leads are attached to the case.

If the temperature of the package case (T ) is determined by a thermocouple, the thermal resistance

T

is computed using the value obtained by the equation (T – T )/P .

J

T

D

As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the

first definition. From a practical standpoint, that value is also suitable for determining the junction

temperature from a case thermocouple reading in forced convection environments. In natural convection,

using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple

reading on the case of the package will estimate a junction temperature slightly hotter than actual

temperature. Hence, the new thermal metric, thermal characterization parameter or Ψ , has been defined

JT

to be (T – T )/P . This value gives a better estimate of the junction temperature in natural convection

J

T

D

when using the surface temperature of the package. Remember that surface temperature readings of

packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and

to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge

thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

5.2

Electrical Design Considerations

CAUTION

This device contains circuitry protecting against damage due to high static

voltage or electrical fields. However, normal precautions should be taken to

avoid exceeding maximum voltage ratings. Reliability of operation is

enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.,

either GND or V ). The suggested value for a pullup or pulldown resistor

CC

is 10 kOhm.

Use the following list of recommendations to assure correct DSP operation:

•

Provide a low-impedance path from the board power supply to each V pin on the DSP and from

the board ground to each GND pin.

CC

Use at least six 0.01–0.1 μF bypass capacitors positioned as close as possible to the four sides of

the package to connect the V power source to GND.

CC

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V and

CC

GND pins are less than 1.2 cm (0.5 inch) per capacitor lead.

•

Use at least a four-layer PCB with two inner layers for V and GND.

CC

Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.

This recommendation particularly applies to the address and data buses as well as the IRQA,

IRQB, IRQC, IRQD, TA and BG pins. Maximum PCB trace lengths on the order of 15 cm

(6 inches) are recommended.

•

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating

capacitance. This is especially critical in systems with higher capacitive loads that could create

higher transient currents in the V and GND circuits.

CC

All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the three

pins with internal pull-up resistors (TMS, TDI, TCK).

DSP56366 Technical Data, Rev. 3.1

5-2

Freescale Semiconductor

•

Take special care to minimize noise levels on the V

and GND pins.

CCP P

If multiple DSP56366 devices are on the same board, check for cross-talk or excessive spikes on

the supplies due to synchronous operation of the devices.

•

RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied

while RESET is being asserted.

At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V

never exceeds 3.95 V.

CC

5.3

Power Consumption Considerations

Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current

consumption are described in this section. Most of the current consumed by CMOS devices is alternating

current (ac), which is charging and discharging the capacitances of the pins and internal nodes.

Current consumption is described by the following formula:

I = C × V × f

where:

C

V

f

= node/pin capacitance

= voltage swing

= frequency of node/pin toggle

Example 1. Current Consumption

For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 120

MHz clock, toggling at its maximum possible rate (60 MHz), the current consumption is

–12

6

I = 50 × 10

× 3.3 × 60 × 10 = 9.9mA

The maximum internal current (I max) value reflects the typical possible switching of the internal buses

CCI

on best-case operation conditions, which is not necessarily a real application case. The typical internal

current (I

) value reflects the average switching of the internal buses on typical operating conditions.

CCItyp

For applications that require very low current consumption, do the following:

•

Set the EBD bit when not accessing external memory.

Minimize external memory accesses and use internal memory accesses.

Minimize the number of pins that are switching.

Minimize the capacitive load on the pins.

Connect the unused inputs to pull-up or pull-down resistors.

Disable unused peripherals.

One way to evaluate power consumption is to use a current per MIPS measurement methodology to

minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP).

A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific

test current measurements, and the following equation to derive the current per MIPS value.

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

5-3

I ⁄ MIPS = I ⁄ MHz = (I

– I

) ⁄ (F2 = F1)

typF1

typF2

where:

I

= current at F2

typF2

= current at F1

typF1

F2

F1

= high frequency (any specified operating frequency)

= low frequency (any specified operating frequency lower than F2)

NOTE

F1 should be significantly less than F2. For example, F2 could be 66 MHz

and F1 could be 33 MHz. The degree of difference between F1 and F2

determines the amount of precision with which the current rating can be

determined for an application.

5.4

PLL Performance Issues

The following explanations should be considered as general observations on expected PLL behavior.

There is no testing that verifies these exact numbers. These observations were measured on a limited

number of parts and were not verified over the entire temperature and voltage ranges.

5.4.1

Phase Jitter Performance

The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL

and the internal DSP clock for a given device in specific temperature, voltage, input frequency and MF.

These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz

and MF ≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10

and input frequencies greater than 10 MHz, this jitter is less than ±2 ns.

5.4.2

Frequency Jitter Performance

The frequency jitter of the PLL is defined as the variation of the frequency of the internal DSP clock. For

small MF (MF < 10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this jitter is

between 0.5% and approximately 2%. For large MF (MF > 500), the frequency jitter is 2–3%.

5.4.3

Input (EXTAL) Jitter Requirements

The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL

is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency

of the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be

2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the

prescribed values.

DSP56366 Technical Data, Rev. 3.1

5-4

Freescale Semiconductor

5.5

Host Port Considerations

Careful synchronization is required when reading multi-bit registers that are written by another

asynchronous system. This synchronization is a common problem when two asynchronous systems are

connected, as they are in the host interface. The following paragraphs present considerations for proper

operation.

5.5.1

Host Programming Considerations

•

Unsynchronized Reading of Receive Byte Registers—When reading the receive byte registers,

receive register high (RXH), receive register middle (RXM), or receive register low (RXL), the

host interface programmer should use interrupts or poll the receive register data full (RXDF) flag

that indicates whether data is available. This ensures that the data in the receive byte registers will

be valid.

•

Overwriting Transmit Byte Registers—The host interface programmer should not write to the

transmit byte registers, transmit register high (TXH), transmit register middle (TXM), or transmit

register low (TXL), unless the transmit register data empty (TXDE) bit is set, indicating that the

transmit byte registers are empty. This ensures that the transmit byte registers will transfer valid

data to the host receive (HRX) register.

Synchronization of Status Bits from DSP to Host—HC, HOREQ, DMA, HF3, HF2, TRDY,

TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host processor

(refer to the user’s manual for descriptions of these status bits). The host can read these status bits

very quickly without regard to the clock rate used by the DSP, but the state of the bit could be

changing during the read operation. This is not generally a system problem, because the bit will be read

correctly in the next pass of any host polling routine.

However, if the host asserts HEN for more than timing number 31, with

a minimum cycle time of timing number 31 + 32, then these status bits are guaranteed to be

stable. Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP

changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits

during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has

significance, the host could read the wrong combination. Therefore, read the bits twice and

check for consensus.

•

Overwriting the Host Vector—The host interface programmer should change the host vector

(HV) register only when the host command (HC) bit is clear. This ensures that the DSP interrupt

control logic will receive a stable vector.

Cancelling a Pending Host Command Exception—The host processor may elect to clear the HC

bit to cancel the host command exception request at any time before it is recognized by the DSP.

Because the host does not know exactly when the exception will be recognized (due to exception

processing synchronization and pipeline delays), the DSP may execute the host command

exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the

same time that the HC bit is cleared.

•

Variance in the Host Interface Timing—The host interface (HDI) may vary (e.g. due to the PLL

lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP should first make

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

5-5

sure that the part has completed its HI port programming (e.g., by setting the INIT bit in ICR then

polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ together

with the INIT and then polling INIT, ISR, and the HOREQ pin).

5.5.2

DSP Programming Considerations

•

Synchronization of Status Bits from Host to DSP—DMA, HF1, HF0, HCP, HTDE, and HRDF

status bits are set or cleared by the host processor side of the interface. These bits are individually

synchronized to the DSP clock. (Refer to the user’s manual for descriptions of these status bits.)

•

Reading HF0 and HF1 as an Encoded Pair—Care must be exercised when reading status bits

HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have

significance). A very small probability exists that the DSP will read the status bits synchronized

during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus.

DSP56366 Technical Data, Rev. 3.1

5-6

Freescale Semiconductor

6 Ordering Information

Consult a Freescale Semiconductor, Inc. sales office or authorized distributor to determine product

availability and to place an order.

For information on ordering DSP Audio products, refer to the current SG1004, DSP Selector Guide, at

http://www.freescale.com

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

6-1

NOTES

DSP56366 Technical Data, Rev. 3.1

6-2

Freescale Semiconductor

Appendix A Power Consumption Benchmark

The following benchmark program permits evaluation of DSP power usage in a test situation. It enables

the PLL, disables the external clock, and uses repeated multiply-accumulate instructions with a set of

synthetic DSP application data to emulate intensive sustained DSP operation.

;********************************************************************;*********

***********************************************************

;* ;* CHECKS

Typical Power Consumption

;********************************************************************

page

200,55,0,0,0

nolist

I_VEC EQU $000000 ; Interrupt vectors for program debug only

START EQU $8000 ; MAIN (external) program starting address

INT_PROG EQU $100 ; INTERNAL program memory starting address

INT_XDAT EQU $0

INT_YDAT EQU $0

; INTERNAL X-data memory starting address

; INTERNAL Y-data memory starting address

INCLUDE "ioequ.asm"

INCLUDE "intequ.asm"

list

org

P:START

;

movep #$0123FF,x:M_BCR; BCR: Area 3 : 1 w.s (SRAM)

; Default: 1 w.s (SRAM)

;

movep

#$0d0000,x:M_PCTL

; XTAL disable

; PLL enable

; CLKOUT disable

;

; Load the program

;

move

#INT_PROG,r0

#PROG_START,r1

do

move

#(PROG_END-PROG_START),PLOAD_LOOP

p:(r1)+,x0

move

x0,p:(r0)+

nop

PLOAD_LOOP

;

; Load the X-data

;

move

#INT_XDAT,r0

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

A-1

move

do

move

#XDAT_START,r1

#(XDAT_END-XDAT_START),XLOAD_LOOP

p:(r1)+,x0

x0,x:(r0)+

XLOAD_LOOP

;

; Load the Y-data

;

move

#INT_YDAT,r0

move

#YDAT_START,r1

do

move

#(YDAT_END-YDAT_START),YLOAD_LOOP

p:(r1)+,x0

move

YLOAD_LOOP

;

x0,y:(r0)+

jmp

INT_PROG

PROG_START

move

;

#$0,r0

#$0,r4

#$3f,m0

#$3f,m4

clr

a

clr

b

move

bset

;

#$0,x0

#$0,x1

#$0,y0

#$0,y1

#4,omr

; ebd

sbr

dor

mac

add

mac

move

#60,_end

x0,y0,a x:(r0)+,x1

x1,y1,a x:(r0)+,x0

a,b

x0,y0,a x:(r0)+,x1

x1,y1,a

y:(r4)+,y1

y:(r4)+,y0

b1,x:$ff

_end

bra

nop

sbr

PROG_END

nop

XDAT_START

org

;

x:0

dc

$262EB9

$86F2FE

$E56A5F

DSP56366 Technical Data, Rev. 3.1

A-2

Freescale Semiconductor

dc

$616CAC

$8FFD75

$9210A

$A06D7B

$CEA798

$8DFBF1

$A063D6

$6C6657

$C2A544

$A3662D

$A4E762

$84F0F3

$E6F1B0

$B3829

$8BF7AE

$63A94F

$EF78DC

$242DE5

$A3E0BA

$EBAB6B

$8726C8

$CA361

$2F6E86

$A57347

$4BE774

$8F349D

$A1ED12

$4BFCE3

$EA26E0

$CD7D99

$4BA85E

$27A43F

$A8B10C

$D3A55

$25EC6A

$2A255B

$A5F1F8

$2426D1

$AE6536

$CBBC37

$6235A4

$37F0D

$63BEC2

$A5E4D3

$8CE810

$3FF09

$60E50E

$CFFB2F

$40753C

$8262C5

$CA641A

$EB3B4B

$2DA928

$AB6641

$28A7E6

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

A-3

dc

$4E2127

$482FD4

$7257D

$E53C72

$1A8C3

$E27540

XDAT_END

YDAT_START

org

;

y:0

dc

$5B6DA

$C3F70B

$6A39E8

$81E801

$C666A6

$46F8E7

$AAEC94

$24233D

$802732

$2E3C83

$A43E00

$C2B639

$85A47E

$ABFDDF

$F3A2C

$2D7CF5

$E16A8A

$ECB8FB

$4BED18

$43F371

$83A556

$E1E9D7

$ACA2C4

$8135AD

$2CE0E2

$8F2C73

$432730

$A87FA9

$4A292E

$A63CCF

$6BA65C

$E06D65

$1AA3A

$A1B6EB

$48AC48

$EF7AE1

$6E3006

$62F6C7

$6064F4

$87E41D

$CB2692

$2C3863

$C6BC60

$43A519

$6139DE

DSP56366 Technical Data, Rev. 3.1

A-4

Freescale Semiconductor

dc

$ADF7BF

$4B3E8C

$6079D5

$E0F5EA

$8230DB

$A3B778

$2BFE51

$E0A6B6

$68FFB7

$28F324

$8F2E8D

$667842

$83E053

$A1FD90

$6B2689

$85B68E

$622EAF

$6162BC

$E4A245

YDAT_END

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

A-5

NOTES

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Document Number: DSP56366

Rev. 3.1

1/2007


型号：	DSP56362P
厂家：	Freescale
描述：	24-Bit Audio Digital Signal Processor 24位音频数字信号处理器数字信号处理器
文件：	总110页 (文件大小：1941K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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