DSP56364UM_技术文档

Document Number: DSP56364

Rev. 4.1, 10/2007

Freescale Semiconductor

Technical Data

DSP56364

24-Bit Audio Digital Signal Processor

Contents

1 Overview

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

2 Signal/Connection Descriptions. . . . . . . . . 2-1

3 Specifications. . . . . . . . . . . . . . . . . . . . . . . . 3-1

4 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

5 Design Considerations . . . . . . . . . . . . . . . . 5-1

6 Ordering Information . . . . . . . . . . . . . . . . . . 6-1

A IBIS Model. . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

The DSP56364 supports digital audio applications

requiring sound field processing, acoustic equalization,

and other digital audio algorithms. The DSP56364 uses

the high performance, single-clock-per-cycle DSP56300

core family of programmable CMOS digital signal

processors (DSPs) combined with the audio signal

processing capability of the Freescale Symphony™ DSP

family, as shown in Figure 1-1. This design provides a

two-fold performance increase over Freescale’s popular

Symphony family of DSPs while retaining code

compatibility. Significant architectural enhancements

include a barrel shifter, 24-bit addressing, instruction

cache, and direct memory access (DMA). The

DSP56364 offers 100 million instructions per second

(MIPS) using an internal 100 MHz clock at 3.3 V.

Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its

products.

Overview

Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

Used to indicate a signal that is active when pulled low (For example, the RESET pin is active

when low.)

“asserted”

Means that a high true (active high) signal is high or that a low true (active low) signal is low

Means that a high true (active high) signal is low or that a low true (active low) signal is high

“deasserted”

Examples:

Signal/Symbol

Logic State

Signal State

Voltage*

True

False

True

Asserted

Deasserted

Asserted

V_IL/ V_OL

V_IH/ V_OH

V_IL/ V_OL

False

Deasserted

Note: *Values for V_IL, V_OL, V_IH, and V_OHare defined by individual product specifications.

4

12

5

PROGRAMRAM

0.5Kx24

X

Y

MEMORY

RAM

MEMORY

RAM

SHI

GPIO

ESAI

PROGRAMROM

8Kx24

1KX24

1.5KX24

PERIPHERAL

EXPANSION

AREA

BootstrapROM

192x24

MEMORY

EXPANSION

AREA

ADDRESS

18

YAB

ADDRESS

EXTERNAL

ADDRESS

BUS

XAB

PAB

DAB

GENERATION UNIT

SIX CHANNELS

DMA UNIT

SWITCH

24-BIT

DSP56300

CORE

CONTROL

6

DRAM &SRAM

BUS

INTERFACE

DDB

YDB

XDB

PDB

GDB

DATA

8

EXTERNAL

DATA BUS

SWITCH

INTERNAL

DATA BUS

SWITCH

POWER

MGMT

DATA ALU

PLL

+

PROGRAM

INTERRUPT

CONT

PROGRAM

DECODE

CONT

PROGRAM

ADDRESS

GEN

24X24 56 56-BITMAC

→

4

JTAG

TWO56-BIT

ACCUMULATORS

BARRELSHIFTER

CLOCK

GEN

OnCE™

EXTAL

MODA/IRQA

MODB/IRQB

MODD/IRQD

24 BITS BUS

RESET

PINIT/NMI

Figure 1-1 DSP56364 Block Diagram

DSP56364 Technical Data, Rev. 4.1

1-2

Freescale Semiconductor

Overview

1.1

Features

1.1.1

Digital Signal Processing Core

•

100 Million Instructions Per Second (MIPS) with an 100 MHz clock at 3.3V.

Object Code Compatible with the 56000 core.

Data ALU with a 24 × 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic

support.

•

Program Control with position independent code support and instruction cache support.

Six-channel DMA controller.

PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors

i

(1 to 16) and power saving clock divider (2 : i = 0 to 7). Reduces clock noise.

•

Internal address tracing support and OnCE™ for Hardware/Software debugging.

JTAG port.

Very low-power CMOS design, fully static design with operating frequencies down to DC.

STOP and WAIT low-power standby modes.

1.1.2

On-Chip Memory Configuration

•

1.5K × 24 Bit Y-Data RAM.

1K × 24 Bit X-Data RAM.

8K × 24 Bit Program ROM.

0.5K × 24 Bit Program RAM and 192 × 24 Bit Bootstrap ROM.

0.75K × 24 Bit from Y Data RAM can be switched to Program RAM resulting in up to 1.25K × 24

Bit of Program RAM.

1.1.3

Off-Chip Memory Expansion

•

External Memory Expansion Port with 8-bit data bus.

Off-chip expansion up to 2 × 16M × 8-bit word of Data/Program memory when using DRAM.

Off-chip expansion up to 2 × 256k × 8-bit word of Data/Program memory when using SRAM.

Simultaneous glueless interface to SRAM and DRAM.

1.1.4

Peripheral Modules

•

Enhanced Serial Audio Interface (ESAI): 6 serial lines, 4 selectable as receive or transmit and 2

transmit only, master or slave. I S, Sony, AC97, network and other programmable protocols.

2

Unused pins of ESAI may be used as GPIO lines.

2

•

Serial Host Interface (SHI): SPI and I C protocols, 10-word receive FIFO, support for 8, 16 and

24-bit words.

Four dedicated GPIO lines.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

1-3

Overview

1.1.5

Packaging

•

100-pin plastic TQFP package.

1.2

Documentation

Table 1-1 lists the documents that provide a complete description of the DSP56364 and are required to

design properly with the part. Documentation is available from a local Freescale distributor, a Freescale

semiconductor sales office, a Freescale Literature Distribution Center, or through the Freescale DSP home

page on the Internet (the source for the latest information).

Table 1-1 DSP56364 Documentation

Document Name

Description

Order Number

DSP56300 Family Manual

Detailed description of the 56000-family

architecture and the 24-bit core processor and

instruction set

DSP56300FM

DSP56364 User’s Manual

DSP56364 Product Brief

Detailed description of memory, peripherals, and

interfaces

DSP56364UM

Brief description of the chip

DSP56364P

DSP56364

DSP56364 Technical Data Sheet

(this document)

Electrical and timing specifications; pin and

package descriptions

DSP56364 Technical Data, Rev. 4.1

1-4

Freescale Semiconductor

2 Signal/Connection Descriptions

2.1

Signal Groupings

The input and output signals of the DSP56364 are organized into functional groups, which are listed in

Table 2-1 and illustrated in Figure 2-1.

The DSP56364 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special

notice for this feature is added to the signal descriptions of those inputs.

Table 2-1 DSP56364 Functional Signal Groupings

Number of

Signals

Detailed

Description

Functional Group

Power (V_CC

)

18

14

3

Table 2-2

Table 2-3

Table 2-4

Table 2-5

Table 2-6

Table 2-7

Table 2-8

Table 2-12

Table 2-9

Table 2-10

Table 2-11

Ground (GND)

Clock and PLL

Address bus

Data bus

18

8

Port A¹

Bus control

6

Interrupt and mode control

General Purpose I/O

SHI

4

Port B²

Port C³

4

5

ESAI

12

4

JTAG/OnCE Port

1

2

3

Port A is the external memory interface port, including the external address bus, data bus, and control signals.

Port B signals are the GPIO signals.

Port C signals are the ESAI port signals multiplexed with the GPIO signals.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

2-1

Signal Groupings

OnCE™ ON-CHIP EMULATION/

PORT A ADDRESS BUS

JTAG PORT

TDI

A0-A17

TCK

TDO

TMS

VCCA (4)

GNDA (4)

DSP56364

PORT A DATA BUS

D0-D7

VCCD (1)

Port B

GPIO

PB0-PB3

GNDD (1)

PORT A BUS CONTROL

AA0-AA1/RAS0-RAS1

CAS

RD

WR

TA

VCCC (1)

GNDC (1)

RESERVED (4)

SERIAL AUDIO INTERFACE (ESAI)

Port C

SCKT [PC3]

FST [PC4]

HCKT [PC5]

SCKR [PC0]

FSR [PC1]

INTERRUPT AND

MODE CONTROL

MODA/IRQA

HCKR [PC2]

SDO0 [PC11]

SDO1 [PC10]

SDO2/SDI3 [PC9]

MODB/IRQB

MODD/IRQD

SDO3/SDI2 [PC8]

SDO4/SDI1 [PC7]

SDO5/SDI0 [PC6]

VCCSS (3)

RESET

PLL AND CLOCK

GNDS (3)

PINIT/NMI

SERIAL HOST INTERFACE (SHI)

PCAP

VCCP

GNDP

MOSI/HA0

SS/HA2

MISO/SDA

SCK/SCL

HREQ

EXTAL

QUIET POWER

VCCHQ (4)

VCCLQ (4)

GNDQ (4)

Figure 2-1 Signals Identified by Functional Group

DSP56364 Technical Data, Rev. 4.1

2-2

Freescale Semiconductor

Power

2.2

Power

Table 2-2 Power Inputs

Description

Power Name

V_CCP

PLL Power—V_CCPis V_CCdedicated for PLL use. The voltage should be well-regulated and the input should

be provided with an extremely low impedance path to the V_CCpower rail. There is one V_CCPinput.

V_CCLQ(4)

Quiet Core (Low) Power—V_CCLQis an isolated power for the internal processing logic. This input must be

tied externally to all other chip power inputs. The user must provide adequate external decoupling

capacitors. There are four V_CCLQinputs.

V_CCHQ(4)

Quiet External (High) Power—V_CCHQis a quiet power source for I/O lines. This input must be tied

externally to all other chip power inputs. The user must provide adequate decoupling capacitors. There are

four V_CCHQinputs.

V_CCA(4)

Address Bus Power—V_CCAis an isolated power for sections of the address bus

I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate

external decoupling capacitors. There are four V_CCAinputs.

V_CCD(1)

Data Bus Power—V_CCDis an isolated power for sections of the data bus I/O drivers. This input must be

tied externally to all other chip power inputs. The user must provide adequate external decoupling

capacitors. There is one V_CCDinputs.

V_CCC(1)

Bus Control Power—V_CCCis an isolated power for the bus control I/O drivers. This input must be tied

externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

There is one V_CCCinputs.

V_CCS(3)

SHI and ESAI —V_CCSis an isolated power for the SHI and ESAI. This input must be tied externally to all

other chip power inputs_L. The user must provide adequate external decoupling capacitors. There are three

V_CCSinputs.

2.3

Ground

Table 2-3 Grounds

Description

Ground Name

GND_P

PLL Ground—GND_Pis ground-dedicated for PLL use. The connection should be provided with an

extremely low-impedance path to ground. V_CCPshould be bypassed to GND_Pby a 0.47 μF capacitor

located as close as possible to the chip package. There is one GND_Pconnection.

GND_Q(4)

GND_A(4)

GND_D(1)

Quiet Ground—GND_Qis an isolated ground for the internal processing logic. This connection must be tied

externally to all other chip ground connections. The user must provide adequate external decoupling

capacitors. There are four GND_Qconnections.

Address Bus Ground—GND_Ais an isolated ground for sections of the address bus I/O drivers. This

connection must be tied externally to all other chip ground connections. The user must provide adequate

external decoupling capacitors. There are four GND_Aconnections.

Data Bus Ground—GND_Dis an isolated ground for sections of the data bus I/O drivers. This connection

must be tied externally to all other chip ground connections. The user must provide adequate external

decoupling capacitors. There is one GND_Dconnections.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

2-3

Clock and PLL

Table 2-3 Grounds (continued)

Description

Ground Name

GND_C(1)

Bus Control Ground—GND_Cis an isolated ground for the bus control I/O drivers. This connection must

be tied externally to all other chip ground connections. The user must provide adequate external decoupling

capacitors. There is one GND_Cconnections.

GND_S(3)

SHI and ESAI —GND_Sis an isolated ground for the SHI and ESAI. This connection must be tied externally

to all other chip ground connections. The user must provide adequate external decoupling capacitors.

There are three GND_Sconnections.

2.4

Clock and PLL

Table 2-4 Clock and PLL Signals

State During

Signal Name Type

Signal Description

Reset

EXTAL

Input

External Clock Input—An external clock source must be connected to EXTAL in

order to supply the clock to the internal clock generator and PLL.

PCAP

Input

PLL Capacitor—PCAP is an input connecting an off-chip capacitor to the PLL filter.

Connect one capacitor terminal to PCAP and the other terminal to V_CCP

.

If the PLL is not used, PCAP may be tied to V_CC, GND, or left floating.

PINIT/NMI

Input

PLL Initial/Nonmaskable Interrupt—During assertion of RESET, the value of

PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,

determining whether the PLL is enabled or disabled. After RESET de assertion and

during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a

negative-edge-triggered nonmaskable interrupt (NMI) request internally

synchronized to internal system clock.

This input is 5 V tolerant.

2.5

External Memory Expansion Port (Port A)

When the DSP56364 enters a low-power standby mode (stop or wait), it tri-states the relevant port A

signals: D0–D7, AA0, AA1, RD, WR, CAS.

2.5.1

External Address Bus

Table 2-5 External Address Bus Signals

State During

Reset

Signal Name

Type

Signal Description

A0–A17

Output

Keeper active Address Bus—A0–A17 are active-high outputs that specify the address for

external program and data memory accesses. Otherwise, the signals are kept

to their previous values by internal weak keepers. To minimize power

dissipation, A0–A17 do not change state when external memory spaces are not

being accessed.

DSP56364 Technical Data, Rev. 4.1

2-4

Freescale Semiconductor

External Memory Expansion Port (Port A)

2.5.2

External Data Bus

Table 2-6 External Data Bus Signals

Signal

Name

State During

Reset

Type

Signal Description

D0–D7

Input/

Output

Tri-stated

Data Bus—D0–D7 are active-high, bidirectional input/outputs that provide the

bidirectional data bus for external program and data memory accesses. D0–D7 are

tri-stated during hardware reset and when the DSP is in the stop or wait low-power

standby mode.

2.5.3

External Bus Control

Table 2-7 External Bus Control Signals

State During

Reset

Signal Name

Type

Signal Description

AA0–AA1/

Output

Tri-stated

Address Attribute or Row Address Strobe—When defined as AA, these signals

can be used as chip selects or additional address lines. When defined as RAS,

these signals can be used as RAS for DRAM interface. These signals are

tri-stateable outputs with programmable polarity. These signals are tri-stated during

hardware reset and when the DSP is in the stop or wait low-power standby mode.

RAS0–RAS1

CAS

RD

WR

TA

Output

Input

Tri-stated

Column Address Strobe— CAS is an active-low output used by DRAM to strobe

the column address. This signal is tri-stated during hardware reset and when the

DSP is in the stop or wait low-power standby mode.

Read Enable—RD is an active-low output that is asserted to read external memory

on the data bus. This signal is tri-stated during hardware reset and when the DSP

is in the stop or wait low-power standby mode.

Write Enable— WR is an active-low output that is asserted to write external

memory on the data bus. This signal is tri-stated during hardware reset and when

the DSP is in the stop or wait low-power standby mode.

Ignored Input Transfer Acknowledge—If there is no external bus activity, the TA input is ignored.

The TA input is a data transfer acknowledge (DTACK) function that can extend an

external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be

added to the wait states inserted by the BCR by keeping TA deasserted. In typical

operation, TA is deasserted at the start of a bus cycle, is asserted to enable

completion of the bus cycle, and is deasserted before the next bus cycle. The

current bus cycle completes one clock period after TA is asserted synchronous to

the internal system clock. The number of wait states is determined by the TA input

or by the bus control register (BCR), whichever is longer. The BCR can be used to

set the minimum number of wait states in external bus cycles.

In order to use the TA functionality, the BCR must be programmed to at least one

wait state. A zero wait state access cannot be extended by TA deassertion,

otherwise improper operation may result. TA can operate synchronously or

asynchronously, depending on the setting of the TAS bit in the operating mode

register (OMR).

TA functionality may not be used while performing DRAM type accesses, otherwise

improper operation may result.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

2-5

Interrupt and Mode Control

2.6

Interrupt and Mode Control

The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.

After RESET is deasserted, these inputs are hardware interrupt request lines.

Table 2-8 Interrupt and Mode Control

State During

Signal Name

Type

Signal Description

Reset

MODA/IRQA

Input

Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low

Schmitt-trigger input, internally synchronized to the internal system clock.

MODA/IRQA selects the initial chip operating mode during hardware reset and

becomes a level-sensitive or negative-edge-triggered, maskable interrupt request

input during normal instruction processing. MODA, MODB, and MODD select one

of 8 initial chip operating modes, latched into the OMR when the RESET signal

is deasserted. If IRQA is asserted synchronous to the internal system clock,

multiple processors can be re synchronized using the WAIT instruction and

asserting IRQA to exit the wait state. If the processor is in the stop standby state

and IRQA is asserted, the processor will exit the stop state.

This input is 5 V tolerant.

MODB/IRQB

MODD/IRQD

RESET

Input

Mode Select B/External Interrupt Request B—MODB/IRQB is an active-low

Schmitt-trigger input, internally synchronized to the internal system clock.

MODB/IRQB selects the initial chip operating mode during hardware reset and

becomes a level-sensitive or negative-edge-triggered, maskable interrupt request

input during normal instruction processing. MODA, MODB, and MODD select one

of 8 initial chip operating modes, latched into OMR when the RESET signal is

deasserted. If IRQB is asserted synchronous to the internal system clock,

multiple processors can be re-synchronized using the WAIT instruction and

asserting IRQB to exit the wait state.

This input is 5 V tolerant.

Mode Select D/External Interrupt Request D—MODD/IRQD is an active-low

Schmitt-trigger input, internally synchronized to the internal system clock.

MODD/IRQD selects the initial chip operating mode during hardware reset and

becomes a level-sensitive or negative-edge-triggered, maskable interrupt request

input during normal instruction processing. MODA, MODB, and MODD select one

of 8 initial chip operating modes, latched into OMR when the RESET signal is

deasserted. If IRQD is asserted synchronous to the internal system clock,

multiple processors can be re synchronized using the WAIT instruction and

asserting IRQD to exit the wait state.

This input is 5 V tolerant.

Reset—RESET is an active-low, Schmitt-trigger input. When asserted, the chip

is placed in the reset state and the internal phase generator is reset. The

Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to

reset the chip reliably. When the RESET signal is deasserted, the initial chip

operating mode is latched from the MODA, MODB, and MODD inputs. The

RESET signal must be asserted during power up. A stable EXTAL signal must

be supplied before deassertion of RESET.

This input is 5 V tolerant.

DSP56364 Technical Data, Rev. 4.1

2-6

Freescale Semiconductor

Serial Host Interface

2.7

Serial Host Interface

2

The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I C mode.

Table 2-9 Serial Host Interface Signals

Signal

Name

Signal

Type

State During

Reset

Signal Description

SCK

Input or

output

Tri-stated

SPI Serial Clock—The SCK signal is an output when the SPI is configured as a master

and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is

configured as a master, the SCK signal is derived from the internal SHI clock generator.

When the SPI is configured as a slave, the SCK signal is an input, and the clock signal

from the external master synchronizes the data transfer. The SCK signal is ignored by

the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both

the master and slave SPI devices, data is shifted on one edge of the SCK signal and is

sampled on the opposite edge where data is stable. Edge polarity is determined by the

SPI transfer protocol.

SCL

Input or

output

Tri-stated

I²C Serial Clock—SCL carries the clock for I²C bus transactions in the I²C mode. SCL

is a Schmitt-trigger input when configured as a slave and an open-drain output when

configured as a master. SCL should be connected to V_CCthrough a pull-up resistor.

This signal is tri-stated during hardware, software, and individual reset. Thus, there is

no need for an external pull-up in this state.

This input is 5 V tolerant.

MISO

SDA

Input or

output

Tri-stated

SPI Master-In-Slave-Out—When the SPI is configured as a master, MISO is the

master data input line. The MISO signal is used in conjunction with the MOSI signal for

transmitting and receiving serial data. This signal is a Schmitt-trigger input when

configured for the SPI Master mode, an output when configured for the SPI Slave

mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. An

external pull-up resistor is not required for SPI operation.

Input or

open-drain

output

I²C Data and Acknowledge—In I²C mode, SDA is a Schmitt-trigger input when

receiving and an open-drain output when transmitting. SDA should be connected to

V

_CCthrough a pull-up resistor. SDA carries the data for I²C transactions. The data in

SDA must be stable during the high period of SCL. The data in SDA is only allowed to

change when SCL is low. When the bus is free, SDA is high. The SDA line is only

allowed to change during the time SCL is high in the case of start and stop events. A

high-to-low transition of the SDA line while SCL is high is a unique situation, and is

defined as the start event. A low-to-high transition of SDA while SCL is high is a unique

situation defined as the stop event.

This signal is tri-stated during hardware, software, and individual reset. Thus, there is

no need for an external pull-up in this state.

This input is 5 V tolerant.

MOSI

Input or

output

Tri-stated

SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI is the

master data output line. The MOSI signal is used in conjunction with the MISO signal

for transmitting and receiving serial data. MOSI is the slave data input line when the

SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for

the SPI Slave mode.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

2-7

Serial Host Interface

Table 2-9 Serial Host Interface Signals (continued)

Signal

Name

Signal

Type

State During

Signal Description

Reset

HA0

Input

Tri-stated

I²C Slave Address 0—This signal uses a Schmitt-trigger input when configured for the

I²C mode. When configured for I²C slave mode, the HA0 signal is used to form the

slave device address. HA0 is ignored when configured for the I²C master mode.

This signal is tri-stated during hardware, software, and individual reset. Thus, there is

no need for an external pull-up in this state.

This input is 5 V tolerant.

SS

Input

SPI Slave Select—This signal is an active low Schmitt-trigger input when configured

for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable

the SPI slave for transfer. When configured for the SPI master mode, this signal should

be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus

error condition is flagged. If SS is deasserted, the SHI ignores SCK clocks and keeps

the MISO output signal in the high-impedance state.

HA2

I²C Slave Address 2—This signal uses a Schmitt-trigger input when configured for the

I²C mode. When configured for the I²C Slave mode, the HA2 signal is used to form the

slave device address. HA2 is ignored in the I²C master mode.

This signal is tri-stated during hardware, software, and individual reset. Thus, there is

no need for an external pull-up in this state.

This input is 5 V tolerant.

HREQ

Input or

Output

Tri-stated

Host Request—This signal is an active low Schmitt-trigger input when configured for

the master mode but an active low output when configured for the slave mode.

When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready

for the next data word transfer and deasserted at the first clock pulse of the new data

word transfer. When configured for the master mode, HREQ is an input. When asserted

by the external slave device, it will trigger the start of the data word transfer by the

master. After finishing the data word transfer, the master will await the next assertion of

HREQ to proceed to the next transfer.

This signal is tri-stated during hardware, software, personal reset, or when the

HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in

this state.

This input is 5 V tolerant.

DSP56364 Technical Data, Rev. 4.1

2-8

Freescale Semiconductor

Enhanced Serial Audio Interface

2.8

Enhanced Serial Audio Interface

Table 2-10 Enhanced Serial Audio Interface Signals

Signal

Name

State During

Reset

Signal Type

Signal Description

HCKR

Input or output

GPIO

High Frequency Clock for Receiver—When programmed as an input, this

disconnected signal provides a high frequency clock source for the ESAI receiver as an

alternate to the DSP core clock. When programmed as an output, this signal

can serve as a high-frequency sample clock (e.g., for external digital to analog

converters [DACs]) or as an additional system clock.

PC2

Input, output, or

disconnected

GPIO

Port C 2—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

HCKT

Input or output

GPIO

High Frequency Clock for Transmitter—When programmed as an input, this

disconnected signal provides a high frequency clock source for the ESAI transmitter as an

alternate to the DSP core clock. When programmed as an output, this signal

can serve as a high frequency sample clock (e.g., for external DACs) or as an

additional system clock.

PC5

FSR

Input, output, or

disconnected

GPIO

Port C 5—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Input or output

GPIO

Frame Sync for Receiver—This is the receiver frame sync input/output signal.

disconnected In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync

input or output used by all the enabled receivers. In the synchronous mode

(SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the

transmitter external buffer enable control (TEBE=1, RFSD=1).

When this pin is configured as serial flag pin, its direction is determined by the

RFSD bit in the RCCR register. When configured as the output flag OF1, this

pin will reflect the value of the OF1 bit in the SAICR register, and the data in the

OF1 bit will show up at the pin synchronized to the frame sync in normal mode

or the slot in network mode. When configured as the input flag IF1, the data

value at the pin will be stored in the IF1 bit in the SAISR register, synchronized

by the frame sync in normal mode or the slot in network mode.

PC1

FST

Input, output, or

disconnected

GPIO

Port C 1—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Input or output

GPIO

Frame Sync for Transmitter—This is the transmitter frame sync input/output

disconnected signal. For synchronous mode, this signal is the frame sync for both transmitters

and receivers. For asynchronous mode, FST is the frame sync for the

transmitters only. The direction is determined by the transmitter frame sync

direction (TFSD) bit in the ESAI transmit clock control register (TCCR).

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

2-9

Enhanced Serial Audio Interface

Table 2-10 Enhanced Serial Audio Interface Signals (continued)

Signal

Name

State During

Reset

Signal Type

Signal Description

PC4

Input, output, or

disconnected

GPIO

Port C 4—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SCKR

Input or output

GPIO

Receiver Serial Clock—SCKR provides the receiver serial bit clock for the

disconnected ESAI. The SCKR operates as a clock input or output used by all the enabled

receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the

synchronous mode (SYN=1).

When this pin is configured as serial flag pin, its direction is determined by the

RCKD bit in the RCCR register. When configured as the output flag OF0, this

pin will reflect the value of the OF0 bit in the SAICR register, and the data in the

OF0 bit will show up at the pin synchronized to the frame sync in normal mode

or the slot in network mode. When configured as the input flag IF0, the data

value at the pin will be stored in the IF0 bit in the SAISR register, synchronized

by the frame sync in normal mode or the slot in network mode.

PC0

Input, output, or

disconnected

GPIO

Port C 0—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SCKT

PC3

Input or output

GPIO

Transmitter Serial Clock—This signal provides the serial bit rate clock for the

disconnected ESAI. SCKT is a clock input or output used by all enabled transmitters and

receivers in synchronous mode, or by all enabled transmitters in asynchronous

mode.

Input, output, or

disconnected

GPIO

Port C 3—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO5

SDI0

PC6

Output

Input

GPIO

Serial Data Output 5—When programmed as a transmitter, SDO5 is used to

disconnected transmit data from the TX5 serial transmit shift register.

GPIO

Serial Data Input 0—When programmed as a receiver, SDI0 is used to receive

disconnected serial data into the RX0 serial receive shift register.

Input, output, or

disconnected

GPIO

Port C 6—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO4

Output

GPIO

Serial Data Output 4—When programmed as a transmitter, SDO4 is used to

disconnected transmit data from the TX4 serial transmit shift register.

DSP56364 Technical Data, Rev. 4.1

2-10

Freescale Semiconductor

Enhanced Serial Audio Interface

Table 2-10 Enhanced Serial Audio Interface Signals (continued)

Signal

Name

State During

Reset

Signal Type

Signal Description

SDI1

Input

GPIO

Serial Data Input 1—When programmed as a receiver, SDI1 is used to receive

disconnected serial data into the RX1 serial receive shift register.

PC7

Input, output, or

disconnected

GPIO Port C 7—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO3

SDI2

PC8

Output

Input

GPIO

Serial Data Output 3—When programmed as a transmitter, SDO3 is used to

disconnected transmit data from the TX3 serial transmit shift register.

GPIO

Serial Data Input 2—When programmed as a receiver, SDI2 is used to receive

disconnected serial data into the RX2 serial receive shift register.

Input, output, or

disconnected

GPIO

Port C 8—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO2

SDI3

PC9

Output

Input

GPIO

Serial Data Output 2—When programmed as a transmitter, SDO2 is used to

disconnected transmit data from the TX2 serial transmit shift register

GPIO

Serial Data Input 3—When programmed as a receiver, SDI3 is used to receive

disconnected serial data into the RX3 serial receive shift register.

Input, output, or

disconnected

GPIO

Port C 9—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO1

PC10

Output

GPIO

Serial Data Output 1—SDO1 is used to transmit data from the TX1 serial

disconnected transmit shift register.

Input, output, or

disconnected

GPIO

Port C 10—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO0

PC11

Output

GPIO

Serial Data Output 0—SDO0 is used to transmit data from the TX0 serial

disconnected transmit shift register.

Input, output, or

disconnected

GPIO

Port C 11—When the ESAI is configured as GPIO, this signal is individually

disconnected programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

2-11

JTAG/OnCE Interface

2.9

JTAG/OnCE Interface

Table 2-11 JTAG/OnCE Interface

Signal

Name

Signal State During

Signal Description

Type

Reset

TCK

Input

Test Clock—TCK is a test clock input signal used to synchronize the JTAG test logic.

It has an internal pull-up resistor.

This input is 5 V tolerant.

TDI

Input

Test Data Input—TDI is a test data serial input signal used for test instructions and

data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor.

This input is 5 V tolerant.

TDO

TMS

Output

Input

Tri-stated

Input

Test Data Output—TDO is a test data serial output signal used for test instructions and

data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller

states. TDO changes on the falling edge of TCK.

Test Mode Select—TMS is an input signal used to sequence the test controller’s state

machine. TMS is sampled on the rising edge of TCK and has an internal pull-up

resistor.

This input is 5 V tolerant.

Table 2-12 GPIO Signals

Signal

Name

State During

Signal Type

Signal Description

Reset

GPIO0–

GPIO3

Input, output or

disconnected

Disconnected

GPIO0–3—The General Purpose I/O pins are used for control and

handshake functions between the DSP and external circuitry. Each Port B

GPIO pin may be individually programmed as an input, output or

disconnected

DSP56364 Technical Data, Rev. 4.1

2-12

Freescale Semiconductor

3 Specifications

3.1

Introduction

The DSP56364 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs

and outputs. The DSP56364 specifications are preliminary and are from design simulations, and may not

be fully tested or guaranteed. Finalized specifications will be published after full characterization and

device qualifications are complete.

3.2

Maximum Ratings

CAUTION

This device contains circuitry protecting against damage due to high static

voltage or electrical fields. However, normal precautions should be taken to

avoid exceeding maximum voltage ratings. Reliability of operation is

enhanced if unused inputs are pulled to an appropriate logic voltage level

(e.g., either GND or V ). The suggested value for a pull-up or pull-down

CC

resistor is 10 kΩ.

NOTE

In the calculation of timing requirements, adding a maximum value of one

specification to a minimum value of another specification does not yield a

reasonable sum. A maximum specification is calculated using a worst case

variation of process parameter values in one direction. The minimum

specification is calculated using the worst case for the same parameters in

the opposite direction. Therefore, a “maximum” value for a specification

will never occur in the same device that has a “minimum” value for another

specification; adding a maximum to a minimum represents a condition that

can never exist.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-1

Thermal Characteristics

Table 3-1 Maximum Ratings

Rating¹

Symbol

Value^{1, 2}

−0.3 to +4.0

Unit

V

Supply Voltage

V_CC

All input voltages excluding “5 V tolerant” inputs³

All “5 V tolerant” input voltages³

V_IN

V_IN5

I

GND -0.3 to V_CC+ 0.3

GND − 0.3 to V_CC+ 3.95

10

V

Current drain per pin excluding V_CCand GND

Operating temperature range

mA

°C

T_J

-40 to +105

Storage temperature

T_STG

−55 to +125

1

GND = 0 V, V_CC= 3.3 V 0.16 V, T_J= –0°C to +105°C, C_L= 50 pF

Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the maximum rating may affect device reliability or cause permanent damage to the device.

2

3

CAUTION: All “5 V Tolerant” input voltages must not be more than 3.95 V greater than the supply voltage; this restriction

applies to “power on”, as well as during normal operation. In any case, the input voltages cannot be more than 5.75 V. “5 V

Tolerant” inputs are inputs that tolerate 5 V.

3.3

Thermal Characteristics

Table 3-2 Thermal Characteristics

Characteristic

Symbol

R_θJAor θ_JA

R_θJCor θ_JC

Ψ_JT

TQFP Value

49.87

Unit

°C/W

Junction-to-ambient thermal resistance¹

Junction-to-case thermal resistance²

Thermal characterization parameter

9.26

2.0

1

Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per SEMI

G38-87 in natural convection. (SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd.,

Mountain View, CA 94043, (415) 964-5111.)

Measurements were done with parts mounted on thermal test boards conforming to specification EIA/JESD51-3.

2

Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that

the cold plate temperature is used for the case temperature.

DSP56364 Technical Data, Rev. 4.1

3-2

Freescale Semiconductor

DC Electrical Characteristics

3.4

DC Electrical Characteristics

1

Table 3-3 DC Electrical Characteristics

Characteristics

Symbol

Min

Typ

Max

Unit

V

Supply voltage

V_CC

3.14

3.3

3.46

Input high voltage

• D(0:7), TA

V

V_IH

2.0

—

V_CC

• MOD²/IRQ², RESET, PINIT/NMI and all

JTAG/ESAI/GPIO/SHI (SPI mode) pins

V_IHP

V_CC+ 3.95

• SHI (I2C mode) pins

• EXTAL³

V_IHP

V_IHX

1.5

—

V_CC+ 3.95

V_CC

0.8 × V_CC

Input low voltage

V

• D(0:7), TA, MOD²/IRQ², RESET, PINIT

V_IL

V_ILP

V_ILX

I_IN

–0.3

-0.3

–0.3

–10

—

0.8

• JTAG/ESAI/GPIO/SHI (SPI mode)pins

• SHI (I2C mode) pins

0.3x V_CC

0.2 × V_CC

10

• EXTAL³

Input leakage current

μA

High impedance (off-state) input current (@ 2.4 V / 0.4 V)

I_TSI

V_OH

10

Output high voltage

• TTL (I_OH= –0.4 mA)^4,5

2.4

—

V

• CMOS (I_OH= –10 μA)⁴

V_CC– 0.01

Output low voltage

V_OL

• TTL (I_OL= 3.0 mA, open-drain pins I_OL= 6.7 mA)^4,5

—

0.4

• CMOS (I_OL= 10 μA)⁴

0.01

Internal supply current⁶at internal clock of 100 MHz

• In Normal mode

I_CCI

I_CCW

I_CCS

—

127

7. 5

100

1

181

11

mA

μA

• In Wait mode⁷

• In Stop mode⁸

PLL supply current

Input capacitance⁴

150

2.5

10

mA

pF

C_IN

—

1

V_CC= 3.3 V .16 V; T_J= 0°C to +105°C, C_L= 50 pF

2

3

Refers to MODA/IRQA, MODB/IRQB, and MODD/IRQD pins

Driving EXTAL to the low V_IHXor the high V_ILXvalue may cause additional power consumption (DC current). To minimize

power consumption, the minimum V_IHXshould be no lower than 0.9 × V_CCand the maximum V_ILXshould be no higher than

0.1 × V_CC

.

4

Periodically sampled and not 100% tested

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-3

AC Electrical Characteristics

5

This characteristic does not apply to PCAP.

6

Section 5, "Design Considerations" provides a formula to compute the estimated current requirements in Normal

mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on

synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results

of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with V_CC= 3.3 V at T_J

= 105°C. Maximum internal supply current is measured with V_CC= 3.46 V at T_J= 105°C.

7

In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signal is disabled during Stop

state.

8

In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to

float).

3.5

AC Electrical Characteristics

The timing waveforms shown in the AC electrical characteristics section are tested with a V maximum

IL

of 0.3 V and a V minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels

IH

8

shown in Note of the previous table. AC timing specifications, which are referenced to a device input

signal, are measured in production with respect to the 50% point of the respective input signal’s transition.

DSP56364 output levels are measured with the production test machine V and V reference levels set

OL

OH

at 0.4 V and 2.4 V, respectively.

NOTE

Although the minimum value for the frequency of EXTAL is 0 MHz, the

device AC test conditions are 15 MHz and rated speed.

3.6

Internal Clocks

Table 3-4 Internal Clocks

Expression^{1, 2}

Characteristics

Symbol

Min

Typ

Max

Internal operation frequency with PLL enabled

f

—

(Ef × MF)/

—

(PDF × DF)

Internal operation frequency with PLL disabled

Internal clock high period

f

—

Ef/2

—

T_H

• With PLL disabled

—

ET_C

—

• With PLL enabled and MF ≤ 4

0.49 × ET_C

×

0.51 × ET_C×

PDF × DF/MF

• With PLL enabled and MF > 4

0.47 × ET_C

×

—

0.53 × ET_C

×

PDF × DF/MF

DSP56364 Technical Data, Rev. 4.1

3-4

Freescale Semiconductor

External Clock Operation

Table 3-4 Internal Clocks (continued)

Expression^{1, 2}

Characteristics

Symbol

Min

Typ

Max

Internal clock low period

T_L

• With PLL disabled

—

ET_C

—

• With PLL enabled and MF ≤ 4

0.49 × ET_C

×

0.51 × ET_C×

PDF × DF/MF

• With PLL enabled and MF > 4

0.47 × ET_C

×

—

0.53 × ET_C

×

PDF × DF/MF

Internal clock cycle time with PLL enabled

T_C

—

ET_C× PDF ×

—

DF/MF

Internal clock cycle time with PLL disabled

Instruction cycle time

T_C

—

2 × ET_C

—

I_CYC

T_C

1

DF = Division Factor

Ef = External frequency

ET_C= External clock cycle

MF = Multiplication Factor

PDF = Predivision Factor

T_C= internal clock cycle

2

See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL.

3.7

External Clock Operation

The DSP56364 system clock is an externally supplied square wave voltage source connected to EXTAL

(See Figure 3-1).

V_IHC

Midpoint

EXTAL

ETH

ETL

V_ILC

2

3

4

ETC

Note: The midpoint is 0.5 (V_IHC+ V_ILC).

Figure 3-1 External Clock Timing

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-5

Phase Lock Loop (PLL) Characteristics

Table 3-5 Clock Operation

Characteristics

Frequency of EXTAL (EXTAL Pin Frequency)

No.

Symbol

Min

Max

1

Ef

0

100.0

The rise and fall time of this external clock should be 3 ns maximum.

2

3

4

EXTAL input high^{1, 2}

• With PLL disabled (46.7%–53.3% duty cycle⁶)

ET_H

ET_L

ET_C

4.67 ns

4.25 ns

∞

• With PLL enabled (42.5%–57.5% duty cycle⁶)

157.0 μs

EXTAL input low^{1, 2}

• With PLL disabled (46.7%–53.3% duty cycle⁶)

4.67 ns

4.25 ns

∞

• With PLL enabled (42.5%–57.5% duty cycle⁶)

157.0 μs

EXTAL cycle time²

• With PLL disabled

10.00 ns

∞

• With PLL enabled

273.1 μs

1

2

Measured at 50% of the input transition.

The maximum value for PLL enabled is given for minimum V_COand maximum MF.

3.8

Phase Lock Loop (PLL) Characteristics

Table 3-6 PLL Characteristics

Characteristics

Min

Max

Unit

MHz

pF

V_COfrequency when PLL enabled (MF × E_f× 2/PDF)

30

200

1

PLL external capacitor (PCAP pin to V_CCP) (C_PCAP

)

• @ MF ≤ 4

(MF × 580) − 100

MF × 830

(MF × 780) − 140

MF × 1470

• @ MF > 4

1

C_PCAPis the value of the PLL capacitor (connected between the P_CAPpin and V_CCP). The recommended value in pF for

C_PCAPcan be computed from one of the following equations:

(MF x 680)-120, for MF ≤ 4, or

MF x 1100, for MF > 4.

DSP56364 Technical Data, Rev. 4.1

3-6

Freescale Semiconductor

Reset, Stop, Mode Select, and Interrupt Timing

3.9

Reset, Stop, Mode Select, and Interrupt Timing

1

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing

No.

Characteristics

Expression²

Min

Max

Unit

8

9

Delay from RESET assertion to all pins at reset value³

—

26.0

ns

Required RESET duration⁴

• Power on, external clock generator, PLL disabled

50 × ET_C

1000 × ET_C

75000 × ET_C

2.5 × T_C

500.0

10.0

0.75

25.0

—

ns

• Power on, external clock generator, PLL enabled

• Power on, internal oscillator

μs

ms

ns

• During STOP, XTAL disabled (PCTL Bit 16 = 0)

• During STOP, XTAL enabled (PCTL Bit 16 = 1)

• During normal operation

2.5 × T_C

10

Delay from asynchronous RESET deassertion to first

external address output (internal reset deassertion)⁵

• Minimum

3.25 × T_C+ 2.0

34.5

—

211.5

—

ns

• Maximum

20.25 T_C+ 7.50

13

14

15

16

17

Mode select setup time

30.0

0.0

6.6

Mode select hold time

—

Minimum edge-triggered interrupt request assertion width

Minimum edge-triggered interrupt request deassertion width

—

Delay from IRQA, IRQB, IRQD, NMI assertion to external

memory access address out valid

• Caused by first interrupt instruction fetch

4.25 × T_C+ 2.0

7.25 × T_C+ 2.0

10 × T_C+ 5.0

44.5

74.5

—

ns

• Caused by first interrupt instruction execution

18

19

20

Delay from IRQA, IRQB, IRQD, NMI assertion to

general-purpose transfer output valid caused by first

interrupt instruction execution

105.0

Delay from address output valid caused by first interrupt

instruction execute to interrupt request deassertion for level

sensitive fast interrupts ^{6, 7}

3.75 × T_C+ WS × T_C– 10.94

3.25 × T_C+ WS × T_C– 10.94

—

ns

Delay from RD assertion to interrupt request deassertion

for level sensitive fast interrupts^{6, 7}

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-7

Reset, Stop, Mode Select, and Interrupt Timing

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing (continued)

1

No.

Characteristics

Expression²

Min

Max

Unit

21

Delay from WR assertion to interrupt request deassertion

for level sensitive fast interrupts^{6, 7}

ns

• DRAM for all WS

(WS + 3.5) × T_C– 10.94

(WS + 3) × T_C– 10.94

(WS + 2.5) × T_C– 10.94

—

• SRAM WS = 1

• SRAM WS = 2, 3

—

• SRAM WS ≥ 4

—

24

25

Duration for IRQA assertion to recover from Stop state

5.9

Delay from IRQA assertion to fetch of first instruction (when

exiting Stop)^{3, 8}

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is enabled (OMR Bit 6 = 0)

PLC × ET_C× PDF +

(128 K − PLC/2) × T_C

1.3

13.6

ms

ns

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is not enabled (OMR Bit 6 = 1)

PLC × ET_C× PDF +

(23.75 ± 0.5) × T_C

232.5

ns

12.3

ms

• PLL is active during Stop (PCTL Bit 17 = 1) (Implies No

Stop Delay)

(8.25 ± 0.5) × T_C

77.5

87.5

26

Duration of level sensitive IRQA assertion to ensure

interrupt service (when exiting Stop)^{3, 8}

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is enabled (OMR Bit 6 = 0)

PLC × ET_C× PDF +

(128 K − PLC/2) × T_C

13.6

12.3

55.0

—

ms

ns

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is not enabled (OMR Bit 6 = 1)

PLC × ET_C× PDF +

(20.5 ± 0.5) × T_C

• PLL is active during Stop (PCTL Bit 17 = 1) (implies no

Stop delay)

5.5 × T_C

27

Interrupt Requests Rate

• ESAI, SCI

12T_C

8T_C

—

120.0

80.0

ns

• DMA

• IRQ, NMI (edge trigger)

• IRQ, NMI (level trigger)

8T_C

80.0

12T_C

120.0

28

DMA Requests Rate

• Data read from ESAI, SCI

6T_C

7T_C

3T_C

—

60.0

70.0

30.0

ns

• Data write to ESAI, SCI

• IRQ, NMI (edge trigger)

DSP56364 Technical Data, Rev. 4.1

3-8

Freescale Semiconductor

Reset, Stop, Mode Select, and Interrupt Timing

1

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing (continued)

No.

Characteristics

Expression²

Min

Max

Unit

29

Delay from IRQA, IRQB, IRQD, NMI assertion to external

memory (DMA source) access address out valid

4.25 × T_C+ 2.0

44.0

—

ns

1

2

3

4

V_CC= 3.3 V 0.16 V; T_J= 0°C to + 105°C, C_L= 50 pF

Use expression to compute maximum value.

Periodically sampled and not 100% tested

For an external clock generator, RESET duration is measured during the time in which RESET is asserted, V_CCis valid, and

the EXTAL input is active and valid.

For internal oscillator, RESET duration is measured during the time in which RESET is asserted and V_CCis valid. The specified

timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the

crystal and other components connected to the oscillator and reflects worst case conditions.

When the V_CCis valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the

device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should

minimize this state to the shortest possible duration.

5

For an external clock generator, RESET duration is measured during the time in which RESET is asserted, V_CCis valid, and

the EXTAL input is active and valid.

For internal oscillator, RESET duration is measured during the time in which RESET is asserted and V_CCis valid. The specified

timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the

crystal and other components connected to the oscillator and reflects worst case conditions.

When the V_CCis valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the

device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should

minimize this state to the shortest possible duration.

6

When using fast interrupts and IRQA, IRQB, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent

multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using

fast interrupts. Long interrupts are recommended when using Level-sensitive mode.

7

8

WS = number of wait states (measured in clock cycles, number of T_C)

This timing depends on several settings:

For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL

Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before executing programs. In that case, resetting

the Stop delay (OMR Bit 6 = 0) will provide the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended

and these specifications do not guarantee timings for that case.

For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization

delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored).

For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by

the PCTL Bit 17 and OMR Bit 6 settings.

For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked.

The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in

parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs. The stop delay

counter completes count or PLL lock procedure completion.

PLC value for PLL disable is 0.

The maximum value for ET_Cis 4096 (maximum MF) divided by the desired internal frequency (i.e., for 100 MHz it is 4096/100

MHz = 40 μs). During the stabilization period, T_C, T_H,and T_Lwill not be constant, and their width may vary, so timing may vary

as well.

9. If PLL does not lose lock.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-9

Reset, Stop, Mode Select, and Interrupt Timing

V_IH

RESET

9

10

8

All Pins

Reset Value

A0–A17

First Fetch

AA0460

Figure 3-2 Reset Timing

First Interrupt Instruction

A0–A17

RD

Execution/Fetch

20

WR

21

19

17

IRQA, IRQB,

IRQD,

NMI

a) First Interrupt Instruction Execution

General

Purpose

I/O

18

IRQA, IRQB,

IRQD,

NMI

b) General Purpose I/O

AA0462

Figure 3-3 External Fast Interrupt Timing

DSP56364 Technical Data, Rev. 4.1

3-10

Freescale Semiconductor

Reset, Stop, Mode Select, and Interrupt Timing

IRQA, IRQB,

IRQD, NMI

15

16

IRQA, IRQB,

IRQD, NMI

AA0463

Figure 3-4 External Interrupt Timing (Negative Edge-Triggered)

V_IH

RESET

13

14

V_IH

V_IL

V_IH

V_IL

IRQA, IRQB,

IRQD, NMI

MODA,

MODB,MODD,

PINIT

AA0465

Figure 3-5 Operating Mode Select Timing

24

IRQA

25

A0–A17

First Instruction Fetch

AA0466

Figure 3-6 Recovery from Stop State Using IRQA

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-11

External Memory Expansion Port (Port A)

26

IRQA

25

A0–A17

First IRQA Interrupt Instruction Fetch

AA0467

Figure 3-7 Recovery from Stop State Using IRQA Interrupt Service

DMA Source Address

A0–A17

RD

WR

29

IRQA, IRQB,

IRQD,

First Interrupt Instruction Execution

NMI

AA1104

Figure 3-8 External Memory Access (DMA Source) Timing

3.10 External Memory Expansion Port (Port A)

3.10.1 SRAM Timing

1

Table 3-8 SRAM Read and Write Accesses

No.

Characteristics

Symbol

Expression²

Min

Max

Unit

100 Address valid and AA assertion pulse width

t_RC, t_WC

(WS + 1) × T_C− 4.0

[1 ≤ WS ≤ 3]

16.0

—

ns

(WS + 2) × T_C− 4.0

[4 ≤ WS ≤ 7]

56.0

—

ns

(WS + 3) × T_C− 4.0

[WS ≥ 8]

106.0

DSP56364 Technical Data, Rev. 4.1

3-12

Freescale Semiconductor

External Memory Expansion Port (Port A)

1

Table 3-8 SRAM Read and Write Accesses (continued)

No.

Characteristics

Symbol

Expression²

Min

Max

Unit

101 Address and AA valid to WR assertion

t_AS

0.25 × T_C− 2.0

0.5

—

ns

[WS = 1]

0.75 × T_C− 2.0

[2 ≤ WS ≤ 3]

5.5

—

ns

1.25 × T_C− 2.0

[WS ≥ 4]

10.5

11.0

16.0

102 WR assertion pulse width

t_WP

1.5 × T_C− 4.0

[WS = 1]

All frequencies:

WS × T_C− 4.0

[2 ≤ WS ≤ 3]

(WS − 0.5) × T_C− 4.0

[WS ≥ 4]

31.0

0.5

—

ns

103 WR deassertion to address not valid

t_WR

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

10.5

20.5

8.5

2.25 × T_C− 2.0

[WS ≥ 8]

All frequencies:

1.25 × T_C− 4.0

[4 ≤ WS ≤ 7]

2.25 × T_C− 4.0

[WS ≥ 8]

18.5

—

10.5

5.5

ns

104 Address and AA valid to input data valid

105 RD assertion to input data valid

t_AA, t_AC

(WS + 0.75) × T_C− 7.0

[WS ≥ 1]

t_OE

(WS + 0.25) × T_C− 7.0

[WS ≥ 1]

—

106 RD deassertion to data not valid (data hold time)

107 Address valid to WR deassertion³

t_OHZ

t_AW

0.0

—

ns

(WS + 0.75) × T_C− 4.0

[WS ≥ 1]

13.5

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-13

External Memory Expansion Port (Port A)

Table 3-8 SRAM Read and Write Accesses (continued)

1

No.

Characteristics

Symbol

t_DS(t_DW

Expression²

Min

Max

Unit

108 Data valid to WR deassertion (data setup time)

)

(WS − 0.25) × T_C− 3.0

[WS ≥ 1]

4.5

—

ns

109 Data hold time from WR deassertion

t_DH

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

0.5

10.5

20.5

3.5

—

ns

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

2.25 × T_C− 2.0

[WS ≥ 8]

113 RD deassertion time

0.75 × T_C− 4.0

[1 ≤ WS ≤ 3]

1.75 × T_C− 4.0

[4 ≤ WS ≤ 7]

13.5

23.5

1.0

2.75 × T_C− 4.0

[WS ≥ 8]

114 WR deassertion time

0.5 × T_C− 4.0

[WS = 1]

T_C− 2.0

6.0

[2 ≤ WS ≤ 3]

2.5 × T_C− 4.0

[4 ≤ WS ≤ 7]

21.0

31.0

3.5 × T_C− 4.0

[WS ≥ 8]

115 Address valid to RD assertion

116 RD assertion pulse width

0.5 × T_C− 4.0

1.0

8.5

0.5

—

ns

(WS + 0.25) × T_C−4.0

117 RD deassertion to address not valid

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

10.5

20.5

—

ns

2.25 × T_C− 2.0

[WS ≥ 8]

DSP56364 Technical Data, Rev. 4.1

3-14

Freescale Semiconductor

External Memory Expansion Port (Port A)

1

Table 3-8 SRAM Read and Write Accesses (continued)

No.

Characteristics

Symbol

Expression²

Min

4.5

0

Max

—

Unit

ns

118 TA setup before RD or WR deassertion⁴

119 TA hold after RD or WR deassertion

0.25 × T_C+ 2.0

—

ns

1

2

3

4

All timings for 100 MHz are measured from 0.5 · Vcc to .05 · Vcc

WS is the number of wait states specified in the BCR.

Timings 100, 107 are guaranteed by design, not tested.

In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active.

100

A0–A17

AA0–AA1

117

106

113

116

RD

115

105

WR

104

119

118

TA

Data

In

D0–D7

AA0468

Figure 3-9 SRAM Read Access

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-15

External Memory Expansion Port (Port A)

100

A0–A17

AA0–AA3

107

101

102

103

WR

114

RD

TA

118

119

108

111

110

109

112

Data

Out

D0–D23

AA0469

Figure 3-10 SRAM Write Access

3.10.2 DRAM Timing

The selection guides provided in Figure 3-11 and Figure 3-14 should be used for primary selection only.

Final selection should be based on the timing provided in the following tables. As an example, the selection

guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode DRAM.

However, by using the information in the appropriate table, a designer may choose to evaluate whether

fewer wait states might be used by determining which timing prevents operation at 100 MHz, running the

chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available), and control

factors such as capacitive and resistive load to improve overall system performance.

DSP56364 Technical Data, Rev. 4.1

3-16

Freescale Semiconductor

External Memory Expansion Port (Port A)

Note: This figure should be use for primary selection. For

exact and detailed timings see the following tables.

DRAM Type

(tRAC ns)

100

80

70

60

50

Chip Frequency

(MHz)

120

40

66

80

100

1 Wait States

2 Wait States

3 Wait States

4 Wait States

AA0472

Figure 3-11 DRAM Page Mode Wait States Selection Guide

1, 2, 3

Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)

20 MHz⁴

30 MHz⁴

No.

Characteristics

Symbol

Expression

Unit

Min

Max

Min

Max

131 Page mode cycle time for two

consecutive accesses of the same

direction

t_PC

2 × T_C

100.0

—

66.7

—

ns

Page mode cycle time for mixed (read

and write) accesses

1.25 × T_C

62.5

—

41.7

—

132 CAS assertion to data valid (read)

t_CAC

t_AA

T_C− 7.5

—

42.5

67.5

—

25.8

42.5

ns

133 Column address valid to data valid

(read)

1.5 × T_C− 7.5

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-17

External Memory Expansion Port (Port A)

1, 2, 3

Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)

(continued)

20 MHz⁴

30 MHz⁴

No.

Characteristics

Symbol

t_OFF

Expression

Unit

Min

Max

Min

Max

134 CAS deassertion to data not valid

(read hold time)

0.0

—

0.0

—

ns

135 Last CAS assertion to RAS

deassertion

t_RSH

0.75 × T_C− 4.0

2 × T_C− 4.0

33.5

96.0

—

21.0

62.7

—

136 Previous CAS deassertion to RAS

deassertion

t_RHCP

137 CAS assertion pulse width

t_CAS

t_CRP

0.75 × T_C− 4.0

1.75 × T_C− 6.0

33.5

81.5

—

21.0

52.3

—

ns

138 Last CAS deassertion to RAS

deassertion⁵

BRW[1:0] = 00

• BRW[1:0] = 01

3.25 × T_C− 6.0

4.25 × T_C− 6.0

6.25 × T_C– 6.0

0.5 × T_C− 4.0

156.5

206.5

306.5

21.0

102.2

135.5

202.1

12.7

—

ns

• BRW[1:0] = 10

• BRW[1:0] = 11

—

139 CAS deassertion pulse width

t_CP

140 Column address valid to CAS

assertion

t_ASC

21.0

12.7

141 CAS assertion to column address not

valid

t_CAH

0.75 × T_C− 4.0

2 × T_C− 4.0

33.5

96.0

—

21.0

62.7

—

ns

142 Last column address valid to RAS

deassertion

t_RAL

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

t_RCS

t_RCH

t_WCH

t_WP

0.75 × T_C− 3.8

0.25 × T_C− 3.7

0.5 × T_C− 4.2

1.5 × T_C− 4.5

1.75 × T_C− 4.3

0.25 × T_C− 4.0

0.75 × T_C− 4.0

T_C− 4.3

33.7

8.8

—

21.2

4.6

—

ns

20.8

70.5

83.2

8.5

12.5

45.5

54.0

4.3

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (Write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

t_DH

33.5

45.7

21.0

29.0

t_WCS

DSP56364 Technical Data, Rev. 4.1

3-18

Freescale Semiconductor

External Memory Expansion Port (Port A)

1, 2, 3

Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)

(continued)

20 MHz⁴

30 MHz⁴

No.

Characteristics

Symbol

Expression

Unit

Min

Max

—

Min

46.0

—

Max

—

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t_ROH

t_GA

1.5 × T_C− 4.0

T_C− 7.5

71.0

—

ns

42.5

—

25.8

—

154 RD deassertion to data not valid ⁶

155 WR assertion to data active

t_GZ

0.0

37.2

—

0.0

24.7

—

0.75 × T_C− 0.3

0.25 × T_C

—

156 WR deassertion to data high

impedance

12.5

8.3

1

2

3

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t_PCequals 2 × TC for

read-after-read or write-after-write sequences).

4

5

Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See Figure 3-14.).

BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page

access.

6

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-19

External Memory Expansion Port (Port A)

Table 3-10 DRAM Page Mode Timings, Two Wait States

1, 2, 3, 4

66 MHz

80 MHz

No.

Characteristics

Symbol

Expression⁵

2 × T_C

Unit

ns

Min

Max

Min

Max

131 Page mode cycle time for two consecutive

accesses of the same direction

t_PC

45.4

—

37.5

—

Page mode cycle time for mixed (read and

write) accesses

1.25 × T_C

41.1

—

34.4

—

ns

132 CAS assertion to data valid (read)

t_CAC

1.5 × T_C− 7.5

1.5 × T_C− 6.5

2.5 × T_C− 7.5

2.5 × T_C− 6.5

—

15.2

—

12.3

—

ns

133 Column address valid to data valid (read)

t_AA

—

30.4

—

24.8

—

134 CAS deassertion to data not valid (read hold

time)

t_OFF

0.0

—

0.0

135 Last CAS assertion to RAS deassertion

t_RSH

1.75 × T_C− 4.0

3.25 × T_C− 4.0

22.5

45.2

—

17.9

36.6

—

ns

136 Previous CAS deassertion to RAS

deassertion

t_RHCP

137 CAS assertion pulse width

t_CAS

1.5 × T_C− 4.0

18.7

—

14.8

—

ns

138 Last CAS deassertion to RAS deassertion⁶

• BRW[1:0] = 00

t_CRP

2.0 × T_C− 6.0

3.5 × T_C− 6.0

4.5 × T_C− 6.0

6.5 × T_C− 6.0

1.25 × T_C− 4.0

T_C− 4.0

24.4

47.2

62.4

92.8

14.9

11.2

22.5

41.5

—

19.0

37.8

50.3

75.3

11.6

8.5

—

ns

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

139 CAS deassertion pulse width

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

t_CP

t_ASC

t_CAH

t_RAL

1.75 × T_C− 4.0

3 × T_C− 4.0

17.9

33.5

142 Last column address valid to RAS

deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

t_RCS

t_RCH

t_WCH

t_WP

1.25 × T_C− 3.8

0.5 × T_C− 3.7

1.5 × T_C− 4.2

2.5 × T_C− 4.5

15.1

3.9

—

11.8

2.6

—

ns

18.5

33.5

14.6

26.8

DSP56364 Technical Data, Rev. 4.1

3-20

Freescale Semiconductor

External Memory Expansion Port (Port A)

1, 2, 3, 4

Table 3-10 DRAM Page Mode Timings, Two Wait States

(continued)

66 MHz

80 MHz

No.

Characteristics

Symbol

Expression⁵

Unit

Min

Max

—

Min

Max

—

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

t_RWL

t_CWL

t_DS

2.75 × T_C− 4.3

2.5 × T_C− 4.3

0.25 × T_C− 3.7

0.25 × T_C− 3.0

1.75 × T_C− 4.0

T_C− 4.3

33.4

33.6

0.1

26.8

27.0

—

ns

—

0.1

17.9

8.2

27.3

—

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t_DH

t_WCS

t_ROH

t_GA

22.5

10.9

33.9

—

2.5 × T_C− 4.0

1.75 × T_C− 7.5

1.75 × T_C− 6.5

—

19.0

—

15.4

—

154 RD deassertion to data not valid⁷

155 WR assertion to data active

t_GZ

0.0

—

0.0

9.1

—

0.75 × T_C− 0.3

0.25 × T_C

11.1

—

156 WR deassertion to data high impedance

3.8

3.1

1

2

3

4

5

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for DSP56364.

There are no DRAMs fast enough to fit to two wait states Page mode @ 100 MHz (See Figure 3-11).

All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t_PCequals 3 × T_Cfor

read-after-read or write-after-write sequences).

6

7

BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page

access.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-21

External Memory Expansion Port (Port A)

Table 3-11 DRAM Page Mode Timings, Three Wait States

1, 2, 3

No.

Characteristics

Symbol

Expression⁴

Min

Max

Unit

131 Page mode cycle time for two consecutive accesses of the

same direction

t_PC

2 × T_C

40.0

—

ns

Page mode cycle time for mixed (read and write) accesses

132 CAS assertion to data valid (read)

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

1.25 × T_C

2 × T_C− 7.0

3 × T_C− 7.0

35.0

—

13.0

23.0

—

t_CAC

t_AA

ns

—

t_OFF

t_RSH

t_RHCP

t_CAS

0.0

2.5 × T_C− 4.0

4.5 × T_C− 4.0

2 × T_C− 4.0

21.0

41.0

16.0

—

138 Last CAS deassertion to RAS assertion⁵

• BRW[1:0] = 00

t_CRP

2.25 × T_C− 6.0

3.75 × T_C− 6.0

4.75 × T_C− 6.0

6.75 × T_C− 6.0

1.5 × T_C− 4.0

T_C− 4.0

—

ns

• BRW[1:0] = 01

—

• BRW[1:0] = 10

41.5

61.5

11.0

6.0

• BRW[1:0] = 11

139 CAS deassertion pulse width

t_CP

t_ASC

t_CAH

t_RAL

t_RCS

t_RCH

t_WCH

t_WP

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

2.5 × T_C− 4.0

4 × T_C− 4.0

21.0

36.0

8.5

1.25 × T_C− 4.0

0.75 × T_C− 4.0

2.25 × T_C− 4.2

3.5 × T_C− 4.5

3.75 × T_C− 4.3

3.25 × T_C− 4.3

0.5 × T_C− 4.0

2.5 × T_C− 4.0

1.25 × T_C− 4.3

3.5

18.3

30.5

33.2

28.2

1.0

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

t_DH

21.0

8.2

t_WCS

DSP56364 Technical Data, Rev. 4.1

3-22

Freescale Semiconductor

External Memory Expansion Port (Port A)

1, 2, 3

Table 3-11 DRAM Page Mode Timings, Three Wait States

(continued)

No.

Characteristics

Symbol

t_ROH

t_GA

Expression⁴

Min

31.0

—

Max

—

Unit

ns

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

3.5 × T_C− 4.0

2.5 × T_C− 7.0

18.0

—

ns

154 RD deassertion to data not valid⁶

155 WR assertion to data active

t_GZ

0.0

7.2

—

ns

0.75 × T_C− 0.3

0.25 × T_C

—

ns

156 WR deassertion to data high impedance

2.5

ns

1

2

3

4

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for DSP56364.

All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 4 ¥ TC for

read-after-read or write-after-write sequences).

5

6

BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of

page-access.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

1, 2, 3

Table 3-12 DRAM Page Mode Timings, Four Wait States

No.

Characteristics

Symbol

Expression⁴

Min

Max

Unit

131 Page mode cycle time for two consecutive accesses of the

same direction.

t_PC

2 × T_C

50.0

—

ns

Page mode cycle time for mixed (read and write) accesses.

132 CAS assertion to data valid (read)

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

1.25 × T_C

45.0

—

20.5

30.5

—

ns

t_CAC

t_AA

2.75 × T_C− 7.0

3.75 × T_C− 7.0

—

t_OFF

t_RSH

t_RHCP

t_CAS

0.0

3.5 × T_C− 4.0

6 × T_C− 4.0

31.0

56.0

21.0

—

2.5 × T_C− 4.0

—

138 Last CAS deassertion to RAS assertion⁵

• BRW[1:0] = 00

t_CRP

2.75 × T_C− 6.0

4.25 × T_C− 6.0

5.25 × T_C− 6.0

7.25 × T_C− 6.0

—

ns

• BRW[1:0] = 01

46.5

66.5

• BRW[1:0] = 10

• BRW[1:0] = 11

139 CAS deassertion pulse width

t_CP

2 × T_C− 4.0

16.0

—

ns

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-23

External Memory Expansion Port (Port A)

Table 3-12 DRAM Page Mode Timings, Four Wait States

1, 2, 3

(continued)

No.

Characteristics

Symbol

t_ASC

t_CAH

t_RAL

t_RCS

t_RCH

t_WCH

t_WP

Expression⁴

T_C− 4.0

Min

6.0

Max

—

Unit

ns

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

3.5 × T_C− 4.0

5 × T_C− 4.0

31.0

46.0

8.5

—

1.25 × T_C− 4.0

3.25 × T_C− 4.2

4.5 × T_C− 4.5

4.75 × T_C− 4.3

3.75 × T_C− 4.3

0.5 × T_C− 4.0

3.5 × T_C− 4.0

1.25 × T_C− 4.3

4.5 × T_C− 4.0

3.25 × T_C− 7.0

—

8.5

—

28.3

40.5

43.2

33.2

1.0

—

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

—

t_DH

31.0

8.2

—

t_WCS

t_ROH

t_GA

—

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

41.0

—

25.5

—

154 RD deassertion to data not valid⁶

155 WR assertion to data active

t_GZ

0.0

0.75 × T_C− 0.3

0.25 × T_C

7.2

—

156 WR deassertion to data high impedance

—

2.5

1

2

3

4

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for DSP56364.

All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t_PCequals 3 × T_Cfor

read-after-read or write-after-write sequences).

5

6

BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page

access.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

DSP56364 Technical Data, Rev. 4.1

3-24

Freescale Semiconductor

External Memory Expansion Port (Port A)

RAS

CAS

136

135

131

137

139

141

138

142

140

151

Column

Address

Last Column

Address

Column

Address

Row

Add

A0–A17

144

143

147

145

WR

RD

146

148

155

149

156

150

D0–D7

Data Out

AA0473

Figure 3-12 DRAM Page Mode Write Accesses

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-25

External Memory Expansion Port (Port A)

RAS

136

135

131

CAS

137

140

139

141

138

142

Last Column

Address

Row

Add

Column

Address

Column

Address

A0–A17

WR

143

132

133

153

152

RD

134

154

D0–D7

Data In

AA0474

Figure 3-13 DRAM Page Mode Read Accesses

DSP56364 Technical Data, Rev. 4.1

3-26

Freescale Semiconductor

External Memory Expansion Port (Port A)

DRAM Type

(tRAC ns)

Note: This figure should be use for primary selection. For exact and

detailed timings see the following tables.

100

80

70

60

50

Chip Frequency

(MHz)

120

40

66

80

100

4 Wait States

8 Wait States

11 Wait States

15 Wait States

AA0475

Figure 3-14 DRAM Out-of-Page Wait States Selection Guide

1, 2

Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

20 MHz⁴

30 MHz⁴

No.

Characteristics³

Symbol

Expression

Unit

Min

250.0

—

Max

—

Min

Max

—

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

t_RC

t_RAC

t_CAC

t_AA

5 × T_C

166.7

—

ns

2.75 × T_C− 7.5

1.25 × T_C− 7.5

1.5 × T_C− 7.5

130.0

55.0

67.5

84.2

34.2

42.5

—

160 Column address valid to data valid

(read)

—

161 CAS deassertion to data not valid

(read hold time)

t_OFF

0.0

—

0.0

—

ns

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t_RP

1.75 × T_C− 4.0

3.25 × T_C− 4.0

1.75 × T_C− 4.0

83.5

158.5

83.5

—

54.3

104.3

54.3

—

ns

t_RAS

t_RSH

164 CAS assertion to RAS deassertion

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-27

External Memory Expansion Port (Port A)

1, 2

Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

20 MHz⁴

(continued)

30 MHz⁴

No.

Characteristics³

Symbol

Expression

Unit

Min

Max

Min

87.7

37.7

48.0

39.7

71.0

54.3

37.7

4.3

Max

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

2.75 × T_C− 4.0

1.25 × T_C− 4.0

1.5 × T_C± 2

133.5

58.5

73.0

60.5

108.5

83.5

58.5

8.5

—

ns

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

77.0

64.5

—

52.0

43.7

—

1.25 × T_C± 2

2.25 × T_C− 4.0

1.75 × T_C− 4.0

1.25 × T_C− 4.0

0.25 × T_C− 4.0

—

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

t_ASR

t_RAH

t_ASC

—

173 Column address valid to CAS

assertion

—

174 CAS assertion to column address not

valid

t_CAH

1.75 × T_C− 4.0

3.25 × T_C− 4.0

2 × T_C− 4.0

83.5

158.5

96.0

—

54.3

104.3

62.7

—

ns

175 RAS assertion to column address not

valid

t_AR

176 Column address valid to RAS

deassertion

t_RAL

177 WR deassertion to CAS assertion

178 CAS deassertion to WR assertion

179 RAS deassertion to WR assertion

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

1.5 × T_C− 3.8

0.75 × T_C− 3.7

0.25 × T_C− 3.7

1.5 × T_C− 4.2

3 × T_C− 4.2

71.2

33.8

—

46.2

21.3

4.6

—

ns

8.8

70.8

45.8

95.8

145.5

154.0

137.4

71.0

54.3

104.3

145.8

220.5

233.2

208.2

108.5

83.5

4.5 × T_C− 4.5

4.75 × T_C− 4.3

4.25 × T_C− 4.3

2.25 × T_C− 4.0

1.75 × T_C− 4.0

3.25 × T_C− 4.0

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

t_RWL

t_CWL

t_DS

t_DH

t_DHR

158.5

DSP56364 Technical Data, Rev. 4.1

3-28

Freescale Semiconductor

External Memory Expansion Port (Port A)

1, 2

Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

(continued)

30 MHz⁴

20 MHz⁴

No.

Characteristics³

Symbol

Expression

Unit

Min

Max

—

Min

95.7

12.7

Max

188 WR assertion to CAS assertion

t_WCS

t_CSR

3 × T_C− 4.3

145.7

21.0

—

ns

189 CAS assertion to RAS assertion

(refresh)

0.5 × T_C− 4.0

—

190 RAS deassertion to CAS assertion

(refresh)

t_RPC

1.25 × T_C− 4.0

58.5

—

37.7

—

ns

191 RD assertion to RAS deassertion

192 RD assertion to data valid

t_ROH

t_GA

4.5 × T_C− 4.0

4 × T_C− 7.5

221.0

—

192.5

—

146.0

—

125.8

—

ns

193 RD deassertion to data not valid³

194 WR assertion to data active

t_GZ

0.0

0.75 × T_C− 0.3

0.25 × T_C

37.2

—

24.7

—

195 WR deassertion to data high

impedance

12.5

8.3

1

2

3

4

The number of wait states for out of page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (See Figure 3-17).

1, 2

Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States

66 MHz

80 MHz

No.

Characteristics³

Symbol

Expression⁴

Unit

Min

Max

—

Min

Max

—

157 Random read or write cycle time

158 RAS assertion to data valid (read)

t_RC

9 × T_C

136.4

—

112.5

—

ns

t_RAC

4.75 × T_C− 7.5

4.75 × T_C− 6.5

2.25 × T_C− 7.5

2.25 × T_C− 6.5

3 × T_C− 7.5

64.5

—

52.9

—

159 CAS assertion to data valid (read)

t_CAC

—

26.6

—

21.6

—

160 Column address valid to data valid

(read)

t_AA

—

40.0

—

3 × T_C− 6.5

—

31.0

—

161 CAS deassertion to data not valid

(read hold time)

t_OFF

0.0

—

0.0

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t_RP

3.25 × T_C− 4.0

5.75 × T_C− 4.0

45.2

83.1

—

36.6

67.9

—

ns

t_RAS

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-29

External Memory Expansion Port (Port A)

Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States

1, 2

(continued)

80 MHz

66 MHz

No.

Characteristics³

Symbol

Expression⁴

Unit

Min

Max

—

Min

36.6

55.5

24.1

29.3

19.9

49.1

30.4

36.6

17.9

5.4

Max

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

3.25 × T_C− 4.0

4.75 × T_C− 4.0

2.25 × T_C− 4.0

2.5 × T_C± 2

45.2

68.0

30.1

35.9

24.5

59.8

37.7

45.2

22.5

7.4

—

ns

—

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

39.9

28.5

—

33.3

23.9

—

1.75 × T_C± 2

4.25 × T_C− 4.0

2.75 × T_C− 4.0

3.25 × T_C− 4.0

1.75 × T_C− 4.0

0.75 × T_C− 4.0

—

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

t_ASR

t_RAH

t_ASC

—

173 Column address valid to CAS

assertion

—

174 CAS assertion to column address not

valid

t_CAH

3.25 × T_C− 4.0

5.75 × T_C− 4.0

4 × T_C− 4.0

45.2

83.1

56.6

—

36.6

67.9

46.0

—

ns

175 RAS assertion to column address not

valid

t_AR

176 Column address valid to RAS

deassertion

t_RAL

177 WR deassertion to CAS assertion

178 CAS deassertion to WR⁵assertion

179 RAS deassertion to WR⁵assertion

t_RCS

t_RCH

t_RRH

2 × T_C− 3.8

1.25 × T_C− 3.7

0.25 × T_C− 3.7

0.25 × T_C− 3.0

3 × T_C− 4.2

26.5

15.2

0.1

—

21.2

11.9

—

ns

—

0.1

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t_WCH

t_WCR

t_WP

41.3

79.1

124.3

128.3

113.1

68.0

33.3

64.6

101.8

105.1

92.6

55.4

5.5 × T_C− 4.2

8.5 × T_C− 4.5

8.75 × T_C− 4.3

7.75 × T_C− 4.3

4.75 × T_C− 4.0

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

t_RWL

t_CWL

t_DS

DSP56364 Technical Data, Rev. 4.1

3-30

Freescale Semiconductor

External Memory Expansion Port (Port A)

1, 2

Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States

(continued)

80 MHz

66 MHz

No.

Characteristics³

Symbol

Expression⁴

Unit

Min

Max

—

Min

36.6

67.9

64.5

14.8

Max

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

t_DH

3.25 × T_C− 4.0

5.75 × T_C− 4.0

5.5 × T_C− 4.3

1.5 × T_C− 4.0

45.2

83.1

79.0

18.7

—

ns

t_DHR

t_WCS

t_CSR

—

189 CAS assertion to RAS assertion

(refresh)

—

190 RAS deassertion to CAS assertion

(refresh)

t_RPC

1.75 × T_C− 4.0

22.5

—

17.9

—

ns

191 RD assertion to RAS deassertion

192 RD assertion to data valid

t_ROH

t_GA

8.5 × T_C− 4.0

7.5 × T_C− 7.5

7.5 × T_C− 6.5

0.0

124.8

—

106.1

—

102.3

—

ns

—

87.3

—

193 RD deassertion to data not valid³

194 WR assertion to data active

t_GZ

0.0

11.1

—

0.0

9.1

—

0.75 × T_C− 0.3

0.25 × T_C

—

195 WR deassertion to data high

impedance

3.8

3.1

1

2

3

4

5

The number of wait states for out-of-page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

The asynchronous delays specified in the expressions are valid for DSP56364.

Either t_RCHor t_RRHmust be satisfied for read cycles.

.

1, 2

Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States

No.

Characteristics³

Symbol

t_RC

Expression⁴

12 × T_C

Min

120.0

—

Max

—

Unit

ns

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

161 CAS deassertion to data not valid (read hold time)

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t_RAC

t_CAC

t_AA

6.25 × T_C− 7.0

3.75 × T_C− 7.0

4.5 × T_C− 7.0

55.5

30.5

38.0

—

ns

—

ns

—

ns

t_OFF

t_RP

0.0

ns

4.25 × T_C− 4.0

7.75 × T_C− 4.0

38.5

73.5

—

ns

t_RAS

—

ns

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-31

External Memory Expansion Port (Port A)

Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States

1, 2

(continued)

No.

Characteristics³

Symbol

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

Expression⁴

5.25 × T_C− 4.0

6.25 × T_C− 4.0

3.75 × T_C− 4.0

2.5 × T_C± 4.0

1.75 × T_C± 4.0

5.75 × T_C− 4.0

4.25 × T_C− 4.0

1.75 × T_C− 4.0

0.75 × T_C− 4.0

5.25 × T_C− 4.0

7.75 × T_C− 4.0

6 × T_C− 4.0

Min

48.5

58.5

33.5

21.0

13.5

53.5

38.5

13.5

3.5

Max

—

Unit

ns

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

—

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

29.0

21.5

—

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

178 CAS deassertion to WR⁵assertion

179 RAS deassertion to WR⁵assertion

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t_ASR

t_RAH

t_ASC

t_CAH

t_AR

—

48.5

73.5

56.0

26.0

13.5

0.5

—

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

—

3.0 × T_C− 4.0

1.75 × T_C− 4.0

0.25 × T_C− 2.0

5 × T_C− 4.2

—

45.8

70.8

110.5

113.2

103.2

53.5

48.5

73.5

60.7

11.0

23.5

—

7.5 × T_C− 4.2

11.5 × T_C− 4.5

11.75 × T_C− 4.3

10.25 × T_C− 4.3

5.75 × T_C− 4.0

5.25 × T_C− 4.0

7.75 × T_C− 4.0

6.5 × T_C− 4.3

1.5 × T_C− 4.0

2.75 × T_C− 4.0

—

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

—

t_DH

—

t_DHR

t_WCS

t_CSR

t_RPC

—

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

—

DSP56364 Technical Data, Rev. 4.1

3-32

Freescale Semiconductor

External Memory Expansion Port (Port A)

1, 2

Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States

(continued)

No.

Characteristics³

Symbol

t_ROH

t_GA

Expression⁴

11.5 × T_C− 4.0

10 × T_C− 7.0

Min

111.0

—

Max

—

Unit

ns

191 RD assertion to RAS deassertion

192 RD assertion to data valid

93.0

—

ns

193 RD deassertion to data not valid³

194 WR assertion to data active

t_GZ

0.0

ns

0.75 × T_C− 0.3

0.25 × T_C

7.2

—

ns

195 WR deassertion to data high impedance

—

2.5

ns

1

2

3

4

5

The number of wait states for out-of-page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

The asynchronous delays specified in the expressions are valid for DSP56364.

Either t_RCHor t_RRHmust be satisfied for read cycles.

.

1, 2

Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States

No.

Characteristics³

Symbol

t_RC

Expression

16 × T_C

Min

160.0

—

Max

Unit

ns

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

161 CAS deassertion to data not valid (read hold time)

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

—

76.8

41.8

49.3

—

t_RAC

t_CAC

t_AA

8.25 × T_C− 5.7

4.75 × T_C− 5.7

5.5 × T_C− 5.7

0.0

—

t_OFF

t_RP

0.0

6.25 × T_C− 4.0

9.75 × T_C− 4.0

6.25 × T_C− 4.0

8.25 × T_C− 4.0

4.75 × T_C− 4.0

3.5 × T_C± 2

58.5

93.5

58.5

78.5

43.5

33.0

25.5

73.5

58.5

23.5

—

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

—

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

—

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

37.0

29.5

—

2.75 × T_C± 2

7.75 × T_C− 4.0

6.25 × T_C− 4.0

2.75 × T_C− 4.0

—

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

t_ASR

t_RAH

—

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-33

External Memory Expansion Port (Port A)

Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States

1, 2

(continued)

No.

Characteristics³

Symbol

t_ASC

t_CAH

t_AR

Expression

0.75 × T_C− 4.0

6.25 × T_C− 4.0

9.75 × T_C− 4.0

7 × T_C− 4.0

Min

3.5

Max

Unit

ns

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

178 CAS deassertion to WR⁴assertion

179 RAS deassertion to WR⁴assertion

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

—

58.5

93.5

66.0

46.2

13.8

0.5

—

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

—

5 × T_C− 3.8

—

1.75 × T_C− 3.7

0.25 × T_C− 2.0

6 × T_C− 4.2

—

55.8

90.8

150.5

153.2

138.2

83.5

58.5

93.5

90.7

11.0

43.5

151.0

—

9.5 × T_C− 4.2

15.5 × T_C− 4.5

—

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

15.75 × T_C− 4.3

14.25 × T_C− 4.3

8.75 × T_C− 4.0

6.25 × T_C− 4.0

9.75 × T_C− 4.0

9.5 × T_C− 4.3

1.5 × T_C− 4.0

4.75 × T_C− 4.0

15.5 × T_C− 4.0

14 × T_C− 5.7

—

t_DH

—

t_DHR

t_WCS

t_CSR

t_RPC

t_ROH

t_GA

—

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

192 RD assertion to data valid

—

134.3

—

193 RD deassertion to data not valid³

194 WR assertion to data active

t_GZ

0.0

0.75 × T_C− 0.3

0.25 × T_C

7.2

—

195 WR deassertion to data high impedance

—

2.5

1

2

3

4

The number of wait states for out-of-page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

Either t_RCHor t_RRHmust be satisfied for read cycles.

DSP56364 Technical Data, Rev. 4.1

3-34

Freescale Semiconductor

External Memory Expansion Port (Port A)

157

163

165

162

169

RAS

167

168

164

170

166

CAS

171

173

174

175

Row Address

172

Column Address

176

A0–A17

177

179

191

WR

RD

168

160

159

193

158

192

161

Data

In

D0–D7

AA0476

Figure 3-15 DRAM Out-of-Page Read Access

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-35

External Memory Expansion Port (Port A)

157

162

163

165

162

RAS

167

168

164

169

166

170

CAS

171

173

172

174

176

Row Address

Column Address

A0–A17

181

175

188

180

182

WR

RD

184

183

187

186

185

195

194

Data Out

D0–D7

AA0477

Figure 3-16 DRAM Out-of-Page Write Access

DSP56364 Technical Data, Rev. 4.1

3-36

Freescale Semiconductor

Serial Host Interface SPI Protocol Timing

157

162

163

165

162

RAS

CAS

190

170

189

177

WR

AA0478

Figure 3-17 DRAM Refresh Access

3.11 Serial Host Interface SPI Protocol Timing

Table 3-17 Serial Host Interface SPI Protocol Timing

Filter

No.

Characteristics

Mode

Expression

Min

Max

Unit

Mode

Bypassed

Narrow

Wide

140 Tolerable spike width on clock or data in

141 Minimum serial clock cycle = t_SPICC(min)

142 Serial clock high period

—

0

50

100

—

ns

—

Master Bypassed

Narrow

6×T_C+46

106

212

283

43

6×T_C+152

6×T_C+223

0.5×t_SPICC–10

2.5×T_C+12

2.5×T_C+102

2.5×T_C+189

Wide

Master Bypassed

Narrow

96

Wide

131

37

Slave

Bypassed

Narrow

Wide

127

214

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-37

Serial Host Interface SPI Protocol Timing

Table 3-17 Serial Host Interface SPI Protocol Timing (continued)

Filter

Mode

No.

Characteristics

Mode

Expression

Min

Max

Unit

143 Serial clock low period

Master Bypassed

Narrow

0.5×t_SPICC–10

43

96

131

37

127

214

—

50

0

—

10

2000

—

9

ns

0.5×t_SPICC–10

Wide

0.5×t_SPICC–10

Slave

Bypassed

Narrow

Wide

2.5×T_C+12

2.5×T_C+102

2.5×T_C+189

144 Serial clock rise/fall time

Master

Slave

—

146 SS assertion to first SCK edge

CPHA = 0

Bypassed

Narrow

Wide

3.5×T_C+15

0

CPHA = 1

Slave

Bypassed

Narrow

Wide

10

0

147 Last SCK edge to SS not asserted

Bypassed

Narrow

Wide

12

102

189

0

102

189

148 Data input valid to SCK edge (data input set-up Master/ Bypassed

time) Slave

0

MAX{(20-T_C), 0}

MAX{(40-T_C), 0}

2.5×T_C+10

2.5×T_C+30

2.5×T_C+50

2

Narrow

10

30

35

55

75

2

Wide

149 SCK last sampling edge to data input not valid Master/ Bypassed

Slave

Narrow

Wide

150 SS assertion to data out active

Slave

—

151 SS deassertion to data high impedance

9

—

DSP56364 Technical Data, Rev. 4.1

3-38

Freescale Semiconductor

Serial Host Interface SPI Protocol Timing

Table 3-17 Serial Host Interface SPI Protocol Timing (continued)

Filter

Mode

No.

Characteristics

Mode

Expression

Min

Max

Unit

152 SCK edge to data out valid

(data out delay time)

Master/ Bypassed

2×T_C+33

2×T_C+123

2×T_C+210

T_C+5

—

53

143

230

—

ns

Slave

Narrow

Wide

—

153 SCK edge to data out not valid

(data out hold time)

Master/ Bypassed

15

65

116

—

Slave

Narrow

T_C+55

—

Wide

T_C+106

T_C+33

—

154 SS assertion to data out valid

(CPHA = 0)

Slave

—

43

157 First SCK sampling edge to HREQ output

deassertion

Bypassed

Narrow

Wide

2.5×T_C+30

2.5×T_C+120

2.5×T_C+217

2.5×T_C+30

2.5×T_C+80

2.5×T_C+136

2.5×T_C+30

—

55

145

242

—

ns

—

158 Last SCK sampling edge to HREQ output not

deasserted (CPHA = 1)

Slave

Bypassed

Narrow

Wide

55

105

161

55

—

159 SS deassertion to HREQ output not deasserted

(CPHA = 0)

Slave

—

160 SS deassertion pulse width (CPHA = 0)

161 HREQ in assertion to first SCK edge

—

T_C+6

16

—

ns

Master Bypassed

0.5 × t_SPICC

2.5×T_C+43

+

121

Narrow

0.5 ×t_SPICC

2.5×T_C+43

+

174

209

0

—

ns

Wide

0.5 ×t_SPICC

2.5×T_C+43

+

162 HREQ in deassertion to last SCK sampling

edge (HREQ in set-up time) (CPHA = 1)

Master

—

0

163 First SCK edge to HREQ in not asserted

(HREQ in hold time)

0

Note: Periodically sampled, not 100% tested

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-39

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

141

142

144

SCK (CPOL = 0)

(Output)

142

143

SCK (CPOL = 1)

(Output)

148

149

148

149

MISO

(Input)

MSB

Valid

LSB

Valid

153

152

MSB

MOSI

(Output)

LSB

161

163

HREQ

(Input)

AA0271

Figure 3-18 SPI Master Timing (CPHA = 0)

DSP56364 Technical Data, Rev. 4.1

3-40

Freescale Semiconductor

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

142

141

144

142

143

144

SCK (CPOL = 0)

(Output)

141

144

SCK (CPOL = 1)

(Output)

148

149

MISO

(Input)

MSB

Valid

LSB

Valid

152

153

MOSI

(Output)

MSB

LSB

161

162

163

HREQ

(Input)

AA0272

Figure 3-19 SPI Master Timing (CPHA = 1)

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-41

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

141

147

142

144

160

SCK (CPOL = 0)

(Input)

146

142

144

143

SCK (CPOL = 1)

(Input)

154

152

153

151

LSB

150

MISO

(Output)

MSB

148

149

MSB

Valid

MOSI

(Input)

LSB

Valid

157

159

HREQ

(Output)

AA0273

Figure 3-20 SPI Slave Timing (CPHA = 0)

DSP56364 Technical Data, Rev. 4.1

3-42

Freescale Semiconductor

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

141

147

142

144

SCK (CPOL = 0)

(Input)

146

142

144

143

SCK (CPOL = 1)

(Input)

152

153

151

150

MISO

(Output)

MSB

LSB

148

149

MSB

Valid

LSB

Valid

MOSI

(Input)

157

158

HREQ

(Output)

AA0274

Figure 3-21 SPI Slave Timing (CPHA = 1)

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-43

Serial Host Interface (SHI) I²C Protocol Timing

2

3.12 Serial Host Interface (SHI) I C Protocol Timing

2

Table 3-18 SHI I C Protocol Timing

Standard I²C¹

Standard-Mode

Symbol/

Fast-Mode

Min

Unit

No.

Characteristics

Expression

Min

Max

Tolerable spike width on SCL or SDA

• Filters bypassed

—

0

50

—

0

ns

kHz

μs

ns

μs

pF

• Narrow filters enabled

• Wide filters enabled

50

—

100

—

100

400

—

171 SCL clock frequency

172 Bus free time

F_SCL

T_BUF

—

4.7

4.0

4.7

4.0

—

1.3

0.6

1.3

173 Start condition set-up time

174 Start condition hold time

175 SCL low period

T_SU;STA

T_HD;STA

T_LOW

—

176 SCL high period

T_HIGH

—

177 SCL and SDA rise time

178 SCL and SDA fall time

179 Data set-up time

T

1000

300

—

20 + 0.1 × C_b

300

—

R

T

—

20 + 0.1 × C_b

F

T_SU;DAT

T_HD;DAT

T_SU;STO

C_b

250

0.0

4.0

—

100

0.0

0.6

—

180 Data hold time

—

0.9

—

181 Stop condition set-up time

182 Capacitive load for each line

183 DSP clock frequency

• Filters bypassed

—

400

F_DSP

10.6

11.8

13.1

0.0

—

28.5

39.7

61.0

0.0

—

MHz

ns

• Narrow filters enabled

• Wide filters enabled

184 HREQ in deassertion to last SCL edge

(HREQ in set-up time)

t_SU;RQI

DSP56364 Technical Data, Rev. 4.1

3-44

Freescale Semiconductor

Serial Host Interface (SHI) I²C Protocol Timing

2

Table 3-18 SHI I C Protocol Timing (continued)

Standard I²C¹

Standard-Mode

Symbol/

Fast-Mode

Min

Unit

No.

Characteristics

Expression

Min

Max

186 First SCL sampling edge to HREQ output

deassertion

T_NG;RQO

ns

• Filters bypassed

2 × T_C+ 30

2 × T_C+ 120

2 × T_C+ 208

T_AS;RQO

—

50

—

50

ns

• Narrow filters enabled

• Wide filters enabled

140

228

140

228

ns

187 Last SCL edge to HREQ output not

deasserted

• Filters bypassed

2 × T_C+ 30

2 × T_C+ 80

2 × T_C+ 135

T_AS;RQI

50

—

50

—

ns

• Narrow filters enabled

100

155

100

155

• Wide filters enabled

ns

188 HREQ in assertion to first SCL edge

0.5 × T_I2_CCP

-

0.5 × T_C- 21

• Filters bypassed

4327

4282

4238

—

927

882

838

—

ns

• Narrow filters enabled

• Wide filters enabled

R_P(min) = 1.5 k¾

1

3.12.1 Programming the Serial Clock

2

The programmed serial clock cycle, T

HCKR (SHI clock control register).

, is specified by the value of the HDM[5:0] and HRS bits of the

I CCP

2

The expression for T

is

I CCP

T

= [T × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]

C

I²CCP

where

HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is

operational. When HRS is set, the prescaler is bypassed.

HDM[7:0] are the divider modulus select bits.

A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-45

Serial Host Interface (SHI) I²C Protocol Timing

2

In I C mode, the user may select a value for the programmed serial clock cycle from

6 × T (if HDMS[5:0] = $02 and HRS = 1)

C

to

4096 × T (if HDMS[7:0] =

$FF and HRS = 0)

C

2

The programmed serial clock cycle (T

), SCL rise time (T ), and the filters selected should be chosen

R

I CCP

in order to achieve the desired SCL frequency, as shown in Table 3-19.

Table 3-19 SCL Serial Clock Cycle Generated as Master

2

Filters bypassed

T_{I CCP}+ 2.5 × T_C+ 45ns + T_R

2

Narrow filters enabled

Wide filters enabled

T_{I CCP}+ 2.5 × T_C+ 135ns + T_R

2

T_{I CCP}+ 2.5 × T_C+ 223ns + T_R

EXAMPLE:

2

For DSP clock frequency of 100 MHz (i.e. T = 10ns), operating in a standard-mode I C environment

C

(F

= 100 KHz (i.e. T

= 10μs), T = 1000ns), with filters bypassed

SCL

SCL R

T

= 10μs – 2.5 × 10ns – 45ns – 1000ns = 893ns

I²CCP

Choosing HRS = 0 gives

HDM[7:0] = (8930ns) ⁄ (2 × 10ns × 8) – 1 = 55.8

Thus the HDM[7:0] value should be programmed to $38 (=56).

171

173

176

175

SCL

SDA

177

180

178

172

179

MSB

LSB

ACK

Stop

Start

174

188

186

182

183

187

189

184

HREQ

AA0275

2

Figure 3-22 I C Timing

DSP56364 Technical Data, Rev. 4.1

3-46

Freescale Semiconductor

Enhanced Serial Audio Interface Timing

3.13 Enhanced Serial Audio Interface Timing

Table 3-20 Enhanced Serial Audio Interface Timing

No.

Characteristics^{1, 2, 3}

Symbol

Expression

Min

40.0

30.0

40.0

Max Condition⁴Unit

430 Clock cycle⁵

t_SSICC

4 × T

—

i ck

x ck

ns

C

3 × T

C

TXC:max[3*tc; t454]

431 Clock high period

• For internal clock

ns

—

2 × T − 10.0

10.0

15.0

—

C

• For external clock

1.5 × T

C

432 Clock low period

• For internal clock

2 × T − 10.0

10.0

15.0

—

C

• For external clock

1.5 × T

C

433 RXC rising edge to FSR out (bl) high

—

37.0

22.0

x ck

ns

i ck a

434 RXC rising edge to FSR out (bl) low

435 RXC rising edge to FSR out (wr) high⁶

436 RXC rising edge to FSR out (wr) low⁶

437 RXC rising edge to FSR out (wl) high

438 RXC rising edge to FSR out (wl) low

—

37.0

22.0

x ck

i ck a

—

39.0

24.0

x ck

i ck a

—

39.0

24.0

x ck

i ck a

—

36.0

21.0

x ck

i ck a

—

37.0

22.0

x ck

i ck a

439 Data in setup time before RXC (SCK in

synchronous mode) falling edge

0.0

—

x ck

i ck

19.0

440 Data in hold time after RXC falling edge

5.0

3.0

—

x ck

i ck

441 FSR input (bl, wr) high before RXC falling

edge⁶

23.0

1.0

—

x ck

i ck a

442 FSR input (wl) high before RXC falling edge

1.0

—

x ck

23.0

i ck a

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-47

Enhanced Serial Audio Interface Timing

Table 3-20 Enhanced Serial Audio Interface Timing (continued)

No.

Characteristics^{1, 2, 3}

Symbol

Expression

Min

Max Condition⁴Unit

443 FSR input hold time after RXC falling edge

444 Flags input setup before RXC falling edge

445 Flags input hold time after RXC falling edge

446 TXC rising edge to FST out (bl) high

447 TXC rising edge to FST out (bl) low

448 TXC rising edge to FST out (wr) high⁶

449 TXC rising edge to FST out (wr) low⁶

450 TXC rising edge to FST out (wl) high

451 TXC rising edge to FST out (wl) low

—

3.0

0.0

—

x ck

ns

i ck a

—

0.0

—

x ck

19.0

i ck s

—

6.0

0.0

—

x ck

i ck s

—

29.0

15.0

x ck

i ck

—

31.0

17.0

x ck

i ck

—

31.0

17.0

x ck

i ck

—

33.0

19.0

x ck

i ck

—

30.0

16.0

x ck

i ck

—

31.0

17.0

x ck

i ck

452 TXC rising edge to data out enable from high

impedance

—

31.0

17.0

x ck

i ck

453 TXC rising edge to transmitter #0 drive enable

assertion

—

34.0

20.0

x ck

i ck

454 TXC rising edge to data out valid

23 + 0.5 × T

—

28.0

21.0

x ck

i ck

C

21.0

455 TXC rising edge to data out high impedance⁷

—

31.0

16.0

x ck

i ck

456 TXC rising edge to transmitter #0 drive enable

deassertion⁷

—

34.0

20.0

x ck

i ck

457 FST input (bl, wr) setup time before TXC

falling edge⁶

2.0

—

x ck

i ck

21.0

458 FST input (wl) to data out enable from high

impedance

—

27.0

—

DSP56364 Technical Data, Rev. 4.1

3-48

Freescale Semiconductor

Enhanced Serial Audio Interface Timing

Table 3-20 Enhanced Serial Audio Interface Timing (continued)

No.

Characteristics^{1, 2, 3}

Symbol

Expression

Min

Max Condition⁴Unit

459 FST input (wl) to transmitter #0 drive enable

assertion

—

31.0

—

ns

460 FST input (wl) setup time before TXC falling

edge

—

2.0

—

x ck

i ck

ns

21.0

461 FST input hold time after TXC falling edge

462 Flag output valid after TXC rising edge

4.0

0.0

—

x ck

i ck

ns

—

32.0

18.0

x ck

i ck

463 HCKR/HCKT clock cycle

—

40.0

—

ns

464 HCKT input rising edge to TXC output

465 HCKR input rising edge to RXC output

27.5

—

1

2

V_CC= 3.16 V 0.16 V; T_J= 0°C to +105°C, C_L= 50 pF.

i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode (asynchronous implies that TXC and RXC are two different clocks)

i ck s = internal clock, synchronous mode (synchronous implies that TXC and RXC are the same clock)

3

4

bl = bit length

wl = word length

wr = word length relative

TXC (SCKT pin) = transmit clock

RXC (SCKR pin) = receive clock

FST (FST pin) = transmit frame sync

FSR (FSR pin) = receive frame sync

HCKT (HCKT pin) = transmit high speed clock

HCKR (HCKR pin) = receive high speed clock

5

6

For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync

signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one

before last bit clock of the first word in frame.

7

Periodically sampled and not 100% tested

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-49

Enhanced Serial Audio Interface Timing

430

431

432

TXC

(Input/Output)

446

447

FST (Bit)

Out

450

451

FST (Word)

Out

454

452

454

455

Data Out

First Bit

Last Bit

459

Transmitter

#0 Drive

Enable

457

453

456

FST (Bit) In

461

460

458

461

FST (Word) In

Flags Out

462

See Note

Note: In network mode, output flag transitions can occur at the start of each time slot within the

frame. In normal mode, the output flag state is asserted for the entire frame period.

AA0490

Figure 3-23 ESAI Transmitter Timing

DSP56364 Technical Data, Rev. 4.1

3-50

Freescale Semiconductor

Enhanced Serial Audio Interface Timing

430

431

432

RXC

(Input/Output)

433

434

FSR (Bit)

Out

437

438

FSR (Word)

Out

440

439

443

Last Bit

First Bit

Data In

441

FSR (Bit)

In

442

443

445

FSR (Word)

In

444

Flags In

AA0491

Figure 3-24 ESAI Receiver Timing

HCKT

463

SCKT (output)

464

Figure 3-25 ESAI HCKT Timing

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-51

GPIO Timing

HCKR

463

SCKR (output)

465

Figure 3-26 ESAI HCKR Timing

3.14 GPIO Timing

Table 3-21 GPIO Timing

No.

Characteristics¹

Expression

Min

—

Max

32.8

—

Unit

ns

490²EXTAL edge to GPIO out valid (GPIO out delay time)

491 EXTAL edge to GPIO out not valid (GPIO out hold time)

492 GPIO In valid to EXTAL edge (GPIO in set-up time)

493 EXTAL edge to GPIO in not valid (GPIO in hold time)

494²Fetch to EXTAL edge before GPIO change

495 GPIO out rise time

4.8

10.2

1.8

65.7

—

ns

—

ns

—

ns

6.75 × T_C-1.8

—

ns

—

13

ns

496 GPIO out fall time

—

13

ns

1

2

V_CC= 3.3 V 0.16 V; T_J= 0°C to +105°C, C_L= 50 pF

Valid only when PLL enabled with multiplication factor equal to one.

DSP56364 Technical Data, Rev. 4.1

3-52

Freescale Semiconductor

JTAG Timing

EXTAL

(Input)

490

491

GPIO

(Output)

492

493

GPIO

(Input)

Valid

A0–A17

494

Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO

and R0 contains the address of GPIO data register.

GPIO

(Output)

495

496

Figure 3-27 GPIO Timing

3.15 JTAG Timing

1. 2

Table 3-22 JTAG Timing

All Frequencies

No.

Characteristics

Unit

Min

0.0

Max

22.0

—

500 TCK frequency of operation (1/(T_C× 3); maximum 22 MHz)

501 TCK cycle time in Crystal mode

502 TCK clock pulse width measured at 1.5 V

503 TCK rise and fall times

MHz

ns

45.0

20.0

0.0

—

ns

3.0

—

ns

504 Boundary scan input data setup time

505 Boundary scan input data hold time

506 TCK low to output data valid

5.0

ns

24.0

0.0

—

ns

40.0

—

ns

507 TCK low to output high impedance

508 TMS, TDI data setup time

0.0

ns

5.0

ns

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-53

JTAG Timing

1. 2

Table 3-22 JTAG Timing

Characteristics

(continued)

All Frequencies

No.

Unit

Min

25.0

0.0

Max

—

509 TMS, TDI data hold time

510 TCK low to TDO data valid

ns

44.0

511 TCK low to TDO high impedance

0.0

1

2

V_CC= 3.3 V 0.16 V; T_J= 0°C to +105°C, C_L= 50 pF

All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

501

502

VM

502

VM

VIH

503

TCK

(Input)

VIL

503

AA0496

Figure 3-28 Test Clock Input Timing Diagram

VIH

TCK

(Input)

VIL

504

Input Data Valid

505

Data

Inputs

506

507

506

Data

Output Data Valid

Outputs

Data

Outputs

Data

Outputs

Output Data Valid

AA0497

Figure 3-29 Boundary Scan (JTAG) Timing Diagram

DSP56364 Technical Data, Rev. 4.1

3-54

Freescale Semiconductor

JTAG Timing

VIH

509

TCK

(Input)

VIL

508

Input Data Valid

TDI

TMS

(Input)

510

TDO

(Output)

Output Data Valid

511

TDO

(Output)

510

TDO

(Output)

Output Data Valid

AA0498

Figure 3-30 Test Access Port Timing Diagram

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-55

JTAG Timing

NOTES

DSP56364 Technical Data, Rev. 4.1

3-56

Freescale Semiconductor

4 Packaging

4.1

Pin-Out and Package Information

This section provides information about the available package for this product, including diagrams of the

package pinouts and tables describing how the signals described in Section 2, "Signal/Connection

Descriptions" are allocated for the package. The DSP56364 is available in a 100-pin TQFP package.

Table 4-1 and Table 4-2show the pin/name assignments for the packages.

4.1.1

TQFP Package Description

Top view of the 100-pin TQFP package is shown in Figure 4-1 with its pin-outs. The 100-pin TQFP

package mechanical drawing is shown in Figure 4-2.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

4-1

Pin-Out and Package Information

MODD

MODB

1

2

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

D0

A17

MODA

3

A16

FST

4

GNDA

VCCA

A15

FSR

5

SCKT

6

SCKR

7

A14

VCCS

8

A13

GNDS

9

A12

HCKT

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

VCCLQ

GNDQ

GNDA

VCCA

A11

VCCLQ

GNDQ

DSP56364

100-Pin TQPF

HCKR

SDO0

VCCHQ

SDO1

VCCHQ

A10

SDO2/SDI3

SDO3/SDI2

SDO4/SDI1

SDO5/SDI0

VCCS

A9

A8

A7

GNDA

VCCA

A6

GNDS

SS/HA2

MOSI/HA0

MISO/SDA

A5

A4

A3

Figure 4-1 DSP56364 100-Pin Thin Quad Flat Pack (TQFP), Top View

DSP56364 Technical Data, Rev. 4.1

4-2

Freescale Semiconductor

Pin-Out and Package Information

Table 4-1 DSP56364 100-Pin TQFP Signal Identification by Pin Number

No.

Signal Name

SCK/SCL

Signal Name

1

MODD/IRQD

MODB/IRQB

MODA/IRQA

FST

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

A3

A4

A5

A6

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

D1

D2

D3

2

HREQ

PINIT/NMI

RESET

No Connect

VCCP

PCAP

3

4

VCCD

GNDD

D4

5

FSR

VCCA

GNDA

A7

6

SCKT

7

SCKR

D5

8

VCCS

GNDP

EXTAL

VCCHQ

GNDQ

VCCLQ

TA

A8

D6

9

GNDS

A9

D7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

HCKT

A10

No Connect

VCCLQ

GNDQ

VCCHQ

No Connect

GPIO0

VCCS

GNDS

GPIO1

GPIO2

GPIO3

TDO

VCCLQ

GNDQ

VCCHQ

A11

HCKR

VCCA

GNDA

GNDQ

VCCLQ

A12

SDO0

CAS

VCCHQ

SDO1

WR

RD

VCCC

GNDC

AA1/RAS1

AA0/RAS0

A0

SDO2/SDI3

SDO3/SDI2

SDO4/SDI1

SDO5/SDI0

VCCS

A13

A14

A15

VCCA

GNDA

A16

A1

GNDS

VCCA

GNDA

SS/HA2

MOSI/HA0

MISO/SDA

TDI

A17

TCK

A2

D0

100 TMS

Note: Signal names are based on configured functionality. Most pins supply a single signal. Some pins provide a signal

with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted,

but act as interrupt lines during operation.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

4-3

Pin-Out and Package Information

Table 4-2 DSP56364 100-Pin TQFP Signal Identification by Name

No.

Signal Name

A0

A1

46

47

60

62

67

68

69

70

73

74

50

51

52

53

54

57

58

59

45

44

39

75

76

77

78

D4

81

82

83

84

34

5

HCKR

HCKT

13

10

27

25

3

SDO4/SDI1

TA

19

38

99

98

97

100

48

55

63

71

42

79

15

35

61

89

11

37

66

87

31

8

D5

A10

A11

A12

A13

A14

A15

A16

A17

A2

D6

HREQ

TCK

D7

MISO/SDA

MODA/IRQA

MODB/IRQB

MODD/IRQD

MOSI/HA0

No Connect

PCAP

TDI

EXTAL

FSR

TD0

2

TMS

FST

4

1

VCCA

VCCC

VCCD

VCCHQ

VCCLQ

VCCP

VCCS

WR

GNDA

GNDC

GNDD

GNDP

GNDQ

GNDS

GPIO0

GPIO1

GPIO2

GPIO3

49

56

64

72

43

80

33

12

36

65

88

9

24

30

85

86

90

32

28

41

29

26

7

A3

A4

A5

PINIT/NMI

RD

A6

A7

RESET

A8

SCK/SCL

SCKR

A9

AA0

AA1

CAS

D0

SCKT

6

22

93

91

94

95

96

SDO0

14

16

20

23

17

18

SDO1

SDO5/SDI0

SS/HA2

D1

21

92

40

D2

SDO2/SDI3

SDO3/SDI2

D3

DSP56364 Technical Data, Rev. 4.1

4-4

Freescale Semiconductor

Pin-Out and Package Information

4.1.2

TQFP Package Mechanical Drawing

Figure 4-2 DSP56364 100-pin TQFP Package

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

4-5

Pin-Out and Package Information

DSP56364 Technical Data, Rev. 4.1

4-6

Freescale Semiconductor

5 Design Considerations

5.1

Thermal Design Considerations

An estimation of the chip junction temperature, T , in °C can be obtained from the following equation:

J

T = T + (P × R )

θJA

J

A

D

Where:

T

= ambient temperature °C

= package junction-to-ambient thermal resistance °C/W

= power dissipation in package W

A

R

qJA

D

P

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and

a case-to-ambient thermal resistance.

R

= R

+ R

θJA

θJC

θCA

Where:

R

= package junction-to-ambient thermal resistance °C/W

= package junction-to-case thermal resistance °C/W

= package case-to-ambient thermal resistance °C/W

θJA

θJC

θCA

R

is device-related and cannot be influenced by the user. The user controls the thermal environment to

θJC

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

θCA

the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB), or

otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This

model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through

the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where

the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the

device thermal performance may need the additional modeling capability of a system level thermal

simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which

the package is mounted. Again, if the estimations obtained from R

the thermal performance is adequate, a system level model may be appropriate.

do not satisfactorily answer whether

θJA

A complicating factor is the existence of three common ways for determining the junction-to-case thermal

resistance in plastic packages.

•

To minimize temperature variation across the surface, the thermal resistance is measured from the

junction to the outside surface of the package (case) closest to the chip mounting area when that

surface has a proper heat sink.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

5-1

Electrical Design Considerations

•

To define a value approximately equal to a junction-to-board thermal resistance, the thermal

resistance is measured from the junction to where the leads are attached to the case.

If the temperature of the package case (T ) is determined by a thermocouple, the thermal resistance

T

is computed using the value obtained by the equation:

(T – T ) ⁄ P

D

J

T

As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the

first definition. From a practical standpoint, that value is also suitable for determining the junction

temperature from a case thermocouple reading in forced convection environments. In natural convection,

using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple

reading on the case of the package will estimate a junction temperature slightly hotter than actual

temperature. Hence, the new thermal metric, thermal characterization parameter or Ψ , has been defined

JT

to be (T – T )/P . This value gives a better estimate of the junction temperature in natural convection

J

T

D

when using the surface temperature of the package. Remember that surface temperature readings of

packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and

to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge

thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

5.2

Electrical Design Considerations

CAUTION

This device contains circuitry protecting against damage due to high static

voltage or electrical fields. However, normal precautions should be taken to

avoid exceeding maximum voltage ratings. Reliability of operation is

enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.,

either GND or V ). The suggested value for a pull-up or pull-down resistor

CC

is 10 k ohm.

Use the following list of recommendations to assure correct DSP operation:

•

Provide a low-impedance path from the board power supply to each V pin on the DSP and from

the board ground to each GND pin.

CC

Use at least six 0.01–0.1 μF bypass capacitors positioned as close as possible to the four sides of

the package to connect the V power source to GND.

CC

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V and

CC

GND pins are less than 1.2 cm (0.5 inch) per capacitor lead.

•

Use at least a four-layer PCB with two inner layers for V and GND.

CC

Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.

This recommendation particularly applies to the address and data buses as well as the IRQA,

IRQB, IRQD, and TA pins. Maximum PCB trace lengths on the order of 15 cm (6 inches) are

recommended.

•

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating

capacitance. This is especially critical in systems with higher capacitive loads that could create

higher transient currents in the V and GND circuits.

CC

DSP56364 Technical Data, Rev. 4.1

5-2

Freescale Semiconductor

Power Consumption Considerations

•

All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the three

pins with internal pull-up resistors (TMS, TDI, TCK).

•

Take special care to minimize noise levels on the V

and GND pins.

CCP P

If multiple DSP56364 devices are on the same board, check for cross-talk or excessive spikes on

the supplies due to synchronous operation of the devices.

•

RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied

before deassertion of RESET.

At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V

never exceeds 3.95 V.

CC

5.3

Power Consumption Considerations

Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current

consumption are described in this section. Most of the current consumed by CMOS devices is alternating

current (ac), which is charging and discharging the capacitances of the pins and internal nodes.

Current consumption is described by the following formula:

I = C × V × f

where

C

V

f

= node/pin capacitance

= voltage swing

= frequency of node/pin toggle

Example 1. Current Consumption

For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 100

MHz clock, toggling at its maximum possible rate (50 MHz), the current consumption is

–12

6

I = 50 × 10

× 3.3 × 50 × 10 = 8.25mA

The maximum internal current (I max) value reflects the typical possible switching of the internal buses

CCI

on best-case operation conditions, which is not necessarily a real application case. The typical internal

current (I

) value reflects the average switching of the internal buses on typical operating conditions.

CCItyp

For applications that require very low current consumption, do the following:

•

Set the EBD bit when not accessing external memory.

Minimize external memory accesses and use internal memory accesses.

Minimize the number of pins that are switching.

Minimize the capacitive load on the pins.

Connect the unused inputs to pull-up or pull-down resistors.

Disable unused peripherals.

One way to evaluate power consumption is to use a current per MIPS measurement methodology to

minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP).

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

5-3

PLL Performance Issues

A benchmark power consumption test algorithm is listed in Appendix A, "IBIS Model". Use the test

algorithm, specific test current measurements, and the following equation to derive the current per MIPS

value.

I ⁄ MIPS = I ⁄ MHz = (I

– I

) ⁄ (F2 – F1)

typF1

typF2

where:

I

F2

F1

= current at F2

= current at F1

= high frequency (any specified operating frequency)

typF2

typF1

= low frequency (any specified operating frequency lower than F2)

NOTE

F1 should be significantly less than F2. For example, F2 could be 66 MHz

and F1 could be 33 MHz. The degree of difference between F1 and F2

determines the amount of precision with which the current rating can be

determined for an application.

5.4

PLL Performance Issues

The following explanations should be considered as general observations on expected PLL behavior.

There is no testing that verifies these exact numbers. These observations were measured on a limited

number of parts and were not verified over the entire temperature and voltage ranges.

5.4.1

Input (EXTAL) Jitter Requirements

The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL

is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency

of the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be

2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the

prescribed values.

DSP56364 Technical Data, Rev. 4.1

5-4

Freescale Semiconductor

6 Ordering Information

Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability

and to place an order.

1, 2

Table 6-1 Ordering Information

Supply

Voltage

Count

Frequency

(MHz)

Part

Package Type

Order Number

DSP56364

3.3 V

Thin quad flat pack (TQFP)

Quad flat pack (QFP)

100

112

100

XCB56364FU100

XCB56364PV100

1

2

The DSP56364 can include factory-programmed ROM. The listed ‘B’ ROM code is a generic unused ROM available

to any customer. Variations will be supported for Dolby digital (AC-3), DTS, MPEG2, and other features. These

products are only available to authorized licensees of those technologies. Please consult the web site at

www.freescale.com/dsp for current availability.

Future products in the DSP56364 family may include other ROM-based options. For additional information on future

part development, or to request customer-specific ROM-based support, call your local Freescale Semiconductor

sales office or authorized distributor.

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

6-1

NOTES

DSP56364 Technical Data, Rev. 4.1

6-2

Freescale Semiconductor

Appendix A IBIS Model

IBIS Model

[IBIS Ver]

[File name]

[File Rev]

[Date]

3.2

56364_e.ibs

e

Feb 13, 2002

[Component]

[Manufacturer]

[Package]

| variable

R_pkg

56364

Freescale SEMI CONDUCTOR Ltd.

typ

min

max

75.0m

4.3nH

45.0m

2.5nH

1.3pF

22.0m

1.1nH

1.2pF

L_pkg

C_pkg

1.4pF

[Pin]

1

2

3

4

5

6

7

8

signal_name

irqd_

model_name

ipad5v_io

power

R_pin

L_pin

C_pin

irqb_

irqa_

fst

fsr

sckt

sckr

vccs

9

gnds

gnd

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

31

32

33

34

35

hckt

vcclq

gndq

hckr

sdo0

ipad5v_io

power

gnd

ipad5v_io

power

ipad5v_io

power

vcchq

sdo1

sdo2/sdi3

sdo3/sdi2

sdo4/sdi1

sdo5/sdi0

vccs

gnds

gnd

ss_/ha2

mosi/ha0

miso/sda

sck/scl

hreq_

pinit/nmi_

reset_

vccp

pcap

gndp

extal

vcchq

ipad5v_io

ipad5i_io

ipad5v_io

power

gnd

ipadex_i

power

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-1

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

87

88

89

91

92

93

gndq

vcclq

ta_

cas_

wr_

gnd

power

ipadn_io

ipadm_3st

ipadn_io

power

rd_

vccc

gndc

aa1/ras1_

aa0/ras0_

a0

gnd

ipado_3st

ipada_3st

a1

vcca

gnda

a2

a3

a4

a5

a6

vcca

gnda

a7

a8

a9

a10

vcchq

a11

vcca

gnda

gndq

vcclq

a12

a13

a14

a15

vcca

gnda

a16

a17

d0

d1

d2

d3

vccd

gndd

d4

d5

d6

power

gnd

ipada_3st

power

gnd

ipada_3st

power

ipada_3st

power

gnd

power

ipada_3st

power

gnd

ipada_3st

ipadd_io

power

gnd

ipadd_io

power

gnd

power

ipad5v_io

power

gnd

d7

vcclq

gndq

vcchq

gpio0

vccs

gnds

DSP56364 Technical Data, Rev. 4.1

A-2

Freescale Semiconductor

94

95

96

97

98

99

100

gpio1

gpio2

gpio3

tdo

tdi

tck

ipad5v_io

ipad5f_io

tms

[Model]

ipad5f_io

| ""

Model_type

Vinl = 0.8

Vinh = 2

| variable

C_comp

I/O

typ

1.96p

typ

min

1.87p

min

max

2.06p

max

120.0

| variable

[Temperature Range] 40.0

0.0

| variable

[Voltage Range]

|

typ

3.30V

min

3.00V

max

3.60V

[Pulldown]

| pulldown in the table = pulldown subtract gnd_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-142.303u -76.239u -215.182u

-149.700u -80.226u -226.432u

-157.861u -84.616u -238.866u

-166.908u -89.472u -252.678u

-176.992u -94.869u -268.107u

-188.295u -100.900u -285.446u

-201.049u -107.679u -305.068u

-215.545u -115.349u -327.446u

-232.155u -124.094u -353.191u

-251.367u -134.145u -383.107u

-273.825u -145.808u -418.273u

-300.403u -159.488u -460.167u

-332.314u -175.737u -510.874u

-371.286u -195.318u -573.418u

-419.868u -219.325u -652.360u

-481.968u -249.369u -754.892u

-563.882u -287.925u -893.013u

-676.382u -338.973u

-839.410u -409.300u

-1.094m -511.367u

-1.537m -670.350u

-2.451m -943.845u

-1.088m

-1.383m

-1.873m

-2.819m

-5.162m

-4.857m

-10.606m

-14.267m

-13.851m

-12.481m

-10.883m

-9.156m

-7.378m

-5.572m

-3.741m

-1.486m -12.214m

-2.746m -20.764m

-5.259m -21.749m

-7.108m -20.142m

-7.168m -18.211m

-6.348m -15.981m

-5.339m -13.503m

-4.288m -10.922m

-3.224m

-2.154m

-8.282m

-5.584m

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-3

-0.10V

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

-1.885m

1.898p

1.857m

3.630m

5.323m

6.936m

8.467m

9.915m

-1.080m

1.419p

1.057m

2.064m

3.023m

3.935m

4.798m

5.611m

6.371m

-2.825m

1.871p

2.800m

5.482m

8.052m

10.508m

12.849m

15.073m

17.176m

19.155m

21.011m

56.704m

60.708m

64.383m

67.726m

70.735m

73.414m

75.766m

77.783m

79.441m

80.724m

81.651m

82.294m

82.744m

83.074m

83.332m

83.543m

83.724m

83.884m

84.030m

84.165m

84.290m

84.409m

84.515m

84.491m

81.077m

79.736m

80.276m

82.430m

85.482m

91.743m

94.219m

96.276m

98.249m

11.275m

12.546m

13.723m

36.925m

39.391m

41.612m

43.585m

45.305m

46.773m

47.997m

48.985m

49.733m

50.257m

50.612m

50.858m

51.040m

51.182m

51.302m

51.405m

51.497m

51.581m

51.658m

51.727m

51.757m

51.229m

49.190m

49.441m

51.034m

54.363m

57.165m

58.834m

60.328m

61.725m

63.035m

64.319m

65.598m

66.836m

67.999m

69.069m

70.046m

70.938m

71.751m

72.476m

73.089m

73.531m

73.651m

72.901m

7.078m

7.726m

20.745m

22.074m

23.244m

24.247m

25.079m

25.741m

26.251m

26.633m

26.905m

27.092m

27.223m

27.321m

27.399m

27.465m

27.522m

27.572m

27.618m

27.657m

27.674m

27.587m

27.577m

28.700m

30.042m

31.171m

32.199m

33.153m

34.039m

34.872m

35.686m

36.495m

37.291m

38.051m

38.755m

39.394m 100.059m

39.962m 101.849m

40.453m 103.628m

40.840m 105.345m

41.065m 106.956m

40.952m 108.448m

40.067m 109.826m

39.395m 111.106m

39.313m 112.297m

39.358m 113.400m

39.410m 114.401m

DSP56364 Technical Data, Rev. 4.1

A-4

Freescale Semiconductor

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

71.005m

70.389m

70.321m

70.361m

70.422m

70.489m

70.557m

70.624m

70.690m

70.753m

70.817m

70.881m

70.949m

39.460m 115.267m

39.508m 115.917m

39.552m 116.139m

39.595m 114.582m

39.634m 111.344m

39.672m 110.612m

39.708m 110.449m

39.743m 110.455m

39.777m 110.515m

39.812m 110.595m

39.848m 110.686m

39.886m 110.783m

39.929m 110.885m

|

[Pullup]

| pullup in the table = pullup subtract power_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

-0.00V

0.10V

75.797u

90.464u

7.914u 161.477u

17.699u 181.779u

27.445u 202.314u

37.119u 223.007u

46.694u 243.785u

56.144u 264.581u

65.447u 285.332u

74.582u 305.982u

83.527u 326.474u

92.262u 346.757u

105.160u

119.836u

134.451u

148.966u

163.342u

177.543u

191.536u

205.285u

218.754u 100.766u 366.776u

231.907u 109.016u 386.478u

244.706u 116.988u 405.807u

257.106u 124.659u 424.699u

269.061u 131.998u 443.089u

280.519u 138.978u 460.899u

291.423u 145.565u 478.046u

301.710u 151.723u 494.457u

311.348u 157.417u 521.406u

729.899u 162.626u

10.510m 445.517u

1.612m

14.832m

13.576m

12.231m

10.854m

9.483m

8.169m

6.971m

5.921m

4.953m

3.978m

2.987m

2.003m

1.005m

24.081p

9.629m

8.670m

7.693m

6.732m

5.825m

5.004m

4.261m

3.549m

2.841m

2.135m

6.444m

5.833m

5.190m

4.551m

3.942m

3.382m

2.869m

2.381m

1.902m

1.426m

1.437m 951.489u

722.340u 478.341u

22.329p

-708.556u -465.927u -990.647u

3.311p

0.20V

0.30V

-1.377m -903.637u

-2.007m -1.319m

-1.943m

-2.832m

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-5

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

-2.614m

-3.192m

-3.738m

-4.253m

-4.736m

-5.185m

-5.600m

-5.980m

-6.324m

-1.710m

-2.079m

-2.423m

-2.742m

-3.037m

-3.305m

-3.547m

-3.762m

-3.948m

-3.702m

-4.537m

-5.336m

-6.096m

-6.817m

-7.499m

-8.139m

-8.737m

-9.292m

-9.802m

-6.631m -17.709m

-29.730m -18.279m -10.265m

-30.749m -18.747m -45.983m

-31.630m -19.131m -47.620m

-32.393m -19.454m -49.086m

-33.055m -19.730m -50.392m

-33.632m -19.973m -51.551m

-34.135m -20.188m -52.571m

-34.575m -20.381m -53.463m

-34.960m -20.556m -54.240m

-35.302m -20.715m -54.917m

-35.608m -20.861m -55.510m

-35.884m -20.997m -56.035m

-36.137m -21.123m -56.505m

-36.370m -21.241m -56.932m

-36.586m -21.352m -57.322m

-36.788m -21.457m -57.683m

-36.978m -21.556m -58.019m

-37.157m -21.650m -58.334m

-37.327m -21.741m -58.631m

-37.489m -21.827m -58.913m

-37.643m -21.909m -59.181m

-37.791m -21.989m -59.436m

-37.933m -22.067m -59.681m

-38.070m -22.143m -59.916m

-38.202m -22.216m -60.142m

-38.332m -22.284m -60.361m

-38.460m -22.352m -60.573m

-38.590m -22.420m -60.780m

-38.714m -22.490m -60.986m

-38.828m -22.561m -61.194m

-38.949m -22.635m -61.406m

-39.076m -22.713m -61.623m

-39.211m -22.798m -61.819m

-39.357m -22.892m -62.024m

-39.516m -22.997m -62.254m

-39.693m -23.116m -62.506m

-39.893m -23.253m -62.785m

-40.121m -23.411m -63.098m

-40.384m -23.595m -63.453m

-40.689m -23.801m -63.860m

-41.043m -24.032m -64.330m

-41.444m -24.288m -64.874m

-41.886m -24.570m -65.505m

-42.370m -24.880m -66.214m

-42.899m -25.217m -66.983m

DSP56364 Technical Data, Rev. 4.1

A-6

Freescale Semiconductor

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-43.473m -25.585m -67.815m

-44.095m -25.983m -68.711m

-44.769m -26.415m -69.678m

-45.498m -26.884m -70.721m

-46.287m -27.390m -71.848m

-47.140m -27.929m -73.065m

-48.049m -28.487m -74.374m

-48.990m -29.080m -75.748m

|

[GND_clamp]

|

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

-1.875

-1.793

-1.074

-1.029

-2.155

-2.059

-1.963

-1.771

-1.675

-1.579

-1.483

-1.388

-1.292

-1.197

-1.102

-1.007

-1.711 -983.765m

-1.548 -893.931m

-1.466 -849.071m

-1.385 -804.256m

-1.303 -759.489m

-1.221 -714.777m

-1.140 -670.127m

-1.059 -625.548m

-977.735m -581.048m

-896.773m -536.642m

-735.446m -448.177m -817.634m

-655.171m -404.164m -723.409m

-575.242m -360.342m -629.587m

-495.760m -316.758m -536.295m

-416.878m -273.482m -443.730m

-338.839m -230.618m -352.222m

-262.067m -188.327m -262.384m

-187.395m -146.891m -175.533m

-116.756m -106.839m -95.231m

-16.024m -37.029m

-2.254m -14.319m

-6.612m

-2.370m

-476.015u

-85.877u -295.354u -147.930u

-8.033u -33.637u -9.999u

-432.304n -3.576u -310.975n

-20.874n -340.944n -8.593n

-964.564p -30.895n -258.649p

-72.583p -2.560n -43.910p

-2.883m -845.181u

-33.685p -210.508p -34.610p

-27.665p -30.628p -29.748p

0.10V

0.20V

0.30V

0.40V

-22.754p

-18.303p

-14.129p

13.546p -25.110p

48.356p -20.906p

81.869p -16.971p

0.50V

-9.979p 114.849p -13.050p

0.60V

0.70V

0.80V

0.90V

1.10V

1.20V

-5.833p 147.499p

-1.689p 179.924p

2.454p 212.188p

6.596p 244.335p

14.877p 308.388p

19.017p 340.335p

-9.130p

-5.210p

-1.291p

2.628p

10.466p

14.384p

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-7

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.10V

3.20V

3.30V

23.157p 372.250p

27.297p 404.143p

31.436p 436.027p

35.576p 467.910p

39.715p 499.805p

43.855p 531.722p

47.995p 563.675p

56.277p 627.761p

60.418p 659.933p

64.561p 692.106p

68.706p 723.142p

72.847p 751.973p

76.869p 780.264p

80.074p 808.442p

82.499p 835.513p

84.837p 860.391p

18.302p

22.221p

26.139p

30.057p

33.974p

37.892p

41.810p

49.646p

53.564p

57.482p

61.400p

65.319p

69.237p

73.156p

77.065p

80.794p

86.195p

88.344p

90.478p

89.018p

89.573p

103.108p

1.265n

1.305n

1.593n

|

[POWER_clamp]

|

|Voltage

|

I(typ)

I(min)

I(max)

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-33.685p -340.944n -20.906p

-72.583p -3.576u -25.110p

-964.564p -33.637u -29.748p

-20.874n -295.354u -34.610p

-432.304n

-2.883m -43.910p

-8.033u -14.319m -258.649p

-85.877u -37.029m

-2.254m -106.839m

-8.593n

-9.999u

-16.024m -146.891m -147.930u

-55.636m -188.327m -845.181u

-116.756m -230.618m

-187.395m -273.482m

-2.370m

-6.612m

-262.067m -316.758m -33.199m

-338.839m -360.342m -95.231m

-416.878m -404.164m -175.533m

-495.760m -448.177m -262.384m

-655.171m -536.642m -443.730m

-735.446m -581.048m -536.295m

-815.997m -625.548m -629.587m

-896.773m -670.127m -723.409m

-977.735m -714.777m -817.634m

-1.059 -759.489m -912.174m

-1.140 -804.256m

-1.221 -849.071m

-1.303 -893.931m

-1.466 -983.765m

-1.007

-1.102

-1.197

-1.388

-1.483

-1.579

-1.675

-1.771

-1.867

-1.548

-1.630

-1.711

-1.793

-1.875

-1.029

-1.074

-1.119

-1.164

-1.209

DSP56364 Technical Data, Rev. 4.1

A-8

Freescale Semiconductor

|

[Ramp]

|Voltage

|

I(typ)

I(min)

I(max)

dV/dt_f

|

dV/dt_r

2.04/136.004p 1.86/237.542p 2.23/85.504p

2.05/194.744p 1.86/343.805p 2.23/118.850p

R_load=10000ohms

| R_load was connected to ground for Ramp_up test and power for Ramp_dn test

|

|End model

[Model]

ipad5i_io

I/O

| ""

Model_type

Vinl = 0.8

Vinh = 2

| variable

C_comp

typ

4.44p

typ

min

3.89p

min

max

4.56p

max

120.0

| variable

[Temperature Range] 40.0

0.0

| variable

[Voltage Range]

|

typ

3.30V

min

3.00V

max

3.60V

[Pulldown]

| pulldown in the table = pulldown subtract gnd_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-142.303u -76.239u -215.182u

-149.700u -80.226u -226.432u

-157.861u -84.616u -238.866u

-166.908u -89.472u -252.678u

-176.992u -94.869u -268.107u

-188.295u -100.900u -285.446u

-201.049u -107.679u -305.068u

-215.545u -115.349u -327.446u

-232.155u -124.094u -353.191u

-251.367u -134.145u -383.107u

-273.825u -145.808u -418.273u

-300.403u -159.488u -460.167u

-332.314u -175.737u -510.874u

-371.286u -195.318u -573.418u

-419.868u -219.325u -652.360u

-481.968u -249.369u -754.892u

-563.882u -287.925u -893.013u

-676.382u -338.973u

-839.410u -409.300u

-1.094m -511.367u

-1.537m -670.350u

-2.451m -943.845u

-1.088m

-1.383m

-1.873m

-2.819m

-5.162m

-4.857m

-10.606m

-14.267m

-13.851m

-12.481m

-10.883m

-9.156m

-1.486m -12.214m

-2.746m -20.764m

-5.259m -21.749m

-7.108m -20.142m

-7.168m -18.211m

-6.348m -15.981m

-5.339m -13.503m

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-9

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

-7.378m

-5.572m

-3.741m

-1.885m

1.898p

1.857m

3.630m

5.323m

6.936m

-4.288m -10.922m

-3.224m

-2.154m

-1.080m

1.419p

-8.282m

-5.584m

-2.825m

1.871p

1.057m

2.800m

2.064m

5.482m

3.023m

8.052m

3.935m

4.798m

5.611m

6.371m

7.078m

7.726m

10.508m

12.849m

15.073m

17.176m

19.155m

21.011m

56.704m

60.708m

64.383m

67.726m

70.735m

73.414m

75.766m

77.783m

79.441m

80.724m

81.651m

82.294m

82.744m

83.074m

83.332m

83.543m

83.724m

83.884m

84.030m

84.165m

84.290m

84.409m

84.519m

84.574m

83.365m

80.948m

81.423m

83.424m

87.158m

91.951m

94.228m

96.276m

98.249m

8.467m

9.915m

11.275m

12.546m

13.723m

36.925m

39.391m

41.612m

43.585m

45.305m

46.773m

47.997m

48.985m

49.733m

50.257m

50.612m

50.858m

51.040m

51.182m

51.302m

51.405m

51.497m

51.581m

51.658m

51.729m

51.781m

51.640m

50.282m

50.273m

51.871m

55.121m

57.228m

58.838m

60.328m

61.725m

63.035m

64.321m

65.602m

66.844m

68.012m

69.088m

70.072m

70.973m

71.794m

72.529m

73.152m

20.745m

22.074m

23.244m

24.247m

25.079m

25.741m

26.251m

26.633m

26.905m

27.092m

27.223m

27.321m

27.399m

27.465m

27.522m

27.572m

27.618m

27.658m

27.683m

27.643m

27.704m

28.793m

30.065m

31.174m

32.200m

33.153m

34.039m

34.872m

35.687m

36.498m

37.296m

38.059m

38.767m

39.409m 100.060m

39.982m 101.853m

40.478m 103.638m

40.871m 105.361m

41.102m 106.982m

40.996m 108.484m

40.118m 109.875m

39.453m 111.168m

DSP56364 Technical Data, Rev. 4.1

A-10

Freescale Semiconductor

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

73.605m

73.737m

72.999m

71.115m

70.512m

70.457m

70.511m

70.586m

70.667m

70.749m

70.831m

70.911m

70.989m

71.068m

71.148m

71.230m

39.379m 112.374m

39.432m 113.492m

39.492m 114.510m

39.551m 115.392m

39.608m 116.061m

39.661m 116.301m

39.713m 114.763m

39.762m 111.545m

39.809m 110.833m

39.855m 110.689m

39.899m 110.716m

39.944m 110.796m

39.988m 110.897m

40.034m 111.009m

40.083m 111.127m

40.136m 111.250m

|

[Pullup]

| pullup in the table = pullup subtract power_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

-0.00V

357.190u 184.381u 591.381u

356.622u 184.121u 590.188u

356.193u 183.920u 589.287u

355.875u 183.765u 588.617u

355.641u 183.645u 588.129u

355.468u 183.550u 587.779u

355.340u 183.472u 587.528u

355.242u 183.405u 587.349u

355.163u 183.345u 587.218u

355.097u 183.288u 587.118u

355.036u 183.233u 587.036u

354.978u 183.177u 586.964u

354.920u 183.119u 586.896u

354.860u 183.060u 586.829u

354.799u 182.997u 586.762u

354.734u 182.931u 586.692u

354.666u 182.862u 586.621u

354.595u 182.788u 586.574u

354.559u 182.711u 597.934u

764.198u 182.650u

10.536m 460.815u

1.674m

14.880m

13.612m

12.257m

10.870m

9.492m

8.173m

6.972m

5.921m

4.953m

3.978m

2.985m

2.002m

1.005m

24.891p

9.648m

8.683m

7.701m

6.737m

5.827m

5.004m

4.262m

3.549m

2.841m

2.134m

6.455m

5.841m

5.195m

4.554m

3.944m

3.383m

2.870m

2.382m

1.902m

1.426m

1.434m 951.249u

721.882u 477.946u

23.094p

36.805p

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-11

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

-708.040u -465.659u -990.277u

-1.374m -903.549u

-1.941m

-2.832m

-3.702m

-4.537m

-5.336m

-6.096m

-6.817m

-7.499m

-8.139m

-8.737m

-9.292m

-9.802m

-2.007m

-2.614m

-3.192m

-3.738m

-4.253m

-4.736m

-5.185m

-5.600m

-5.980m

-6.324m

-1.319m

-1.710m

-2.079m

-2.423m

-2.742m

-3.037m

-3.305m

-3.547m

-3.762m

-3.948m

-6.631m -17.709m

-29.730m -18.279m -10.265m

-30.749m -18.747m -45.983m

-31.630m -19.131m -47.620m

-32.393m -19.454m -49.086m

-33.055m -19.730m -50.392m

-33.632m -19.973m -51.551m

-34.135m -20.188m -52.571m

-34.575m -20.381m -53.463m

-34.960m -20.556m -54.240m

-35.302m -20.715m -54.917m

-35.608m -20.861m -55.510m

-35.884m -20.997m -56.035m

-36.137m -21.123m -56.505m

-36.370m -21.241m -56.932m

-36.586m -21.352m -57.322m

-36.788m -21.457m -57.683m

-36.978m -21.556m -58.019m

-37.157m -21.650m -58.334m

-37.327m -21.741m -58.631m

-37.489m -21.827m -58.913m

-37.643m -21.909m -59.181m

-37.791m -21.989m -59.436m

-37.933m -22.067m -59.681m

-38.070m -22.143m -59.916m

-38.202m -22.216m -60.142m

-38.332m -22.284m -60.361m

-38.460m -22.352m -60.573m

-38.590m -22.420m -60.780m

-38.714m -22.490m -60.986m

-38.828m -22.561m -61.194m

-38.949m -22.635m -61.406m

-39.076m -22.713m -61.623m

-39.211m -22.798m -61.819m

-39.357m -22.892m -62.024m

-39.516m -22.997m -62.254m

-39.693m -23.116m -62.506m

-39.893m -23.253m -62.785m

-40.121m -23.411m -63.098m

-40.384m -23.595m -63.453m

-40.689m -23.801m -63.860m

-41.043m -24.032m -64.330m

-41.444m -24.288m -64.874m

DSP56364 Technical Data, Rev. 4.1

A-12

Freescale Semiconductor

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-41.886m -24.570m -65.505m

-42.370m -24.880m -66.214m

-42.899m -25.217m -66.983m

-43.473m -25.585m -67.815m

-44.095m -25.983m -68.711m

-44.769m -26.415m -69.678m

-45.498m -26.884m -70.721m

-46.287m -27.390m -71.848m

-47.140m -27.929m -73.065m

-48.049m -28.487m -74.374m

-48.990m -29.080m -75.748m

|

[GND_clamp]

|

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

-1.875

-1.793

-1.074

-1.029

-2.155

-2.059

-1.963

-1.771

-1.675

-1.579

-1.483

-1.388

-1.292

-1.197

-1.102

-1.007

-1.711 -983.769m

-1.548 -893.934m

-1.466 -849.075m

-1.385 -804.259m

-1.303 -759.493m

-1.221 -714.781m

-1.140 -670.131m

-1.059 -625.551m

-977.740m -581.052m

-896.779m -536.646m

-735.452m -448.180m -817.639m

-655.177m -404.167m -723.415m

-575.247m -360.345m -629.593m

-495.766m -316.761m -536.300m

-416.883m -273.485m -443.735m

-338.844m -230.621m -352.227m

-262.072m -188.330m -262.388m

-187.399m -146.893m -175.537m

-116.760m -106.842m -95.235m

-16.027m -37.031m

-2.255m -14.321m

-6.614m

-2.370m

-476.049u

-85.878u -295.501u -147.930u

-8.033u -33.646u -9.999u

-432.308n -3.576u -310.979n

-20.878n -340.971n -8.597n

-968.068p -30.900n -262.449p

-75.987p -2.564n -47.610p

-2.884m -845.183u

-36.990p -214.009p -38.210p

-30.869p -34.018p -33.249p

0.10V

0.20V

0.30V

0.40V

-25.858p

-21.307p

-17.033p

10.263p -28.510p

45.181p -24.206p

78.801p -20.171p

0.50V

0.60V

-12.783p 111.888p -16.150p

-8.537p 144.645p -12.130p

0.70V

0.80V

-4.293p 177.177p

-49.635f 209.548p

-8.110p

-4.091p

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-13

0.90V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.10V

3.20V

3.30V

4.192p 241.802p -71.907f

12.674p 306.070p

16.914p 338.124p

21.154p 370.146p

25.393p 402.147p

29.633p 434.138p

-31.788p 466.129p

7.965p

11.984p

16.002p

20.020p

24.038p

28.056p

38.112p 498.131p -33.622p

42.352p 530.156p

46.592p 562.217p

55.074p 626.519p

59.316p 658.799p

63.559p 691.080p

67.803p 722.224p

72.044p 751.129p

76.162p 779.443p

79.409p 807.731p

81.838p 835.534p

84.178p 864.770p

36.092p

40.110p

48.146p

52.164p

56.182p

60.200p

64.219p

68.237p

72.256p

76.265p

80.080p

85.501p

87.652p

89.793p

88.733p

90.025p

96.129p

1.234n

1.247n

1.274n

|

[POWER_clamp]

|

|Voltage

|

I(typ)

I(min)

I(max)

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.10V

6.20V

6.30V

-36.990p -340.971n -24.206p

-75.987p -3.576u -28.510p

-968.068p -33.646u -33.249p

-20.878n -295.501u -38.210p

-432.308n

-2.884m -47.610p

-8.033u -14.321m -262.449p

-85.878u -37.031m

-2.255m -106.842m

-8.597n

-9.999u

-16.027m -146.893m -147.930u

-55.640m -188.330m -845.183u

-116.760m -230.621m

-187.399m -273.485m

-2.370m

-6.614m

-262.072m -316.761m -33.203m

-338.844m -360.345m -95.235m

-416.883m -404.167m -175.537m

-495.766m -448.180m -262.388m

-655.177m -536.646m -443.735m

-735.452m -581.052m -536.300m

-816.003m -625.551m -629.593m

-896.779m -670.131m -723.415m

-977.740m -714.781m -817.639m

-1.059 -759.493m -912.179m

-1.140 -804.259m

-1.221 -849.075m

-1.303 -893.934m

-1.466 -983.769m

-1.007

-1.102

-1.197

-1.388

-1.483

-1.579

-1.548

-1.630

-1.029

-1.074

DSP56364 Technical Data, Rev. 4.1

A-14

Freescale Semiconductor

6.40V

6.50V

6.60V

-1.711

-1.793

-1.875

-1.119

-1.164

-1.209

-1.675

-1.771

-1.867

|

[Ramp]

|Voltage

|

I(typ)

I(min)

I(max)

dV/dt_f

|

dV/dt_r

2.01/129.093p 1.83/223.594p 2.20/79.668p

2.02/200.492p 1.83/352.515p 2.20/122.321p

R_load=10000ohms

| R_load was connected to ground for Ramp_up test and power for Ramp_dn test

|

|End model

[Model]

ipad5v_io

I/O

| ""

Model_type

Vinl = 0.8

Vinh = 2

| variable

C_comp

typ

1.96p

typ

min

1.87p

min

max

2.06p

max

120.0

| variable

[Temperature Range] 40.0

0.0

| variable

[Voltage Range]

|

typ

3.30V

min

3.00V

max

3.60V

[Pulldown]

| pulldown in the table = pulldown subtract gnd_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-142.303u -76.239u -215.182u

-149.700u -80.226u -226.432u

-157.861u -84.616u -238.866u

-166.908u -89.472u -252.678u

-176.992u -94.869u -268.107u

-188.295u -100.900u -285.446u

-201.049u -107.679u -305.068u

-215.545u -115.349u -327.446u

-232.155u -124.094u -353.191u

-251.367u -134.145u -383.107u

-273.825u -145.808u -418.273u

-300.403u -159.488u -460.167u

-332.314u -175.737u -510.874u

-371.286u -195.318u -573.418u

-419.868u -219.325u -652.360u

-481.968u -249.369u -754.892u

-563.882u -287.925u -893.013u

-676.382u -338.973u

-839.410u -409.300u

-1.094m -511.367u

-1.537m -670.350u

-2.451m -943.845u

-1.088m

-1.383m

-1.873m

-2.819m

-5.162m

-4.857m

-10.606m

-14.267m

-13.851m

-1.486m -12.214m

-2.746m -20.764m

-5.259m -21.749m

-7.108m -20.142m

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-15

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

-12.481m

-10.883m

-9.156m

-7.378m

-5.572m

-3.741m

-1.885m

1.898p

-7.168m -18.211m

-6.348m -15.981m

-5.339m -13.503m

-4.288m -10.922m

-3.224m

-2.154m

-1.080m

1.419p

-8.282m

-5.584m

-2.825m

1.871p

1.857m

3.630m

5.323m

6.936m

8.467m

9.915m

1.057m

2.800m

2.064m

5.482m

3.023m

8.052m

3.935m

4.798m

5.611m

6.371m

7.078m

7.726m

10.508m

12.849m

15.073m

17.176m

19.155m

21.011m

56.704m

60.708m

64.383m

67.726m

70.735m

73.414m

75.766m

77.783m

79.441m

80.724m

81.651m

82.294m

82.744m

83.074m

83.332m

83.543m

83.724m

83.884m

84.030m

84.165m

84.290m

84.409m

84.515m

84.491m

81.077m

79.736m

80.276m

82.430m

85.482m

91.743m

94.219m

96.276m

98.249m

11.275m

12.546m

13.723m

36.925m

39.391m

41.612m

43.585m

45.305m

46.773m

47.997m

48.985m

49.733m

50.257m

50.612m

50.858m

51.040m

51.182m

51.302m

51.405m

51.497m

51.581m

51.658m

51.727m

51.757m

51.229m

49.190m

49.441m

51.034m

54.363m

57.165m

58.834m

60.328m

61.725m

63.035m

64.319m

65.598m

66.836m

67.999m

69.069m

70.046m

70.938m

20.745m

22.074m

23.244m

24.247m

25.079m

25.741m

26.251m

26.633m

26.905m

27.092m

27.223m

27.321m

27.399m

27.465m

27.522m

27.572m

27.618m

27.657m

27.674m

27.587m

27.577m

28.700m

30.042m

31.171m

32.199m

33.153m

34.039m

34.872m

35.686m

36.495m

37.291m

38.051m

38.755m

39.394m 100.059m

39.962m 101.849m

40.453m 103.628m

40.840m 105.345m

41.065m 106.956m

DSP56364 Technical Data, Rev. 4.1

A-16

Freescale Semiconductor

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

71.751m

72.476m

73.089m

73.531m

73.651m

72.901m

71.005m

70.389m

70.321m

70.361m

70.422m

70.489m

70.557m

70.624m

70.690m

70.753m

70.817m

70.881m

70.949m

40.952m 108.448m

40.067m 109.826m

39.395m 111.106m

39.313m 112.297m

39.358m 113.400m

39.410m 114.401m

39.460m 115.267m

39.508m 115.917m

39.552m 116.139m

39.595m 114.582m

39.634m 111.344m

39.672m 110.612m

39.708m 110.449m

39.743m 110.455m

39.777m 110.515m

39.812m 110.595m

39.848m 110.686m

39.886m 110.783m

39.929m 110.885m

|

[Pullup]

| pullup in the table = pullup subtract power_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

75.797u

90.464u

7.914u 161.477u

17.699u 181.779u

27.445u 202.314u

37.119u 223.007u

46.694u 243.785u

56.144u 264.581u

65.447u 285.332u

74.582u 305.982u

83.527u 326.474u

92.262u 346.757u

105.160u

119.836u

134.451u

148.966u

163.342u

177.543u

191.536u

205.285u

218.754u 100.766u 366.776u

231.907u 109.016u 386.478u

244.706u 116.988u 405.807u

257.106u 124.659u 424.699u

269.061u 131.998u 443.089u

280.519u 138.978u 460.899u

291.423u 145.565u 478.046u

301.710u 151.723u 494.457u

311.348u 157.417u 521.406u

729.899u 162.626u

10.510m 445.517u

1.612m

14.832m

13.576m

12.231m

10.854m

9.483m

8.169m

6.971m

5.921m

4.953m

9.629m

8.670m

7.693m

6.732m

5.825m

5.004m

4.261m

3.549m

6.444m

5.833m

5.190m

4.551m

3.942m

3.382m

2.869m

2.381m

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-17

-0.40V

-0.30V

-0.20V

-0.10V

-0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

2.841m

2.135m

1.437m 951.489u

1.902m

1.426m

3.978m

2.987m

2.003m

1.005m

24.081p

722.340u 478.341u

22.329p

-708.556u -465.927u -990.647u

36.936p

-1.377m -903.637u

-1.943m

-2.832m

-3.702m

-4.537m

-5.336m

-6.096m

-6.817m

-7.499m

-8.139m

-8.737m

-9.292m

-9.802m

-2.007m

-2.614m

-3.192m

-3.738m

-4.253m

-4.736m

-5.185m

-5.600m

-5.980m

-6.324m

-1.319m

-1.710m

-2.079m

-2.423m

-2.742m

-3.037m

-3.305m

-3.547m

-3.762m

-3.948m

-6.631m -17.709m

-29.730m -18.279m -10.265m

-30.749m -18.747m -45.983m

-31.630m -19.131m -47.620m

-32.393m -19.454m -49.086m

-33.055m -19.730m -50.392m

-33.632m -19.973m -51.551m

-34.135m -20.188m -52.571m

-34.575m -20.381m -53.463m

-34.960m -20.556m -54.240m

-35.302m -20.715m -54.917m

-35.608m -20.861m -55.510m

-35.884m -20.997m -56.035m

-36.137m -21.123m -56.505m

-36.370m -21.241m -56.932m

-36.586m -21.352m -57.322m

-36.788m -21.457m -57.683m

-36.978m -21.556m -58.019m

-37.157m -21.650m -58.334m

-37.327m -21.741m -58.631m

-37.489m -21.827m -58.913m

-37.643m -21.909m -59.181m

-37.791m -21.989m -59.436m

-37.933m -22.067m -59.681m

-38.070m -22.143m -59.916m

-38.202m -22.216m -60.142m

-38.332m -22.284m -60.361m

-38.460m -22.352m -60.573m

-38.590m -22.420m -60.780m

-38.714m -22.490m -60.986m

-38.828m -22.561m -61.194m

-38.949m -22.635m -61.406m

-39.076m -22.713m -61.623m

-39.211m -22.798m -61.819m

-39.357m -22.892m -62.024m

-39.516m -22.997m -62.254m

-39.693m -23.116m -62.506m

-39.893m -23.253m -62.785m

DSP56364 Technical Data, Rev. 4.1

A-18

Freescale Semiconductor

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-40.121m -23.411m -63.098m

-40.384m -23.595m -63.453m

-40.689m -23.801m -63.860m

-41.043m -24.032m -64.330m

-41.444m -24.288m -64.874m

-41.886m -24.570m -65.505m

-42.370m -24.880m -66.214m

-42.899m -25.217m -66.983m

-43.473m -25.585m -67.815m

-44.095m -25.983m -68.711m

-44.769m -26.415m -69.678m

-45.498m -26.884m -70.721m

-46.287m -27.390m -71.848m

-47.140m -27.929m -73.065m

-48.049m -28.487m -74.374m

-48.990m -29.080m -75.748m

|

[GND_clamp]

|

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

-1.875

-1.793

-1.074

-1.029

-2.155

-2.059

-1.963

-1.771

-1.675

-1.579

-1.483

-1.388

-1.292

-1.197

-1.102

-1.007

-1.711 -983.765m

-1.548 -893.931m

-1.466 -849.071m

-1.385 -804.256m

-1.303 -759.489m

-1.221 -714.777m

-1.140 -670.127m

-1.059 -625.548m

-977.735m -581.048m

-896.773m -536.642m

-735.446m -448.177m -817.634m

-655.171m -404.164m -723.409m

-575.242m -360.342m -629.587m

-495.760m -316.758m -536.295m

-416.878m -273.482m -443.730m

-338.839m -230.618m -352.222m

-262.067m -188.327m -262.384m

-187.395m -146.891m -175.533m

-116.756m -106.839m -95.231m

-16.024m -37.029m

-2.254m -14.319m

-6.612m

-2.370m

-476.015u

-85.877u -295.354u -147.930u

-8.033u -33.637u -9.999u

-432.304n -3.576u -310.975n

-20.874n -340.944n -8.593n

-964.564p -30.895n -258.649p

-72.583p -2.560n -43.910p

-2.883m -845.181u

-33.685p -210.508p -34.610p

-27.665p -30.628p -29.748p

0.10V

0.20V

0.30V

-22.754p

-18.303p

13.546p -25.110p

48.356p -20.906p

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-19

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.10V

3.20V

3.30V

-14.129p

-9.979p 114.849p -13.050p

81.869p -16.971p

-5.833p 147.499p

-1.689p 179.924p

2.454p 212.188p

6.596p 244.335p

14.877p 308.388p

19.017p 340.335p

23.157p 372.250p

27.297p 404.143p

31.436p 436.027p

35.576p 467.910p

39.715p 499.805p

43.855p 531.722p

47.995p 563.675p

56.277p 627.761p

60.418p 659.933p

64.561p 692.106p

68.706p 723.142p

72.847p 751.973p

76.869p 780.264p

80.074p 808.442p

82.499p 835.513p

84.837p 860.391p

-9.130p

-5.210p

-1.291p

2.628p

10.466p

14.384p

18.302p

22.221p

26.139p

30.057p

33.974p

37.892p

41.810p

49.646p

53.564p

57.482p

61.400p

65.319p

69.237p

73.156p

77.065p

80.794p

86.195p

88.344p

90.478p

89.018p

89.573p

103.108p

1.265n

1.305n

1.593n

|

[POWER_clamp]

|

|Voltage

|

I(typ)

I(min)

I(max)

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

-33.685p -340.944n -20.906p

-72.583p -3.576u -25.110p

-964.564p -33.637u -29.748p

-20.874n -295.354u -34.610p

-432.304n

-2.883m -43.910p

-8.033u -14.319m -258.649p

-85.877u -37.029m

-2.254m -106.839m

-8.593n

-9.999u

-16.024m -146.891m -147.930u

-55.636m -188.327m -845.181u

-116.756m -230.618m

-187.395m -273.482m

-2.370m

-6.612m

-262.067m -316.758m -33.199m

-338.839m -360.342m -95.231m

-416.878m -404.164m -175.533m

-495.760m -448.177m -262.384m

-655.171m -536.642m -443.730m

-735.446m -581.048m -536.295m

-815.997m -625.548m -629.587m

-896.773m -670.127m -723.409m

-977.735m -714.777m -817.634m

-1.059 -759.489m -912.174m

-1.140 -804.256m

-1.007

DSP56364 Technical Data, Rev. 4.1

A-20

Freescale Semiconductor

5.80V

5.90V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-1.221 -849.071m

-1.303 -893.931m

-1.466 -983.765m

-1.102

-1.197

-1.388

-1.483

-1.579

-1.675

-1.771

-1.867

-1.548

-1.630

-1.711

-1.793

-1.875

-1.029

-1.074

-1.119

-1.164

-1.209

|

[Ramp]

|Voltage

|

I(typ)

I(min)

I(max)

dV/dt_f

|

dV/dt_r

2.04/134.002p 1.86/235.405p 2.23/85.874p

2.05/194.838p 1.86/341.412p 2.23/118.822p

R_load=10000ohms

| R_load was connected to ground for Ramp_up test and power for Ramp_dn test

|

|End model

[Model]

ipada_3st

3-state

typ

2.32p

typ

| ""

Model_type

| variable

C_comp

| variable

[Temperature Range] 40.0

min

2.17p

min

max

2.48p

max

120.0

0.0

| variable

[Voltage Range]

|

typ

3.30V

min

3.00V

max

3.60V

[Pulldown]

| pulldown in the table = pulldown subtract gnd_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-157.134u -99.256u -219.000u

-165.037u -104.127u -230.250u

-173.749u -109.479u -242.685u

-183.400u -115.386u -256.500u

-194.148u -121.936u -271.934u

-206.189u -129.240u -289.286u

-219.766u -137.431u -308.933u

-235.190u -146.680u -331.355u

-252.856u -157.199u -357.176u

-273.283u -169.265u -387.219u

-297.162u -183.236u -422.595u

-325.427u -199.590u -464.837u

-359.384u -218.976u -516.117u

-400.901u -242.299u -579.623u

-452.750u -270.851u -660.217u

-519.217u -306.549u -765.681u

-607.277u -352.346u -909.270u

-729.045u -413.024u

-907.407u -496.811u

-1.191m -619.011u

-1.699m -811.079u

-1.115m

-1.434m

-1.987m

-3.133m

-6.243m

-2.799m

-5.689m

-1.146m

-1.822m -12.974m

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-21

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

-10.416m

-12.342m

-11.672m

-10.528m

-9.204m

-7.770m

-6.286m

-4.766m

-3.214m

-3.302m -17.948m

-5.449m -17.964m

-6.479m -16.692m

-6.146m -15.152m

-5.387m -13.338m

-4.535m -11.313m

-3.652m

-2.754m

-1.846m

-9.190m

-6.999m

-4.740m

-2.410m

-1.607f

2.391m

-1.627m -928.990u

32.871e-18 18.541e-18

1.604m 910.814u

3.124m

4.566m

5.928m

7.210m

8.411m

1.775m

2.595m

3.372m

4.105m

4.792m

5.432m

6.023m

6.563m

7.051m

7.486m

7.865m

8.189m

64.562m

66.208m

4.661m

6.817m

8.858m

10.784m

12.593m

14.284m

15.855m

17.306m

18.639m

19.856m

20.957m

21.944m

22.817m

23.575m

9.529m

10.562m

11.508m

12.367m

13.138m

13.821m

14.417m

14.930m

117.094m

119.708m

121.667m

123.055m

124.020m

124.711m

125.232m

125.650m

126.000m

126.305m

126.577m

126.823m

127.050m

127.260m

127.457m

127.643m

127.818m

127.986m

128.147m

128.304m

128.458m

128.614m

128.776m

128.948m

129.140m

129.361m

129.621m

129.934m

130.316m

130.784m

67.513m 184.138m

68.498m 187.874m

69.206m 190.647m

69.710m 192.621m

70.083m 194.017m

70.374m 195.034m

70.612m 195.815m

70.814m 196.447m

70.992m 196.983m

71.151m 197.453m

71.296m 197.876m

71.428m 198.263m

71.551m 198.622m

71.666m 198.958m

71.774m 199.275m

71.876m 199.576m

71.973m 199.863m

72.066m 200.138m

72.156m 200.405m

72.245m 200.667m

72.335m 200.928m

72.428m 201.194m

72.527m 201.472m

72.638m 201.774m

72.764m 202.113m

72.914m 202.503m

73.093m 202.966m

73.311m 203.524m

73.579m 204.203m

DSP56364 Technical Data, Rev. 4.1

A-22

Freescale Semiconductor

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

131.358m

132.060m

132.912m

133.939m

135.166m

136.619m

138.324m

140.308m

142.597m

145.217m

148.192m

151.545m

155.300m

159.478m

164.097m

169.177m

174.734m

73.906m 205.033m

74.304m 206.045m

74.787m 207.276m

75.368m 208.763m

76.060m 210.544m

76.878m 212.659m

77.836m 215.149m

78.948m 218.056m

80.230m 221.419m

81.694m 225.277m

83.355m 229.669m

85.224m 234.630m

87.316m 240.194m

89.640m 246.393m

92.208m 253.255m

95.029m 260.806m

98.112m 269.070m

180.781m 101.465m 278.065m

187.333m 105.096m 287.810m

194.400m 109.009m 298.319m

201.993m 113.211m 309.602m

210.118m 117.705m 321.670m

|

[Pullup]

| pullup in the table = pullup subtract power_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

132.979u 100.794u 170.075u

138.984u 105.115u 178.000u

145.559u 109.825u 186.702u

152.789u 114.981u 196.300u

160.778u 120.648u 206.941u

169.651u 126.906u 218.803u

179.562u 133.852u 232.110u

190.706u 141.605u 247.141u

203.326u 150.317u 264.253u

217.736u 160.174u 283.910u

234.344u 171.418u 306.723u

253.692u 184.362u 333.513u

276.513u 199.421u 365.415u

303.830u 217.155u 404.033u

337.102u 238.340u 451.722u

378.494u 264.081u 512.067u

431.351u 296.004u 590.810u

501.113u 336.601u 697.730u

597.240u 389.880u 850.877u

737.641u 462.700u

960.395u 567.748u

1.361m 731.012u

1.087m

1.497m

2.348m

4.712m

10.148m

12.062m

11.029m

9.778m

8.443m

2.237m

4.644m

8.090m

8.032m

7.118m

6.128m

1.013m

1.583m

2.907m

4.727m

4.754m

4.128m

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-23

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

-0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.109m

4.082m

3.056m

2.033m

3.441m

2.746m

2.053m

1.363m

7.052m

5.644m

4.233m

2.821m

1.410m

1.014m 678.856u

58.687e-18 58.622e-18 117.504e-18

-987.106u -655.604u

-1.381m

-2.709m

-3.988m

-5.216m

-6.392m

-7.516m

-8.587m

-9.602m

-1.928m

-2.828m

-3.685m

-4.499m

-5.269m

-5.994m

-6.673m

-7.306m

-7.890m

-8.424m

-8.907m

-1.274m

-1.859m

-2.412m

-2.931m

-3.416m

-3.866m

-4.280m

-4.658m -10.561m

-4.999m -11.461m

-5.301m -12.302m

-5.563m -13.081m

-9.339m -65.539m -13.798m

-110.103m -67.611m -154.438m

-113.807m -69.311m -170.370m

-117.010m -70.713m -176.323m

-119.783m -71.893m -181.647m

-122.195m -72.910m -186.387m

-124.297m -73.804m -190.581m

-126.131m -74.599m -194.261m

-127.733m -75.311m -197.468m

-129.139m -75.954m -200.255m

-130.384m -76.540m -202.683m

-131.498m -77.077m -204.814m

-132.504m -77.575m -206.704m

-133.423m -78.037m -208.399m

-134.270m -78.470m -209.937m

-135.057m -78.877m -211.346m

-135.792m -79.261m -212.650m

-136.483m -79.625m -213.864m

-137.136m -79.971m -215.004m

-137.756m -80.302m -216.079m

-138.345m -80.617m -217.098m

-138.908m -80.920m -218.067m

-139.447m -81.210m -218.993m

-139.964m -81.490m -219.880m

-140.462m -81.761m -220.732m

-140.943m -82.022m -221.552m

-141.408m -82.277m -222.344m

-141.860m -82.525m -223.112m

-142.300m -82.769m -223.858m

-142.733m -83.010m -224.586m

-143.159m -83.250m -225.300m

-143.585m -83.493m -226.006m

-144.013m -83.740m -226.709m

-144.449m -83.996m -227.417m

-144.899m -84.265m -228.137m

-145.370m -84.551m -228.879m

-145.871m -84.861m -229.656m

DSP56364 Technical Data, Rev. 4.1

A-24

Freescale Semiconductor

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-146.411m -85.200m -230.481m

-147.001m -85.575m -231.368m

-147.652m -85.993m -232.336m

-148.379m -86.464m -233.404m

-149.195m -86.995m -234.592m

-150.115m -87.597m -235.924m

-151.157m -88.280m -237.426m

-152.339m -89.054m -239.124m

-153.678m -89.930m -241.046m

-155.194m -90.921m -243.223m

-156.907m -92.038m -245.685m

-158.839m -93.294m -248.465m

-161.011m -94.701m -251.595m

-163.444m -96.273m -255.109m

-166.160m -98.023m -259.041m

-169.182m -99.963m -263.425m

-172.531m -102.106m -268.293m

|

[GND_clamp]

|

|Voltage

|

I(typ)

-2.637

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

-1.514

-1.451

-1.387

-1.259

-1.195

-1.132

-1.068

-1.004

-3.063

-2.926

-2.789

-2.515

-2.378

-2.242

-2.105

-1.969

-1.833

-1.697

-1.561

-1.425

-1.155

-1.021

-2.521

-2.406

-2.174

-2.059

-1.943

-1.828

-1.713

-1.598 -941.073m

-1.483 -877.750m

-1.368 -814.544m

-1.254 -751.475m

-1.026 -625.847m

-912.311m -563.357m

-799.377m -501.149m -886.904m

-687.103m -439.297m -753.859m

-575.715m -377.904m -621.897m

-465.583m -317.129m -491.519m

-357.354m -257.221m -363.667m

-252.314m -198.614m -240.395m

-153.494m -142.138m -127.373m

-19.457m -45.305m -11.215m

-3.535m -16.226m

-877.640u -3.288m

-156.838u -397.909u -271.662u

-14.514u -53.601u -18.044u

-780.351n

-37.668n -598.098n -15.437n

-1.699n -55.739n -411.332p

-4.650m

-1.613m

-6.086u -560.308n

-92.071p

-27.709p

-5.410n -29.683p

-1.212n -18.939p

0.10V

0.20V

-22.802p -890.771p -16.163p

-19.598p -810.054p -13.516p

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-25

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.10V

3.20V

3.30V

-16.468p -745.765p -10.874p

-13.353p -683.799p

-10.247p -622.802p

-7.147p -562.404p

-8.234p

-5.595p

-2.956p

-4.050p -502.414p -318.962f

-955.896f -442.712p

2.136p -383.217p

8.315p -264.634p

11.404p -205.467p

14.492p -146.346p

17.579p -87.245p

20.666p -28.141p

2.318p

4.954p

10.227p

12.862p

15.498p

18.133p

20.768p

23.404p

26.039p

28.674p

31.310p

36.581p

39.216p

41.852p

44.489p

47.125p

49.762p

52.401p

55.040p

57.675p

61.928p

63.585p

65.236p

23.754p

26.841p

30.987p

90.164p

29.929p 149.414p

33.018p 208.769p

39.198p 327.949p

42.291p 387.873p

45.385p 448.012p

48.483p 507.296p

51.583p 563.856p

54.673p 619.785p

57.468p 676.156p

59.647p 733.868p

61.717p 807.258p

65.859p

68.003p

5.906n

59.801n

72.601p 620.266n

|

[POWER_clamp]

|

|Voltage

|

I(typ)

I(min)

I(max)

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

-27.709p -598.098n -10.874p

-92.071p -6.086u -13.516p

-1.699n -53.601u -16.163p

-37.668n -397.909u -18.939p

-780.351n

-3.288m -29.683p

-14.514u -16.226m -411.332p

-156.838u -45.305m -15.437n

-3.535m -142.138m -18.044u

-19.457m -198.614m -271.662u

-69.631m -257.221m

-153.494m -317.129m

-1.613m

-4.650m

-252.314m -377.904m -11.215m

-357.354m -439.297m -43.562m

-465.583m -501.149m -127.373m

-575.715m -563.357m -240.395m

-687.103m -625.847m -363.667m

-912.311m -751.475m -621.897m

-1.026 -814.544m -753.859m

-1.140 -877.750m -886.904m

-1.254 -941.073m

-1.021

-1.155

-1.290

-1.368

-1.483

-1.004

-1.068

DSP56364 Technical Data, Rev. 4.1

A-26

Freescale Semiconductor

5.70V

5.80V

5.90V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-1.598

-1.713

-1.828

-2.059

-2.174

-2.290

-2.406

-2.521

-2.637

-1.132

-1.195

-1.259

-1.387

-1.451

-1.514

-1.578

-1.642

-1.706

-1.425

-1.561

-1.697

-1.969

-2.105

-2.242

-2.378

-2.515

-2.652

|

[Ramp]

|Voltage

|

I(typ)

I(min)

I(max)

dV/dt_f

|

dV/dt_r

1.99/110.010p 1.81/184.463p 2.17/69.974p

2.04/120.172p 1.85/212.126p 2.21/73.179p

R_load=10000ohms

| R_load was connected to ground for Ramp_up test and power for Ramp_dn test

|

|End model

[Model]

ipadd_io

I/O

| ""

Model_type

Vinl = 0.8

Vinh = 2

| variable

C_comp

typ

2.34p

typ

min

2.21p

min

max

2.52p

max

120.0

| variable

[Temperature Range] 40.0

0.0

| variable

[Voltage Range]

|

typ

3.30V

min

3.00V

max

3.60V

[Pulldown]

| pulldown in the table = pulldown subtract gnd_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-157.134u -99.256u -219.000u

-165.037u -104.127u -230.250u

-173.749u -109.479u -242.685u

-183.400u -115.386u -256.500u

-194.148u -121.936u -271.934u

-206.189u -129.240u -289.286u

-219.766u -137.431u -308.933u

-235.190u -146.680u -331.355u

-252.856u -157.199u -357.176u

-273.283u -169.265u -387.219u

-297.162u -183.236u -422.595u

-325.427u -199.590u -464.837u

-359.384u -218.976u -516.117u

-400.901u -242.299u -579.623u

-452.750u -270.851u -660.217u

-519.217u -306.549u -765.681u

-607.277u -352.346u -909.270u

-729.045u -413.024u

-907.407u -496.811u

-1.191m -619.011u

-1.115m

-1.434m

-1.987m

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-27

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

-1.699m -811.079u

-3.133m

-6.243m

-2.799m

-5.689m

-10.416m

-12.342m

-11.672m

-10.528m

-9.204m

-7.770m

-6.286m

-4.766m

-3.214m

-1.146m

-1.822m -12.974m

-3.302m -17.948m

-5.449m -17.964m

-6.479m -16.692m

-6.146m -15.152m

-5.387m -13.338m

-4.535m -11.313m

-3.652m

-2.754m

-1.846m

-9.190m

-6.999m

-4.740m

-2.410m

-1.607f

2.391m

4.661m

6.817m

8.858m

10.784m

12.593m

14.284m

15.855m

17.306m

18.639m

19.856m

20.957m

21.944m

22.817m

23.575m

-1.627m -928.990u

32.871e-18 18.540e-18

1.604m 910.814u

3.124m

4.566m

5.928m

7.210m

8.411m

1.775m

2.595m

3.372m

4.105m

4.792m

5.432m

6.023m

6.563m

7.051m

7.486m

7.865m

8.189m

64.562m

66.208m

67.513m 184.138m

68.498m 187.874m

69.206m 190.647m

69.710m 192.621m

70.083m 194.017m

70.374m 195.034m

70.612m 195.815m

70.814m 196.447m

70.992m 196.983m

71.151m 197.453m

71.296m 197.876m

71.428m 198.263m

71.551m 198.622m

71.666m 198.958m

71.774m 199.275m

71.876m 199.576m

71.973m 199.863m

72.066m 200.138m

72.156m 200.405m

72.245m 200.667m

72.335m 200.928m

72.428m 201.194m

72.527m 201.472m

72.638m 201.774m

72.764m 202.113m

72.914m 202.503m

9.529m

10.562m

11.508m

12.367m

13.138m

13.821m

14.417m

14.930m

117.094m

119.708m

121.667m

123.055m

124.020m

124.711m

125.232m

125.650m

126.000m

126.305m

126.577m

126.823m

127.050m

127.260m

127.457m

127.643m

127.818m

127.986m

128.147m

128.304m

128.458m

128.614m

128.776m

128.948m

129.140m

129.361m

129.621m

DSP56364 Technical Data, Rev. 4.1

A-28

Freescale Semiconductor

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

129.934m

130.316m

130.784m

131.358m

132.060m

132.912m

133.939m

135.166m

136.619m

138.324m

140.308m

142.597m

145.217m

148.192m

151.545m

155.300m

159.478m

164.097m

169.177m

174.734m

73.093m 202.966m

73.311m 203.524m

73.579m 204.203m

73.906m 205.033m

74.304m 206.045m

74.787m 207.276m

75.368m 208.763m

76.060m 210.544m

76.878m 212.659m

77.836m 215.149m

78.948m 218.056m

80.230m 221.419m

81.694m 225.277m

83.355m 229.669m

85.224m 234.630m

87.316m 240.194m

89.640m 246.393m

92.208m 253.255m

95.029m 260.806m

98.112m 269.070m

180.781m 101.465m 278.065m

187.333m 105.096m 287.810m

194.400m 109.009m 298.319m

201.993m 113.211m 309.602m

210.118m 117.705m 321.670m

|

[Pullup]

| pullup in the table = pullup subtract power_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

132.979u 100.794u 170.075u

138.984u 105.115u 178.000u

145.559u 109.825u 186.702u

152.789u 114.981u 196.300u

160.778u 120.648u 206.941u

169.651u 126.906u 218.803u

179.562u 133.852u 232.110u

190.706u 141.605u 247.141u

203.326u 150.317u 264.253u

217.736u 160.174u 283.910u

234.344u 171.418u 306.723u

253.692u 184.362u 333.513u

276.513u 199.421u 365.415u

303.830u 217.155u 404.033u

337.102u 238.340u 451.722u

378.494u 264.081u 512.067u

431.351u 296.004u 590.810u

501.113u 336.601u 697.730u

597.240u 389.880u 850.877u

737.641u 462.700u

960.395u 567.748u

1.361m 731.012u

1.087m

1.497m

2.348m

4.712m

10.148m

12.062m

2.237m

4.644m

8.090m

1.013m

1.583m

2.907m

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-29

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

-0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

8.032m

7.118m

6.128m

5.109m

4.082m

3.056m

2.033m

4.727m

4.754m

4.128m

3.441m

2.746m

2.053m

1.363m

11.029m

9.778m

8.443m

7.052m

5.644m

4.233m

2.821m

1.410m

1.014m 678.856u

58.687e-18 58.622e-18 117.504e-18

-987.106u -655.604u

-1.381m

-2.709m

-3.988m

-5.216m

-6.392m

-7.516m

-8.587m

-9.602m

-1.928m

-2.828m

-3.685m

-4.499m

-5.269m

-5.994m

-6.673m

-7.306m

-7.890m

-8.424m

-8.907m

-1.274m

-1.859m

-2.412m

-2.931m

-3.416m

-3.866m

-4.280m

-4.658m -10.561m

-4.999m -11.461m

-5.301m -12.302m

-5.563m -13.081m

-9.339m -65.539m -13.798m

-110.103m -67.611m -154.438m

-113.807m -69.311m -170.370m

-117.010m -70.713m -176.323m

-119.783m -71.893m -181.647m

-122.195m -72.910m -186.387m

-124.297m -73.804m -190.581m

-126.131m -74.599m -194.261m

-127.733m -75.311m -197.468m

-129.139m -75.954m -200.255m

-130.384m -76.540m -202.683m

-131.498m -77.077m -204.814m

-132.504m -77.575m -206.704m

-133.423m -78.037m -208.399m

-134.270m -78.470m -209.937m

-135.057m -78.877m -211.346m

-135.792m -79.261m -212.650m

-136.483m -79.625m -213.864m

-137.136m -79.971m -215.004m

-137.756m -80.302m -216.079m

-138.345m -80.617m -217.098m

-138.908m -80.920m -218.067m

-139.447m -81.210m -218.993m

-139.964m -81.490m -219.880m

-140.462m -81.761m -220.732m

-140.943m -82.022m -221.552m

-141.408m -82.277m -222.344m

-141.860m -82.525m -223.112m

-142.300m -82.769m -223.858m

-142.733m -83.010m -224.586m

-143.159m -83.250m -225.300m

-143.585m -83.493m -226.006m

-144.013m -83.740m -226.709m

-144.449m -83.996m -227.417m

DSP56364 Technical Data, Rev. 4.1

A-30

Freescale Semiconductor

4.70V

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-144.899m -84.265m -228.137m

-145.370m -84.551m -228.879m

-145.871m -84.861m -229.656m

-146.411m -85.200m -230.481m

-147.001m -85.575m -231.368m

-147.652m -85.993m -232.336m

-148.379m -86.464m -233.404m

-149.195m -86.995m -234.592m

-150.115m -87.597m -235.924m

-151.157m -88.280m -237.426m

-152.339m -89.054m -239.124m

-153.678m -89.930m -241.046m

-155.194m -90.921m -243.223m

-156.907m -92.038m -245.685m

-158.839m -93.294m -248.465m

-161.011m -94.701m -251.595m

-163.444m -96.273m -255.109m

-166.160m -98.023m -259.041m

-169.182m -99.963m -263.425m

-172.531m -102.106m -268.293m

|

[GND_clamp]

|

|Voltage

|

I(typ)

-2.637

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

-1.514

-1.451

-1.387

-1.259

-1.195

-1.132

-1.068

-1.004

-3.063

-2.926

-2.789

-2.515

-2.378

-2.242

-2.105

-1.969

-1.833

-1.697

-1.561

-1.425

-1.155

-1.021

-2.521

-2.406

-2.174

-2.059

-1.943

-1.828

-1.713

-1.598 -941.073m

-1.483 -877.750m

-1.368 -814.544m

-1.254 -751.475m

-1.026 -625.847m

-912.311m -563.357m

-799.377m -501.149m -886.904m

-687.103m -439.297m -753.859m

-575.715m -377.904m -621.897m

-465.583m -317.129m -491.519m

-357.354m -257.221m -363.667m

-252.314m -198.614m -240.395m

-153.494m -142.138m -127.373m

-19.457m -45.305m -11.215m

-3.535m -16.226m

-877.640u -3.288m

-156.838u -397.909u -271.662u

-14.514u -53.601u -18.044u

-780.351n

-37.668n -598.098n -15.437n

-1.699n -55.739n -411.332p

-4.650m

-1.613m

-6.086u -560.308n

-92.071p

-5.410n -29.683p

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-31

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.10V

3.20V

3.30V

-27.709p

-1.212n -18.939p

-22.802p -890.771p -16.163p

-19.598p -810.054p -13.516p

-16.468p -745.765p -10.874p

-13.353p -683.799p

-10.247p -622.802p

-7.147p -562.404p

-8.234p

-5.595p

-2.956p

-4.050p -502.414p -318.962f

-955.896f -442.712p

2.136p -383.217p

8.315p -264.634p

11.404p -205.467p

14.492p -146.346p

17.579p -87.245p

20.666p -28.141p

2.318p

4.954p

10.227p

12.862p

15.498p

18.133p

20.768p

23.404p

26.039p

28.674p

31.310p

36.581p

39.216p

41.852p

44.489p

47.125p

49.762p

52.401p

55.040p

57.675p

61.928p

63.585p

65.236p

23.754p

26.841p

30.987p

90.164p

29.929p 149.414p

33.018p 208.769p

39.198p 327.949p

42.291p 387.873p

45.385p 448.012p

48.483p 507.296p

51.583p 563.856p

54.673p 619.785p

57.468p 676.156p

59.647p 733.868p

61.717p 807.258p

65.859p

68.003p

72.601p 620.266n

5.906n

59.801n

|

[POWER_clamp]

|

|Voltage

|

I(typ)

I(min)

I(max)

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.10V

5.20V

5.30V

-27.709p -598.098n -10.874p

-92.071p -6.086u -13.516p

-1.699n -53.601u -16.163p

-37.668n -397.909u -18.939p

-780.351n

-3.288m -29.683p

-14.514u -16.226m -411.332p

-156.838u -45.305m -15.437n

-3.535m -142.138m -18.044u

-19.457m -198.614m -271.662u

-69.631m -257.221m

-153.494m -317.129m

-1.613m

-4.650m

-252.314m -377.904m -11.215m

-357.354m -439.297m -43.562m

-465.583m -501.149m -127.373m

-575.715m -563.357m -240.395m

-687.103m -625.847m -363.667m

-912.311m -751.475m -621.897m

-1.026 -814.544m -753.859m

-1.140 -877.750m -886.904m

DSP56364 Technical Data, Rev. 4.1

A-32

Freescale Semiconductor

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-1.254 -941.073m

-1.021

-1.155

-1.290

-1.425

-1.561

-1.697

-1.969

-2.105

-2.242

-2.378

-2.515

-2.652

-1.368

-1.483

-1.598

-1.713

-1.828

-2.059

-2.174

-2.290

-2.406

-2.521

-2.637

-1.004

-1.068

-1.132

-1.195

-1.259

-1.387

-1.451

-1.514

-1.578

-1.642

-1.706

|

[Ramp]

|Voltage

|

I(typ)

I(min)

I(max)

dV/dt_f

|

dV/dt_r

1.99/104.603p 1.81/183.924p 2.18/69.643p

2.04/123.810p 1.85/215.062p 2.20/73.602p

R_load=10000ohms

| R_load was connected to ground for Ramp_up test and power for Ramp_dn test

|

|End model

[Model]

ipadex_i

Input

| ""

Model_type

Vinl = 0.8

Vinh = 2

| variable

C_comp

typ

2.92p

typ

min

2.78p

min

max

2.96p

max

120.0

| variable

[Temperature Range] 40.0

0.0

| variable

typ

min

max

[Voltage Range]

3.30V

3.00V

3.60V

|

[GND_clamp]

|

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-831.819m -473.616m -909.150m

-796.528m -454.528m -869.534m

-761.255m -435.451m -829.938m

-690.773m -397.335m -750.811m

-655.569m -378.299m -711.286m

-620.391m -359.279m -671.789m

-585.244m -340.277m -632.324m

-550.131m -321.295m -592.895m

-515.057m -302.336m -553.507m

-480.027m -283.402m -514.167m

-445.047m -264.496m -474.880m

-410.126m -245.624m -435.657m

-340.501m -207.998m -357.451m

-305.826m -189.259m -318.503m

-271.273m -170.582m -279.692m

-236.871m -151.981m -241.057m

-202.665m -133.474m -202.657m

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-33

-1.40V

-1.30V

-1.20V

-1.10V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.10V

3.20V

3.30V

-168.722m -115.088m -164.583m

-135.151m -96.861m -126.991m

-102.140m -78.852m -90.181m

-70.064m -61.160m -54.834m

-14.097m -27.650m

-1.307m -13.160m -53.501u

-36.639u -3.159m -768.589n

-2.799m

-903.944n -256.975u -10.997n

-22.242n -13.934u -172.415p

-567.014p -730.372n -16.888p

-32.976p -38.990n -13.767p

-18.575p

-2.810n -12.822p

-16.945p -867.431p -11.909p

-15.630p -713.428p -10.996p

-14.322p -652.886p -10.084p

-13.014p -597.227p

-11.707p -541.823p

-10.399p -486.432p

-9.092p -431.043p

-7.784p -375.653p

-6.477p -320.263p

-5.169p -264.873p

-3.862p -209.483p

-9.171p

-8.258p

-7.345p

-6.432p

-5.520p

-4.607p

-3.694p

-2.781p

-1.246p -98.704p -955.508f

61.165f -43.314p -42.711f

1.369p

2.676p

12.076p 870.085f

67.466p

1.783p

2.696p

3.609p

4.521p

5.434p

6.347p

8.173p

9.085p

9.998p

10.911p

11.824p

12.736p

13.649p

14.562p

15.475p

17.301p

18.213p

19.126p

3.984p 122.856p

5.291p 178.246p

6.599p 233.635p

7.906p 289.025p

9.214p 344.415p

11.829p 455.195p

13.137p 510.585p

14.444p 565.974p

15.752p 621.364p

17.059p 676.754p

18.367p 732.144p

19.674p 787.535p

20.982p 842.946p

22.290p 898.735p

24.905p

26.212p

27.520p

1.163n

4.019n

57.671n

|

[POWER_clamp]

|

|Voltage

|

I(typ)

I(min)

I(max)

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

-15.630p -38.990n

-16.945p -730.372n

-18.575p -13.934u -10.084p

-32.976p -256.975u -10.996p

-8.258p

-9.171p

-567.014p

-3.159m -11.909p

-22.242n -13.160m -12.822p

DSP56364 Technical Data, Rev. 4.1

A-34

Freescale Semiconductor

3.90V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-903.944n -27.650m -13.767p

-1.307m -61.160m -172.415p

-14.097m -78.852m -10.997n

-39.803m -96.861m -768.589n

-70.064m -115.088m -53.501u

-102.140m -133.474m

-2.799m

-135.151m -151.981m -22.990m

-168.722m -170.582m -54.834m

-202.665m -189.259m -90.181m

-236.871m -207.998m -126.991m

-305.826m -245.624m -202.657m

-340.501m -264.496m -241.057m

-375.273m -283.402m -279.692m

-410.126m -302.336m -318.503m

-445.047m -321.295m -357.451m

-480.027m -340.277m -396.509m

-515.057m -359.279m -435.657m

-550.131m -378.299m -474.880m

-585.244m -397.335m -514.167m

-655.569m -435.451m -592.895m

-690.773m -454.528m -632.324m

-726.003m -473.616m -671.789m

-761.255m -492.715m -711.286m

-796.528m -511.823m -750.811m

-831.819m -530.941m -790.363m

|

|End model

[Model]

Model_type

| variable

C_comp

ipadm_3st

3-state

typ

1.99p

typ

| ""

min

1.86p

min

max

2.15p

max

120.0

| variable

[Temperature Range] 40.0

0.0

| variable

[Voltage Range]

|

typ

3.30V

min

3.00V

max

3.60V

[Pulldown]

| pulldown in the table = pulldown subtract gnd_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-157.134u -99.256u -219.000u

-165.037u -104.127u -230.250u

-173.749u -109.479u -242.685u

-183.400u -115.386u -256.500u

-194.148u -121.936u -271.934u

-206.189u -129.240u -289.286u

-219.766u -137.431u -308.933u

-235.190u -146.680u -331.355u

-252.856u -157.199u -357.176u

-273.283u -169.265u -387.219u

-297.162u -183.236u -422.595u

-325.427u -199.590u -464.837u

-359.384u -218.976u -516.117u

-400.901u -242.299u -579.623u

-452.750u -270.851u -660.217u

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-35

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

-519.217u -306.549u -765.681u

-607.277u -352.346u -909.270u

-729.045u -413.024u

-907.407u -496.811u

-1.191m -619.011u

-1.699m -811.079u

-1.115m

-1.434m

-1.987m

-3.133m

-6.243m

-2.799m

-5.689m

-10.416m

-12.342m

-11.672m

-10.528m

-9.204m

-7.770m

-6.286m

-4.766m

-3.214m

-1.146m

-1.822m -12.974m

-3.302m -17.948m

-5.449m -17.964m

-6.479m -16.692m

-6.146m -15.152m

-5.387m -13.338m

-4.535m -11.313m

-3.652m

-2.754m

-1.846m

-9.190m

-6.999m

-4.740m

-2.410m

-1.607f

2.391m

-1.627m -928.990u

32.755e-18 18.548e-18

1.604m 910.814u

3.124m

4.566m

5.928m

7.210m

8.411m

1.775m

2.595m

3.372m

4.105m

4.792m

5.432m

6.023m

6.563m

7.051m

7.486m

7.865m

8.189m

47.725m

48.943m

49.908m 136.139m

50.637m 138.902m

51.160m 140.954m

51.534m 142.415m

51.810m 143.449m

52.024m 144.201m

52.201m 144.779m

52.351m 145.246m

52.482m 145.642m

52.600m 145.990m

52.706m 146.303m

52.804m 146.590m

52.895m 146.855m

52.980m 147.104m

53.060m 147.338m

53.135m 147.560m

53.207m 147.772m

53.276m 147.976m

53.343m 148.174m

53.408m 148.367m

53.475m 148.560m

4.661m

6.817m

8.858m

10.784m

12.593m

14.284m

15.855m

17.306m

18.639m

19.856m

20.957m

21.944m

22.817m

23.575m

9.529m

10.562m

11.508m

12.367m

13.138m

13.821m

14.417m

14.930m

86.564m

88.497m

89.946m

90.974m

91.689m

92.200m

92.586m

92.895m

93.154m

93.380m

93.581m

93.764m

93.931m

94.087m

94.233m

94.370m

94.500m

94.624m

94.744m

94.859m

94.974m

95.089m

DSP56364 Technical Data, Rev. 4.1

A-36

Freescale Semiconductor

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

95.208m

95.336m

95.478m

95.641m

95.833m

96.065m

96.347m

96.693m

97.117m

97.636m

98.266m

99.024m

99.931m

101.005m

102.264m

103.730m

105.422m

107.357m

109.556m

112.034m

114.809m

117.897m

121.311m

125.066m

129.172m

133.642m

138.485m

143.709m

149.320m

155.326m

53.543m 148.757m

53.617m 148.963m

53.699m 149.186m

53.792m 149.436m

53.902m 149.725m

54.035m 150.067m

54.196m 150.479m

54.394m 150.981m

54.635m 151.594m

54.930m 152.342m

55.287m 153.252m

55.716m 154.350m

56.227m 155.666m

56.831m 157.230m

57.539m 159.070m

58.361m 161.218m

59.308m 163.704m

60.391m 166.555m

61.618m 169.801m

63.000m 173.468m

64.545m 177.581m

66.263m 182.163m

68.160m 187.235m

70.245m 192.816m

72.524m 198.924m

75.002m 205.573m

77.685m 212.776m

80.578m 220.544m

83.683m 228.885m

87.004m 237.805m

|

[Pullup]

| pullup in the table = pullup subtract power_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

132.979u 100.794u 170.075u

138.984u 105.115u 178.000u

145.559u 109.825u 186.702u

152.789u 114.981u 196.300u

160.778u 120.648u 206.941u

169.651u 126.906u 218.803u

179.562u 133.852u 232.110u

190.706u 141.605u 247.141u

203.326u 150.317u 264.253u

217.736u 160.174u 283.910u

234.344u 171.418u 306.723u

253.692u 184.362u 333.513u

276.513u 199.421u 365.415u

303.830u 217.155u 404.033u

337.102u 238.340u 451.722u

378.494u 264.081u 512.067u

431.351u 296.004u 590.810u

501.113u 336.601u 697.730u

597.240u 389.880u 850.877u

737.641u 462.700u

1.087m

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-37

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

-0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

960.396u 567.748u

1.361m 731.012u

1.497m

2.348m

4.712m

10.148m

12.062m

11.029m

9.778m

8.443m

7.052m

5.644m

4.233m

2.821m

1.410m

2.237m

4.644m

8.090m

8.032m

7.118m

6.128m

5.109m

4.082m

3.056m

2.033m

1.013m

1.583m

2.907m

4.727m

4.754m

4.128m

3.441m

2.746m

2.053m

1.363m

1.014m 678.856u

58.687e-18 58.622e-18 117.504e-18

-987.106u -655.604u

-1.381m

-2.709m

-3.988m

-5.216m

-6.392m

-7.516m

-8.587m

-9.602m

-1.928m

-2.828m

-3.685m

-4.499m

-5.269m

-5.994m

-6.673m

-7.306m

-7.890m

-8.424m

-8.907m

-1.274m

-1.859m

-2.412m

-2.931m

-3.416m

-3.866m

-4.280m

-4.658m -10.561m

-4.999m -11.461m

-5.301m -12.302m

-5.563m -13.081m

-9.339m -47.451m -13.837m

-79.705m -48.954m -118.519m

-82.391m -50.187m -123.324m

-84.713m -51.203m -127.640m

-86.724m -52.057m -131.501m

-88.472m -52.794m -134.939m

-89.996m -53.442m -137.982m

-91.327m -54.017m -140.655m

-92.489m -54.533m -142.987m

-93.511m -54.999m -145.014m

-94.415m -55.424m -146.781m

-95.224m -55.814m -148.333m

-95.955m -56.174m -149.709m

-96.623m -56.510m -150.943m

-97.238m -56.824m -152.063m

-97.809m -57.119m -153.088m

-98.343m -57.398m -154.036m

-98.846m -57.662m -154.920m

-99.320m -57.913m -155.749m

-99.770m -58.152m -156.531m

-100.198m -58.381m -157.272m

-100.607m -58.601m -157.977m

-100.998m -58.812m -158.650m

-101.374m -59.015m -159.295m

-101.735m -59.211m -159.914m

-102.084m -59.401m -160.510m

-102.422m -59.585m -161.086m

-102.750m -59.766m -161.644m

-103.070m -59.942m -162.186m

DSP56364 Technical Data, Rev. 4.1

A-38

Freescale Semiconductor

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-103.384m -60.117m -162.715m

-103.694m -60.291m -163.234m

-104.002m -60.467m -163.747m

-104.313m -60.647m -164.257m

-104.629m -60.832m -164.770m

-104.955m -61.027m -165.293m

-105.296m -61.234m -165.831m

-105.659m -61.459m -166.394m

-106.050m -61.704m -166.991m

-106.477m -61.975m -167.634m

-106.949m -62.278m -168.334m

-107.474m -62.619m -169.106m

-108.064m -63.003m -169.965m

-108.730m -63.439m -170.928m

-109.483m -63.932m -172.012m

-110.337m -64.492m -173.239m

-111.305m -65.126m -174.627m

-112.401m -65.843m -176.199m

-113.640m -66.651m -177.978m

-115.036m -67.560m -179.986m

-116.606m -68.578m -182.247m

-118.365m -69.715m -184.785m

-120.329m -70.981m -187.626m

-122.513m -72.384m -190.793m

-124.935m -73.935m -194.311m

|

[GND_clamp]

|

|Voltage

|

I(typ)

-2.165

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-0.90V

-0.80V

-0.70V

-0.60V

-1.242

-1.190

-1.138

-1.033

-2.500

-2.388

-2.277

-2.054

-1.942

-1.831

-1.720

-1.609

-1.498

-1.387

-1.276

-1.166

-2.070

-1.975

-1.786

-1.691 -981.185m

-1.597 -929.174m

-1.503 -877.220m

-1.408 -825.330m

-1.314 -773.514m

-1.220 -721.779m

-1.126 -670.140m

-1.032 -618.610m

-845.771m -515.958m -945.908m

-752.887m -464.892m -836.403m

-660.410m -414.052m -727.373m

-568.461m -363.494m -618.970m

-477.221m -313.301m -511.430m

-386.980m -263.597m -405.149m

-298.248m -214.579m -300.867m

-212.028m -166.582m -200.187m

-130.668m -120.248m -107.496m

-17.375m -40.029m

-2.837m -14.886m

-656.331u

-8.803m

-3.451m

-1.195m

-3.014m

-116.521u -336.317u -201.636u

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-39

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.10V

3.20V

3.30V

-10.789u -41.964u -13.420u

-580.051n -4.632u -416.799n

-27.994n -450.005n -11.484n

-1.269n -41.862n -311.158p

-74.463p

-26.215p

-4.218n -27.092p

-1.078n -18.737p

-22.114p -826.325p -16.303p

-19.278p -754.146p -13.966p

-16.497p -694.188p -11.632p

-13.726p -635.953p

-10.963p -578.437p

-8.203p -521.365p

-5.446p -464.595p

-2.691p -408.039p

62.079f -351.636p

5.566p -239.133p

8.316p -182.975p

11.067p -126.851p

13.817p -70.743p

16.567p -14.634p

-9.300p

-6.968p

-4.637p

-2.307p

22.980f

2.353p

7.011p

9.340p

11.669p

13.998p

16.327p

18.656p

20.985p

23.313p

25.642p

30.300p

32.629p

34.958p

37.288p

39.618p

41.948p

44.279p

46.611p

48.939p

52.772p

54.319p

55.861p

19.317p

22.067p

41.493p

97.654p

24.817p 153.868p

27.568p 210.159p

33.072p 323.083p

35.825p 379.789p

38.581p 436.650p

41.339p 492.867p

44.098p 547.026p

46.849p 600.695p

49.356p 654.682p

51.378p 709.650p

53.315p 776.122p

57.193p

59.183p

4.552n

44.522n

62.959p 466.732n

|

[POWER_clamp]

|

|Voltage

|

I(typ)

I(min)

I(max)

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

-26.215p -450.005n -11.632p

-74.463p -4.632u -13.966p

-1.269n -41.964u -16.303p

-27.994n -336.317u -18.737p

-580.051n

-3.014m -27.092p

-10.789u -14.886m -311.158p

-116.521u -40.029m -11.484n

-2.837m -120.248m -13.420u

-17.375m -166.582m -201.636u

-60.888m -214.579m

-130.668m -263.597m

-212.028m -313.301m

-1.195m

-3.451m

-8.803m

-298.248m -363.494m -37.420m

-386.980m -414.052m -107.496m

DSP56364 Technical Data, Rev. 4.1

A-40

Freescale Semiconductor

4.80V

4.90V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-477.221m -464.892m -200.187m

-568.461m -515.958m -300.867m

-752.887m -618.610m -511.430m

-845.771m -670.140m -618.970m

-938.979m -721.779m -727.373m

-1.032 -773.514m -836.403m

-1.126 -825.330m -945.908m

-1.220 -877.220m

-1.314 -929.174m

-1.408 -981.185m

-1.056

-1.166

-1.276

-1.387

-1.609

-1.720

-1.831

-1.942

-2.054

-2.165

-1.503

-1.691

-1.786

-1.881

-1.975

-2.070

-2.165

-1.033

-1.138

-1.190

-1.242

-1.294

-1.346

-1.399

|

[Ramp]

|Voltage

|

I(typ)

I(min)

I(max)

dV/dt_f

|

dV/dt_r

1.99/116.478p 1.81/206.384p 2.17/80.687p

2.02/147.722p 1.84/253.853p 2.19/93.030p

R_load=10000ohms

| R_load was connected to ground for Ramp_up test and power for Ramp_dn test

|

|End model

[Model]

ipadn_io

I/O

| ""

Model_type

Vinl = 0.8

Vinh = 2

| variable

C_comp

typ

2.03p

typ

min

1.90p

min

max

2.18p

max

120.0

| variable

[Temperature Range] 40.0

0.0

| variable

[Voltage Range]

|

typ

3.30V

min

3.00V

max

3.60V

[Pulldown]

| pulldown in the table = pulldown subtract gnd_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-157.134u -99.256u -219.000u

-165.037u -104.127u -230.250u

-173.749u -109.479u -242.685u

-183.400u -115.386u -256.500u

-194.148u -121.936u -271.934u

-206.189u -129.240u -289.286u

-219.766u -137.431u -308.933u

-235.190u -146.680u -331.355u

-252.856u -157.199u -357.176u

-273.283u -169.265u -387.219u

-297.162u -183.236u -422.595u

-325.427u -199.590u -464.837u

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-41

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

-359.384u -218.976u -516.117u

-400.901u -242.299u -579.623u

-452.750u -270.851u -660.217u

-519.217u -306.549u -765.681u

-607.277u -352.346u -909.270u

-729.045u -413.024u

-907.407u -496.811u

-1.191m -619.011u

-1.699m -811.079u

-1.115m

-1.434m

-1.987m

-3.133m

-6.243m

-2.799m

-5.689m

-10.416m

-12.342m

-11.672m

-10.528m

-9.204m

-7.770m

-6.286m

-4.766m

-3.214m

-1.146m

-1.822m -12.974m

-3.302m -17.948m

-5.449m -17.964m

-6.479m -16.692m

-6.146m -15.152m

-5.387m -13.338m

-4.535m -11.313m

-3.652m

-2.754m

-1.846m

-9.190m

-6.999m

-4.740m

-2.410m

-1.607f

2.391m

-1.627m -928.990u

32.755e-18 18.548e-18

1.604m 910.814u

3.124m

4.566m

5.928m

7.210m

8.411m

1.775m

2.595m

3.372m

4.105m

4.792m

5.432m

6.023m

6.563m

7.051m

7.486m

7.865m

8.189m

47.725m

48.943m

49.908m 136.139m

50.637m 138.902m

51.160m 140.954m

51.534m 142.415m

51.810m 143.449m

52.024m 144.201m

52.201m 144.779m

52.351m 145.246m

52.482m 145.642m

52.600m 145.990m

52.706m 146.303m

52.804m 146.590m

52.895m 146.855m

52.980m 147.104m

53.060m 147.338m

53.135m 147.560m

53.207m 147.772m

53.276m 147.976m

4.661m

6.817m

8.858m

10.784m

12.593m

14.284m

15.855m

17.306m

18.639m

19.856m

20.957m

21.944m

22.817m

23.575m

9.529m

10.562m

11.508m

12.367m

13.138m

13.821m

14.417m

14.930m

86.564m

88.497m

89.946m

90.974m

91.689m

92.200m

92.586m

92.895m

93.154m

93.380m

93.581m

93.764m

93.931m

94.087m

94.233m

94.370m

94.500m

94.624m

94.744m

DSP56364 Technical Data, Rev. 4.1

A-42

Freescale Semiconductor

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

94.859m

94.974m

95.089m

95.208m

95.336m

95.478m

95.641m

95.833m

96.065m

96.347m

96.693m

97.117m

97.636m

98.266m

99.024m

99.931m

101.005m

102.264m

103.730m

105.422m

107.357m

109.556m

112.034m

114.809m

117.897m

121.311m

125.066m

129.172m

133.642m

138.485m

143.709m

149.320m

155.326m

53.343m 148.174m

53.408m 148.367m

53.475m 148.560m

53.543m 148.757m

53.617m 148.963m

53.699m 149.186m

53.792m 149.436m

53.902m 149.725m

54.035m 150.067m

54.196m 150.479m

54.394m 150.981m

54.635m 151.594m

54.930m 152.342m

55.287m 153.252m

55.716m 154.350m

56.227m 155.666m

56.831m 157.230m

57.539m 159.070m

58.361m 161.218m

59.308m 163.704m

60.391m 166.555m

61.618m 169.801m

63.000m 173.468m

64.545m 177.581m

66.263m 182.163m

68.160m 187.235m

70.245m 192.816m

72.524m 198.924m

75.002m 205.573m

77.685m 212.776m

80.578m 220.544m

83.683m 228.885m

87.004m 237.805m

|

[Pullup]

| pullup in the table = pullup subtract power_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

132.979u 100.794u 170.075u

138.984u 105.115u 178.000u

145.559u 109.825u 186.702u

152.789u 114.981u 196.300u

160.778u 120.648u 206.941u

169.651u 126.906u 218.803u

179.562u 133.852u 232.110u

190.706u 141.605u 247.141u

203.326u 150.317u 264.253u

217.736u 160.174u 283.910u

234.344u 171.418u 306.723u

253.692u 184.362u 333.513u

276.513u 199.421u 365.415u

303.830u 217.155u 404.033u

337.102u 238.340u 451.722u

378.494u 264.081u 512.067u

431.351u 296.004u 590.810u

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-43

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

-0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

501.113u 336.601u 697.730u

597.240u 389.880u 850.877u

737.641u 462.700u

960.396u 567.748u

1.361m 731.012u

1.087m

1.497m

2.348m

4.712m

10.148m

12.062m

11.029m

9.778m

8.443m

7.052m

5.644m

4.233m

2.821m

1.410m

2.237m

4.644m

8.090m

8.032m

7.118m

6.128m

5.109m

4.082m

3.056m

2.033m

1.013m

1.583m

2.907m

4.727m

4.754m

4.128m

3.441m

2.746m

2.053m

1.363m

1.014m 678.856u

58.687e-18 58.622e-18 117.504e-18

-987.106u -655.604u

-1.381m

-2.709m

-3.988m

-5.216m

-6.392m

-7.516m

-8.587m

-9.602m

-1.928m

-2.828m

-3.685m

-4.499m

-5.269m

-5.994m

-6.673m

-7.306m

-7.890m

-8.424m

-8.907m

-1.274m

-1.859m

-2.412m

-2.931m

-3.416m

-3.866m

-4.280m

-4.658m -10.561m

-4.999m -11.461m

-5.301m -12.302m

-5.563m -13.081m

-9.339m -47.451m -13.901m

-79.705m -48.954m -118.519m

-82.391m -50.187m -123.324m

-84.713m -51.203m -127.640m

-86.724m -52.057m -131.501m

-88.472m -52.794m -134.939m

-89.996m -53.442m -137.982m

-91.327m -54.017m -140.655m

-92.489m -54.533m -142.987m

-93.511m -54.999m -145.014m

-94.415m -55.424m -146.781m

-95.224m -55.814m -148.333m

-95.955m -56.174m -149.709m

-96.623m -56.510m -150.943m

-97.238m -56.824m -152.063m

-97.809m -57.119m -153.088m

-98.343m -57.398m -154.036m

-98.846m -57.662m -154.920m

-99.320m -57.913m -155.749m

-99.770m -58.152m -156.531m

-100.198m -58.381m -157.272m

-100.607m -58.601m -157.977m

-100.998m -58.812m -158.650m

-101.374m -59.015m -159.295m

-101.735m -59.211m -159.914m

-102.084m -59.401m -160.510m

DSP56364 Technical Data, Rev. 4.1

A-44

Freescale Semiconductor

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-102.422m -59.585m -161.086m

-102.750m -59.766m -161.644m

-103.070m -59.942m -162.186m

-103.384m -60.117m -162.715m

-103.694m -60.291m -163.234m

-104.002m -60.467m -163.747m

-104.313m -60.647m -164.257m

-104.629m -60.832m -164.770m

-104.955m -61.027m -165.293m

-105.296m -61.234m -165.831m

-105.659m -61.459m -166.394m

-106.050m -61.704m -166.991m

-106.477m -61.975m -167.634m

-106.949m -62.278m -168.334m

-107.474m -62.619m -169.106m

-108.064m -63.003m -169.965m

-108.730m -63.439m -170.928m

-109.483m -63.932m -172.012m

-110.337m -64.492m -173.239m

-111.305m -65.126m -174.627m

-112.401m -65.843m -176.199m

-113.640m -66.651m -177.978m

-115.036m -67.560m -179.986m

-116.606m -68.578m -182.247m

-118.365m -69.715m -184.785m

-120.329m -70.981m -187.626m

-122.513m -72.384m -190.793m

-124.935m -73.935m -194.311m

|

[GND_clamp]

|

|Voltage

|

I(typ)

-2.165

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-0.90V

-1.242

-1.190

-1.138

-1.033

-2.500

-2.388

-2.277

-2.054

-1.942

-1.831

-1.720

-1.609

-1.498

-1.387

-1.276

-1.166

-2.070

-1.975

-1.786

-1.691 -981.185m

-1.597 -929.174m

-1.503 -877.220m

-1.408 -825.330m

-1.314 -773.514m

-1.220 -721.779m

-1.126 -670.140m

-1.032 -618.610m

-845.771m -515.958m -945.908m

-752.887m -464.892m -836.403m

-660.410m -414.052m -727.373m

-568.461m -363.494m -618.970m

-477.221m -313.301m -511.430m

-386.980m -263.597m -405.149m

-298.248m -214.579m -300.867m

-212.028m -166.582m -200.187m

-130.668m -120.248m -107.496m

-17.375m -40.029m

-8.803m

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-45

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.10V

3.20V

3.30V

-2.837m -14.886m

-656.331u -3.014m

-116.521u -336.317u -201.636u

-10.789u -41.964u -13.420u

-3.451m

-1.195m

-580.051n

-4.632u -416.799n

-27.994n -450.005n -11.484n

-1.269n -41.862n -311.158p

-74.463p

-26.215p

-4.218n -27.092p

-1.078n -18.737p

-22.114p -826.325p -16.303p

-19.278p -754.146p -13.966p

-16.497p -694.188p -11.632p

-13.726p -635.953p

-10.963p -578.437p

-8.203p -521.365p

-5.446p -464.595p

-2.691p -408.039p

62.079f -351.636p

5.566p -239.133p

8.316p -182.975p

11.067p -126.851p

13.817p -70.743p

16.567p -14.634p

-9.300p

-6.968p

-4.637p

-2.307p

22.980f

2.353p

7.011p

9.340p

11.669p

13.998p

16.327p

18.656p

20.985p

23.313p

25.642p

30.300p

32.629p

34.958p

37.288p

39.618p

41.948p

44.279p

46.611p

48.939p

52.772p

54.319p

55.861p

19.317p

22.067p

41.493p

97.654p

24.817p 153.868p

27.568p 210.159p

33.072p 323.083p

35.825p 379.789p

38.581p 436.650p

41.339p 492.867p

44.098p 547.026p

46.849p 600.695p

49.356p 654.682p

51.378p 709.650p

53.315p 776.122p

57.193p

59.183p

4.552n

44.522n

62.959p 466.732n

|

[POWER_clamp]

|

|Voltage

|

I(typ)

I(min)

I(max)

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.10V

4.20V

4.30V

4.40V

-26.215p -450.005n -11.632p

-74.463p -4.632u -13.966p

-1.269n -41.964u -16.303p

-27.994n -336.317u -18.737p

-580.051n

-3.014m -27.092p

-10.789u -14.886m -311.158p

-116.521u -40.029m -11.484n

-2.837m -120.248m -13.420u

-17.375m -166.582m -201.636u

-60.888m -214.579m

-130.668m -263.597m

-1.195m

-3.451m

DSP56364 Technical Data, Rev. 4.1

A-46

Freescale Semiconductor

4.50V

4.60V

4.70V

4.80V

4.90V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-212.028m -313.301m

-8.803m

-298.248m -363.494m -37.420m

-386.980m -414.052m -107.496m

-477.221m -464.892m -200.187m

-568.461m -515.958m -300.867m

-752.887m -618.610m -511.430m

-845.771m -670.140m -618.970m

-938.979m -721.779m -727.373m

-1.032 -773.514m -836.403m

-1.126 -825.330m -945.908m

-1.220 -877.220m

-1.314 -929.174m

-1.408 -981.185m

-1.056

-1.166

-1.276

-1.387

-1.609

-1.720

-1.831

-1.942

-2.054

-2.165

-1.503

-1.691

-1.786

-1.881

-1.975

-2.070

-2.165

-1.033

-1.138

-1.190

-1.242

-1.294

-1.346

-1.399

|

[Ramp]

|Voltage

|

I(typ)

I(min)

I(max)

dV/dt_f

|

dV/dt_r

2.00/112.556p 1.82/199.937p 2.17/74.356p

2.02/146.245p 1.84/252.851p 2.20/93.872p

R_load=10000ohms

| R_load was connected to ground for Ramp_up test and power for Ramp_dn test

|

|End model

[Model]

ipadni_io

I/O

| ""

Model_type

Vinl = 0.8

Vinh = 2

| variable

C_comp

typ

2.01p

typ

min

1.89p

min

max

2.17p

max

120.0

| variable

[Temperature Range] 40.0

0.0

| variable

[Voltage Range]

|

typ

3.30V

min

3.00V

max

3.60V

[Pulldown]

| pulldown in the table = pulldown subtract gnd_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-157.134u -99.256u -219.000u

-165.037u -104.127u -230.250u

-173.749u -109.479u -242.685u

-183.400u -115.386u -256.500u

-194.148u -121.936u -271.934u

-206.189u -129.240u -289.286u

-219.766u -137.431u -308.933u

-235.190u -146.680u -331.355u

-252.856u -157.199u -357.176u

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-47

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

-273.283u -169.265u -387.219u

-297.162u -183.236u -422.595u

-325.427u -199.590u -464.837u

-359.384u -218.976u -516.117u

-400.901u -242.299u -579.623u

-452.750u -270.851u -660.217u

-519.217u -306.549u -765.681u

-607.277u -352.346u -909.270u

-729.045u -413.024u

-907.407u -496.811u

-1.191m -619.011u

-1.699m -811.079u

-1.115m

-1.434m

-1.987m

-3.133m

-6.243m

-2.799m

-5.689m

-10.416m

-12.342m

-11.672m

-10.528m

-9.204m

-7.770m

-6.286m

-4.766m

-3.214m

-1.146m

-1.822m -12.974m

-3.302m -17.948m

-5.449m -17.964m

-6.479m -16.692m

-6.146m -15.152m

-5.387m -13.338m

-4.535m -11.313m

-3.652m

-2.754m

-1.846m

-9.190m

-6.999m

-4.740m

-2.410m

-1.607f

2.391m

-1.627m -928.990u

32.755e-18 18.548e-18

1.604m 910.814u

3.124m

4.566m

5.928m

7.210m

8.411m

1.775m

2.595m

3.372m

4.105m

4.792m

5.432m

6.023m

6.563m

7.051m

7.486m

7.865m

8.189m

47.725m

48.943m

49.908m 136.139m

50.637m 138.902m

51.160m 140.954m

51.534m 142.415m

51.810m 143.449m

52.024m 144.201m

52.201m 144.779m

52.351m 145.246m

52.482m 145.642m

52.600m 145.990m

52.706m 146.303m

52.804m 146.590m

52.895m 146.855m

52.980m 147.104m

53.060m 147.338m

4.661m

6.817m

8.858m

10.784m

12.593m

14.284m

15.855m

17.306m

18.639m

19.856m

20.957m

21.944m

22.817m

23.575m

9.529m

10.562m

11.508m

12.367m

13.138m

13.821m

14.417m

14.930m

86.564m

88.497m

89.946m

90.974m

91.689m

92.200m

92.586m

92.895m

93.154m

93.380m

93.581m

93.764m

93.931m

94.087m

94.233m

94.370m

DSP56364 Technical Data, Rev. 4.1

A-48

Freescale Semiconductor

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

94.500m

94.624m

94.744m

94.859m

94.974m

95.089m

95.208m

95.336m

95.478m

95.641m

95.833m

96.065m

96.347m

96.693m

97.117m

97.636m

98.266m

99.024m

99.931m

101.005m

102.264m

103.730m

105.422m

107.357m

109.556m

112.034m

114.809m

117.897m

121.311m

125.066m

129.172m

133.642m

138.485m

143.709m

149.320m

155.326m

53.135m 147.560m

53.207m 147.772m

53.276m 147.976m

53.343m 148.174m

53.408m 148.367m

53.475m 148.560m

53.543m 148.757m

53.617m 148.963m

53.699m 149.186m

53.792m 149.436m

53.902m 149.725m

54.035m 150.067m

54.196m 150.479m

54.394m 150.981m

54.635m 151.594m

54.930m 152.342m

55.287m 153.252m

55.716m 154.350m

56.227m 155.666m

56.831m 157.230m

57.539m 159.070m

58.361m 161.218m

59.308m 163.704m

60.391m 166.555m

61.618m 169.801m

63.000m 173.468m

64.545m 177.581m

66.263m 182.163m

68.160m 187.235m

70.245m 192.816m

72.524m 198.924m

75.002m 205.573m

77.685m 212.776m

80.578m 220.544m

83.683m 228.885m

87.004m 237.805m

|

[Pullup]

| pullup in the table = pullup subtract power_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

132.979u 100.794u 170.075u

138.984u 105.115u 178.000u

145.559u 109.825u 186.702u

152.789u 114.981u 196.300u

160.778u 120.648u 206.941u

169.651u 126.906u 218.803u

179.562u 133.852u 232.110u

190.706u 141.605u 247.141u

203.326u 150.317u 264.253u

217.736u 160.174u 283.910u

234.344u 171.418u 306.723u

253.692u 184.362u 333.513u

276.513u 199.421u 365.415u

303.830u 217.155u 404.033u

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-49

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

-0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

337.102u 238.340u 451.722u

378.494u 264.081u 512.067u

431.351u 296.004u 590.810u

501.113u 336.601u 697.730u

597.240u 389.880u 850.877u

737.641u 462.700u

960.396u 567.748u

1.361m 731.012u

1.087m

1.497m

2.348m

4.712m

10.148m

12.062m

11.029m

9.778m

8.443m

7.052m

5.644m

4.233m

2.821m

1.410m

2.237m

4.644m

8.090m

8.032m

7.118m

6.128m

5.109m

4.082m

3.056m

2.033m

1.013m

1.583m

2.907m

4.727m

4.754m

4.128m

3.441m

2.746m

2.053m

1.363m

1.014m 678.856u

58.687e-18 58.622e-18 117.504e-18

-987.106u -655.604u

-1.381m

-2.709m

-3.988m

-5.216m

-6.392m

-7.516m

-8.587m

-9.602m

-1.928m

-2.828m

-3.685m

-4.499m

-5.269m

-5.994m

-6.673m

-7.306m

-7.890m

-8.424m

-8.907m

-1.274m

-1.859m

-2.412m

-2.931m

-3.416m

-3.866m

-4.280m

-4.658m -10.561m

-4.999m -11.461m

-5.301m -12.302m

-5.563m -13.081m

-9.339m -47.451m -13.901m

-79.705m -48.954m -118.519m

-82.391m -50.187m -123.324m

-84.713m -51.203m -127.640m

-86.724m -52.057m -131.501m

-88.472m -52.794m -134.939m

-89.996m -53.442m -137.982m

-91.327m -54.017m -140.655m

-92.489m -54.533m -142.987m

-93.511m -54.999m -145.014m

-94.415m -55.424m -146.781m

-95.224m -55.814m -148.333m

-95.955m -56.174m -149.709m

-96.623m -56.510m -150.943m

-97.238m -56.824m -152.063m

-97.809m -57.119m -153.088m

-98.343m -57.398m -154.036m

-98.846m -57.662m -154.920m

-99.320m -57.913m -155.749m

-99.770m -58.152m -156.531m

-100.198m -58.381m -157.272m

-100.607m -58.601m -157.977m

-100.998m -58.812m -158.650m

DSP56364 Technical Data, Rev. 4.1

A-50

Freescale Semiconductor

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-101.374m -59.015m -159.295m

-101.735m -59.211m -159.914m

-102.084m -59.401m -160.510m

-102.422m -59.585m -161.086m

-102.750m -59.766m -161.644m

-103.070m -59.942m -162.186m

-103.384m -60.117m -162.715m

-103.694m -60.291m -163.234m

-104.002m -60.467m -163.747m

-104.313m -60.647m -164.257m

-104.629m -60.832m -164.770m

-104.955m -61.027m -165.293m

-105.296m -61.234m -165.831m

-105.659m -61.459m -166.394m

-106.050m -61.704m -166.991m

-106.477m -61.975m -167.634m

-106.949m -62.278m -168.334m

-107.474m -62.619m -169.106m

-108.064m -63.003m -169.965m

-108.730m -63.439m -170.928m

-109.483m -63.932m -172.012m

-110.337m -64.492m -173.239m

-111.305m -65.126m -174.627m

-112.401m -65.843m -176.199m

-113.640m -66.651m -177.978m

-115.036m -67.560m -179.986m

-116.606m -68.578m -182.247m

-118.365m -69.715m -184.785m

-120.329m -70.981m -187.626m

-122.513m -72.384m -190.793m

-124.935m -73.935m -194.311m

|

[GND_clamp]

|

|Voltage

|

I(typ)

-2.165

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.242

-1.190

-1.138

-1.033

-2.500

-2.388

-2.277

-2.054

-1.942

-1.831

-1.720

-1.609

-1.498

-1.387

-1.276

-1.166

-2.070

-1.975

-1.786

-1.691 -981.185m

-1.597 -929.174m

-1.503 -877.220m

-1.408 -825.330m

-1.314 -773.514m

-1.220 -721.779m

-1.126 -670.140m

-1.032 -618.610m

-845.771m -515.958m -945.908m

-752.887m -464.892m -836.403m

-660.410m -414.052m -727.373m

-568.461m -363.494m -618.970m

-477.221m -313.301m -511.430m

-386.980m -263.597m -405.149m

-298.248m -214.579m -300.867m

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-51

-1.20V

-1.10V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.10V

3.20V

3.30V

-212.028m -166.582m -200.187m

-130.668m -120.248m -107.496m

-17.375m -40.029m

-2.837m -14.886m

-8.803m

-3.451m

-1.195m

-656.331u

-3.014m

-116.521u -336.317u -201.636u

-10.789u -41.964u -13.420u

-580.051n

-4.632u -416.799n

-27.994n -450.005n -11.484n

-1.269n -41.862n -311.158p

-74.463p

-26.215p

-4.218n -27.092p

-1.078n -18.737p

-22.114p -826.325p -16.303p

-19.278p -754.146p -13.966p

-16.497p -694.188p -11.632p

-13.726p -635.953p

-10.963p -578.437p

-8.203p -521.365p

-5.446p -464.595p

-2.691p -408.039p

62.079f -351.636p

5.566p -239.133p

8.316p -182.975p

11.067p -126.851p

13.817p -70.743p

16.567p -14.634p

-9.300p

-6.968p

-4.637p

-2.307p

22.980f

2.353p

7.011p

9.340p

11.669p

13.998p

16.327p

18.656p

20.985p

23.313p

25.642p

30.300p

32.629p

34.958p

37.288p

39.618p

41.948p

44.279p

46.611p

48.939p

52.772p

54.319p

55.861p

19.317p

22.067p

41.493p

97.654p

24.817p 153.868p

27.568p 210.159p

33.072p 323.083p

35.825p 379.789p

38.581p 436.650p

41.339p 492.867p

44.098p 547.026p

46.849p 600.695p

49.356p 654.682p

51.378p 709.650p

53.315p 776.122p

57.193p

59.183p

4.552n

44.522n

62.959p 466.732n

|

[POWER_clamp]

|

|Voltage

|

I(typ)

I(min)

I(max)

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.10V

-26.215p -450.005n -11.632p

-74.463p -4.632u -13.966p

-1.269n -41.964u -16.303p

-27.994n -336.317u -18.737p

-580.051n

-3.014m -27.092p

-10.789u -14.886m -311.158p

-116.521u -40.029m -11.484n

-2.837m -120.248m -13.420u

DSP56364 Technical Data, Rev. 4.1

A-52

Freescale Semiconductor

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-17.375m -166.582m -201.636u

-60.888m -214.579m

-130.668m -263.597m

-212.028m -313.301m

-1.195m

-3.451m

-8.803m

-298.248m -363.494m -37.420m

-386.980m -414.052m -107.496m

-477.221m -464.892m -200.187m

-568.461m -515.958m -300.867m

-752.887m -618.610m -511.430m

-845.771m -670.140m -618.970m

-938.979m -721.779m -727.373m

-1.032 -773.514m -836.403m

-1.126 -825.330m -945.908m

-1.220 -877.220m

-1.314 -929.174m

-1.408 -981.185m

-1.056

-1.166

-1.276

-1.387

-1.609

-1.720

-1.831

-1.942

-2.054

-2.165

-1.503

-1.691

-1.786

-1.881

-1.975

-2.070

-2.165

-1.033

-1.138

-1.190

-1.242

-1.294

-1.346

-1.399

|

[Ramp]

|Voltage

|

I(typ)

I(min)

I(max)

dV/dt_f

|

dV/dt_r

2.00/113.266p 1.82/197.371p 2.17/74.028p

2.02/147.014p 1.84/251.849p 2.20/93.411p

R_load=10000ohms

| R_load was connected to ground for Ramp_up test and power for Ramp_dn test

|

|End model

[Model]

ipado_3st

3-state

typ

1.99p

typ

| ""

Model_type

| variable

C_comp

| variable

[Temperature Range] 40.0

min

1.86p

min

max

2.15p

max

120.0

0.0

| variable

[Voltage Range]

|

typ

3.30V

min

3.00V

max

3.60V

[Pulldown]

| pulldown in the table = pulldown subtract gnd_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-157.134u -99.256u -219.000u

-165.037u -104.127u -230.250u

-173.749u -109.479u -242.685u

-183.400u -115.386u -256.500u

-194.148u -121.936u -271.934u

-206.189u -129.240u -289.286u

-219.766u -137.431u -308.933u

-235.190u -146.680u -331.355u

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-53

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

-252.856u -157.199u -357.176u

-273.283u -169.265u -387.219u

-297.162u -183.236u -422.595u

-325.427u -199.590u -464.837u

-359.384u -218.976u -516.117u

-400.901u -242.299u -579.623u

-452.750u -270.851u -660.217u

-519.217u -306.549u -765.681u

-607.277u -352.346u -909.270u

-729.045u -413.024u

-907.407u -496.811u

-1.191m -619.011u

-1.699m -811.079u

-1.115m

-1.434m

-1.987m

-3.133m

-6.243m

-2.799m

-5.689m

-10.416m

-12.342m

-11.672m

-10.528m

-9.204m

-7.770m

-6.286m

-4.766m

-3.214m

-1.146m

-1.822m -12.974m

-3.302m -17.948m

-5.449m -17.964m

-6.479m -16.692m

-6.146m -15.152m

-5.387m -13.338m

-4.535m -11.313m

-3.652m

-2.754m

-1.846m

-9.190m

-6.999m

-4.740m

-2.410m

-1.607f

2.391m

-1.627m -928.990u

32.755e-18 18.548e-18

1.604m 910.814u

3.124m

4.566m

5.928m

7.210m

8.411m

1.775m

2.595m

3.372m

4.105m

4.792m

5.432m

6.023m

6.563m

7.051m

7.486m

7.865m

8.189m

47.725m

48.943m

49.908m 136.139m

50.637m 138.902m

51.160m 140.954m

51.534m 142.415m

51.810m 143.449m

52.024m 144.201m

52.201m 144.779m

52.351m 145.246m

52.482m 145.642m

52.600m 145.990m

52.706m 146.303m

52.804m 146.590m

52.895m 146.855m

52.980m 147.104m

4.661m

6.817m

8.858m

10.784m

12.593m

14.284m

15.855m

17.306m

18.639m

19.856m

20.957m

21.944m

22.817m

23.575m

9.529m

10.562m

11.508m

12.367m

13.138m

13.821m

14.417m

14.930m

86.564m

88.497m

89.946m

90.974m

91.689m

92.200m

92.586m

92.895m

93.154m

93.380m

93.581m

93.764m

93.931m

94.087m

94.233m

DSP56364 Technical Data, Rev. 4.1

A-54

Freescale Semiconductor

3.00V

3.10V

3.20V

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

94.370m

94.500m

94.624m

94.744m

94.859m

94.974m

95.089m

95.208m

95.336m

95.478m

95.641m

95.833m

96.065m

96.347m

96.693m

97.117m

97.636m

98.266m

99.024m

99.931m

101.005m

102.264m

103.730m

105.422m

107.357m

109.556m

112.034m

114.809m

117.897m

121.311m

125.066m

129.172m

133.642m

138.485m

143.709m

149.320m

155.326m

53.060m 147.338m

53.135m 147.560m

53.207m 147.772m

53.276m 147.976m

53.343m 148.174m

53.408m 148.367m

53.475m 148.560m

53.543m 148.757m

53.617m 148.963m

53.699m 149.186m

53.792m 149.436m

53.902m 149.725m

54.035m 150.067m

54.196m 150.479m

54.394m 150.981m

54.635m 151.594m

54.930m 152.342m

55.287m 153.252m

55.716m 154.350m

56.227m 155.666m

56.831m 157.230m

57.539m 159.070m

58.361m 161.218m

59.308m 163.704m

60.391m 166.555m

61.618m 169.801m

63.000m 173.468m

64.545m 177.581m

66.263m 182.163m

68.160m 187.235m

70.245m 192.816m

72.524m 198.924m

75.002m 205.573m

77.685m 212.776m

80.578m 220.544m

83.683m 228.885m

87.004m 237.805m

|

[Pullup]

| pullup in the table = pullup subtract power_clamp

|Voltage

|

I(typ)

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-3.00V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

132.979u 100.794u 170.075u

138.984u 105.115u 178.000u

145.559u 109.825u 186.702u

152.789u 114.981u 196.300u

160.778u 120.648u 206.941u

169.651u 126.906u 218.803u

179.562u 133.852u 232.110u

190.706u 141.605u 247.141u

203.326u 150.317u 264.253u

217.736u 160.174u 283.910u

234.344u 171.418u 306.723u

253.692u 184.362u 333.513u

276.513u 199.421u 365.415u

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-55

-2.00V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.30V

-1.20V

-1.10V

-1.00V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

-0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.00V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.00V

3.10V

3.20V

3.30V

3.40V

303.830u 217.155u 404.033u

337.102u 238.340u 451.722u

378.494u 264.081u 512.067u

431.351u 296.004u 590.810u

501.113u 336.601u 697.730u

597.240u 389.880u 850.877u

737.641u 462.700u

960.396u 567.748u

1.361m 731.012u

1.087m

1.497m

2.348m

4.712m

10.148m

12.062m

11.029m

9.778m

8.443m

7.052m

5.644m

4.233m

2.821m

1.410m

2.237m

4.644m

8.090m

8.032m

7.118m

6.128m

5.109m

4.082m

3.056m

2.033m

1.013m

1.583m

2.907m

4.727m

4.754m

4.128m

3.441m

2.746m

2.053m

1.363m

1.014m 678.856u

58.687e-18 58.622e-18 117.504e-18

-987.106u -655.604u

-1.381m

-2.709m

-3.988m

-5.216m

-6.392m

-7.516m

-8.587m

-9.602m

-1.928m

-2.828m

-3.685m

-4.499m

-5.269m

-5.994m

-6.673m

-7.306m

-7.890m

-8.424m

-8.907m

-1.274m

-1.859m

-2.412m

-2.931m

-3.416m

-3.866m

-4.280m

-4.658m -10.561m

-4.999m -11.461m

-5.301m -12.302m

-5.563m -13.081m

-9.339m -47.451m -13.837m

-79.705m -48.954m -118.519m

-82.391m -50.187m -123.324m

-84.713m -51.203m -127.640m

-86.724m -52.057m -131.501m

-88.472m -52.794m -134.939m

-89.996m -53.442m -137.982m

-91.327m -54.017m -140.655m

-92.489m -54.533m -142.987m

-93.511m -54.999m -145.014m

-94.415m -55.424m -146.781m

-95.224m -55.814m -148.333m

-95.955m -56.174m -149.709m

-96.623m -56.510m -150.943m

-97.238m -56.824m -152.063m

-97.809m -57.119m -153.088m

-98.343m -57.398m -154.036m

-98.846m -57.662m -154.920m

-99.320m -57.913m -155.749m

-99.770m -58.152m -156.531m

-100.198m -58.381m -157.272m

-100.607m -58.601m -157.977m

DSP56364 Technical Data, Rev. 4.1

A-56

Freescale Semiconductor

3.50V

3.60V

3.70V

3.80V

3.90V

4.00V

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.00V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.00V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-100.998m -58.812m -158.650m

-101.374m -59.015m -159.295m

-101.735m -59.211m -159.914m

-102.084m -59.401m -160.510m

-102.422m -59.585m -161.086m

-102.750m -59.766m -161.644m

-103.070m -59.942m -162.186m

-103.384m -60.117m -162.715m

-103.694m -60.291m -163.234m

-104.002m -60.467m -163.747m

-104.313m -60.647m -164.257m

-104.629m -60.832m -164.770m

-104.955m -61.027m -165.293m

-105.296m -61.234m -165.831m

-105.659m -61.459m -166.394m

-106.050m -61.704m -166.991m

-106.477m -61.975m -167.634m

-106.949m -62.278m -168.334m

-107.474m -62.619m -169.106m

-108.064m -63.003m -169.965m

-108.730m -63.439m -170.928m

-109.483m -63.932m -172.012m

-110.337m -64.492m -173.239m

-111.305m -65.126m -174.627m

-112.401m -65.843m -176.199m

-113.640m -66.651m -177.978m

-115.036m -67.560m -179.986m

-116.606m -68.578m -182.247m

-118.365m -69.715m -184.785m

-120.329m -70.981m -187.626m

-122.513m -72.384m -190.793m

-124.935m -73.935m -194.311m

|

[GND_clamp]

|

|Voltage

|

I(typ)

-2.165

I(min)

I(max)

-3.30V

-3.20V

-3.10V

-2.90V

-2.80V

-2.70V

-2.60V

-2.50V

-2.40V

-2.30V

-2.20V

-2.10V

-1.90V

-1.80V

-1.70V

-1.60V

-1.50V

-1.40V

-1.242

-1.190

-1.138

-1.033

-2.500

-2.388

-2.277

-2.054

-1.942

-1.831

-1.720

-1.609

-1.498

-1.387

-1.276

-1.166

-2.070

-1.975

-1.786

-1.691 -981.185m

-1.597 -929.174m

-1.503 -877.220m

-1.408 -825.330m

-1.314 -773.514m

-1.220 -721.779m

-1.126 -670.140m

-1.032 -618.610m

-845.771m -515.958m -945.908m

-752.887m -464.892m -836.403m

-660.410m -414.052m -727.373m

-568.461m -363.494m -618.970m

-477.221m -313.301m -511.430m

-386.980m -263.597m -405.149m

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-57

-1.30V

-1.20V

-1.10V

-0.90V

-0.80V

-0.70V

-0.60V

-0.50V

-0.40V

-0.30V

-0.20V

-0.10V

0.00V

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

0.90V

1.10V

1.20V

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.10V

2.20V

2.30V

2.40V

2.50V

2.60V

2.70V

2.80V

2.90V

3.10V

3.20V

3.30V

-298.248m -214.579m -300.867m

-212.028m -166.582m -200.187m

-130.668m -120.248m -107.496m

-17.375m -40.029m

-2.837m -14.886m

-8.803m

-3.451m

-1.195m

-656.331u

-3.014m

-116.521u -336.317u -201.636u

-10.789u -41.964u -13.420u

-580.051n

-4.632u -416.799n

-27.994n -450.005n -11.484n

-1.269n -41.862n -311.158p

-74.463p

-26.215p

-4.218n -27.092p

-1.078n -18.737p

-22.114p -826.325p -16.303p

-19.278p -754.146p -13.966p

-16.497p -694.188p -11.632p

-13.726p -635.953p

-10.963p -578.437p

-8.203p -521.365p

-5.446p -464.595p

-2.691p -408.039p

62.079f -351.636p

5.566p -239.133p

8.316p -182.975p

11.067p -126.851p

13.817p -70.743p

16.567p -14.634p

-9.300p

-6.968p

-4.637p

-2.307p

22.980f

2.353p

7.011p

9.340p

11.669p

13.998p

16.327p

18.656p

20.985p

23.313p

25.642p

30.300p

32.629p

34.958p

37.288p

39.618p

41.948p

44.279p

46.611p

48.939p

52.772p

54.319p

55.861p

19.317p

22.067p

41.493p

97.654p

24.817p 153.868p

27.568p 210.159p

33.072p 323.083p

35.825p 379.789p

38.581p 436.650p

41.339p 492.867p

44.098p 547.026p

46.849p 600.695p

49.356p 654.682p

51.378p 709.650p

53.315p 776.122p

57.193p

59.183p

4.552n

44.522n

62.959p 466.732n

|

[POWER_clamp]

|

|Voltage

|

I(typ)

I(min)

I(max)

3.30V

3.40V

3.50V

3.60V

3.70V

3.80V

3.90V

-26.215p -450.005n -11.632p

-74.463p -4.632u -13.966p

-1.269n -41.964u -16.303p

-27.994n -336.317u -18.737p

-580.051n

-3.014m -27.092p

-10.789u -14.886m -311.158p

-116.521u -40.029m -11.484n

DSP56364 Technical Data, Rev. 4.1

A-58

Freescale Semiconductor

4.10V

4.20V

4.30V

4.40V

4.50V

4.60V

4.70V

4.80V

4.90V

5.10V

5.20V

5.30V

5.40V

5.50V

5.60V

5.70V

5.80V

5.90V

6.10V

6.20V

6.30V

6.40V

6.50V

6.60V

-2.837m -120.248m -13.420u

-17.375m -166.582m -201.636u

-60.888m -214.579m

-130.668m -263.597m

-212.028m -313.301m

-1.195m

-3.451m

-8.803m

-298.248m -363.494m -37.420m

-386.980m -414.052m -107.496m

-477.221m -464.892m -200.187m

-568.461m -515.958m -300.867m

-752.887m -618.610m -511.430m

-845.771m -670.140m -618.970m

-938.979m -721.779m -727.373m

-1.032 -773.514m -836.403m

-1.126 -825.330m -945.908m

-1.220 -877.220m

-1.314 -929.174m

-1.408 -981.185m

-1.056

-1.166

-1.276

-1.387

-1.609

-1.720

-1.831

-1.942

-2.054

-2.165

-1.503

-1.691

-1.786

-1.881

-1.975

-2.070

-2.165

-1.033

-1.138

-1.190

-1.242

-1.294

-1.346

-1.399

|

[Ramp]

|Voltage

|

I(typ)

I(min)

I(max)

dV/dt_f

|

dV/dt_r

1.99/130.331p 1.81/220.000p 2.17/83.712p

2.03/153.657p 1.84/260.814p 2.20/92.663p

R_load=10000ohms

| R_load was connected to ground for Ramp_up test and power for Ramp_dn test

|

|End model

[End]

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

A-59

NOTES

DSP56364 Technical Data, Rev. 4.1

A-60

Freescale Semiconductor

Index

out of page and refresh timings

11 wait states 31

15 wait states 33

4 wait states 27

A

ac electrical characteristics 4

8 wait states 29

Page mode

read accesses 26

wait states selection guide 17

write accesses 25

Page mode timings

1 wait state 17

B

Boundary Scan (JTAG Port) timing diagram 54

bus

2 wait states 20

external address 4

external data 4

3 wait states 22

4 wait states 23

refresh access 37

C

E

Clock 4

clock

electrical design considerations 3

emory 3

Enhanced Serial Audio Interface 9

ESAI 9

external 4

operation 6

clocks

internal 4

configuration 3

receiver timing 51, 52

timings 47

transmitter timing 50

EXTAL jitter 4

external address bus 4

D

external bus control 4, 5

external clock operation 4

external data bus 4

external interrupt timing (negative edge-triggered)

11

external level-sensitive fast interrupt timing 10

external memory access (DMA Source) timing 12

External Memory Expansion Port 4, 12

dc electrical characteristics 3

design considerations

electrical 3

PLL 4

power consumption 3

thermal 1

DRAM

out of page

wait states selection guide 27

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

Index-1

F

O

functional signal groups 1

OnCE module 12

operating mode select timing 11

G

P

GPIO timing 52

Ground 3

package

PLL 3

TQFP description 1, 3

Peripheral modules 3

Phase Lock Loop 6

PLL 4, 6

I

Characteristics 6

performance issues 4

PLL design considerations 4

PLL performance issues 4

Port A 4

Port C 9

Power 2

internal clocks 4

interrupt and mode control 6

interrupt control 6

interrupt timing 7

external level-sensitive fast 10

external negative edge-triggered 11

power consumption design considerations 3

R

J

recovery from Stop state using IRQA 11, 12

RESET 6

Reset timing 7, 10

Jitter 4

JTAG 12

JTAG Port

timing 53, 54

S

M

Serial Audio Interface (ESAI) 3

Serial Host Interface 7

Serial Host Interface (SHI) 3

SHI 7

signal groupings 1

signals 1

maximum ratings 1, 2

Memory 3

Memory Configuration 3

mode control 6

Mode select timing 7

SRAM

DSP56364 Technical Data, Rev. 4.1

Index-2

Freescale Semiconductor

read and write accesses 12

Stop state

recovery from 11, 12

Stop timing 7

supply voltage 2

T

Test Access Port timing diagram 55

Test Clock (TCLK) input timing diagram 54

thermal characteristics 2

thermal design considerations 1

Timing

Enhanced Serial Audio Interface (ESAI) 50

General Purpose I/O (GPIO) Timing 47

OnCE™ (On Chip Emulator) Timing 47

Serial Host Interface (SHI) SPI Protocol Tim-

ing 37

Serial Host Interface (SHI) Timing 37

timing

interrupt 7

mode select 7

Reset 7

Stop 7

TQFP

pin list by number 3

pin-out drawing (top) 1

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

Index-3

How to Reach Us:

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Freescale Semiconductor products. There are no express or implied copyright licenses granted

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Document Number: DSP56364

Rev. 4.1

10/2007


型号：	DSP56364UM
厂家：	Freescale
描述：	24-Bit Audio Digital Signal Processor 24位音频数字信号处理器数字信号处理器
文件：	总148页 (文件大小：1798K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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