DSP56364 [MOTOROLA]
24-Bit Audio Digital Signal Processor; 24位音频数字信号处理器![DSP56364](http://pdffile.icpdf.com/pdf1/p00076/img/icpdf/DSP56364_401538_icpdf.jpg)
型号: | DSP56364 |
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描述: | 24-Bit Audio Digital Signal Processor |
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Freescale Semiconductor, Inc.
Advance Information
DSP56364/D
Rev. 3.2, 08/2003
24-Bit Audio Digital
Signal Processor
Topic
Page
Overview
Overview .....................................i
Features .................................... ii
The DSP56364 supports digital audio applications requiring sound field processing,
acoustic equalization, and other digital audio algorithms. The DSP56364 uses the
high performance, single-clock-per-cycle DSP56300 core family of programmable
CMOS digital signal processors (DSPs) combined with the audio signal processing
capability of the Motorola Symphony™ DSP family, as shown in Figure 1. This
design provides a two-fold performance increase over Motorola’s popular
Symphony family of DSPs while retaining code compatibility. Significant
architectural enhancements include a barrel shifter, 24-bit addressing, instruction
cache, and direct memory access (DMA). The DSP56364 offers 100 million
instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V.
Signal/Connection
Descriptions .......................1-1
Specifications ..........................2-1
Packaging ...............................3-1
Design Considerations ...........4-1
Ordering Information ...............5-1
IBIS Model ............................. A-1
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted”
Used to indicate a signal that is active when pulled low (For
example, the RESET pin is active when low.)
Means that a high true (active high) signal is high or that a low
true (active low) signal is low
“deasserted” Means that a high true (active high) signal is low or that a low
true (active low) signal is high
Examples:
Signal/
Logic State
Signal State
Voltage*
Symbol
PIN
PIN
PIN
PIN
True
False
True
Asserted
Deasserted
Asserted
VIL / VOL
VIH / VOH
VIH / VOH
VIL / VOL
False
Deasserted
Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product
specifications.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
IMOTOROLA
DSP56364 Advance Information
1
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Overview
Features
4
12
5
PROGRAMRAM
0.5Kx24
X
Y
MEMORY
RAM
MEMORY
RAM
SHI
GPIO
ESAI
PROGRAM ROM
8Kx24
1KX24
1.5KX24
PERIPHERAL
EXPANSION
AREA
BootstrapROM
192x24
MEMORY
EXPANSION
AREA
ADDRESS
CONTROL
YAB
ADDRESS
EXTERNAL
ADDRESS BUS
SWITCH
GENERATION UNIT
XAB
PAB
DAB
18
6
SIX CHANNELS
DMA UNIT
24-BIT
DSP56300
CORE
DRAM &SRAM
BUS
INTERFACE
DDB
YDB
XDB
PDB
GDB
DATA
EXTERNAL
DATABUS
SWITCH
INTERNAL
DATA BUS
SWITCH
8
POWER
MGMT
DATA ALU
PLL
+
PROGRAM
INTERRUPT
CONT
PROGRAM
DECODE
CONT
PROGRAM
ADDRESS
GEN
24X24 56→56-BITMAC
TWO56-BIT
4
JTAG
ACCUMULATORS
BARRELSHIFTER
CLOCK
OnCE™
EXTAL
MODA/IRQA
MODB/IRQB
MODD/IRQD
24 BITS BUS
RESET
PINIT/NMI
Figure 1 DSP56364 Block Diagram
1
Features
1.1
Digital Signal Processing Core
•
100 Million Instructions Per Second (MIPS) with an 100 MHz clock at 3.3V.
Object Code Compatible with the 56000 core.
•
•
•
•
•
Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support.
Program Control with position independent code support and instruction cache support.
Six-channel DMA controller.
PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors (1
to 16) and power saving clock divider (2i: i=0 to 7). Reduces clock noise.
Internal address tracing support and OnCE for Hardware/Software debugging.
•
2
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Overview
Documentation
•
•
•
JTAG port.
Very low-power CMOS design, fully static design with operating frequencies down to DC.
STOP and WAIT low-power standby modes.
1.2
On-chip Memory Configuration
•
•
•
•
•
1.5Kx24 Bit Y-Data RAM.
1Kx24 Bit X-Data RAM.
8Kx24 Bit Program ROM.
0.5Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM.
0.75Kx24 Bit from Y Data RAM can be switched to Program RAM resulting in up to 1.25Kx24 Bit of
Program RAM.
1.3
Off-chip memory expansion
•
•
•
•
External Memory Expansion Port with 8-bit data bus.
Off-chip expansion up to 2 x 16M x 8-bit word of Data/Program memory when using DRAM.
Off-chip expansion up to 2 x 256k x 8-bit word of Data/Program memory when using SRAM.
Simultaneous glueless interface to SRAM and DRAM.
1.4
Peripheral modules
•
Enhanced Serial Audio Interface (ESAI): 6 serial lines, 4 selectable as receive or transmitt and 2
transmitt only, master or slave. I2S, Sony, AC97, network and other programmable protocols.
Unused pins of ESAI may be used as GPIO lines.
•
•
Serial Host Interface (SHI): SPI and I2C protocols, 10-word receive FIFO, support for 8, 16 and
24-bit words.
Four dedicated GPIO lines.
1.5
Packaging
•
100-pin plastic TQFP package.
2
Documentation
Table 1 lists the documents that provide a complete description of the DSP56364 and are required to
design properly with the part. Documentation is available from a local Motorola distributor, a Motorola
semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home
page on the Internet (the source for the latest information).
MOTOROLA
DSP56364 Advance Information
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Overview
Documentation
Table 1 DSP56364 Documentation
Description
Document Name
Order Number
DSP56300 Family Manual
Detailed description of the 56000-family
architecture and the 24-bit core processor
and instruction set
DSP56300FM/AD
DSP56364 User’s Manual
Detailed description of memory, peripher-
als, and interfaces
DSP56364UM/AD
DSP56364/D
DSP56364 Technical Data Sheet
Electrical and timing specifications; pin
and package descriptions
There is also a product brief for this chip.
Brief description of the chip
DSP56364 Product Brief
DSP56364P/D
4
DSP56364 Advance Information
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SECTION 1
SIGNAL/CONNECTION DESCRIPTIONS
1.1
SIGNAL GROUPINGS
The input and output signals of the DSP56364 are organized into functional groups, which are listed in
Table 1-1 and illustrated in Figure 1-1.
The DSP56364 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special
notice for this feature is added to the signal descriptions of those inputs.
Table 1-1 DSP56364 Functional Signal Groupings
Number of
Signals
Detailed
Description
Functional Group
Power (VCC
)
18
14
3
Table 1-2
Table 1-3
Table 1-4
Table 1-5
Table 1-6
Table 1-7
Table 1-8
Table 1-12
Table 1-9
Table 1-10
Table 1-11
Ground (GND)
Clock and PLL
Address bus
Data bus
18
8
Port A1
Bus control
6
Interrupt and mode control
General Purpose I/O
SHI
4
Port B2
Port C3
4
5
ESAI
12
4
JTAG/OnCE Port
Notes: 1. Port A is the external memory interface port, including the external address bus, data bus, and control
signals.
2. Port B signals are the GPIO signals.
3. Port C signals are the ESAI port signals multiplexed with the GPIO signals.
MOTOROLA
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Signal/Connection Descriptions
Signal Groupings
OnCE ON-CHIP EMULATION/
PORT A ADDRESS BUS
JTAG PORT
TDI
A0-A17
TCK
TDO
TMS
VCCA (4)
GNDA (4)
DSP56364
PORT A DATA BUS
D0-D7
VCCD (1)
Port B
GPIO
PB0-PB3
GNDD (1)
PORT A BUS CONTROL
AA0-AA1/RAS0-RAS1
CAS
RD
WR
TA
VCCC (1)
GNDC (1)
RESERVED (4)
SERIAL AUDIO INTERFACE (ESAI)
Port C
SCKT [PC3]
FST [PC4]
HCKT [PC5]
SCKR [PC0]
FSR [PC1]
INTERRUPT AND
MODE CONTROL
MODA/IRQA
HCKR [PC2]
SDO0 [PC11]
SDO1 [PC10]
MODB/IRQB
SDO2/SDI3 [PC9]
MODD/IRQD
SDO3/SDI2 [PC8]
SDO4/SDI1 [PC7]
SDO5/SDI0 [PC6]
VCCSS (3)
RESET
PLL AND CLOCK
GNDS (3)
PINIT/NMI
SERIAL HOST INTERFACE (SHI)
PCAP
VCCP
GNDP
MOSI/HA0
SS/HA2
MISO/SDA
SCK/SCL
HREQ
EXTAL
QUIET POWER
VCCHQ (4)
VCCLQ (4)
GNDQ (4)
Figure 1-1 Signals Identified by Functional Group
1-2
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Signal/Connection Descriptions
Power
1.2
POWER
Table 1-2 Power Inputs
Description
Power Name
VCCP
PLL Power—VCCP is VCC dedicated for PLL use. The voltage should be well-regulated
and the input should be provided with an extremely low impedance path to the VCC
power rail. There is one VCCP input.
VCCQL (4)
Quiet Core (Low) Power—VCCQL is an isolated power for the internal processing logic.
This input must be tied externally to all other chip power inputs. The user must provide
adequate external decoupling capacitors. There are four VCCQL inputs.
VCCQH (4)
Quiet External (High) Power—VCCQH is a quiet power source for I/O lines. This input
must be tied externally to all other chip power inputs. The user must provide adequate
decoupling capacitors. There are four VCCQH inputs.
VCCA (4)
Address Bus Power—VCCA is an isolated power for sections of the address bus
I/O drivers. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors. There are four VCCA inputs.
V
V
CCD (1)
Data Bus Power—VCCD is an isolated power for sections of the data bus I/O drivers.
This input must be tied externally to all other chip power inputs. The user must provide
adequate external decoupling capacitors. There is one VCCD inputs.
CCC (1)
Bus Control Power—VCCC is an isolated power for the bus control I/O drivers. This
input must be tied externally to all other chip power inputs. The user must provide ade-
quate external decoupling capacitors. There is one VCCC inputs.
VCCS (3)
SHI and ESAI —VCCS is an isolated power for the SHI and ESAI. This input must be
tied externally to all other chip power inputsL. The user must provide adequate external
decoupling capacitors. There are three VCCS inputs.
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1-3
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Signal/Connection Descriptions
Ground
1.3
GROUND
Table 1-3 Grounds
Description
Ground
Name
GNDP
PLL Ground—GNDP is ground-dedicated for PLL use. The connection should be pro-
vided with an extremely low-impedance path to ground. VCCP should be bypassed to
GNDP by a 0.47 µF capacitor located as close as possible to the chip package. There is
one GNDP connection.
GNDQ (4)
GNDA (4)
Quiet Ground—GNDQ is an isolated ground for the internal processing logic. This con-
nection must be tied externally to all other chip ground connections. The user must pro-
vide adequate external decoupling capacitors. There are four GNDQ connections.
Address Bus Ground—GNDA is an isolated ground for sections of the address bus
I/O drivers. This connection must be tied externally to all other chip ground connec-
tions. The user must provide adequate external decoupling capacitors. There are four
GNDA connections.
GNDD (1)
Data Bus Ground—GNDD is an isolated ground for sections of the data bus
I/O drivers. This connection must be tied externally to all other chip ground connec-
tions. The user must provide adequate external decoupling capacitors. There is one
GNDD connections.
GNDC (1)
GNDS (3)
Bus Control Ground—GNDC is an isolated ground for the bus control I/O drivers. This
connection must be tied externally to all other chip ground connections. The user must
provide adequate external decoupling capacitors. There is one GNDC connections.
SHI and ESAI —GNDS is an isolated ground for the SHI and ESAI. This connection
must be tied externally to all other chip ground connections. The user must provide
adequate external decoupling capacitors. There are three GNDS connections.
1-4
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Signal/Connection Descriptions
Clock and PLL
1.4
CLOCK AND PLL
Table 1-4 Clock and PLL Signals
State
during
Reset
Signal
Name
Type
Signal Description
EXTAL
Input
Input
External Clock Input—An external clock source must be connected
to EXTAL in order to supply the clock to the internal clock generator
and PLL.
PCAP
Input
Input
PLL Capacitor—PCAP is an input connecting an off-chip capacitor
to the PLL filter. Connect one capacitor terminal to PCAP and the
other terminal to VCCP
.
If the PLL is not used, PCAP may be tied to VCC, GND, or left float-
ing.
PINIT/NMI Input
Input
PLL Initial/Nonmaskable Interrupt—During assertion of RESET,
the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the
PLL control register, determining whether the PLL is enabled or dis-
abled. After RESET de assertion and during normal instruction pro-
cessing, the PINIT/NMI Schmitt-trigger input is a
negative-edge-triggered nonmaskable interrupt (NMI) request inter-
nally synchronized to internal system clock.
This input is 5 V tolerant.
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Signal/Connection Descriptions
External Memory Expansion Port (Port A)
1.5
EXTERNAL MEMORY EXPANSION PORT (PORT A)
When the DSP56364 enters a low-power standby mode (stop or wait), it tri-states the relevant port A
signals: D0–D7, AA0, AA1, RD, WR, CAS.
1.5.1
External Address Bus
Table 1-5 External Address Bus Signals
State during
Reset
Signal Name
Type
Signal Description
A0–A17
Output
Keeper
active
Address Bus—A0–A17 are active-high outputs that spec-
ify the address for external program and data memory
accesses. Otherwise, the signals are kept to their previous
values by internal weak keepers. To minimize power dissi-
pation, A0–A17 do not change state when external mem-
ory spaces are not being accessed.
1.5.2
External Data Bus
Table 1-6 External Data Bus Signals
State during
Reset
Signal Name
Type
Signal Description
D0–D7
Input/
Output
Tri-stated
Data Bus—D0–D7 are active-high, bidirectional input/out-
puts that provide the bidirectional data bus for external
program and data memory accesses. D0–D7 are tri-stated
during hardware reset and when the DSP is in the stop or
wait low-power standby mode.
1-6
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Signal/Connection Descriptions
External Memory Expansion Port (Port A)
1.5.3
External Bus Control
Table 1-7 External Bus Control Signals
State
during
Reset
Signal Name
Type
Signal Description
AA0–AA1/
Output
Tri-stated
Address Attribute or Row Address Strobe—When defined as AA, these
signals can be used as chip selects or additional address lines. When
defined as RAS, these signals can be used as RAS for DRAM interface.
These signals are tri-statable outputs with programmable polarity. These
signals are tri-stated during hardware reset and when the DSP is in the
stop or wait low-power standby mode.
RAS0–RAS1
Output
Output
Output
Input
Tri-stated
Tri-stated
Tri-stated
Column Address Strobe— CAS is an active-low output used by DRAM
to strobe the column address. This signal is tri-stated during hardware
reset and when the DSP is in the stop or wait low-power standby mode.
CAS
RD
Read Enable—RD is an active-low output that is asserted to read exter-
nal memory on the data bus. This signal is tri-stated during hardware reset
and when the DSP is in the stop or wait low-power standby mode.
Write Enable— WR is an active-low output that is asserted to write exter-
nal memory on the data bus. This signal is tri-stated during hardware reset
and when the DSP is in the stop or wait low-power standby mode.
WR
TA
Ignored
Input
Transfer Acknowledge—If there is no external bus activity, the TA input
is ignored. The TA input is a data transfer acknowledge (DTACK) function
that can extend an external bus cycle indefinitely. Any number of wait
states (1, 2. . .infinity) may be added to the wait states inserted by the
BCR by keeping TA deasserted. In typical operation, TA is deasserted at
the start of a bus cycle, is asserted to enable completion of the bus cycle,
and is deasserted before the next bus cycle. The current bus cycle com-
pletes one clock period after TA is asserted synchronous to the internal
system clock. The number of wait states is determined by the TA input or
by the bus control register (BCR), whichever is longer. The BCR can be
used to set the minimum number of wait states in external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at
least one wait state. A zero wait state access cannot be extended by TA
deassertion, otherwise improper operation may result. TA can operate
synchronously or asynchronously, depending on the setting of the TAS bit
in the operating mode register (OMR).
TA functionality may not be used while performing DRAM type accesses,
otherwise improper operation may result.
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Signal/Connection Descriptions
Interrupt and Mode Control
1.6
INTERRUPT AND MODE CONTROL
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.
After RESET is deasserted, these inputs are hardware interrupt request lines.
Table 1-8 Interrupt and Mode Control
State
Signal Name
Type
during
Reset
Signal Description
Input
Input
Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low
Schmitt-trigger input, internally synchronized to the internal system clock.
MODA/IRQA selects the initial chip operating mode during hardware reset and
becomes a level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. MODA, MODB, and MODD
select one of 8 initial chip operating modes, latched into the OMR when the
RESET signal is deasserted. If IRQA is asserted synchronous to the internal
system clock, multiple processors can be re synchronized using the WAIT
instruction and asserting IRQA to exit the wait state. If the processor is in the
stop standby state and IRQA is asserted, the processor will exit the stop state.
MODA/IRQA
This input is 5 V tolerant.
Input
Input
Input
Input
Input
Input
Mode Select B/External Interrupt Request B—MODB/IRQB is an active-low
Schmitt-trigger input, internally synchronized to the internal system clock.
MODB/IRQB selects the initial chip operating mode during hardware reset and
becomes a level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. MODA, MODB, and MODD
select one of 8 initial chip operating modes, latched into OMR when the RESET
signal is deasserted. If IRQB is asserted synchronous to the internal system
clock, multiple processors can be re-synchronized using the WAIT instruction
and asserting IRQB to exit the wait state.
MODB/IRQB
MODD/IRQD
RESET
This input is 5 V tolerant.
Mode Select D/External Interrupt Request D—MODD/IRQD is an active-low
Schmitt-trigger input, internally synchronized to the internal system clock.
MODD/IRQD selects the initial chip operating mode during hardware reset and
becomes a level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. MODA, MODB, and MODD
select one of 8 initial chip operating modes, latched into OMR when the RESET
signal is deasserted. If IRQD is asserted synchronous to the internal system
clock, multiple processors can be re synchronized using the WAIT instruction
and asserting IRQD to exit the wait state.
This input is 5 V tolerant.
Reset—RESET is an active-low, Schmitt-trigger input. When asserted, the chip
is placed in the reset state and the internal phase generator is reset. The
Schmitt-trigger input allows a slowly rising input (such as a capacitor charging)
to reset the chip reliably. When the RESET signal is deasserted, the initial chip
operating mode is latched from the MODA, MODB, and MODD inputs. The
RESET signal must be asserted during power up. A stable EXTAL signal must
be supplied before deassertionof RESET.
This input is 5 V tolerant.
1-8
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Signal/Connection Descriptions
Serial Host Interface
1.7
SERIAL HOST INTERFACE
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.
Table 1-9 Serial Host Interface Signals
Signal
Name
Signal
Type
State during
Reset
Signal Description
SCK
Input or
output
Tri-stated
SPI Serial Clock—The SCK signal is an output when the SPI is configured as
a master and a Schmitt-trigger input when the SPI is configured as a slave.
When the SPI is configured as a master, the SCK signal is derived from the
internal SHI clock generator. When the SPI is configured as a slave, the SCK
signal is an input, and the clock signal from the external master synchronizes
the data transfer. The SCK signal is ignored by the SPI if it is defined as a
slave and the slave select (SS) signal is not asserted. In both the master and
slave SPI devices, data is shifted on one edge of the SCK signal and is sam-
pled on the opposite edge where data is stable. Edge polarity is determined by
the SPI transfer protocol.
SCL
Input or
output
Tri-stated
I2C Serial Clock—SCL carries the clock for I2C bus transactions in the I2C
mode. SCL is a Schmitt-trigger input when configured as a slave and an
open-drain output when configured as a master. SCL should be connected to
VCC through a pull-up resistor.
This signal is tri-stated during hardware, software, and individual reset. Thus,
there is no need for an external pull-up in this state.
This input is 5 V tolerant.
MISO
Input or
output
Tri-stated
Tri-stated
SPI Master-In-Slave-Out—When the SPI is configured as a master, MISO is
the master data input line. The MISO signal is used in conjunction with the
MOSI signal for transmitting and receiving serial data. This signal is a
Schmitt-trigger input when configured for the SPI Master mode, an output
when configured for the SPI Slave mode, and tri-stated if configured for the
SPI Slave mode when SS is deasserted. An external pull-up resistor is not
required for SPI operation.
SDA
Input or
open-drain
output
I2C Data and Acknowledge—In I2C mode, SDA is a Schmitt-trigger input
when receiving and an open-drain output when transmitting. SDA should be
connected to VCC through a pull-up resistor. SDA carries the data for I2C
transactions. The data in SDA must be stable during the high period of SCL.
The data in SDA is only allowed to change when SCL is low. When the bus is
free, SDA is high. The SDA line is only allowed to change during the time SCL
is high in the case of start and stop events. A high-to-low transition of the SDA
line while SCL is high is a unique situation, and is defined as the start event. A
low-to-high transition of SDA while SCL is high is a unique situation defined as
the stop event.
This signal is tri-stated during hardware, software, and individual reset. Thus,
there is no need for an external pull-up in this state.
This input is 5 V tolerant.
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Signal/Connection Descriptions
Serial Host Interface
Table 1-9 Serial Host Interface Signals (continued)
Signal
Name
Signal
Type
State during
Reset
Signal Description
MOSI
Input or
output
Tri-stated
Tri-stated
SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI is
the master data output line. The MOSI signal is used in conjunction with the
MISO signal for transmitting and receiving serial data. MOSI is the slave data
input line when the SPI is configured as a slave. This signal is a Schmitt-trig-
ger input when configured for the SPI Slave mode.
HA0
Input
I2C Slave Address 0—This signal uses a Schmitt-trigger input when config-
ured for the I2C mode. When configured for I2C slave mode, the HA0 signal is
used to form the slave device address. HA0 is ignored when configured for the
I2C master mode.
This signal is tri-stated during hardware, software, and individual reset. Thus,
there is no need for an external pull-up in this state.
This input is 5 V tolerant.
Input
Input
Input
Input
SPI Slave Select—This signal is an active low Schmitt-trigger input when
configured for the SPI mode. When configured for the SPI Slave mode, this
signal is used to enable the SPI slave for transfer. When configured for the
SPI master mode, this signal should be kept deasserted (pulled high). If it is
asserted while configured as SPI master, a bus error condition is flagged. If
SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output
signal in the high-impedance state.
SS
HA2
I2C Slave Address 2—This signal uses a Schmitt-trigger input when config-
ured for the I2C mode. When configured for the I2C Slave mode, the HA2 sig-
nal is used to form the slave device address. HA2 is ignored in the I2C master
mode.
This signal is tri-stated during hardware, software, and individual reset. Thus,
there is no need for an external pull-up in this state.
This input is 5 V tolerant.
Input or
Output
Tri-stated
Host Request—This signal is an active low Schmitt-trigger input when config-
ured for the master mode but an active low output when configured for the
slave mode.
HREQ
When configured for the slave mode, HREQ is asserted to indicate that the
SHI is ready for the next data word transfer and deasserted at the first clock
pulse of the new data word transfer. When configured for the master mode,
HREQ is an input. When asserted by the external slave device, it will trigger
the start of the data word transfer by the master. After finishing the data word
transfer, the master will await the next assertion of HREQ to proceed to the
next transfer.
This signal is tri-stated during hardware, software, personal reset, or when the
HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external
pull-up in this state.
This input is 5 V tolerant.
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Signal/Connection Descriptions
Enhanced Serial Audio Interface
1.8
ENHANCED SERIAL AUDIO INTERFACE
Table 1-10 Enhanced Serial Audio Interface Signals
Signal
Name
State during
Signal Type
Signal Description
Reset
HCKR
Input or output
GPIO
disconnected
High Frequency Clock for Receiver—When programmed as an
input, this signal provides a high frequency clock source for the
ESAI receiver as an alternate to the DSP core clock. When pro-
grammed as an output, this signal can serve as a high-frequency
sample clock (e.g., for external digital to analog converters [DACs])
or as an additional system clock.
PC2
Input, output,
or
GPIO
disconnected
Port C 2—When the ESAI is configured as GPIO, this signal is indi-
vidually programmable as input, output, or internally disconnected.
disconnected
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
HCKT
Input or output
GPIO
disconnected
High Frequency Clock for Transmitter—When programmed as
an input, this signal provides a high frequency clock source for the
ESAI transmitter as an alternate to the DSP core clock. When pro-
grammed as an output, this signal can serve as a high frequency
sample clock (e.g., for external DACs) or as an additional system
clock.
PC5
FSR
Input, output,
or
disconnected
GPIO
disconnected
Port C 5—When the ESAI is configured as GPIO, this signal is indi-
vidually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
Input or output
GPIO
disconnected
Frame Sync for Receiver—This is the receiver frame sync
input/output signal. In the asynchronous mode (SYN=0), the FSR
pin operates as the frame sync input or output used by all the
enabled receivers. In the synchronous mode (SYN=1), it operates
as either the serial flag 1 pin (TEBE=0), or as the transmitter exter-
nal buffer enable control (TEBE=1, RFSD=1).
When this pin is configured as serial flag pin, its direction is deter-
mined by the RFSD bit in the RCCR register. When configured as
the output flag OF1, this pin will reflect the value of the OF1 bit in
the SAICR register, and the data in the OF1 bit will show up at the
pin synchronized to the frame sync in normal mode or the slot in
network mode. When configured as the input flag IF1, the data
value at the pin will be stored in the IF1 bit in the SAISR register,
synchronized by the frame sync in normal mode or the slot in net-
work mode.
PC1
Input, output,
or
GPIO
disconnected
Port C 1—When the ESAI is configured as GPIO, this signal is indi-
vidually programmable as input, output, or internally disconnected.
disconnected
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
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Signal/Connection Descriptions
Enhanced Serial Audio Interface
Table 1-10 Enhanced Serial Audio Interface Signals (continued)
Signal
Name
State during
Reset
Signal Type
Signal Description
FST
Input or output
GPIO
disconnected
Frame Sync for Transmitter—This is the transmitter frame sync
input/output signal. For synchronous mode, this signal is the frame
sync for both transmitters and receivers. For asynchronous mode,
FST is the frame sync for the transmitters only. The direction is
determined by the transmitter frame sync direction (TFSD) bit in the
ESAI transmit clock control register (TCCR).
PC4
Input, output,
or
GPIO
disconnected
Port C 4—When the ESAI is configured as GPIO, this signal is indi-
vidually programmable as input, output, or internally disconnected.
disconnected
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SCKR
Input or output
GPIO
disconnected
Receiver Serial Clock—SCKR provides the receiver serial bit clock
for the ESAI. The SCKR operates as a clock input or output used by
all the enabled receivers in the asynchronous mode (SYN=0), or as
serial flag 0 pin in the synchronous mode (SYN=1).
When this pin is configured as serial flag pin, its direction is determined
by the RCKD bit in the RCCR register. When configured as the output
flag OF0, this pin will reflect the value of the OF0 bit in the SAICR regis-
ter, and the data in the OF0 bit will show up at the pin synchronized to
the frame sync in normal mode or the slot in network mode. When con-
figured as the input flag IF0, the data value at the pin will be stored in
the IF0 bit in the SAISR register, synchronized by the frame sync in nor-
mal mode or the slot in network mode.
PC0
Input, output,
or
GPIO
disconnected
Port C 0—When the ESAI is configured as GPIO, this signal is indi-
vidually programmable as input, output, or internally disconnected.
disconnected
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SCKT
PC3
Input or output
GPIO
disconnected
Transmitter Serial Clock—This signal provides the serial bit rate
clock for the ESAI. SCKT is a clock input or output used by all
enabled transmitters and receivers in synchronous mode, or by all
enabled transmitters in asynchronous mode.
Input, output,
or
GPIO
disconnected
Port C 3—When the ESAI is configured as GPIO, this signal is indi-
vidually programmable as input, output, or internally disconnected.
disconnected
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
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Signal/Connection Descriptions
Enhanced Serial Audio Interface
Table 1-10 Enhanced Serial Audio Interface Signals (continued)
Signal
Name
State during
Reset
Signal Type
Signal Description
SDO5
SDI0
PC6
Output
GPIO
disconnected
Serial Data Output 5—When programmed as a transmitter, SDO5
is used to transmit data from the TX5 serial transmit shift register.
Input
GPIO
disconnected
Serial Data Input 0—When programmed as a receiver, SDI0 is
used to receive serial data into the RX0 serial receive shift register.
Input, output,
or
GPIO
disconnected
Port C 6—When the ESAI is configured as GPIO, this signal is indi-
vidually programmable as input, output, or internally disconnected.
disconnected
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SDO4
SDI1
PC7
Output
Input
GPIO
disconnected
Serial Data Output 4—When programmed as a transmitter, SDO4
is used to transmit data from the TX4 serial transmit shift register.
GPIO
disconnected
Serial Data Input 1—When programmed as a receiver, SDI1 is
used to receive serial data into the RX1 serial receive shift register.
Input, output,
or
GPIO
disconnected
Port C 7—When the ESAI is configured as GPIO, this signal is indi-
vidually programmable as input, output, or internally disconnected.
disconnected
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SDO3
SDI2
PC8
Output
Input
GPIO
disconnected
Serial Data Output 3—When programmed as a transmitter, SDO3
is used to transmit data from the TX3 serial transmit shift register.
GPIO
disconnected
Serial Data Input 2—When programmed as a receiver, SDI2 is
used to receive serial data into the RX2 serial receive shift register.
Input, output,
or
GPIO
disconnected
Port C 8—When the ESAI is configured as GPIO, this signal is indi-
vidually programmable as input, output, or internally disconnected.
disconnected
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SDO2
SDI3
PC9
Output
Input
GPIO
disconnected
Serial Data Output 2—When programmed as a transmitter, SDO2
is used to transmit data from the TX2 serial transmit shift register
GPIO
disconnected
Serial Data Input 3—When programmed as a receiver, SDI3 is
used to receive serial data into the RX3 serial receive shift register.
Input, output,
or
GPIO
disconnected
Port C 9—When the ESAI is configured as GPIO, this signal is indi-
vidually programmable as input, output, or internally disconnected.
disconnected
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
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Signal/Connection Descriptions
Enhanced Serial Audio Interface
Table 1-10 Enhanced Serial Audio Interface Signals (continued)
Signal
Name
State during
Reset
Signal Type
Signal Description
SDO1
PC10
Output
GPIO
disconnected
Serial Data Output 1—SDO1 is used to transmit data from the TX1
serial transmit shift register.
Input, output,
or
disconnected
GPIO
disconnected
Port C 10—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally discon-
nected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SDO0
PC11
Output
GPIO
disconnected
Serial Data Output 0—SDO0 is used to transmit data from the TX0
serial transmit shift register.
Input, output,
or
disconnected
GPIO
disconnected
Port C 11—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally discon-
nected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
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Signal/Connection Descriptions
JTAG/OnCE Interface
1.9
JTAG/OnCE INTERFACE
Table 1-11 JTAG/OnCE Interface
State
during
Reset
Signal
Name
Signal
Type
Signal Description
TCK
Input
Input
Test Clock—TCK is a test clock input signal used to synchronize the
JTAG test logic. It has an internal pull-up resistor.
This input is 5 V tolerant.
TDI
Input
Input
Test Data Input—TDI is a test data serial input signal used for test
instructions and data. TDI is sampled on the rising edge of TCK and
has an internal pull-up resistor.
This input is 5 V tolerant.
TDO
TMS
Output
Input
Tri-stated
Input
Test Data Output—TDO is a test data serial output signal used for
test instructions and data. TDO is tri-statable and is actively driven in
the shift-IR and shift-DR controller states. TDO changes on the falling
edge of TCK.
Test Mode Select—TMS is an input signal used to sequence the test
controller’s state machine. TMS is sampled on the rising edge of TCK
and has an internal pull-up resistor.
This input is 5 V tolerant.
Table 1-12 GPIO Signals
Signal
Name
State during
Signal Type
Signal Description
Reset
GPIO0-
GPIO3
Input, output
or
disconnected
Disconnected
GPIO0-3- The General Purpose I/O pins are used for con-
trol and handshake functions between the DSP and exter-
nal circuitry. Each Port B GPIO pin may be individually
programmed as an input, output or disconnected
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SECTION 2
SPECIFICATIONS
2.1
INTRODUCTION
The DSP56364 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs
and outputs. The DSP56364 specifications are preliminary and are from design simulations, and may not
be fully tested or guaranteed. Finalized specifications will be published after full characterization and
device qualifications are complete.
2.2
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting
against damage due to high static voltage or
electrical fields. However, normal precautions
should be taken to avoid exceeding maximum
voltage ratings. Reliability of operation is
enhanced if unused inputs are pulled to an
appropriate logic voltage level (e.g., either
GND or V ). The suggested value for a
CC
pullup or pulldown resistor is 10 kΩ.
Note: In the calculation of timing requirements, adding a maximum value of one
specification to a minimum value of another specification does not yield a
reasonable sum. A maximum specification is calculated using a worst
case variation of process parameter values in one direction. The minimum
specification is calculated using the worst case for the same parameters in
the opposite direction. Therefore, a “maximum” value for a specification
will never occur in the same device that has a “minimum” value for another
specification; adding a maximum to a minimum represents a condition that
can never exist.
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Specifications
Thermal Characteristics
Table 2-1 Maximum Ratings
Symbol
Rating1
Value1, 2
Unit
V
Supply Voltage
VCC
VIN
−0.3 to +4.0
All input voltages excluding “5 V tolerant” inputs3
All “5 V tolerant” input voltages3
GND -0.3 to VCC + 0.3
V
VIN5
V
GND − 0.3 to VCC + 3.95
Current drain per pin excluding VCC and GND
Operating temperature range
I
10
mA
°C
°C
TJ
-40 to +105
Storage temperature
TSTG
−55 to +125
Notes: 1. GND = 0 V, VCC = 3.3 V ± 0.16 V, TJ = –0°C to +105°C, CL = 50 pF
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not
guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent
damage to the device.
3. CAUTION: All “5 V Tolerant” input voltages must not be more than 3.95 V greater than the supply
voltage; this restriction applies to “power on”, as well as during normal operation. In any case, the
input voltages cannot be more than 5.75 V. “5 V Tolerant” inputs are inputs that tolerate 5 V.
2.3
THERMAL CHARACTERISTICS
Table 2-2 Thermal Characteristics
Characteristic
Symbol
TQFP Value
49.87
Unit
°C/W
°C/W
°C/W
Junction-to-ambient thermal resistance1
Junction-to-case thermal resistance2
Thermal characterization parameter
R
θJA or θJA
θJC or θJC
ΨJT
R
9.26
2.0
Notes: 1. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided
printed circuit board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and
Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111.)
Measurements were done with parts mounted on thermal test boards conforming to specification
EIA/JESD51-3.
2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88,
with the exception that the cold plate temperature is used for the case temperature.
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Specifications
DC Electrical Characteristics
2.4
DC ELECTRICAL CHARACTERISTICS
6
Table 2-3 DC Electrical Characteristics
Symb
ol
Characteristics
Min
Typ
Max
Unit
Supply voltage
VCC
3.14
3.3
3.46
V
V
Input high voltage
• D(0:7), TA
VIH
2.0
2.0
—
—
VCC
• MOD1/IRQ1, RESET, PINIT/NMI
and all JTAG/ESAI/GPIO/SHI (SPI
mode)pins
VIHP
VCC + 3.95
VIHP
VIHX
1.5
—
—
VCC + 3.95
VCC
• SHI (I2C mode) pins
• EXTAL8
0.8 × VCC
Input low voltage
V
• D(0:7), TA, MOD1/IRQ1, RESET,
PINIT
VIL
–0.3
–0.3
—
—
0.8
0.8
VILP
• JTAG/ESAI/GPIO/SHI (SPI
mode)pins
VILP
VILX
IIN
-0.3
–0.3
–10
–10
—
—
—
—
0.3xVCC
0.2 × VCC
10
• SHI (I2C mode) pins
• EXTAL8
Input leakage current
µA
µA
High impedance (off-state) input current
(@ 2.4 V / 0.4 V)
ITSI
10
Output high voltage
VOH
• TTL (IOH = –0.4 mA)5,7
2.4
—
—
—
—
V
V
VCC
0.01
–
• CMOS (IOH = –10 µA)5
Output low voltage
VOL
V
—
—
—
0.4
• TTL (IOL = 3.0 mA, open-drain
pins IOL = 6.7 mA)5,7
• CMOS (IOL = 10 µA)5
—
0.01
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Specifications
AC Electrical Characteristics
6
Table 2-3 DC Electrical Characteristics (continued)
Symb
ol
Characteristics
Min
Typ
Max
Unit
Internal supply current2 at internal clock
of 100Mhz
ICCI
—
127
181
mA
• In Normal mode
• In Wait mode3
ICCW
ICCS
—
—
7. 5
100
11
mA
• In Stop mode4
PLL supply current
Input capacitance5
150
µA
—
—
1
2.5
10
mA
pF
CIN
—
Notes: 1. Refers to MODA/IRQA, MODB/IRQB, and MODD/IRQD pins
2. Section 4.3, Power Consumption Considerations on page 3 provides a formula to compute the
estimated current requirements in Normal mode. In order to obtain these results, all inputs must be
terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP
benchmarks. The power consumption numbers in this specification are 90% of the measured results of
this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with
VCC = 3.3 V at TJ = 105°C. Maximum internal supply current is measured with VCC = 3.46 V at TJ =
105°C.
3. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signal is
disabled during Stop state.
4. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be
terminated (i.e., not allowed to float).
5. Periodically sampled and not 100% tested
6.
VCC = 3.3 V ± .16 V; TJ = 0°C to +105°C, CL = 50 pF
7. This characteristic does not apply to PCAP.
8. Driving EXTAL to the low VIHX or the high VILX value may cause additional power consumption (DC
current). To minimize power consumption, the minimum VIHX should be no lower than
0.9 × VCC and the maximum VILX should be no higher than 0.1 × VCC
.
2.5
AC ELECTRICAL CHARACTERISTICS
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of
0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown
in Note 8 of the previous table. AC timing specifications, which are referenced to a device input signal, are
measured in production with respect to the 50% point of the respective input signal’s transition. DSP56364
output levels are measured with the production test machine VOL and VOH reference levels set at 0.4 V
and 2.4 V, respectively.
Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the
device AC test conditions are 15 MHz and rated speed.
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Specifications
Internal Clocks
2.6
INTERNAL CLOCKS
Table 2-4 Internal Clocks
Expression1, 2
Typ
Symbo
Characteristics
l
Min
Max
Internal operation frequency
with PLL enabled
f
f
—
—
(Ef × MF)/
(PDF × DF)
—
Internal operation frequency
with PLL disabled
Ef/2
—
—
Internal clock high period
TH
—
ETC
—
• With PLL disabled
0.49 × ETC ×
PDF × DF/MF
0.51 × ETC ×
PDF × DF/MF
• With PLL enabled and
MF ≤ 4
0.47 × ETC ×
PDF × DF/MF
—
0.53 × ETC ×
PDF × DF/MF
• With PLL enabled and
MF > 4
Internal clock low period
• With PLL disabled
—
ETC
—
—
TL
0.49 × ETC ×
PDF × DF/MF
0.51 × ETC ×
PDF × DF/MF
• With PLL enabled and
MF ≤ 4
0.47 × ETC ×
PDF × DF/MF
—
0.53 × ETC ×
PDF × DF/MF
• With PLL enabled and
MF > 4
Internal clock cycle time with
PLL enabled
TC
—
ETC × PDF ×
—
DF/MF
Internal clock cycle time with
PLL disabled
TC
—
—
2 × ETC
—
—
Instruction cycle time
ICYC
TC
Notes: 1. DF = Division Factor
Ef = External frequency
ETC = External clock cycle
MF = Multiplication Factor
PDF = Predivision Factor
TC = internal clock cycle
2. See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion
of the PLL.
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Specifications
EXTERNAL CLOCK OPERATION
2.7
EXTERNAL CLOCK OPERATION
The DSP56364 system clock is an externally supplied square wave voltage source connected to
EXTAL(See Figure 2-1).
VIHC
Midpoint
EXTAL
ETH
ETL
VILC
2
3
4
ETC
Note: The midpoint is 0.5 (VIHC + VILC).
Figure 2-1 External Clock Timing
Table 2-5 Clock Operation
No.
Characteristics
Symbol
Min
Max
Frequency of EXTAL (EXTAL Pin Frequency)
1
The rise and fall time of this external clock should be
3 ns maximum.
Ef
0
100.0
EXTAL input high1, 2
• With PLL disabled (46.7%–53.3% duty cycle6)
ETH
ETL
ETC
4.67 ns
4.25 ns
∞
2
3
4
• With PLL enabled (42.5%–57.5% duty cycle6)
157.0 µs
EXTAL input low1, 2
• With PLL disabled (46.7%–53.3% duty cycle6)
4.67 ns
4.25 ns
∞
• With PLL enabled (42.5%–57.5% duty cycle6)
157.0 µs
EXTAL cycle time2
• With PLL disabled
10.00 ns
10.00 ns
∞
• With PLL enabled
273.1 µs
Notes: 1. Measured at 50% of the input transition
2. The maximum value for PLL enabled is given for minimum VCO and maximum MF.
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Specifications
Phase Lock Loop (PLL) Characteristics
2.8
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Table 2-6 PLL Characteristics
Characteristics
CO frequency when PLL enabled
Min
Max
Unit
V
30
200
MHz
(MF × Ef × 2/PDF)
PLL external capacitor (PCAP pin to VCCP
(CPCAP
)
pF
1)
(MF × 580) − 100 (MF × 780) − 140
MF × 830 MF × 1470
• @ MF ≤ 4
• @ MF > 4
Notes: 1. CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The
recommended value in pF for CPCAP can be computed from one of the following equations:
(MF x 680)-120, for MF ≤ 4, or
MF x 1100, for MF > 4.
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Specifications
Reset, Stop, Mode Select, and Interrupt Timing
2.9
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
6
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing
No.
Characteristics
Expression
Min
Max
Unit
8
Delay from RESET assertion to all pins at reset
value3
—
—
26.0
ns
9
Required RESET duration4
50 × ETC
500.0
10.0
—
—
ns
ns
• Power on, external clock generator, PLL
disabled
1000 × ETC
• Power on, external clock generator, PLL
enabled
75000 × ETC
75000 × ETC
0.75
0.75
—
—
µs
• Power on, internal oscillator
ms
• During STOP, XTAL disabled
(PCTL Bit 16 = 0)
2.5 × TC
2.5 × TC
25.0
25.0
—
—
ms
ns
• During STOP, XTAL enabled
(PCTL Bit 16 = 1)
• During normal operation
10
Delay from asynchronous RESET deassertion
to first external address output (internal reset
deassertion)5
3.25 × TC + 2.0
34.5
—
—
ns
ns
• Minimum
20.25 TC + 7.50
211.5
• Maximum
13
14
15
Mode select setup time
Mode select hold time
30.0
0.0
—
—
—
ns
ns
ns
Minimum edge-triggered interrupt request
assertion width
6.6
16
17
Minimum edge-triggered interrupt request deas-
sertion width
6.6
—
ns
Delay from IRQA, IRQB, IRQD, NMI asser-
tion to external memory access address out
valid
44.5
74.5
—
—
ns
ns
4.25 × TC + 2.0
7.25 × TC + 2.0
• Caused by first interrupt instruction fetch
• Caused by first interrupt instruction
execution
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Reset, Stop, Mode Select, and Interrupt Timing
6
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (continued)
No.
Characteristics
Expression
Min
Max
Unit
18
Delay from IRQA, IRQB, IRQD, NMI asser-
tion to general-purpose transfer output valid
caused by first interrupt instruction execution
105.0
—
ns
10 × TC + 5.0
19
Delay from address output valid caused by first
interrupt instruction execute to interrupt request
deassertion for level sensitive fast interrupts1
—
—
—
—
ns
3.75 × TC + WS × TC – 10.94
3.25 × TC + WS × TC – 10.94
20
21
Delay from RD assertion to interrupt request
deassertion for level sensitive fast interrupts1
ns
ns
Delay from WR assertion to interrupt request
deassertion for level sensitive fast interrupts1
—
—
(WS + 3.5) × TC – 10.94
• DRAM for all WS
—
—
—
—
—
—
(WS + 3.5) × TC – 10.94
(WS + 3) × TC – 10.94
(WS + 2.5) × TC – 10.94
• SRAM WS = 1
• SRAM WS = 2, 3
• SRAM WS ≥ 4
—
24
25
Duration for IRQA assertion to recover from
Stop state
5.9
Delay from IRQA assertion to fetch of first
instruction (when exiting Stop)2, 3
1.3
13.6
ms
PLC × ETC × PDF + (128 K −
PLC/2) × TC
• PLL is not active during Stop (PCTL Bit
17 = 0) and Stop delay is enabled
(OMR Bit 6 = 0)
232.5
ns
12.3
ms
PLC × ETC × PDF + (23.75 ±
0.5) × TC
• PLL is not active during Stop (PCTL Bit
17 = 0) and Stop delay is not enabled
(OMR Bit 6 = 1)
77.5
87.5
ns
(8.25 ± 0.5) × TC
• PLL is active during Stop (PCTL Bit 17 =
1) (Implies No Stop Delay)
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Specifications
Reset, Stop, Mode Select, and Interrupt Timing
6
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (continued)
No.
Characteristics
Expression
Min
Max
Unit
26
Duration of level sensitive IRQA assertion to
ensure interrupt service (when exiting Stop)2, 3
• PLL is not active during Stop (PCTL Bit
17 = 0) and Stop delay is enabled
(OMR Bit 6 = 0)
13.6
12.3
—
—
ms
ms
PLC × ETC × PDF + (128K −
PLC/2) × TC
PLC × ETC × PDF + (20.5 ±
0.5) × TC
• PLL is not active during Stop (PCTL Bit
17 = 0) and Stop delay is not enabled
(OMR Bit 6 = 1)
55.0
—
ns
5.5 × TC
• PLL is active during Stop (PCTL Bit 17 =
1) (implies no Stop delay)
27
Interrupt Requests Rate
• ESAI, SCI
—
120.0
ns
12TC
8TC
—
—
—
80.0
80.0
ns
ns
ns
• DMA
8TC
• IRQ, NMI (edge trigger)
• IRQ, NMI (level trigger)
120.0
12TC
28
DMA Requests Rate
—
60.0
ns
6TC
7TC
3TC
• Data read from ESAI, SCI
—
—
70.0
30.0
ns
ns
• Data write to ESAI, SCI
• IRQ, NMI (edge trigger)
2-10
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Specifications
Reset, Stop, Mode Select, and Interrupt Timing
6
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (continued)
No.
Characteristics
Expression
Min
Max
Unit
29
Delay from IRQA, IRQB, IRQD, NMI asser-
tion to external memory (DMA source) access
address out valid
4.25 × TC + 2.0
44.0
—
ns
Notes: 1. When using fast interrupts and IRQA, IRQB, and IRQD are defined as level-sensitive, timings 19 through
21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted
Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when
using Level-sensitive mode.
2. This timing depends on several settings:
For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled
during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before
executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide the proper delay.
While it is possible to set OMR Bit 6 = 1, it is not recommended and these specifications do not guarantee
timings for that case.
For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit
17=1), no stabilization delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored).
For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time
will be defined by the PCTL Bit 17 and OMR Bit 6 settings.
For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the
PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to
1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery will end when
the last of these two events occurs. The stop delay counter completes count or PLL lock procedure
completion.
PLC value for PLL disable is 0.
The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 100
MHz it is 4096/100 MHz = 40 µs). During the stabilization period, TC, TH, and TL will not be constant, and
their width may vary, so timing may vary as well.
3. Periodically sampled and not 100% tested
4. For an external clock generator, RESET duration is measured during the time in which RESET is asserted,
VCC is valid, and the EXTAL input is active and valid.
For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is
valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is
affected both by the specifications of the crystal and other components connected to the oscillator and
reflects worst case conditions.
When the VCC is valid, but the other “required RESET duration” conditions (as specified above) have not
been yet met, the device circuitry will be in an uninitialized state that can result in significant power
consumption and heat-up. Designs should minimize this state to the shortest possible duration.
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Specifications
Reset, Stop, Mode Select, and Interrupt Timing
6
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (continued)
No.
Characteristics Expression Min Max
Unit
5. For an external clock generator, RESET duration is measured during the time in which RESET is asserted,
VCC is valid, and the EXTAL input is active and valid.
For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is
valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is
affected both by the specifications of the crystal and other components connected to the oscillator and
reflects worst case conditions.
When the VCC is valid, but the other “required RESET duration” conditions (as specified above) have not
been yet met, the device circuitry will be in an uninitialized state that can result in significant power
consumption and heat-up. Designs should minimize this state to the shortest possible duration.
6. If PLL does not lose lock
7. VCC = 3.3 V ± 0.16 V; TJ = 0°C to + 105°C, CL = 50 pF
8. WS = number of wait states (measured in clock cycles, number of TC)
9. Use expression to compute maximum value.
VIH
RESET
9
10
8
All Pins
A0–A17
Reset Value
First Fetch
AA0460
Figure 2-2 Reset Timing
2-12
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Specifications
Reset, Stop, Mode Select, and Interrupt Timing
First Interrupt Instruction
Execution/Fetch
A0–A17
RD
20
WR
21
19
17
IRQA, IRQB,
IRQD,
NMI
a) First Interrupt Instruction Execution
General
Purpose
I/O
18
IRQA,
IRQB,
IRQD,
NMI
b) General Purpose I/O
AA0462
Figure 2-3 External Fast Interrupt Timing
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Specifications
Reset, Stop, Mode Select, and Interrupt Timing
IRQA, IRQB,
IRQD, NMI
15
16
IRQA, IRQB,
IRQD, NMI
AA0463
Figure 2-4 External Interrupt Timing (Negative Edge-Triggered)
VIH
RESET
13
14
VIH
VIL
VIH
VIL
IRQA, IRQB,
IRQD, NMI
MODA,
MODB,MODD,
PINIT
AA0465
Figure 2-5 Operating Mode Select Timing
24
IRQA
25
First Instruction Fetch
A0–A17
AA0466
Figure 2-6 Recovery from Stop State Using IRQA
2-14
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Specifications
Reset, Stop, Mode Select, and Interrupt Timing
26
IRQA
25
First IRQA Interrupt
Instruction Fetch
A0–A17
AA0467
Figure 2-7 Recovery from Stop State Using IRQA Interrupt Service
DMA Source Address
A0–A17
RD
WR
29
IRQA, IRQB,
IRQD,
First Interrupt Instruction Execution
NMI
AA1104
Figure 2-8 External Memory Access (DMA Source) Timing
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Specifications
External Memory Expansion Port (Port A)
2.10 EXTERNAL MEMORY EXPANSION PORT (PORT A)
2.10.1 SRAM Timing
3
Table 2-8 SRAM Read and Write Accesses
Expression1
No.
Characteristics
Symbol
Min
Max
Unit
100
Address valid and AA assertion
pulse width
tRC, tWC
(WS + 1) × TC − 4.0
[1 ≤ WS ≤ 3]
16.0
—
ns
(WS + 2) × TC − 4.0
[4 ≤ WS ≤ 7]
56.0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
(WS + 3) × TC − 4.0
[WS ≥ 8]
106.
0
101
Address and AA valid to WR
assertion
tAS
0.25 × TC − 2.0
0.5
5.5
[WS = 1]
0.75 × TC − 2.0
[2 ≤ WS ≤ 3]
1.25 × TC − 2.0
[WS ≥ 4]
10.5
11.0
16.0
102
WR assertion pulse width
tWP
1.5 × TC − 4.0
[WS = 1]
All frequencies:
WS × TC − 4.0
[2 ≤ WS ≤ 3]
(WS − 0.5) × TC − 4.0
[WS ≥ 4]
31.0
—
ns
2-16
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Specifications
External Memory Expansion Port (Port A)
3
Table 2-8 SRAM Read and Write Accesses (continued)
Expression1
No.
Characteristics
Symbol
Min
Max
Unit
103
WR deassertion to address not
valid
tWR
0.25 × TC − 2.0
[1 ≤ WS ≤ 3]
0.5
—
ns
1.25 × TC − 2.0
[4 ≤ WS ≤ 7]
10.5
20.5
8.5
—
—
—
ns
ns
ns
2.25 × TC − 2.0
[WS ≥ 8]
All frequencies:
1.25 × TC − 4.0
[4 ≤ WS ≤ 7]
2.25 × TC − 4.0
[WS ≥ 8]
18.5
—
—
10.5
5.5
ns
ns
ns
104
105
Address and AA valid to input
data valid
t
AA, tAC
(WS + 0.75) × TC − 7.0
[WS ≥ 1]
RD assertion to input data valid
tOE
(WS + 0.25) × TC − 7.0
[WS ≥ 1]
—
106
107
RD deassertion to data not valid
(data hold time)
tOHZ
0.0
—
—
ns
ns
Address valid to WR deassertion2
tAW
(WS + 0.75) × TC − 4.0
[WS ≥ 1]
13.5
108
109
Data valid to WR deassertion
(data setup time)
tDS (tDW
)
(WS − 0.25) × TC − 3.0
[WS ≥ 1]
4.5
0.5
—
—
—
—
ns
ns
ns
ns
Data hold time from WR deasser-
tion
tDH
0.25 × TC − 2.0
[1 ≤ WS ≤ 3]
1.25 × TC − 2.0
[4 ≤ WS ≤ 7]
10.5
20.5
2.25 × TC − 2.0
[WS ≥ 8]
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Specifications
External Memory Expansion Port (Port A)
3
Table 2-8 SRAM Read and Write Accesses (continued)
Expression1
No.
Characteristics
RD deassertion time
Symbol
Min
Max
Unit
113
0.75 × TC − 4.0
[1 ≤ WS ≤ 3]
3.5
—
ns
1.75 × TC − 4.0
[4 ≤ WS ≤ 7]
13.5
23.5
1.0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
2.75 × TC − 4.0
[WS ≥ 8]
114
WR deassertion time
0.5 × TC − 4.0
[WS = 1]
TC − 2.0
[2 ≤ WS ≤ 3]
6.0
2.5 × TC − 4.0
[4 ≤ WS ≤ 7]
21.0
31.0
3.5 × TC − 4.0
[WS ≥ 8]
115
116
117
Address valid to RD assertion
RD assertion pulse width
0.5 × TC − 4.0
1.0
8.5
0.5
—
—
—
ns
ns
ns
(WS + 0.25) × TC −4.0
RD deassertion to address not
valid
0.25 × TC − 2.0
[1 ≤ WS ≤ 3]
1.25 × TC − 2.0
[4 ≤ WS ≤ 7]
10.5
20.5
—
—
ns
ns
2.25 × TC − 2.0
[WS ≥ 8]
118
119
TA setup before RD or WR
deassertion4
0.25 × TC + 2.0
4.5
0
—
—
ns
ns
TA hold after RD or WR deasser-
tion
Notes: 1. WS is the number of wait states specified in the BCR.
2. Timings 100, 107 are guaranteed by design, not tested.
3. All timings for 100 MHz are measured from 0.5 · Vcc to .05 · Vcc
4. In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to
remain active
2-18
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Specifications
External Memory Expansion Port (Port A)
100
A0–A17
AA0–AA1
117
106
113
116
RD
115
105
WR
104
119
118
TA
Data
In
D0–D7
AA0468
Figure 2-9 SRAM Read Access
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Specifications
External Memory Expansion Port (Port A)
100
A0–A17
AA0–AA3
107
101
102
103
WR
114
RD
TA
118
119
108
111
110
109
112
Data
Out
D0–D23
AA0469
Figure 2-10 SRAM Write Access
2-20
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Specifications
External Memory Expansion Port (Port A)
2.10.2 DRAM Timing
The selection guides provided in Figure 2-11 and Figure 2-14 should be used for primary selection only.
Final selection should be based on the timing provided in the following tables. As an example, the
selection guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode
DRAM. However, by using the information in the appropriate table, a designer may choose to evaluate
whether fewer wait states might be used by determining which timing prevents operation at 100 MHz,
running the chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available),
and control factors such as capacitive and resistive load to improve overall system performance.
DRAM Type
(tRAC ns)
Note: This figure should be use for primary selection.
For exact and detailed timings see the
following tables.
100
80
70
60
50
Chip Frequency
(MHz)
120
40
66
80
100
1 Wait States
2 Wait States
3 Wait States
4 Wait States
AA047
Figure 2-11 DRAM Page Mode Wait States Selection Guide
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Specifications
External Memory Expansion Port (Port A)
Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3
20 MHz6
30 MHz6
No.
Characteristics
Symbol
Expression
Unit
Min
Max
Min
Max
131 Page mode cycle time for two
consecutive accesses of the
same direction
tPC
2 × TC
100.0
—
66.7
—
ns
Page mode cycle time for
mixed (read and write)
accesses
1.25 × TC
62.5
—
41.7
—
132 CAS assertion to data valid
(read)
tCAC
TC − 7.5
—
—
42.5
67.5
—
—
—
25.8
42.5
—
ns
ns
ns
ns
ns
133 Column address valid to data
valid (read)
tAA
1.5 × TC − 7.5
134 CAS deassertion to data not
valid (read hold time)
tOFF
tRSH
tRHCP
0.0
0.0
135 Last CAS assertion to RAS
deassertion
0.75 × TC − 4.0
2 × TC − 4.0
33.5
96.0
—
21.0
62.7
—
136 Previous CAS deassertion to
RAS deassertion
—
—
137 CAS assertion pulse width
tCAS
tCRP
0.75 × TC − 4.0
1.75 × TC − 6.0
33.5
81.5
—
—
21.0
52.3
—
—
ns
ns
138 Last CAS deassertion to RAS
deassertion4
• BRW[1:0] = 00
• BRW[1:0] = 01
• BRW[1:0] = 10
3.25 × TC − 6.0 156.5
4.25 × TC − 6.0 206.5
6.25 × TC – 6.0 306.5
102.2
135.5
202.1
12.7
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
• BRW[1:0] = 11
139 CAS deassertion pulse width
tCP
0.5 × TC − 4.0
0.5 × TC − 4.0
21.0
21.0
140 Column address valid to CAS
assertion
tASC
12.7
141 CAS assertion to column
address not valid
tCAH
0.75 × TC − 4.0
2 × TC − 4.0
33.5
96.0
—
—
21.0
62.7
—
—
ns
ns
142 Last column address valid to
RAS deassertion
tRAL
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External Memory Expansion Port (Port A)
Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3
20 MHz6
30 MHz6
No.
Characteristics
Symbol
Expression
Unit
Min
Max
Min
Max
143 WR deassertion to CAS asser-
tion
tRCS
tRCH
tWCH
0.75 × TC − 3.8
0.25 × TC − 3.7
0.5 × TC − 4.2
33.7
8.8
—
21.2
4.6
—
ns
ns
ns
144 CAS deassertion to WR asser-
tion
—
—
—
—
145 CAS assertion to WR deasser-
tion
20.8
12.5
146 WR assertion pulse width
tWP
1.5 × TC − 4.5
1.75 × TC − 4.3
70.5
83.2
—
—
45.5
54.0
—
—
ns
ns
147 Last WR assertion to RAS
deassertion
tRWL
148 WR assertion to CAS deasser-
tion
tCWL
1.75 × TC − 4.3
0.25 × TC − 4.0
0.75 × TC − 4.0
TC − 4.3
83.2
8.5
—
—
—
—
—
54.0
4.3
—
—
—
—
—
ns
ns
ns
ns
ns
149 Data valid to CAS assertion
(Write)
tDS
150 CAS assertion to data not valid
(write)
tDH
33.5
45.7
71.0
21.0
29.0
46.0
151 WR assertion to CAS asser-
tion
tWCS
152 Last RD assertion to RAS
deassertion
tROH
1.5 × TC − 4.0
TC − 7.5
153 RD assertion to data valid
tGA
tGZ
—
42.5
—
—
25.8
—
ns
ns
154 RD deassertion to data not
valid 5
0.0
0.0
155 WR assertion to data active
0.75 × TC − 0.3
0.25 × TC
37.2
—
—
24.7
—
—
ns
ns
156 WR deassertion to data high
impedance
12.5
8.3
Notes: 1. The number of wait states for Page mode access is specified in the DCR.
2. The refresh period is specified in the DCR.
3. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC
equals 2 × TC for read-after-read or write-after-write sequences).
4. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each
DRAM out-of-page access.
5. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ
6. Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See Figure 2-14.).
.
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Specifications
External Memory Expansion Port (Port A)
1, 2, 3, 7
Table 2-10 DRAM Page Mode Timings, Two Wait States
66 MHz
Min Max
80 MHz
No.
Characteristics
Symbol
Expression
Unit
Min Max
131 Page mode cycle time for two
consecutive accesses of the
same direction
tPC
2 × TC
45.4
—
37.5
—
ns
Page mode cycle time for
mixed (read and write)
accesses
1.25 × TC
41.1
—
34.4
—
132 CAS assertion to data valid
(read)
tCAC
1.5 × TC − 7.5
1.5 × TC − 6.5
2.5 × TC − 7.5
2.5 × TC − 6.5
—
—
15.2
—
—
—
—
12.3
—
ns
ns
ns
ns
ns
133 Column address valid to data
valid (read)
tAA
—
30.4
—
—
—
—
24.8
—
134 CAS deassertion to data not
valid (read hold time)
tOFF
0.0
—
0.0
135 Last CAS assertion to RAS
deassertion
tRSH
1.75 × TC − 4.0
3.25 × TC − 4.0
22.5
45.2
—
—
17.9
36.6
—
—
ns
ns
136 Previous CAS deassertion to
RAS deassertion
tRHCP
137 CAS assertion pulse width
tCAS
tCRP
1.5 × TC − 4.0
2.0 × TC − 6.0
18.7
24.4
—
—
14.8
19.0
—
—
ns
ns
138 Last CAS deassertion to RAS
deassertion5
• BRW[1:0] = 00
• BRW[1:0] = 01
• BRW[1:0] = 10
3.5 × TC − 6.0
4.5 × TC − 6.0
6.5 × TC − 6.0
1.25 × TC − 4.0
TC − 4.0
47.2
62.4
92.8
14.9
11.2
—
—
—
—
—
37.8
50.3
75.3
11.6
8.5
—
—
—
—
—
ns
ns
ns
ns
ns
• BRW[1:0] = 11
139 CAS deassertion pulse width
tCP
140 Column address valid to CAS
assertion
tASC
141 CAS assertion to column
address not valid
tCAH
1.75 × TC − 4.0
22.5
—
17.9
—
ns
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External Memory Expansion Port (Port A)
1, 2, 3, 7
Table 2-10 DRAM Page Mode Timings, Two Wait States
(continued)
80 MHz
66 MHz
No.
Characteristics
Symbol
Expression
Unit
Min Max Min Max
142 Last column address valid to
RAS deassertion
tRAL
tRCS
tRCH
tWCH
3 × TC − 4.0
1.25 × TC − 3.8
0.5 × TC − 3.7
1.5 × TC − 4.2
41.5
15.1
3.9
—
—
—
—
33.5
11.8
2.6
—
—
—
—
ns
ns
ns
ns
143 WR deassertion to CAS asser-
tion
144 CAS deassertion to WR asser-
tion
145 CAS assertion to WR deasser-
tion
18.5
14.6
146 WR assertion pulse width
tWP
2.5 × TC − 4.5
2.75 × TC − 4.3
33.5
33.4
—
—
26.8
26.8
—
—
ns
ns
147 Last WR assertion to RAS
deassertion
tRWL
148 WR assertion to CAS deasser-
tion
tCWL
2.5 × TC − 4.3
33.6
—
27.0
—
ns
149 Data valid to CAS assertion
(write)
tDS
0.25 × TC − 3.7
0.25 × TC − 3.0
1.75 × TC − 4.0
0.1
—
—
—
—
—
0.1
—
—
—
ns
ns
ns
150 CAS assertion to data not valid
(write)
tDH
tWCS
tROH
tGA
22.5
17.9
151 WR assertion to CAS asser-
tion
TC − 4.3
10.9
33.9
—
—
—
8.2
27.3
—
—
—
—
ns
ns
ns
152 Last RD assertion to RAS
deassertion
2.5 × TC − 4.0
1.75 × TC − 7.5
153 RD assertion to data valid
19.0
1.75 × TC − 6.5
—
—
—
—
15.4
—
ns
ns
154 RD deassertion to data not
valid6
tGZ
0.0
0.0
155 WR assertion to data active
0.75 × TC − 0.3
0.25 × TC
11.1
—
—
9.1
—
—
ns
ns
156 WR deassertion to data high
impedance
3.8
3.1
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Specifications
External Memory Expansion Port (Port A)
1, 2, 3, 7
Table 2-10 DRAM Page Mode Timings, Two Wait States
(continued)
80 MHz
66 MHz
No.
Characteristics
Symbol
Expression
Unit
Min Max
Min Max
Notes: 1. The number of wait states for Page mode access is specified in the DCR.
2. The refresh period is specified in the DCR.
3. The asynchronous delays specified in the expressions are valid for DSP56364.
4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC
equals 3 × TC for read-after-read or write-after-write sequences).
5. BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each
DRAM out-of-page access.
6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
7. There are no DRAMs fast enough to fit to two wait states Page mode @ 100MHz (See Figure 2-11)
1, 2, 3
Table 2-11 DRAM Page Mode Timings, Three Wait States
No.
Characteristics
Symbol
Expression
2 × TC
Min Max Unit
131 Page mode cycle time for two consecutive
accesses of the same direction
tPC
40.0
35.0
—
—
ns
1.25 × TC
Page mode cycle time for mixed (read and
write) accesses
132 CAS assertion to data valid (read)
tCAC
tAA
2 × TC − 7.0
3 × TC − 7.0
—
—
13.0
23.0
—
ns
ns
ns
133 Column address valid to data valid (read)
134 CAS deassertion to data not valid (read hold
time)
tOFF
0.0
135 Last CAS assertion to RAS deassertion
tRSH
2.5 × TC − 4.0
4.5 × TC − 4.0
21.0
41.0
—
—
ns
ns
136 Previous CAS deassertion to RAS deasser-
tion
tRHCP
137 CAS assertion pulse width
tCAS
2 × TC − 4.0
16.0
—
ns
ns
138 Last CAS deassertion to RAS assertion5
• BRW[1:0] = 00
tCRP
2.25 × TC − 6.0
3.75 × TC − 6.0
4.75 × TC − 6.0
6.75 × TC − 6.0
—
—
—
—
—
—
• BRW[1:0] = 01
• BRW[1:0] = 10
41.5
61.5
• BRW[1:0] = 11
139 CAS deassertion pulse width
tCP
1.5 × TC − 4.0
TC − 4.0
11.0
6.0
—
—
ns
ns
140 Column address valid to CAS assertion
tASC
2-26
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Specifications
External Memory Expansion Port (Port A)
1, 2, 3
Table 2-11 DRAM Page Mode Timings, Three Wait States
(continued)
Min Max Unit
No.
Characteristics
Symbol
tCAH
tRAL
tRCS
tRCH
tWCH
tWP
Expression
2.5 × TC − 4.0
4 × TC − 4.0
141 CAS assertion to column address not valid
142 Last column address valid to RAS deassertion
143 WR deassertion to CAS assertion
144 CAS deassertion to WR assertion
145 CAS assertion to WR deassertion
146 WR assertion pulse width
21.0
36.0
8.5
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.25 × TC − 4.0
0.75 × TC − 4.0
—
3.5
—
2.25 × TC − 4.2 18.3
3.5 × TC − 4.5 30.5
—
—
147 Last WR assertion to RAS deassertion
148 WR assertion to CAS deassertion
149 Data valid to CAS assertion (write)
150 CAS assertion to data not valid (write)
151 WR assertion to CAS assertion
152 Last RD assertion to RAS deassertion
153 RD assertion to data valid
tRWL
tCWL
tDS
3.75 × TC − 4.3 33.2
3.25 × TC − 4.3 28.2
—
—
0.5 × TC − 4.0
2.5 × TC − 4.0
1.25 × TC − 4.3
3.5 × TC − 4.0
2.5 × TC − 7.0
1.0
21.0
8.2
31.0
—
—
tDH
—
tWCS
tROH
tGA
—
—
18.0
—
154 RD deassertion to data not valid6
155 WR assertion to data active
tGZ
0.0
7.2
—
0.75 × TC − 0.3
0.25 × TC
—
156 WR deassertion to data high impedance
2.5
Notes: 1. The number of wait states for Page mode access is specified in the DCR.
2. The refresh period is specified in the DCR.
3. The asynchronous delays specified in the expressions are valid for DSP56364.
4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g.,
PC equals 4 × TC for read-after-read or write-after-write sequences).
t
5. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each
DRAM out-of page-access.
6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not
tGZ
.
MOTOROLA
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Specifications
External Memory Expansion Port (Port A)
1, 2, 3
Table 2-12 DRAM Page Mode Timings, Four Wait States
No.
Characteristics
Symbol
Expression
2 × TC
Min Max Unit
131 Page mode cycle time for two consecutive
accesses of the same direction.
tPC
50.0
—
—
ns
1.25 × TC
45.0
Page mode cycle time for mixed (read and
write) accesses.
132 CAS assertion to data valid (read)
tCAC
tAA
2.75 × TC − 7.0
3.75 × TC − 7.0
—
—
20.5
30.5
—
ns
ns
ns
133 Column address valid to data valid (read)
134 CAS deassertion to data not valid (read hold
time)
tOFF
0.0
135 Last CAS assertion to RAS deassertion
tRSH
3.5 × TC − 4.0
6 × TC − 4.0
31.0
56.0
—
—
ns
ns
136 Previous CAS deassertion to RAS deasser-
tion
tRHCP
137 CAS assertion pulse width
tCAS
2.5 × TC − 4.0
21.0
—
ns
ns
138 Last CAS deassertion to RAS assertion5
• BRW[1:0] = 00
tCRP
2.75 × TC − 6.0
4.25 × TC − 6.0
5.25 × TC − 6.0
7.25 × TC − 6.0
—
—
—
—
—
—
• BRW[1:0] = 01
• BRW[1:0] = 10
46.5
66.5
• BRW[1:0] = 11
139 CAS deassertion pulse width
tCP
tASC
tCAH
tRAL
tRCS
tRCH
tWCH
tWP
2 × TC − 4.0
TC − 4.0
16.0
6.0
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
140 Column address valid to CAS assertion
141 CAS assertion to column address not valid
142 Last column address valid to RAS deassertion
143 WR deassertion to CAS assertion
144 CAS deassertion to WR assertion
145 CAS assertion to WR deassertion
146 WR assertion pulse width
3.5 × TC − 4.0
5 × TC − 4.0
1.25 × TC − 4.0
1.25 × TC − 4.0
31.0
46.0
8.5
8.5
3.25 × TC − 4.2 28.3
4.5 × TC − 4.5 40.5
147 Last WR assertion to RAS deassertion
148 WR assertion to CAS deassertion
tRWL
tCWL
4.75 × TC − 4.3 43.2
3.75 × TC − 4.3 33.2
2-28
DSP56364 Advance Information
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Specifications
External Memory Expansion Port (Port A)
1, 2, 3
Table 2-12 DRAM Page Mode Timings, Four Wait States
(continued)
Min Max Unit
No.
Characteristics
Symbol
tDS
Expression
0.5 × TC − 4.0
3.5 × TC − 4.0
1.25 × TC − 4.3
4.5 × TC − 4.0
3.25 × TC − 7.0
149 Data valid to CAS assertion (write)
150 CAS assertion to data not valid (write)
151 WR assertion to CAS assertion
152 Last RD assertion to RAS deassertion
153 RD assertion to data valid
1.0
31.0
8.2
41.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
tDH
tWCS
tROH
tGA
—
—
25.5
—
154 RD deassertion to data not valid6
155 WR assertion to data active
tGZ
0.0
7.2
—
0.75 × TC − 0.3
0.25 × TC
—
156 WR deassertion to data high impedance
2.5
Notes: 1. The number of wait states for Page mode access is specified in the DCR.
2. The refresh period is specified in the DCR.
3. The asynchronous delays specified in the expressions are valid for DSP56364.
4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g.,
tPC equals 3 × TC for read-after-read or write-after-write sequences).
5. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each
DRAM out-of-page access.
6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not
tGZ
.
MOTOROLA
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Specifications
External Memory Expansion Port (Port A)
RAS
136
135
131
CAS
137
140
139
141
138
142
Column
Address
Last Column
Address
Column
Address
Row
Add
A0–A17
151
144
143
145
147
WR
RD
146
148
155
149
156
150
D0–D7
Data Out
Data Out
Data Out
AA0473
Figure 2-12 DRAM Page Mode Write Accesses
2-30
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Specifications
External Memory Expansion Port (Port A)
RAS
136
131
135
CAS
137
140
139
141
138
142
Row
Add
Last Column
Address
Column
Address
Column
Address
A0–A17
WR
143
132
133
153
152
RD
134
154
D0–D7
Data In
Data In
Data In
AA0474
Figure 2-13 DRAM Page Mode Read Accesses
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Specifications
External Memory Expansion Port (Port A)
DRAM Type
(tRAC ns)
Note: This figure should be use for primary selection. For
exact and detailed timings see the following tables.
100
80
70
60
Chip Frequency
(MHz)
50
120
40 66
80
100
4 Wait States
8 Wait States
11 Wait States
15 Wait States
AA0475
Figure 2-14 DRAM Out-of-Page Wait States Selection Guide
1, 2
Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States
20 MHz4
30 MHz4
Characteristics3
No.
Symbol
Expression
Unit
Min
Max
Min
Max
157 Random read or write
cycle time
tRC
tRAC
tCAC
tAA
5 × TC
250.0
—
—
166.7
—
—
ns
ns
ns
ns
158 RAS assertion to data
valid (read)
2.75 × TC − 7.5
1.25 × TC − 7.5
1.5 × TC − 7.5
130.0
55.0
67.5
84.2
34.2
42.5
159 CAS assertion to data
valid (read)
—
—
160 Column address valid to
data valid (read)
—
—
2-32
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External Memory Expansion Port (Port A)
1, 2
Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States
(continued)
20 MHz4
30 MHz4
Characteristics3
No.
Symbol
Expression
Unit
Min
Max
Min
Max
161 CAS deassertion to data
not valid (read hold time)
tOFF
0.0
—
0.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
162 RAS deassertion to RAS
assertion
tRP
1.75 × TC − 4.0
83.5
—
—
54.3
104.3
54.3
87.7
37.7
48.0
39.7
71.0
54.3
54.3
37.7
4.3
—
—
163 RAS assertion pulse
width
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tCP
3.25 × TC − 4.0 158.5
164 CAS assertion to RAS
deassertion
1.75 × TC − 4.0
83.5
—
—
165 RAS assertion to CAS
deassertion
2.75 × TC − 4.0 133.5
—
—
166 CAS assertion pulse
width
1.25 × TC − 4.0
1.5 × TC ± 2
58.5
73.0
60.5
—
—
167 RAS assertion to CAS
assertion
77.0
64.5
—
52.0
43.7
—
168 RAS assertion to column
address valid
1.25 × TC ± 2
169 CAS deassertion to RAS
assertion
2.25 × TC − 4.0 108.5
170 CAS deassertion pulse
width
1.75 × TC − 4.0
1.75 × TC − 4.0
1.25 × TC − 4.0
0.25 × TC − 4.0
1.75 × TC − 4.0
83.5
83.5
58.5
8.5
—
—
171 Row address valid to
RAS assertion
tASR
tRAH
tASC
tCAH
tAR
—
—
172 RAS assertion to row
address not valid
—
—
173 Column address valid to
CAS assertion
—
—
174 CAS assertion to column
address not valid
83.5
—
54.3
104.3
—
175 RAS assertion to column
address not valid
3.25 × TC − 4.0 158.5
—
—
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Specifications
External Memory Expansion Port (Port A)
1, 2
Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States
(continued)
20 MHz4
30 MHz4
Characteristics3
No.
Symbol
Expression
Unit
Min
Max
Min
Max
176 Column address valid to
RAS deassertion
tRAL
tRCS
tRCH
tRRH
tWCH
tWCR
2 × TC − 4.0
1.5 × TC − 3.8
0.75 × TC − 3.7
0.25 × TC − 3.7
1.5 × TC − 4.2
3 × TC − 4.2
96.0
—
62.7
—
ns
ns
ns
ns
ns
ns
177 WR deassertion to CAS
assertion
71.2
33.8
8.8
—
—
—
—
—
46.2
21.3
4.6
—
—
—
—
—
178 CAS deassertion to WR
assertion
179 RAS deassertion to WR
assertion
180 CAS assertion to WR
deassertion
70.8
145.8
220.5
45.8
95.8
181 RAS assertion to WR
deassertion
182 WR assertion pulse width
tWP
4.5 × TC − 4.5
—
—
145.5
154.0
—
—
ns
ns
183 WR assertion to RAS
deassertion
tRWL
4.75 × TC − 4.3 233.2
4.25 × TC − 4.3 208.2
2.25 × TC − 4.0 108.5
184 WR assertion to CAS
deassertion
tCWL
—
—
—
—
—
—
—
—
137.4
71.0
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
185 Data valid to CAS asser-
tion (write)
tDS
186 CAS assertion to data not
valid (write)
tDH
1.75 × TC − 4.0
83.5
54.3
187 RAS assertion to data not
valid (write)
tDHR
tWCS
tCSR
tRPC
tROH
3.25 × TC − 4.0 158.5
104.3
95.7
188 WR assertion to CAS
assertion
3 × TC − 4.3
0.5 × TC − 4.0
1.25 × TC − 4.0
4.5 × TC − 4.0
145.7
21.0
189 CAS assertion to RAS
assertion (refresh)
12.7
190 RAS deassertion to CAS
assertion (refresh)
58.5
37.7
191 RD assertion to RAS
deassertion
221.0
146.0
2-34
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1, 2
Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States
(continued)
20 MHz4
30 MHz4
Characteristics3
No.
Symbol
Expression
Unit
Min
Max
192.5
—
Min
—
Max
125.8
—
192 RD assertion to data valid
tGA
tGZ
4 × TC − 7.5
—
ns
ns
193 RD deassertion to data
not valid3
0.0
0.0
194 WR assertion to data
active
0.75 × TC − 0.3
0.25 × TC
37.2
—
—
24.7
—
—
ns
ns
195 WR deassertion to data
high impedance
12.5
8.3
Notes: 1. The number of wait states for out of page access is specified in the DCR.
2. The refresh period is specified in the DCR.
3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not
tGZ
.
4. Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (See
Figure 2-17).
1, 2
Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States
66 MHz
80 MHz
Characteristics4
Expression3
No.
Symbol
tRC
Unit
Min
Max
Min
Max
157 Random read or write
cycle time
9 × TC
136.4
—
112.5
—
ns
158 RAS assertion to data valid
(read)
tRAC
4.75 × TC − 7.5
4.75 × TC − 6.5
2.25 × TC − 7.5
2.25 × TC − 6.5
3 × TC − 7.5
—
—
—
—
—
—
0.0
64.5
—
—
—
—
—
—
—
0.0
—
52.9
—
ns
ns
ns
ns
ns
ns
ns
159 CAS assertion to data valid
(read)
tCAC
26.6
—
21.6
—
160 Column address valid to
data valid (read)
tAA
40.0
—
3 × TC − 6.5
31.0
—
161 CAS deassertion to data
not valid (read hold time)
tOFF
—
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External Memory Expansion Port (Port A)
1, 2
Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States
(continued)
66 MHz
80 MHz
Characteristics4
Expression3
No.
Symbol
Unit
Min
Max
Min
Max
162 RAS deassertion to RAS
assertion
tRP
3.25 × TC − 4.0
45.2
—
36.6
—
ns
163 RAS assertion pulse width
tRAS
tRSH
5.75 × TC − 4.0
3.25 × TC − 4.0
83.1
45.2
—
—
67.9
36.6
—
—
ns
ns
164 CAS assertion to RAS
deassertion
165 RAS assertion to CAS
deassertion
tCSH
4.75 × TC − 4.0
68.0
—
55.5
—
ns
166 CAS assertion pulse width
tCAS
tRCD
2.25 × TC − 4.0
2.5 × TC ± 2
30.1
35.9
—
24.1
29.3
—
ns
ns
167 RAS assertion to CAS
assertion
39.9
33.3
168 RAS assertion to column
address valid
tRAD
tCRP
tCP
1.75 × TC ± 2
4.25 × TC − 4.0
2.75 × TC − 4.0
3.25 × TC − 4.0
1.75 × TC − 4.0
0.75 × TC − 4.0
3.25 × TC − 4.0
5.75 × TC − 4.0
4 × TC − 4.0
24.5
59.8
37.7
45.2
22.5
7.4
28.5
—
—
—
—
—
—
—
—
—
19.9
49.1
30.4
36.6
17.9
5.4
23.9
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
169 CAS deassertion to RAS
assertion
170 CAS deassertion pulse
width
171 Row address valid to RAS
assertion
tASR
tRAH
tASC
tCAH
tAR
172 RAS assertion to row
address not valid
173 Column address valid to
CAS assertion
174 CAS assertion to column
address not valid
45.2
83.1
56.6
26.5
36.6
67.9
46.0
21.2
175 RAS assertion to column
address not valid
176 Column address valid to
RAS deassertion
tRAL
177 WR deassertion to CAS
assertion
tRCS
2 × TC − 3.8
2-36
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External Memory Expansion Port (Port A)
1, 2
Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States
66 MHz
(continued)
80 MHz
Characteristics4
Expression3
No.
Symbol
Unit
Min
Max
Min
Max
178 CAS deassertion to WR5
assertion
tRCH
1.25 × TC − 3.7
15.2
—
11.9
—
ns
179 RAS deassertion to WR5
assertion
tRRH
0.25 × TC − 3.7
0.25 × TC − 3.0
3 × TC − 4.2
0.1
—
—
—
—
—
0.1
—
—
—
ns
ns
ns
180 CAS assertion to WR deas-
sertion
tWCH
41.3
33.3
181 RAS assertion to WR deas-
sertion
tWCR
5.5 × TC − 4.2
8.5 × TC − 4.5
79.1
—
64.6
—
ns
182 WR assertion pulse width
tWP
124.3
—
—
101.8
105.1
—
—
ns
ns
183 WR assertion to RAS deas-
sertion
tRWL
8.75 × TC − 4.3 128.3
7.75 × TC − 4.3 113.1
184 WR assertion to CAS deas-
sertion
tCWL
—
—
—
—
—
—
—
—
92.6
55.4
36.6
67.9
64.5
14.8
17.9
102.3
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
185 Data valid to CAS assertion
(write)
tDS
4.75 × TC − 4.0
3.25 × TC − 4.0
5.75 × TC − 4.0
5.5 × TC − 4.3
1.5 × TC − 4.0
1.75 × TC − 4.0
8.5 × TC − 4.0
68.0
45.2
83.1
79.0
18.7
22.5
124.8
186 CAS assertion to data not
valid (write)
tDH
187 RAS assertion to data not
valid (write)
tDHR
tWCS
tCSR
tRPC
tROH
tGA
188 WR assertion to CAS
assertion
189 CAS assertion to RAS
assertion (refresh)
190 RAS deassertion to CAS
assertion (refresh)
191 RD assertion to RAS deas-
sertion
192 RD assertion to data valid
7.5 × TC − 7.5
7.5 × TC − 6.5
—
—
106.1
—
—
—
—
ns
ns
87.3
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Specifications
External Memory Expansion Port (Port A)
1, 2
Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States
(continued)
66 MHz
80 MHz
Characteristics4
Expression3
No.
Symbol
Unit
Min
Max
Min
Max
193 RD deassertion to data not
valid4
tGZ
0.0
0.0
—
0.0
—
ns
194 WR assertion to data active
0.75 × TC − 0.3
0.25 × TC
11.1
—
—
9.1
—
—
ns
ns
195 WR deassertion to data
high impedance
3.8
3.1
Notes: 1. The number of wait states for out-of-page access is specified in the DCR.
2. The refresh period is specified in the DCR.
3. The asynchronous delays specified in the expressions are valid for DSP56364.
4. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not
tGZ
5. Either tRCH or tRRH must be satisfied for read cycles.
.
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Specifications
External Memory Expansion Port (Port A)
1, 2
Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States
Characteristics4
Expression3
12 × TC
No.
Symbol
Min
Max
Unit
157 Random read or write cycle time
158 RAS assertion to data valid (read)
159 CAS assertion to data valid (read)
160 Column address valid to data valid (read)
161 CAS deassertion to data not valid (read hold time)
162 RAS deassertion to RAS assertion
163 RAS assertion pulse width
tRC
tRAC
tCAC
tAA
120.0
—
—
55.5
30.5
38.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.25 × TC − 7.0
3.75 × TC − 7.0
4.5 × TC − 7.0
—
—
tOFF
tRP
0.0
4.25 × TC − 4.0
7.75 × TC − 4.0
5.25 × TC − 4.0
6.25 × TC − 4.0
3.75 × TC − 4.0
2.5 × TC ± 4.0
1.75 × TC ± 4.0
5.75 × TC − 4.0
4.25 × TC − 4.0
4.25 × TC − 4.0
1.75 × TC − 4.0
0.75 × TC − 4.0
5.25 × TC − 4.0
7.75 × TC − 4.0
6 × TC − 4.0
38.5
73.5
48.5
58.5
33.5
21.0
13.5
53.5
38.5
38.5
13.5
3.5
—
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tCP
—
164 CAS assertion to RAS deassertion
165 RAS assertion to CAS deassertion
166 CAS assertion pulse width
—
—
—
167 RAS assertion to CAS assertion
168 RAS assertion to column address valid
169 CAS deassertion to RAS assertion
170 CAS deassertion pulse width
29.0
21.5
—
—
171 Row address valid to RAS assertion
172 RAS assertion to row address not valid
173 Column address valid to CAS assertion
174 CAS assertion to column address not valid
175 RAS assertion to column address not valid
176 Column address valid to RAS deassertion
177 WR deassertion to CAS assertion
178 CAS deassertion to WR5 assertion
179 RAS deassertion to WR5 assertion
tASR
tRAH
tASC
tCAH
tAR
—
—
—
48.5
73.5
56.0
26.0
13.5
0.5
—
—
tRAL
tRCS
tRCH
tRRH
—
3.0 × TC − 4.0
1.75 × TC − 4.0
0.25 × TC − 2.0
—
—
—
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Specifications
External Memory Expansion Port (Port A)
1, 2
Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States
(continued)
Characteristics4
Expression3
5 × TC − 4.2
7.5 × TC − 4.2
No.
Symbol
Min
Max
Unit
180 CAS assertion to WR deassertion
181 RAS assertion to WR deassertion
182 WR assertion pulse width
tWCH
tWCR
tWP
45.8
70.8
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11.5 × TC − 4.5 110.5
11.75 × TC − 4.3 113.2
10.25 × TC − 4.3 103.2
—
183 WR assertion to RAS deassertion
184 WR assertion to CAS deassertion
185 Data valid to CAS assertion (write)
186 CAS assertion to data not valid (write)
187 RAS assertion to data not valid (write)
188 WR assertion to CAS assertion
189 CAS assertion to RAS assertion (refresh)
190 RAS deassertion to CAS assertion (refresh)
191 RD assertion to RAS deassertion
192 RD assertion to data valid
tRWL
tCWL
tDS
—
—
5.75 × TC − 4.0
5.25 × TC − 4.0
7.75 × TC − 4.0
6.5 × TC − 4.3
1.5 × TC − 4.0
2.75 × TC − 4.0
53.5
48.5
73.5
60.7
11.0
23.5
—
tDH
—
tDHR
tWCS
tCSR
tRPC
tROH
tGA
—
—
—
—
11.5 × TC − 4.0 111.0
—
10 × TC − 7.0
—
0.0
7.2
—
93.0
—
193 RD deassertion to data not valid4
194 WR assertion to data active
tGZ
0.75 × TC − 0.3
0.25 × TC
—
195 WR deassertion to data high impedance
2.5
Notes: 1. The number of wait states for out-of-page access is specified in the DCR.
2. The refresh period is specified in the DCR.
3. The asynchronous delays specified in the expressions are valid for DSP56364.
4. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ
5. Either tRCH or tRRH must be satisfied for read cycles.
.
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Specifications
External Memory Expansion Port (Port A)
1, 2
Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States
Characteristics3
No.
Symbol
Expression
Min
Max Unit
157 Random read or write cycle time
158 RAS assertion to data valid (read)
159 CAS assertion to data valid (read)
160 Column address valid to data valid (read)
tRC
tRAC
tCAC
tAA
16 × TC
8.25 × TC − 5.7
4.75 × TC − 5.7
5.5 × TC − 5.7
0.0
160.0
—
—
ns
ns
ns
ns
ns
76.8
41.8
49.3
—
—
—
161 CAS deassertion to data not valid (read hold
time)
tOFF
0.0
162 RAS deassertion to RAS assertion
163 RAS assertion pulse width
tRP
6.25 × TC − 4.0
9.75 × TC − 4.0
6.25 × TC − 4.0
8.25 × TC − 4.0
4.75 × TC − 4.0
3.5 × TC ± 2
58.5
93.5
58.5
78.5
43.5
33.0
25.5
73.5
58.5
58.5
23.5
3.5
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tCP
164 CAS assertion to RAS deassertion
165 RAS assertion to CAS deassertion
166 CAS assertion pulse width
—
—
—
167 RAS assertion to CAS assertion
168 RAS assertion to column address valid
169 CAS deassertion to RAS assertion
170 CAS deassertion pulse width
37.0
29.5
—
2.75 × TC ± 2
7.75 × TC − 4.0
6.25 × TC − 4.0
6.25 × TC − 4.0
2.75 × TC − 4.0
0.75 × TC − 4.0
6.25 × TC − 4.0
9.75 × TC − 4.0
7 × TC − 4.0
—
171 Row address valid to RAS assertion
172 RAS assertion to row address not valid
173 Column address valid to CAS assertion
174 CAS assertion to column address not valid
175 RAS assertion to column address not valid
176 Column address valid to RAS deassertion
177 WR deassertion to CAS assertion
178 CAS deassertion to WR5 assertion
179 RAS deassertion to WR5 assertion
tASR
tRAH
tASC
tCAH
tAR
—
—
—
58.5
93.5
66.0
46.2
13.8
0.5
—
—
tRAL
tRCS
tRCH
tRRH
—
5 × TC − 3.8
—
1.75 × TC − 3.7
0.25 × TC − 2.0
—
—
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Specifications
External Memory Expansion Port (Port A)
1, 2
Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States
(continued)
Max Unit
Characteristics3
No.
Symbol
Expression
Min
180 CAS assertion to WR deassertion
181 RAS assertion to WR deassertion
182 WR assertion pulse width
tWCH
tWCR
tWP
6 × TC − 4.2
9.5 × TC − 4.2
15.5 × TC − 4.5
55.8
90.8
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
150.5
183 WR assertion to RAS deassertion
184 WR assertion to CAS deassertion
185 Data valid to CAS assertion (write)
186 CAS assertion to data not valid (write)
187 RAS assertion to data not valid (write)
188 WR assertion to CAS assertion
189 CAS assertion to RAS assertion (refresh)
190 RAS deassertion to CAS assertion (refresh)
191 RD assertion to RAS deassertion
192 RD assertion to data valid
tRWL
tCWL
tDS
15.75 × TC − 4.3 153.2
14.25 × TC − 4.3 138.2
8.75 × TC − 4.0
6.25 × TC − 4.0
9.75 × TC − 4.0
9.5 × TC − 4.3
1.5 × TC − 4.0
4.75 × TC − 4.0
15.5 × TC − 4.0
14 × TC − 5.7
83.5
58.5
93.5
90.7
11.0
43.5
151.0
—
tDH
tDHR
tWCS
tCSR
tRPC
tROH
tGA
134.3 ns
193 RD deassertion to data not valid3
194 WR assertion to data active
tGZ
0.0
—
—
ns
ns
ns
0.75 × TC − 0.3
0.25 × TC
7.2
195 WR deassertion to data high impedance
—
2.5
Notes: 1. The number of wait states for out-of-page access is specified in the DCR.
2. The refresh period is specified in the DCR.
3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not
tGZ
4. Either tRCH or tRRH must be satisfied for read cycles.
.
2-42
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Specifications
External Memory Expansion Port (Port A)
157
162
169
163
165
162
RAS
167
168
164
170
166
CAS
171
173
174
175
Row Address
Column Address
A0–A17
172
176
177
179
191
WR
RD
168
160
159
193
158
192
161
Data
In
D0–D7
AA0476
Figure 2-15 DRAM Out-of-Page Read Access
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Specifications
External Memory Expansion Port (Port A)
157
162
163
165
162
RAS
167
168
164
169
170
166
CAS
171
173
172
174
176
Row Address
Column Address
A0–A17
181
175
188
180
182
WR
RD
184
183
187
186
185
195
194
Data Out
D0–D7
AA0477
Figure 2-16 DRAM Out-of-Page Write Access
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Specifications
External Memory Expansion Port (Port A)
157
162
163
165
162
RAS
CAS
190
170
189
177
WR
AA0478
Figure 2-17 DRAM Refresh Access
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Specifications
Serial Host Interface SPI Protocol Timing
2.11 SERIAL HOST INTERFACE SPI PROTOCOL TIMING
Table 2-17 Serial Host Interface SPI Protocol Timing
Filter
Mode
No.
Characteristics
Mode
Expression
Min
Max
Unit
140 Tolerable spike width on clock or
data in
—
Bypassed
Narrow
Wide
—
—
—
—
0
ns
ns
ns
ns
50
—
—
100
—
141 Minimum serial clock cycle =
Master Bypassed
Narrow
6×TC+46
106
tSPICC(min)
6×TC+152
6×TC+223
212
283
43
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Wide
142 Serial clock high period
143 Serial clock low period
144 Serial clock rise/fall time
Master Bypassed 0.5×tSPICC –10
Narrow
Wide
0.5×tSPICC –10
0.5×tSPICC –10
2.5×TC+12
96
131
37
Slave Bypassed
Narrow
2.5×TC+102
2.5×TC+189
127
214
43
Wide
Master Bypassed 0.5×tSPICC –10
Narrow
Wide
0.5×tSPICC –10
0.5×tSPICC –10
2.5×TC+12
96
131
37
Slave Bypassed
Narrow
2.5×TC+102
2.5×TC+189
127
214
Wide
Master
Slave
—
—
—
—
—
—
10
ns
ns
2000
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Specifications
Serial Host Interface SPI Protocol Timing
Table 2-17 Serial Host Interface SPI Protocol Timing (continued)
Filter
Mode
No.
Characteristics
Mode
Expression
Min
Max
Unit
146 SS assertion to first SCK edge
CPHA = 0
Slave Bypassed
3.5×TC+15
50
—
ns
Narrow
Wide
0
0
0
0
—
—
ns
ns
CPHA = 1
Slave Bypassed
Narrow
10
0
10
0
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
Wide
0
0
147 Last SCK edge to SS not asserted
Slave Bypassed
Narrow
12
102
189
0
12
102
189
0
Wide
148 Data input valid to SCK edge (data
input set-up time)
Master/ Bypassed
Slave
Narrow MAX{(20-TC), 0}
10
Wide
MAX{(40-TC), 0}
2.5×TC+10
30
35
55
75
—
—
—
—
ns
ns
ns
ns
149 SCK last sampling edge to data input Master/ Bypassed
not valid
Slave
Narrow
Wide
2.5×TC+30
2.5×TC+50
150 SS assertion to data out active
Slave
Slave
—
—
2
9
2
—
9
ns
ns
151 SS deassertion to data high imped-
ance
—
152 SCK edge to data out valid
(data out delay time)
Master/ Bypassed
Slave
2×TC+33
2×TC+123
2×TC+210
—
—
—
53
ns
ns
ns
Narrow
143
230
Wide
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Specifications
Serial Host Interface SPI Protocol Timing
Table 2-17 Serial Host Interface SPI Protocol Timing (continued)
Filter
Mode
No.
Characteristics
Mode
Expression
Min
Max
Unit
153 SCK edge to data out not valid
(data out hold time)
Master/ Bypassed
Slave
TC+5
TC+55
TC+106
TC+33
15
65
—
—
—
43
ns
ns
ns
ns
Narrow
Wide
116
—
154 SS assertion to data out valid
(CPHA = 0)
Slave
—
157 First SCK sampling edge to HREQ
output deassertion
Slave Bypassed
Narrow
2.5×TC+30
2.5×TC+120
2.5×TC+217
2.5×TC+30
2.5×TC+80
2.5×TC+136
2.5×TC+30
—
—
55
145
242
—
ns
ns
ns
ns
ns
ns
ns
Wide
—
158 Last SCK sampling edge to HREQ
output not deasserted (CPHA = 1)
Slave Bypassed
Narrow
55
105
161
55
—
Wide
—
159 SS deassertion to HREQ output not
deasserted (CPHA = 0)
Slave
—
—
—
160 SS deassertion pulse width (CPHA = Slave
0)
TC+6
16
—
—
ns
ns
161 HREQ in assertion to first SCK edge Master Bypassed 0.5 × tSPICC
2.5×TC+43
+
121
Narrow
Wide
—
0.5 ×tSPICC
2.5×TC+43
+
174
209
0
—
—
—
ns
ns
ns
0.5 ×tSPICC
2.5×TC+43
+
162 HREQ in deassertion to last SCK
sampling edge (HREQ in set-up time)
(CPHA = 1)
Master
Master
0
0
163 First SCK edge to HREQ in not
asserted
—
0
—
ns
(HREQ in hold time)
Note: Periodically sampled, not 100% tested
2-48
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Specifications
Serial Host Interface SPI Protocol Timing
SS
(Input)
143
141
142
143
144
144
144
144
SCK (CPOL = 0)
(Output)
141
142
SCK (CPOL = 1)
(Output)
148
149
148
149
MISO
(Input)
MSB
Valid
LSB
Valid
153
152
MSB
MOSI
(Output)
LSB
161
163
HREQ
(Input)
AA0271
Figure 2-18 SPI Master Timing (CPHA = 0)
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Specifications
Serial Host Interface SPI Protocol Timing
SS
(Input)
143
142
141
141
144
144
144
144
SCK (CPOL = 0)
(Output)
142
143
SCK (CPOL = 1)
(Output)
148
148
149
149
MISO
(Input)
MSB
Valid
LSB
Valid
152
153
MOSI
(Output)
MSB
LSB
161
162
163
HREQ
(Input)
AA0272
Figure 2-19 SPI Master Timing (CPHA = 1)
2-50
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Specifications
Serial Host Interface SPI Protocol Timing
SS
(Input)
143
141
141
147
142
144
144
144
144
160
SCK (CPOL = 0)
(Input)
146
142
143
SCK (CPOL = 1)
(Input)
154
152
153
153
151
LSB
150
MISO
(Output)
MSB
148
148
149
149
MSB
Valid
MOSI
(Input)
LSB
Valid
157
159
HREQ
(Output)
AA0273
Figure 2-20 SPI Slave Timing (CPHA = 0)
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Specifications
2
Serial Host Interface (SHI) I C Protocol Timing
SS
(Input)
143
142
141
147
144
144
144
SCK (CPOL = 0)
(Input)
146
142
144
143
SCK (CPOL = 1)
(Input)
152
152
153
151
150
MISO
(Output)
MSB
LSB
148
148
149
149
MSB
Valid
LSB
Valid
MOSI
(Input)
157
158
HREQ
(Output)
AA0274
Figure 2-21 SPI Slave Timing (CPHA = 1)
2
2.12 SERIAL HOST INTERFACE (SHI) I C PROTOCOL TIMING
2-52
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Specifications
2
Serial Host Interface (SHI) I C Protocol Timing
2
Table 2-18 SHI I C Protocol Timing
Standard I2C*
Fast-Mode
Min
Standard-Mode
Unit
Symbol/
Expression
No.
Characteristics
Min
Max
Max
Tolerable spike width on SCL
or SDA
—
Filters bypassed
—
—
—
—
0
—
—
—
—
0
ns
ns
Narrow filters enabled
Wide filters enabled
50
50
100
100
100
400
ns
171 SCL clock frequency
172 Bus free time
FSCL
TBUF
kHz
4.7
4.7
4.0
4.7
4.0
—
—
—
1.3
0.6
0.6
1.3
1.3
—
—
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
pF
173 Start condition set-up time
174 Start condition hold time
175 SCL low period
TSU;STA
THD;STA
TLOW
—
—
—
—
176 SCL high period
THIGH
—
—
177 SCL and SDA rise time
178 SCL and SDA fall time
179 Data set-up time
T
R
1000
300
—
300
300
—
20 + 0.1 × Cb
T
F
—
20 + 0.1 × Cb
TSU;DAT
THD;DAT
TSU;STO
Cb
250
0.0
4.0
—
100
0.0
0.6
—
180 Data hold time
—
0.9
—
181 Stop condition set-up time
182 Capacitive load for each line
—
400
400
183 DSP clock frequency
Filters bypassed
FDSP
10.6
11.8
13.1
0.0
—
—
—
—
28.5
39.7
61.0
0.0
—
—
—
—
MHz
MHz
MHz
ns
Narrow filters enabled
Wide filters enabled
184 HREQ in deassertion to last
SCL edge
tSU;RQI
(HREQ in set-up time)
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Specifications
2
Serial Host Interface (SHI) I C Protocol Timing
2
Table 2-18 SHI I C Protocol Timing (continued)
Standard I2C*
Standard-Mode
Fast-Mode
Min
Unit
Symbol/
No.
Characteristics
Expression
Min
Max
Max
186 First SCL sampling edge to
HREQ output deassertion2
TNG;RQO
ns
Filters bypassed
Narrow filters enabled
Wide filters enabled
—
—
—
50
—
—
—
50
2 × TC + 30
2 × TC + 120
2 × TC + 208
TAS;RQO
140
228
140
228
187 Last SCL edge to HREQ out-
put not deasserted2
ns
ns
Filters bypassed
Narrow filters enabled
Wide filters enabled
50
—
—
—
50
—
—
—
2 × TC + 30
2 × TC + 80
2 × TC + 135
TAS;RQI
100
155
100
155
188 HREQ in assertion to first SCL
edge
0.5 × TI2CCP
-
0.5 × TC - 21
Filters bypassed
Narrow filters enabled
Wide filters enabled
4327
4282
4238
—
—
—
927
882
838
—
—
—
RP (min) = 1.5 k¾
2.12.1 Programming the Serial Clock
2
The programmed serial clock cycle, TI CCP, is specified by the value of the HDM[5:0] and HRS bits of the
HCKR (SHI clock control register).
2
The expression for TI CCP is
TI2CCP = [TC × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
where
— HRS is the prescaler rate select bit. When HRS is cleared, the fixed
divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.
— HDM[7:0] are the divider modulus select bits.
— A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected.
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Specifications
2
Serial Host Interface (SHI) I C Protocol Timing
In I2C mode, the user may select a value for the programmed serial clock cycle from
6 × TC
(if HDM[5:0] = $02 and HRS = 1)
to
4096 × TC
(if HDM[7:0] = $FF and HRS = 0)
2
The programmed serial clock cycle (TI CCP), SCL rise time (TR), and the filters selected should be chosen
in order to achieve the desired SCL frequency, as shown in Table 2-19.
Table 2-19 SCL Serial Clock Cycle generated as Master
2
Filters bypassed
T
+ 2.5 × TC + 45ns + T
I CCP
R
2
Narrow filters enabled T
+ 2.5 × TC + 135ns + T
+ 2.5 × TC + 223ns + T
I CCP
R
R
2
Wide filters enabled
T
I CCP
EXAMPLE:
For DSP clock frequency of 100 MHz (i.e. TC = 10ns), operating in a standard-mode I2C environment
(FSCL = 100 KHz (i.e. TSCL = 10µs), TR = 1000ns), with filters bypassed
2
TI CCP = 10µs - 2.5×10ns - 45ns - 1000ns = 8930ns
Choosing HRS = 0 gives
HDM[7:0] = 8930ns / (2× 10ns× 8) - 1 = 55.8
Thus the HDM[7:0] value should be programmed to $38 (=56).
171
173
176
175
SCL
SDA
177
180
178
172
179
MSB
LSB
ACK
Stop
Stop
Start
174
188
186
182
183
187
189
184
HREQ
AA0275
2
Figure 2-22 I C Timing
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Specifications
Enhanced Serial Audio Interface Timing
2.13 ENHANCED SERIAL AUDIO INTERFACE TIMING
Table 2-20 Enhanced Serial Audio Interface Timing
Cond-i
tion4
Characteristics1, 2, 3
No.
Symbol
Expression
Min
Max
Unit
430 Clock cycle5
tSSICC
4 × T
40.0
30.0
40.0
—
—
—
i ck
x ck
x ck
ns
C
3 × T
C
TXC:max[3*tc;
t454]
431 Clock high period
ns
ns
—
—
2 × T − 10.0
10.0
15.0
—
—
C
• For internal clock
• For external clock
432 Clock low period
1.5 × T
C
2 × T − 10.0
10.0
15.0
—
—
C
• For internal clock
1.5 × T
C
• For external clock
433 RXC rising edge to FSR out (bl) high
—
—
—
—
—
—
—
—
—
—
—
—
37.0
22.0 i ck a
x ck
ns
ns
ns
ns
ns
ns
ns
ns
ns
434 RXC rising edge to FSR out (bl) low
435 RXC rising edge to FSR out (wr) high6
436 RXC rising edge to FSR out (wr) low6
437 RXC rising edge to FSR out (wl) high
438 RXC rising edge to FSR out (wl) low
—
—
—
—
—
—
—
—
—
—
37.0
22.0 i ck a
x ck
—
—
39.0
24.0 i ck a
x ck
—
—
39.0
24.0 i ck a
x ck
—
—
36.0
21.0 i ck a
x ck
—
—
37.0
22.0 i ck a
x ck
439 Data in setup time before RXC (SCK in syn-
chronous mode) falling edge
0.0
19.0
—
—
x ck
i ck
440 Data in hold time after RXC falling edge
5.0
3.0
—
—
x ck
i ck
441 FSR input (bl, wr) high before RXC falling
edge 6
23.0
1.0
—
—
x ck
i ck a
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Specifications
Enhanced Serial Audio Interface Timing
Table 2-20 Enhanced Serial Audio Interface Timing (continued)
Cond-i
tion4
Characteristics1, 2, 3
No.
Symbol
Expression
Min
Max
Unit
442 FSR input (wl) high before RXC falling edge
443 FSR input hold time after RXC falling edge
444 Flags input setup before RXC falling edge
445 Flags input hold time after RXC falling edge
446 TXC rising edge to FST out (bl) high
447 TXC rising edge to FST out (bl) low
448 TXC rising edge to FST out (wr) high6
449 TXC rising edge to FST out (wr) low6
450 TXC rising edge to FST out (wl) high
451 TXC rising edge to FST out (wl) low
—
—
1.0
23.0
—
—
x ck
i ck a
ns
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.0
0.0
—
—
x ck
i ck a
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.0
19.0
—
—
x ck
i ck s
6.0
0.0
—
—
x ck
i ck s
—
—
29.0
15.0
x ck
i ck
—
—
31.0
17.0
x ck
i ck
—
—
31.0
17.0
x ck
i ck
—
—
33.0
19.0
x ck
i ck
—
—
30.0
16.0
x ck
i ck
—
—
31.0
17.0
x ck
i ck
452 TXC rising edge to data out enable from
high impedance
—
—
31.0
17.0
x ck
i ck
453 TXC rising edge to transmitter #0 drive
enable assertion
—
—
34.0
20.0
x ck
i ck
454 TXC rising edge to data out valid
23 + 0.5 × T
—
—
28.0
21.0
x ck
i ck
C
21.0
455 TXC rising edge to data out high
impedance7
—
—
—
—
—
—
—
—
31.0
16.0
x ck
i ck
ns
ns
ns
456 TXC rising edge to transmitter #0 drive
enable deassertion7
—
—
34.0
20.0
x ck
i ck
457 FST input (bl, wr) setup time before TXC
falling edge6
2.0
21.0
—
—
x ck
i ck
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Specifications
Enhanced Serial Audio Interface Timing
Table 2-20 Enhanced Serial Audio Interface Timing (continued)
Cond-i
tion4
Characteristics1, 2, 3
No.
Symbol
Expression
Min
Max
Unit
458 FST input (wl) to data out enable from high
impedance
—
—
—
27.0
—
—
ns
459 FST input (wl) to transmitter #0 drive enable
assertion
—
—
—
—
—
—
—
—
—
31.0
ns
ns
ns
ns
460 FST input (wl) setup time before TXC falling
edge
2.0
21.0
—
—
x ck
i ck
461 FST input hold time after TXC falling edge
4.0
0.0
—
—
x ck
i ck
462 Flag output valid after TXC rising edge
—
—
32.0
18.0
x ck
i ck
463 HCKR/HCKT clock cycle
—
—
—
—
—
—
40.0
—
—
ns
ns
ns
464 HCKT input rising edge to TXC output
465 HCKR input rising edge to RXC output
27.5
27.5
—
Notes: 1. VCC = 3.16 V ± 0.16 V; TJ = 0°C to +105°C, CL = 50 pF
2. i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that TXC and RXC are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that TXC and RXC are the same clock)
3. bl = bit length
wl = word length
wr = word length relative
4. TXC(SCKT pin) = transmit clock
RXC(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high speed clock
HCKR(HCKR pin) = receive high speed clock
5. For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the
bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit
length frame sync signal), until the one before last bit clock of the first word in frame.
7. Periodically sampled and not 100% tested
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Specifications
Enhanced Serial Audio Interface Timing
430
431
432
TXC
(Input/Output
)
446
447
FST (Bit)
Out
450
451
FST (Word)
Out
454
452
454
455
First Bit
Last Bit
Data Out
459
Transmitter
#0 Drive
Enable
457
453
456
461
460
FST (Bit) In
458
461
FST (Word)
In
462
See Note
Flags Out
Note: In network mode, output flag transitions can occur at the start of each time slot
within the frame. In normal mode, the output flag state is asserted for the entire
frame period.
AA0490
Figure 2-23 ESAI Transmitter Timing
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Enhanced Serial Audio Interface Timing
430
431
432
RXC
(Input/Output)
433
434
FSR (Bit)
Out
437
438
FSR (Word)
Out
440
439
443
Data In
Last Bit
First Bit
441
FSR (Bit)
In
442
443
445
FSR (Word)
In
444
Flags In
AA0491
Figure 2-24 ESAI Receiver Timing
HCKT
463
SCKT(output)
464
Figure 2-25 ESAI HCKT Timing
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Specifications
GPIO Timing
HCKR
463
SCKR (output)
465
Figure 2-26 ESAI HCKR Timing
2.14 GPIO TIMING
Table 2-21 GPIO Timing
Characteristics1
EXTAL edge to GPIO out valid (GPIO out delay time)
No.
Expression
Min Max Unit
4902
—
32.8
ns
491 EXTAL edge to GPIO out not valid (GPIO out hold time)
492 GPIO In valid to EXTAL edge (GPIO in set-up time)
493 EXTAL edge to GPIO in not valid (GPIO in hold time)
4.8
10.2
1.8
—
—
—
—
ns
ns
ns
ns
4942
Fetch to EXTAL edge before GPIO change
6.75 × TC-1.8
65.7
495 GPIO out rise time
—
—
—
—
13
13
ns
ns
496 GPIO out fall time
Notes: 1. VCC = 3.3 V ± 0.16 V; TJ = 0°C to +105°C, CL = 50 pF
2. Valid only when PLL enabled with multiplication factor equal to one.
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Specifications
GPIO Timing
EXTAL
(Input)
490
491
GPIO
(Output)
492
493
GPIO
(Input)
Valid
A0–A17
494
Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO
and R0 contains the address of GPIO data register.
GPIO
(Output)
495
496
Figure 2-27 GPIO Timing
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Specifications
JTAG Timing
2.15 JTAG TIMING
Table 2-22 JTAG Timing
All frequencies
No.
Characteristics
Unit
Min
Max
500 TCK frequency of operation (1/(TC × 3); maximum 22 MHz)
501 TCK cycle time in Crystal mode
502 TCK clock pulse width measured at 1.5 V
503 TCK rise and fall times
0.0
45.0
20.0
0.0
22.0
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
3.0
—
504 Boundary scan input data setup time
505 Boundary scan input data hold time
506 TCK low to output data valid
5.0
24.0
0.0
—
40.0
40.0
—
507 TCK low to output high impedance
508 TMS, TDI data setup time
0.0
5.0
509 TMS, TDI data hold time
25.0
0.0
—
510 TCK low to TDO data valid
44.0
44.0
511 TCK low to TDO high impedance
Notes: 1. VCC = 3.3 V ± 0.16 V; TJ = 0°C to +105°C, CL = 50 pF
0.0
2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
501
502
502
VM
VM
VIH
TCK
(Input)
VIL
503
503
AA0496
Figure 2-28 Test Clock Input Timing Diagram
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Specifications
JTAG Timing
VIH
TCK
(Input)
VIL
504
505
Data
Inputs
Input Data Valid
506
507
506
Data
Output Data Valid
Outputs
Data
Outputs
Data
Outputs
Output Data Valid
AA0497
Figure 2-29 Boundary Scan (JTAG) Timing Diagram
VIH
509
Input Data Valid
TCK
VIL
(Input)
508
TDI
TMS
(Input)
510
TDO
(Output)
Output Data Valid
511
TDO
(Output)
510
TDO
(Output)
Output Data Valid
AA0498
Figure 2-30 Test Access Port Timing Diagram
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SECTION 3
PACKAGING
3.1
PIN-OUT AND PACKAGE INFORMATION
This section provides information about the available package for this product, including diagrams of the
package pinouts and tables describing how the signals described in Section 1, Signal/Connection
Descriptions are allocated for the package. The DSP56364 is available in a 100-pin TQFP package.
Table 3-1 and Table 3-2show the pin/name assignments for the packages.
3.1.1
TQFP Package Description
Top view of the 100-pin TQFP package is shown in Figure 3-1 with its pin-outs. The 100-pin TQFP
package mechanical drawing is shown in Figure 3-2.
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Packaging
Pin-out and Package Information
MODD
MODB
1
2
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
D0
A17
MODA
3
A16
FST
4
GNDA
VCCA
A15
FSR
5
SCKT
6
SCKR
7
A14
VCCS
8
A13
GNDS
9
A12
HCKT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VCCLQ
GNDQ
GNDA
VCCA
A11
VCCLQ
GNDQ
DSP56364
100-Pin TQPF
HCKR
SDO0
VCCHQ
SDO1
VCCQH
A10
SDO2/SDI3
SDO3/SDI2
SDO4/SDI1
SDO5/SDI0
VCCS
A9
A8
A7
GNDA
VCCA
A6
GNDS
SS/HA2
MOSI/HA0
MISO/SDA
A5
A4
A3
Figure 3-1 DSP56364 100-Pin Thin Quad Flat Pack (TQFP), Top View
3-2
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Pin-out and Package Information
Table 3-1 DSP56364 100-Pin TQFP Signal Identification by Pin Number
Pin
No.
Pin
No.
Pin
No.
Pin
No.
Signal Name
Signal Name
Signal Name
A3
Signal Name
D1
1
MODD/IRQD
MODB/IRQB
MODA/IRQA
FST
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SCK/SCL
HREQ
PINIT/NMI
RESET
No Connect
VCCP
PCAP
GNDP
EXTAL
VCCHQ
GNDQ
VCCLQ
TA
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
2
A4
D2
3
A5
D3
4
A6
VCCD
GNDD
D4
5
FSR
VCCA
GNDA
A7
6
SCKT
7
SCKR
D5
8
VCCS
A8
D6
9
GNDS
A9
D7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
HCKT
A10
No Connect
No Connect
VCCLQ
GNDQ
VCCHQ
No Connect
GPIO0
VCCS
GNDS
GPIO1
GPIO2
GPIO3
TDO
VCCLQ
GNDQ
VCCHQ
A11
HCKR
VCCA
GNDA
GNDQ
VCCLQ
A12
SDO0
CAS
VCCHQ
SDO1
WR
RD
SDO2/SDI3
SDO3/SDI2
SDO4/SDI1
SDO5/SDI0
VCCS
VCCC
GNDC
AA1/RAS1
AA0/RAS0
A0
A13
A14
A15
VCCA
GNDA
A16
GNDS
A1
SS/HA2
MOSI/HA0
MISO/SDA
VCCQ
GNDQ
A2
TDI
A17
TCK
D0
100 TMS
Notes:Signal names are based on configured functionality. Most pins supply a single signal. Some pins provide a
signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is
deasserted, but act as interrupt lines during operation.
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Pin-out and Package Information
Table 3-2 DSP56364 100-Pin TQFP Signal Identification by Name
Pin
No.
Pin
No.
Pin
No.
Pin
No.
Signal Name
Signal Name
Signal Name
Signal Name
A0
A1
46
47
60
62
67
68
69
70
73
74
50
51
52
53
54
57
58
59
45
44
39
75
76
77
78
D4
81
82
83
84
34
5
HCKR
HCKT
13
10
27
25
3
SDO4/SDI1
TA
19
38
99
98
97
100
48
55
63
71
42
79
15
35
61
89
11
37
66
87
31
8
D5
A10
A11
A12
A13
A14
A15
A16
A17
A2
D6
HREQ
TCK
D7
MISO/SDA
MODA/IRQA
MODB/IRQB
MODD/IRQD
MOSI/HA0
No Connect
No Connect
No Connect
No Connect
PCAP
TDI
EXTAL
FSR
TD0
2
TMS
FST
4
1
VCCA
VCCA
VCCA
VCCA
VCCC
VCCD
VCCHQ
VCCHQ
VCCHQ
VCCHQ
VCCLQ
VCCLQ
VCCLQ
VCCLQ
VCCP
VCCS
VCCS
VCCS
WR
GNDA
GNDA
GNDA
GNDA
GNDC
GNDD
GNDP
GNDQ
GNDQ
GNDQ
GNDQ
GNDS
GNDS
GNDS
GPIO0
GPIO1
GPIO2
GPIO3
49
56
64
72
43
80
33
12
36
65
88
9
24
30
85
86
90
32
28
41
29
26
7
A3
A4
A5
PINIT/NMI
RD
A6
A7
RESET
A8
SCK/SCL
SCKR
A9
AA0
AA1
CAS
D0
SCKT
6
22
93
91
94
95
96
SDO0
14
16
20
23
17
18
SDO1
SDO5/SDI0
SS/HA2
D1
21
92
40
D2
SDO2/SDI3
SDO3/SDI2
D3
3-4
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Packaging
Pin-out and Package Information
3.1.2
TQFP Package Mechanical Drawing
Figure 3-2 DSP56364 100-pin TQFP Package
MOTOROLA
DSP56364 Advance Information
3-5
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Packaging
Ordering Drawings
3.2
ORDERING DRAWINGS
The detailed package drawing is available on the Motorola web page at:
http://mot.sps.com/cgi-bin/cases
Use package 983 for the search.
3-6
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
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SECTION 4
DESIGN CONSIDERATIONS
4.1
THERMAL DESIGN CONSIDERATIONS
An estimation of the chip junction temperature, TJ, in °C can be obtained from the following equation:
= T + (P × R
T
)
J
A
D
θJA
Where:
TA = ambient temperature °C
RqJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package W
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance
and a case-to-ambient thermal resistance.
R
= R
+ R
θJA
θJC
θCA
Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
R
θJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow
around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB),
or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated
through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations
where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of
the device thermal performance may need the additional modeling capability of a system level thermal
simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether
the thermal performance is adequate, a system level model may be appropriate.
A complicating factor is the existence of three common ways for determining the junction-to-case thermal
resistance in plastic packages.
•
To minimize temperature variation across the surface, the thermal resistance is measured from the
junction to the outside surface of the package (case) closest to the chip mounting area when that
surface has a proper heat sink.
•
•
To define a value approximately equal to a junction-to-board thermal resistance, the thermal
resistance is measured from the junction to where the leads are attached to the case.
If the temperature of the package case (TT) is determined by a thermocouple, the thermal
resistance is computed using the value obtained by the equation
(TJ – TT)/PD.
MOTOROLA
DSP56364 Advance Information
4-1
For More Information On This Product,
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Freescale Semiconductor, Inc.
Design Considerations
Electrical Design Considerations
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using
the first definition. From a practical standpoint, that value is also suitable for determining the junction
temperature from a case thermocouple reading in forced convection environments. In natural convection,
using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple
reading on the case of the package will estimate a junction temperature slightly hotter than actual
temperature. Hence, the new thermal metric, thermal characterization parameter or ΨJT, has been defined
to be (TJ – TT)/PD. This value gives a better estimate of the junction temperature in natural convection
when using the surface temperature of the package. Remember that surface temperature readings of
packages are subject to significant errors caused by inadequate attachment of the sensor to the surface
and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge
thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
4.2
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
This device contains circuitry protecting
against damage due to high static voltage or
electrical fields. However, normal precautions
should be taken to avoid exceeding maximum
voltage ratings. Reliability of operation is
enhanced if unused inputs are tied to an
appropriate logic voltage level (e.g., either
GND or V ). The suggested value for a
CC
pullup or pulldown resistor is 10 k ohm.
Use the following list of recommendations to assure correct DSP operation:
•
•
•
Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from
the board ground to each GND pin.
Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the four sides of
the package to connect the VCC power source to GND.
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and
GND pins are less than 1.2 cm (0.5 inch) per capacitor lead.
•
•
Use at least a four-layer PCB with two inner layers for VCC and GND.
Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.
This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB,
IRQD, and TA pins. Maximum PCB trace lengths on the order of 15 cm (6 inches) are
recommended.
•
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the VCC and GND circuits.
4-2
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Design Considerations
Power Consumption Considerations
•
All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the three pins
with internal pull-up resistors (TMS, TDI, TCK).
•
•
Take special care to minimize noise levels on the VCCP and GNDP pins.
If multiple DSP56364 devices are on the same board, check for cross-talk or excessive spikes on
the supplies due to synchronous operation of the devices.
•
•
RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied
before deassertion of RESET.
At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip VCC
never exceeds 3.95 V.
4.3
POWER CONSUMPTION CONSIDERATIONS
Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current
consumption are described in this section. Most of the current consumed by CMOS devices is alternating
current (ac), which is charging and discharging the capacitances of the pins and internal nodes.
Current consumption is described by the following formula:
I = C × V × f
where
C = node/pin capacitance
V = voltage swing
f = frequency of node/pin toggle
Example 1 Current Consumption
For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 100 MHz
clock, toggling at its maximum possible rate (50 MHz), the current consumption is
–12
6
I = 50 × 10
× 3.3 × 50 × 10 = 8.25mA
The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses
on best-case operation conditions, which is not necessarily a real application case. The typical internal
current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions.
For applications that require very low current consumption, do the following:
•
•
•
•
•
•
Set the EBD bit when not accessing external memory.
Minimize external memory accesses and use internal memory accesses.
Minimize the number of pins that are switching.
Minimize the capacitive load on the pins.
Connect the unused inputs to pull-up or pull-down resistors.
Disable unused peripherals.
MOTOROLA
DSP56364 Advance Information
4-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Design Considerations
PLL Performance Issues
One way to evaluate power consumption is to use a current per MIPS measurement methodology to
minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A
benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test
current measurements, and the following equation to derive the current per MIPS value.
I ⁄ MIPS = I ⁄ MHz = (I
– I
typF2 typF1
) ⁄ (F2 – F1)
where :
ItypF2 = current at F2
ItypF1 = current at F1
F2 = high frequency (any specified operating frequency)
F1 = low frequency (any specified operating frequency lower than F2)
Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1
could be 33 MHz. The degree of difference between F1 and F2 determines the
amount of precision with which the current rating can be determined for an
application.
4.4
PLL PERFORMANCE ISSUES
The following explanations should be considered as general observations on expected PLL behavior.
There is no testing that verifies these exact numbers. These observations were measured on a limited
number of parts and were not verified over the entire temperature and voltage ranges.
4.4.1
Input (EXTAL) Jitter Requirements
The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is
slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of
the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be 2%.
The phase and frequency jitter performance results are only valid if the input jitter is less than the
prescribed values.
4-4
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
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Freescale Semiconductor, Inc.
SECTION 5
ORDERING INFORMATION
Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability
and to place an order.
Table 5-1 Ordering Information
Supply
Voltage
Pin
Count
Frequency
(MHz)
Part
Package Type
Order Number
DSP56364
3.3 V
Thin quad flat pack (TQFP)
Quad flat pack (QFP)
100
112
100
100
XCB56364FU100
XCB56364PV100
Notes: 1. The DSP56364 can include factory-programmed ROM. The listed ‘B’ ROM code is a generic unused
ROM available to any customer. Variations will be supported for Dolby digital (AC-3), DTS, MPEG2,
and other features. These products are only available to authorized licensees of those technologies.
Please consult the web site at www.dspaudio.motorola.com for current availability.
2. Future products in the DSP56364 family may include other ROM-based options. For additional
information on future part development, or to request customer-specific ROM-based support, call
your local Motorola Semiconductor sales office or authorized distributor.
MOTOROLA
DSP56364 Advance Information
5-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
THIS PAGE INTENTIONALLY LEFT BLANK
For More Information On This Product,
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Freescale Semiconductor, Inc.
APPENDIX A
IBIS MODEL
IBIS Model
[IBIS Ver]
[File name]
[File Rev]
[Date]
3.2
56364_e.ibs
e
Feb 13, 2002
56364
[Component]
[Manufacturer]
[Package]
| variable
R_pkg
L_pkg
C_pkg
MOTOROLA SEMI CONDUCTOR Ltd.
typ
min
max
75.0m
45.0m
2.5nH
1.3pF
22.0m
1.1nH
1.2pF
4.3nH
1.4pF
[Pin]
C_pin
1
2
3
4
5
6
7
signal_name
model_name
R_pin
L_pin
irqd_
ipad5v_io
ipad5v_io
ipad5v_io
ipad5v_io
ipad5v_io
ipad5v_io
ipad5v_io
power
irqb_
irqa_
fst
fsr
sckt
sckr
vccs
8
9
gnds
gnd
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
32
33
34
35
hckt
vcclq
gndq
hckr
sdo0
ipad5v_io
power
gnd
ipad5v_io
ipad5v_io
power
ipad5v_io
ipad5v_io
ipad5v_io
ipad5v_io
ipad5v_io
power
vcchq
sdo1
sdo2/sdi3
sdo3/sdi2
sdo4/sdi1
sdo5/sdi0
vccs
gnds
gnd
ss_/ha2
mosi/ha0
miso/sda
sck/scl
hreq_
pinit/nmi_
reset_
vccp
pcap
gndp
extal
vcchq
ipad5v_io
ipad5v_io
ipad5i_io
ipad5i_io
ipad5i_io
ipad5v_io
ipad5v_io
power
power
gnd
ipadex_i
power
MOTOROLA
DSP56364 Advance Information
A-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
36
gndq
vcclq
ta_
cas_
wr_
gnd
power
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
87
88
89
91
ipadn_io
ipadm_3st
ipadn_io
ipadn_io
power
rd_
vccc
gndc
aa1/ras1_
aa0/ras0_
a0
gnd
ipado_3st
ipado_3st
ipada_3st
ipada_3st
power
a1
vccq
gndq
a2
a3
a4
a5
a6
vcca
gnda
a7
a8
a9
a10
vcchq
a11
vcca
gnda
gndq
vcclq
a12
a13
a14
a15
vcca
gnda
a16
a17
d0
d1
d2
d3
vccd
gndd
d4
d5
d6
gnd
ipada_3st
ipada_3st
ipada_3st
ipada_3st
ipada_3st
power
gnd
ipada_3st
ipada_3st
ipada_3st
ipada_3st
power
ipada_3st
power
gnd
gnd
power
power
ipada_3st
ipada_3st
ipada_3st
power
gnd
ipada_3st
ipada_3st
ipadd_io
ipadd_io
ipadd_io
ipadd_io
power
gnd
ipadd_io
ipadd_io
ipadd_io
ipadd_io
power
gnd
power
ipad5v_io
d7
vcclq
gndq
vcchq
gpio0
A-2
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
92
93
94
95
96
97
98
99
100
vccs
gnds
gpio1
gpio2
gpio3
tdo
tdi
tck
tms
power
gnd
ipad5v_io
ipad5v_io
ipad5v_io
ipad5f_io
ipad5f_io
ipad5f_io
ipad5f_io
[Model]
ipad5f_io
| ""
Model_type
Vinl = 0.8
Vinh = 2
| variable
C_comp
I/O
typ
1.96p
typ
min
1.87p
min
max
2.06p
max
120.0
| variable
[Temperature Range] 40.0
0.0
| variable
[Voltage Range]
|
typ
3.30V
min
3.00V
max
3.60V
[Pulldown]
| pulldown in the table = pulldown subtract gnd_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-142.303u -76.239u -215.182u
-149.700u -80.226u -226.432u
-157.861u -84.616u -238.866u
-166.908u -89.472u -252.678u
-176.992u -94.869u -268.107u
-188.295u -100.900u -285.446u
-201.049u -107.679u -305.068u
-215.545u -115.349u -327.446u
-232.155u -124.094u -353.191u
-251.367u -134.145u -383.107u
-273.825u -145.808u -418.273u
-300.403u -159.488u -460.167u
-332.314u -175.737u -510.874u
-371.286u -195.318u -573.418u
-419.868u -219.325u -652.360u
-481.968u -249.369u -754.892u
-563.882u -287.925u -893.013u
-676.382u -338.973u
-839.410u -409.300u
-1.094m -511.367u
-1.537m -670.350u
-2.451m -943.845u
-1.088m
-1.383m
-1.873m
-2.819m
-5.162m
-4.857m
-10.606m
-14.267m
-13.851m
-12.481m
-10.883m
-1.486m -12.214m
-2.746m -20.764m
-5.259m -21.749m
-7.108m -20.142m
-7.168m -18.211m
-6.348m -15.981m
MOTOROLA
DSP56364 Advance Information
A-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
-9.156m
-7.378m
-5.572m
-3.741m
-1.885m
1.898p
1.857m
3.630m
5.323m
6.936m
-5.339m -13.503m
-4.288m -10.922m
-3.224m
-2.154m
-1.080m
1.419p
-8.282m
-5.584m
-2.825m
1.871p
1.057m
2.800m
2.064m
5.482m
3.023m
8.052m
3.935m
4.798m
5.611m
6.371m
7.078m
7.726m
10.508m
12.849m
15.073m
17.176m
19.155m
21.011m
56.704m
60.708m
64.383m
67.726m
70.735m
73.414m
75.766m
77.783m
79.441m
80.724m
81.651m
82.294m
82.744m
83.074m
83.332m
83.543m
83.724m
83.884m
84.030m
84.165m
84.290m
84.409m
84.515m
84.491m
81.077m
79.736m
80.276m
82.430m
85.482m
91.743m
94.219m
96.276m
98.249m
8.467m
9.915m
11.275m
12.546m
13.723m
36.925m
39.391m
41.612m
43.585m
45.305m
46.773m
47.997m
48.985m
49.733m
50.257m
50.612m
50.858m
51.040m
51.182m
51.302m
51.405m
51.497m
51.581m
51.658m
51.727m
51.757m
51.229m
49.190m
49.441m
51.034m
54.363m
57.165m
58.834m
60.328m
61.725m
63.035m
64.319m
65.598m
66.836m
67.999m
69.069m
70.046m
70.938m
20.745m
22.074m
23.244m
24.247m
25.079m
25.741m
26.251m
26.633m
26.905m
27.092m
27.223m
27.321m
27.399m
27.465m
27.522m
27.572m
27.618m
27.657m
27.674m
27.587m
27.577m
28.700m
30.042m
31.171m
32.199m
33.153m
34.039m
34.872m
35.686m
36.495m
37.291m
38.051m
38.755m
39.394m 100.059m
39.962m 101.849m
40.453m 103.628m
40.840m 105.345m
41.065m 106.956m
A-4
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
4.80V
4.90V
5.00V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
71.751m
72.476m
73.089m
73.531m
73.651m
72.901m
71.005m
70.389m
70.321m
70.361m
70.422m
70.489m
70.557m
70.624m
70.690m
70.753m
70.817m
70.881m
70.949m
40.952m 108.448m
40.067m 109.826m
39.395m 111.106m
39.313m 112.297m
39.358m 113.400m
39.410m 114.401m
39.460m 115.267m
39.508m 115.917m
39.552m 116.139m
39.595m 114.582m
39.634m 111.344m
39.672m 110.612m
39.708m 110.449m
39.743m 110.455m
39.777m 110.515m
39.812m 110.595m
39.848m 110.686m
39.886m 110.783m
39.929m 110.885m
|
[Pullup]
| pullup in the table = pullup subtract power_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
75.797u
90.464u
7.914u 161.477u
17.699u 181.779u
27.445u 202.314u
37.119u 223.007u
46.694u 243.785u
56.144u 264.581u
65.447u 285.332u
74.582u 305.982u
83.527u 326.474u
92.262u 346.757u
105.160u
119.836u
134.451u
148.966u
163.342u
177.543u
191.536u
205.285u
218.754u 100.766u 366.776u
231.907u 109.016u 386.478u
244.706u 116.988u 405.807u
257.106u 124.659u 424.699u
269.061u 131.998u 443.089u
280.519u 138.978u 460.899u
291.423u 145.565u 478.046u
301.710u 151.723u 494.457u
311.348u 157.417u 521.406u
729.899u 162.626u
10.510m 445.517u
1.612m
14.832m
13.576m
12.231m
10.854m
9.483m
8.169m
6.971m
5.921m
4.953m
9.629m
8.670m
7.693m
6.732m
5.825m
5.004m
4.261m
3.549m
6.444m
5.833m
5.190m
4.551m
3.942m
3.382m
2.869m
2.381m
MOTOROLA
DSP56364 Advance Information
A-5
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-0.40V
-0.30V
-0.20V
-0.10V
-0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
2.841m
2.135m
1.437m 951.489u
1.902m
1.426m
3.978m
2.987m
2.003m
1.005m
24.081p
722.340u 478.341u
22.329p
-708.556u -465.927u -990.647u
3.311p
-1.377m -903.637u
-1.943m
-2.832m
-3.702m
-4.537m
-5.336m
-6.096m
-6.817m
-7.499m
-8.139m
-8.737m
-9.292m
-9.802m
-2.007m
-2.614m
-3.192m
-3.738m
-4.253m
-4.736m
-5.185m
-5.600m
-5.980m
-6.324m
-1.319m
-1.710m
-2.079m
-2.423m
-2.742m
-3.037m
-3.305m
-3.547m
-3.762m
-3.948m
-6.631m -17.709m
-29.730m -18.279m -10.265m
-30.749m -18.747m -45.983m
-31.630m -19.131m -47.620m
-32.393m -19.454m -49.086m
-33.055m -19.730m -50.392m
-33.632m -19.973m -51.551m
-34.135m -20.188m -52.571m
-34.575m -20.381m -53.463m
-34.960m -20.556m -54.240m
-35.302m -20.715m -54.917m
-35.608m -20.861m -55.510m
-35.884m -20.997m -56.035m
-36.137m -21.123m -56.505m
-36.370m -21.241m -56.932m
-36.586m -21.352m -57.322m
-36.788m -21.457m -57.683m
-36.978m -21.556m -58.019m
-37.157m -21.650m -58.334m
-37.327m -21.741m -58.631m
-37.489m -21.827m -58.913m
-37.643m -21.909m -59.181m
-37.791m -21.989m -59.436m
-37.933m -22.067m -59.681m
-38.070m -22.143m -59.916m
-38.202m -22.216m -60.142m
-38.332m -22.284m -60.361m
-38.460m -22.352m -60.573m
-38.590m -22.420m -60.780m
-38.714m -22.490m -60.986m
-38.828m -22.561m -61.194m
-38.949m -22.635m -61.406m
-39.076m -22.713m -61.623m
-39.211m -22.798m -61.819m
-39.357m -22.892m -62.024m
-39.516m -22.997m -62.254m
A-6
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
4.90V
5.00V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-39.693m -23.116m -62.506m
-39.893m -23.253m -62.785m
-40.121m -23.411m -63.098m
-40.384m -23.595m -63.453m
-40.689m -23.801m -63.860m
-41.043m -24.032m -64.330m
-41.444m -24.288m -64.874m
-41.886m -24.570m -65.505m
-42.370m -24.880m -66.214m
-42.899m -25.217m -66.983m
-43.473m -25.585m -67.815m
-44.095m -25.983m -68.711m
-44.769m -26.415m -69.678m
-45.498m -26.884m -70.721m
-46.287m -27.390m -71.848m
-47.140m -27.929m -73.065m
-48.049m -28.487m -74.374m
-48.990m -29.080m -75.748m
|
[GND_clamp]
|
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
-1.875
-1.793
-1.074
-1.029
-2.155
-2.059
-1.963
-1.771
-1.675
-1.579
-1.483
-1.388
-1.292
-1.197
-1.102
-1.007
-1.711 -983.765m
-1.548 -893.931m
-1.466 -849.071m
-1.385 -804.256m
-1.303 -759.489m
-1.221 -714.777m
-1.140 -670.127m
-1.059 -625.548m
-977.735m -581.048m
-896.773m -536.642m
-735.446m -448.177m -817.634m
-655.171m -404.164m -723.409m
-575.242m -360.342m -629.587m
-495.760m -316.758m -536.295m
-416.878m -273.482m -443.730m
-338.839m -230.618m -352.222m
-262.067m -188.327m -262.384m
-187.395m -146.891m -175.533m
-116.756m -106.839m -95.231m
-16.024m -37.029m
-2.254m -14.319m
-6.612m
-2.370m
-476.015u
-85.877u -295.354u -147.930u
-8.033u -33.637u -9.999u
-432.304n -3.576u -310.975n
-20.874n -340.944n -8.593n
-964.564p -30.895n -258.649p
-72.583p -2.560n -43.910p
-2.883m -845.181u
MOTOROLA
DSP56364 Advance Information
A-7
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.10V
3.20V
3.30V
-33.685p -210.508p -34.610p
-27.665p -30.628p -29.748p
-22.754p
-18.303p
-14.129p
13.546p -25.110p
48.356p -20.906p
81.869p -16.971p
-9.979p 114.849p -13.050p
-5.833p 147.499p
-1.689p 179.924p
2.454p 212.188p
6.596p 244.335p
14.877p 308.388p
19.017p 340.335p
23.157p 372.250p
27.297p 404.143p
31.436p 436.027p
35.576p 467.910p
39.715p 499.805p
43.855p 531.722p
47.995p 563.675p
56.277p 627.761p
60.418p 659.933p
64.561p 692.106p
68.706p 723.142p
72.847p 751.973p
76.869p 780.264p
80.074p 808.442p
82.499p 835.513p
84.837p 860.391p
-9.130p
-5.210p
-1.291p
2.628p
10.466p
14.384p
18.302p
22.221p
26.139p
30.057p
33.974p
37.892p
41.810p
49.646p
53.564p
57.482p
61.400p
65.319p
69.237p
73.156p
77.065p
80.794p
86.195p
88.344p
90.478p
89.018p
89.573p
103.108p
1.265n
1.305n
1.593n
|
[POWER_clamp]
|
|Voltage
|
I(typ)
I(min)
I(max)
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.10V
-33.685p -340.944n -20.906p
-72.583p -3.576u -25.110p
-964.564p -33.637u -29.748p
-20.874n -295.354u -34.610p
-432.304n
-2.883m -43.910p
-8.033u -14.319m -258.649p
-85.877u -37.029m
-2.254m -106.839m
-8.593n
-9.999u
-16.024m -146.891m -147.930u
-55.636m -188.327m -845.181u
-116.756m -230.618m
-187.395m -273.482m
-2.370m
-6.612m
-262.067m -316.758m -33.199m
-338.839m -360.342m -95.231m
-416.878m -404.164m -175.533m
-495.760m -448.177m -262.384m
-655.171m -536.642m -443.730m
A-8
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-735.446m -581.048m -536.295m
-815.997m -625.548m -629.587m
-896.773m -670.127m -723.409m
-977.735m -714.777m -817.634m
-1.059 -759.489m -912.174m
-1.140 -804.256m
-1.221 -849.071m
-1.303 -893.931m
-1.466 -983.765m
-1.007
-1.102
-1.197
-1.388
-1.483
-1.579
-1.675
-1.771
-1.867
-1.548
-1.630
-1.711
-1.793
-1.875
-1.029
-1.074
-1.119
-1.164
-1.209
|
[Ramp]
|Voltage
|
I(typ)
I(min)
I(max)
dV/dt_f
|
dV/dt_r
2.04/136.004p 1.86/237.542p 2.23/85.504p
2.05/194.744p 1.86/343.805p 2.23/118.850p
R_load=10000ohms
| R_load was connected to ground for Ramp_up test and power for Ramp_dn
test
|
|End model
[Model]
ipad5i_io
I/O
| ""
Model_type
Vinl = 0.8
Vinh = 2
| variable
C_comp
typ
4.44p
typ
min
3.89p
min
max
4.56p
max
120.0
| variable
[Temperature Range] 40.0
0.0
| variable
[Voltage Range]
|
typ
3.30V
min
3.00V
max
3.60V
[Pulldown]
| pulldown in the table = pulldown subtract gnd_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-142.303u -76.239u -215.182u
-149.700u -80.226u -226.432u
-157.861u -84.616u -238.866u
-166.908u -89.472u -252.678u
-176.992u -94.869u -268.107u
-188.295u -100.900u -285.446u
-201.049u -107.679u -305.068u
-215.545u -115.349u -327.446u
-232.155u -124.094u -353.191u
-251.367u -134.145u -383.107u
-273.825u -145.808u -418.273u
-300.403u -159.488u -460.167u
MOTOROLA
DSP56364 Advance Information
A-9
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
-332.314u -175.737u -510.874u
-371.286u -195.318u -573.418u
-419.868u -219.325u -652.360u
-481.968u -249.369u -754.892u
-563.882u -287.925u -893.013u
-676.382u -338.973u
-839.410u -409.300u
-1.094m -511.367u
-1.537m -670.350u
-2.451m -943.845u
-1.088m
-1.383m
-1.873m
-2.819m
-5.162m
-4.857m
-10.606m
-14.267m
-13.851m
-12.481m
-10.883m
-9.156m
-7.378m
-5.572m
-3.741m
-1.885m
1.898p
-1.486m -12.214m
-2.746m -20.764m
-5.259m -21.749m
-7.108m -20.142m
-7.168m -18.211m
-6.348m -15.981m
-5.339m -13.503m
-4.288m -10.922m
-3.224m
-2.154m
-1.080m
1.419p
-8.282m
-5.584m
-2.825m
1.871p
1.857m
1.057m
2.800m
3.630m
2.064m
5.482m
5.323m
3.023m
8.052m
6.936m
8.467m
9.915m
3.935m
4.798m
5.611m
6.371m
7.078m
7.726m
10.508m
12.849m
15.073m
17.176m
19.155m
21.011m
56.704m
60.708m
64.383m
67.726m
70.735m
73.414m
75.766m
77.783m
79.441m
80.724m
81.651m
82.294m
82.744m
83.074m
83.332m
83.543m
83.724m
83.884m
84.030m
84.165m
84.290m
84.409m
11.275m
12.546m
13.723m
36.925m
39.391m
41.612m
43.585m
45.305m
46.773m
47.997m
48.985m
49.733m
50.257m
50.612m
50.858m
51.040m
51.182m
51.302m
51.405m
51.497m
51.581m
51.658m
51.729m
51.781m
51.640m
20.745m
22.074m
23.244m
24.247m
25.079m
25.741m
26.251m
26.633m
26.905m
27.092m
27.223m
27.321m
27.399m
27.465m
27.522m
27.572m
27.618m
27.658m
27.683m
27.643m
27.704m
28.793m
A-10
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
3.20V
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
50.282m
50.273m
51.871m
55.121m
57.228m
58.838m
60.328m
61.725m
63.035m
64.321m
65.602m
66.844m
68.012m
69.088m
70.072m
70.973m
71.794m
72.529m
73.152m
73.605m
73.737m
72.999m
71.115m
70.512m
70.457m
70.511m
70.586m
70.667m
70.749m
70.831m
70.911m
70.989m
71.068m
71.148m
71.230m
30.065m
31.174m
32.200m
33.153m
34.039m
34.872m
35.687m
36.498m
37.296m
38.059m
38.767m
39.409m 100.060m
39.982m 101.853m
40.478m 103.638m
40.871m 105.361m
41.102m 106.982m
40.996m 108.484m
40.118m 109.875m
39.453m 111.168m
39.379m 112.374m
39.432m 113.492m
39.492m 114.510m
39.551m 115.392m
39.608m 116.061m
39.661m 116.301m
39.713m 114.763m
39.762m 111.545m
39.809m 110.833m
39.855m 110.689m
39.899m 110.716m
39.944m 110.796m
39.988m 110.897m
40.034m 111.009m
40.083m 111.127m
40.136m 111.250m
84.519m
84.574m
83.365m
80.948m
81.423m
83.424m
87.158m
91.951m
94.228m
96.276m
98.249m
|
[Pullup]
| pullup in the table = pullup subtract power_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
357.190u 184.381u 591.381u
356.622u 184.121u 590.188u
356.193u 183.920u 589.287u
355.875u 183.765u 588.617u
355.641u 183.645u 588.129u
355.468u 183.550u 587.779u
355.340u 183.472u 587.528u
355.242u 183.405u 587.349u
355.163u 183.345u 587.218u
355.097u 183.288u 587.118u
355.036u 183.233u 587.036u
354.978u 183.177u 586.964u
354.920u 183.119u 586.896u
MOTOROLA
DSP56364 Advance Information
A-11
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
-0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
354.860u 183.060u 586.829u
354.799u 182.997u 586.762u
354.734u 182.931u 586.692u
354.666u 182.862u 586.621u
354.595u 182.788u 586.574u
354.559u 182.711u 597.934u
764.198u 182.650u
10.536m 460.815u
1.674m
14.880m
13.612m
12.257m
10.870m
9.492m
8.173m
6.972m
5.921m
4.953m
3.978m
2.985m
2.002m
1.005m
24.891p
9.648m
8.683m
7.701m
6.737m
5.827m
5.004m
4.262m
3.549m
2.841m
2.134m
6.455m
5.841m
5.195m
4.554m
3.944m
3.383m
2.870m
2.382m
1.902m
1.426m
1.434m 951.249u
721.882u 477.946u
23.094p
36.805p
-708.040u -465.659u -990.277u
-1.374m -903.549u
-1.941m
-2.832m
-3.702m
-4.537m
-5.336m
-6.096m
-6.817m
-7.499m
-8.139m
-8.737m
-9.292m
-9.802m
-2.007m
-2.614m
-3.192m
-3.738m
-4.253m
-4.736m
-5.185m
-5.600m
-5.980m
-6.324m
-1.319m
-1.710m
-2.079m
-2.423m
-2.742m
-3.037m
-3.305m
-3.547m
-3.762m
-3.948m
-6.631m -17.709m
-29.730m -18.279m -10.265m
-30.749m -18.747m -45.983m
-31.630m -19.131m -47.620m
-32.393m -19.454m -49.086m
-33.055m -19.730m -50.392m
-33.632m -19.973m -51.551m
-34.135m -20.188m -52.571m
-34.575m -20.381m -53.463m
-34.960m -20.556m -54.240m
-35.302m -20.715m -54.917m
-35.608m -20.861m -55.510m
-35.884m -20.997m -56.035m
-36.137m -21.123m -56.505m
-36.370m -21.241m -56.932m
-36.586m -21.352m -57.322m
-36.788m -21.457m -57.683m
-36.978m -21.556m -58.019m
-37.157m -21.650m -58.334m
-37.327m -21.741m -58.631m
A-12
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-37.489m -21.827m -58.913m
-37.643m -21.909m -59.181m
-37.791m -21.989m -59.436m
-37.933m -22.067m -59.681m
-38.070m -22.143m -59.916m
-38.202m -22.216m -60.142m
-38.332m -22.284m -60.361m
-38.460m -22.352m -60.573m
-38.590m -22.420m -60.780m
-38.714m -22.490m -60.986m
-38.828m -22.561m -61.194m
-38.949m -22.635m -61.406m
-39.076m -22.713m -61.623m
-39.211m -22.798m -61.819m
-39.357m -22.892m -62.024m
-39.516m -22.997m -62.254m
-39.693m -23.116m -62.506m
-39.893m -23.253m -62.785m
-40.121m -23.411m -63.098m
-40.384m -23.595m -63.453m
-40.689m -23.801m -63.860m
-41.043m -24.032m -64.330m
-41.444m -24.288m -64.874m
-41.886m -24.570m -65.505m
-42.370m -24.880m -66.214m
-42.899m -25.217m -66.983m
-43.473m -25.585m -67.815m
-44.095m -25.983m -68.711m
-44.769m -26.415m -69.678m
-45.498m -26.884m -70.721m
-46.287m -27.390m -71.848m
-47.140m -27.929m -73.065m
-48.049m -28.487m -74.374m
-48.990m -29.080m -75.748m
|
[GND_clamp]
|
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-1.90V
-1.80V
-1.875
-1.793
-1.074
-1.029
-2.155
-2.059
-1.963
-1.771
-1.675
-1.579
-1.483
-1.388
-1.292
-1.197
-1.102
-1.007
-1.711 -983.769m
-1.548 -893.934m
-1.466 -849.075m
-1.385 -804.259m
-1.303 -759.493m
-1.221 -714.781m
-1.140 -670.131m
-1.059 -625.551m
-977.740m -581.052m
-896.779m -536.646m
-735.452m -448.180m -817.639m
-655.177m -404.167m -723.415m
MOTOROLA
DSP56364 Advance Information
A-13
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.10V
3.20V
3.30V
-575.247m -360.345m -629.593m
-495.766m -316.761m -536.300m
-416.883m -273.485m -443.735m
-338.844m -230.621m -352.227m
-262.072m -188.330m -262.388m
-187.399m -146.893m -175.537m
-116.760m -106.842m -95.235m
-16.027m -37.031m
-2.255m -14.321m
-6.614m
-2.370m
-476.049u
-85.878u -295.501u -147.930u
-8.033u -33.646u -9.999u
-432.308n -3.576u -310.979n
-20.878n -340.971n -8.597n
-968.068p -30.900n -262.449p
-75.987p -2.564n -47.610p
-2.884m -845.183u
-36.990p -214.009p -38.210p
-30.869p -34.018p -33.249p
-25.858p
-21.307p
-17.033p
10.263p -28.510p
45.181p -24.206p
78.801p -20.171p
-12.783p 111.888p -16.150p
-8.537p 144.645p -12.130p
-4.293p 177.177p
-49.635f 209.548p
-8.110p
-4.091p
4.192p 241.802p -71.907f
12.674p 306.070p
16.914p 338.124p
21.154p 370.146p
25.393p 402.147p
29.633p 434.138p
-31.788p 466.129p
7.965p
11.984p
16.002p
20.020p
24.038p
28.056p
38.112p 498.131p -33.622p
42.352p 530.156p
46.592p 562.217p
55.074p 626.519p
59.316p 658.799p
63.559p 691.080p
67.803p 722.224p
72.044p 751.129p
76.162p 779.443p
79.409p 807.731p
81.838p 835.534p
84.178p 864.770p
36.092p
40.110p
48.146p
52.164p
56.182p
60.200p
64.219p
68.237p
72.256p
76.265p
80.080p
85.501p
87.652p
89.793p
88.733p
90.025p
96.129p
1.234n
1.247n
1.274n
|
[POWER_clamp]
|
|Voltage
|
I(typ)
I(min)
I(max)
3.30V
-36.990p -340.971n -24.206p
A-14
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-75.987p
-968.068p -33.646u -33.249p
-20.878n -295.501u -38.210p
-3.576u -28.510p
-432.308n
-2.884m -47.610p
-8.033u -14.321m -262.449p
-85.878u -37.031m
-2.255m -106.842m
-16.027m -146.893m -147.930u
-55.640m -188.330m -845.183u
-116.760m -230.621m
-187.399m -273.485m
-262.072m -316.761m -33.203m
-338.844m -360.345m -95.235m
-416.883m -404.167m -175.537m
-495.766m -448.180m -262.388m
-655.177m -536.646m -443.735m
-735.452m -581.052m -536.300m
-816.003m -625.551m -629.593m
-896.779m -670.131m -723.415m
-977.740m -714.781m -817.639m
-1.059 -759.493m -912.179m
-8.597n
-9.999u
-2.370m
-6.614m
-1.140 -804.259m
-1.221 -849.075m
-1.303 -893.934m
-1.466 -983.769m
-1.548
-1.630
-1.711
-1.793
-1.875
-1.007
-1.102
-1.197
-1.388
-1.483
-1.579
-1.675
-1.771
-1.867
-1.029
-1.074
-1.119
-1.164
-1.209
|
[Ramp]
|Voltage
|
I(typ)
I(min)
I(max)
dV/dt_f
|
dV/dt_r
2.01/129.093p 1.83/223.594p 2.20/79.668p
2.02/200.492p 1.83/352.515p 2.20/122.321p
R_load=10000ohms
| R_load was connected to ground for Ramp_up test and power for Ramp_dn
test
|
|End model
[Model]
ipad5v_io
I/O
| ""
Model_type
Vinl = 0.8
Vinh = 2
| variable
C_comp
typ
1.96p
typ
min
1.87p
min
max
2.06p
max
120.0
| variable
[Temperature Range] 40.0
0.0
| variable
typ
min
max
[Voltage Range]
|
3.30V
3.00V
3.60V
MOTOROLA
DSP56364 Advance Information
A-15
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
[Pulldown]
| pulldown in the table = pulldown subtract gnd_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
-142.303u -76.239u -215.182u
-149.700u -80.226u -226.432u
-157.861u -84.616u -238.866u
-166.908u -89.472u -252.678u
-176.992u -94.869u -268.107u
-188.295u -100.900u -285.446u
-201.049u -107.679u -305.068u
-215.545u -115.349u -327.446u
-232.155u -124.094u -353.191u
-251.367u -134.145u -383.107u
-273.825u -145.808u -418.273u
-300.403u -159.488u -460.167u
-332.314u -175.737u -510.874u
-371.286u -195.318u -573.418u
-419.868u -219.325u -652.360u
-481.968u -249.369u -754.892u
-563.882u -287.925u -893.013u
-676.382u -338.973u
-839.410u -409.300u
-1.094m -511.367u
-1.537m -670.350u
-2.451m -943.845u
-1.088m
-1.383m
-1.873m
-2.819m
-5.162m
-4.857m
-10.606m
-14.267m
-13.851m
-12.481m
-10.883m
-9.156m
-7.378m
-5.572m
-3.741m
-1.885m
1.898p
1.857m
3.630m
5.323m
6.936m
8.467m
9.915m
11.275m
12.546m
13.723m
36.925m
39.391m
41.612m
43.585m
45.305m
46.773m
-1.486m -12.214m
-2.746m -20.764m
-5.259m -21.749m
-7.108m -20.142m
-7.168m -18.211m
-6.348m -15.981m
-5.339m -13.503m
-4.288m -10.922m
-3.224m
-2.154m
-1.080m
1.419p
1.057m
2.064m
3.023m
3.935m
4.798m
5.611m
6.371m
7.078m
7.726m
20.745m
22.074m
23.244m
24.247m
25.079m
25.741m
-8.282m
-5.584m
-2.825m
1.871p
2.800m
5.482m
8.052m
10.508m
12.849m
15.073m
17.176m
19.155m
21.011m
56.704m
60.708m
64.383m
67.726m
70.735m
73.414m
A-16
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
47.997m
48.985m
49.733m
50.257m
50.612m
50.858m
51.040m
51.182m
51.302m
51.405m
51.497m
51.581m
51.658m
51.727m
51.757m
51.229m
49.190m
49.441m
51.034m
54.363m
57.165m
58.834m
60.328m
61.725m
63.035m
64.319m
65.598m
66.836m
67.999m
69.069m
70.046m
70.938m
71.751m
72.476m
73.089m
73.531m
73.651m
72.901m
71.005m
70.389m
70.321m
70.361m
70.422m
70.489m
70.557m
70.624m
70.690m
70.753m
70.817m
70.881m
70.949m
26.251m
26.633m
26.905m
27.092m
27.223m
27.321m
27.399m
27.465m
27.522m
27.572m
27.618m
27.657m
27.674m
27.587m
27.577m
28.700m
30.042m
31.171m
32.199m
33.153m
34.039m
34.872m
35.686m
36.495m
37.291m
38.051m
38.755m
39.394m 100.059m
39.962m 101.849m
40.453m 103.628m
40.840m 105.345m
41.065m 106.956m
40.952m 108.448m
40.067m 109.826m
39.395m 111.106m
39.313m 112.297m
39.358m 113.400m
39.410m 114.401m
39.460m 115.267m
39.508m 115.917m
39.552m 116.139m
39.595m 114.582m
39.634m 111.344m
39.672m 110.612m
39.708m 110.449m
39.743m 110.455m
39.777m 110.515m
39.812m 110.595m
39.848m 110.686m
39.886m 110.783m
39.929m 110.885m
75.766m
77.783m
79.441m
80.724m
81.651m
82.294m
82.744m
83.074m
83.332m
83.543m
83.724m
83.884m
84.030m
84.165m
84.290m
84.409m
84.515m
84.491m
81.077m
79.736m
80.276m
82.430m
85.482m
91.743m
94.219m
96.276m
98.249m
MOTOROLA
DSP56364 Advance Information
A-17
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
|
[Pullup]
| pullup in the table = pullup subtract power_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
-0.00V
0.10V
75.797u
90.464u
7.914u 161.477u
17.699u 181.779u
27.445u 202.314u
37.119u 223.007u
46.694u 243.785u
56.144u 264.581u
65.447u 285.332u
74.582u 305.982u
83.527u 326.474u
92.262u 346.757u
105.160u
119.836u
134.451u
148.966u
163.342u
177.543u
191.536u
205.285u
218.754u 100.766u 366.776u
231.907u 109.016u 386.478u
244.706u 116.988u 405.807u
257.106u 124.659u 424.699u
269.061u 131.998u 443.089u
280.519u 138.978u 460.899u
291.423u 145.565u 478.046u
301.710u 151.723u 494.457u
311.348u 157.417u 521.406u
729.899u 162.626u
10.510m 445.517u
1.612m
14.832m
13.576m
12.231m
10.854m
9.483m
8.169m
6.971m
5.921m
4.953m
3.978m
2.987m
2.003m
1.005m
24.081p
9.629m
8.670m
7.693m
6.732m
5.825m
5.004m
4.261m
3.549m
2.841m
2.135m
6.444m
5.833m
5.190m
4.551m
3.942m
3.382m
2.869m
2.381m
1.902m
1.426m
1.437m 951.489u
722.340u 478.341u
22.329p
-708.556u -465.927u -990.647u
36.936p
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
-1.377m -903.637u
-1.943m
-2.832m
-3.702m
-4.537m
-5.336m
-6.096m
-6.817m
-7.499m
-8.139m
-8.737m
-9.292m
-9.802m
-2.007m
-2.614m
-3.192m
-3.738m
-4.253m
-4.736m
-5.185m
-5.600m
-5.980m
-6.324m
-1.319m
-1.710m
-2.079m
-2.423m
-2.742m
-3.037m
-3.305m
-3.547m
-3.762m
-3.948m
-6.631m -17.709m
1.40V
-29.730m -18.279m -10.265m
A-18
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-30.749m -18.747m -45.983m
-31.630m -19.131m -47.620m
-32.393m -19.454m -49.086m
-33.055m -19.730m -50.392m
-33.632m -19.973m -51.551m
-34.135m -20.188m -52.571m
-34.575m -20.381m -53.463m
-34.960m -20.556m -54.240m
-35.302m -20.715m -54.917m
-35.608m -20.861m -55.510m
-35.884m -20.997m -56.035m
-36.137m -21.123m -56.505m
-36.370m -21.241m -56.932m
-36.586m -21.352m -57.322m
-36.788m -21.457m -57.683m
-36.978m -21.556m -58.019m
-37.157m -21.650m -58.334m
-37.327m -21.741m -58.631m
-37.489m -21.827m -58.913m
-37.643m -21.909m -59.181m
-37.791m -21.989m -59.436m
-37.933m -22.067m -59.681m
-38.070m -22.143m -59.916m
-38.202m -22.216m -60.142m
-38.332m -22.284m -60.361m
-38.460m -22.352m -60.573m
-38.590m -22.420m -60.780m
-38.714m -22.490m -60.986m
-38.828m -22.561m -61.194m
-38.949m -22.635m -61.406m
-39.076m -22.713m -61.623m
-39.211m -22.798m -61.819m
-39.357m -22.892m -62.024m
-39.516m -22.997m -62.254m
-39.693m -23.116m -62.506m
-39.893m -23.253m -62.785m
-40.121m -23.411m -63.098m
-40.384m -23.595m -63.453m
-40.689m -23.801m -63.860m
-41.043m -24.032m -64.330m
-41.444m -24.288m -64.874m
-41.886m -24.570m -65.505m
-42.370m -24.880m -66.214m
-42.899m -25.217m -66.983m
-43.473m -25.585m -67.815m
-44.095m -25.983m -68.711m
-44.769m -26.415m -69.678m
-45.498m -26.884m -70.721m
-46.287m -27.390m -71.848m
-47.140m -27.929m -73.065m
-48.049m -28.487m -74.374m
-48.990m -29.080m -75.748m
|
MOTOROLA
DSP56364 Advance Information
A-19
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
[GND_clamp]
|
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
-1.875
-1.793
-1.074
-1.029
-2.155
-2.059
-1.963
-1.771
-1.675
-1.579
-1.483
-1.388
-1.292
-1.197
-1.102
-1.007
-1.711 -983.765m
-1.548 -893.931m
-1.466 -849.071m
-1.385 -804.256m
-1.303 -759.489m
-1.221 -714.777m
-1.140 -670.127m
-1.059 -625.548m
-977.735m -581.048m
-896.773m -536.642m
-735.446m -448.177m -817.634m
-655.171m -404.164m -723.409m
-575.242m -360.342m -629.587m
-495.760m -316.758m -536.295m
-416.878m -273.482m -443.730m
-338.839m -230.618m -352.222m
-262.067m -188.327m -262.384m
-187.395m -146.891m -175.533m
-116.756m -106.839m -95.231m
-16.024m -37.029m
-2.254m -14.319m
-6.612m
-2.370m
-476.015u
-85.877u -295.354u -147.930u
-8.033u -33.637u -9.999u
-432.304n -3.576u -310.975n
-20.874n -340.944n -8.593n
-964.564p -30.895n -258.649p
-72.583p -2.560n -43.910p
-2.883m -845.181u
-33.685p -210.508p -34.610p
-27.665p -30.628p -29.748p
0.10V
0.20V
0.30V
0.40V
-22.754p
-18.303p
-14.129p
13.546p -25.110p
48.356p -20.906p
81.869p -16.971p
0.50V
-9.979p 114.849p -13.050p
0.60V
0.70V
0.80V
0.90V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
-5.833p 147.499p
-1.689p 179.924p
2.454p 212.188p
6.596p 244.335p
14.877p 308.388p
19.017p 340.335p
23.157p 372.250p
27.297p 404.143p
31.436p 436.027p
35.576p 467.910p
39.715p 499.805p
43.855p 531.722p
47.995p 563.675p
-9.130p
-5.210p
-1.291p
2.628p
10.466p
14.384p
18.302p
22.221p
26.139p
30.057p
33.974p
37.892p
41.810p
1.90V
A-20
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.10V
3.20V
3.30V
56.277p 627.761p
60.418p 659.933p
64.561p 692.106p
68.706p 723.142p
72.847p 751.973p
76.869p 780.264p
80.074p 808.442p
82.499p 835.513p
84.837p 860.391p
49.646p
53.564p
57.482p
61.400p
65.319p
69.237p
73.156p
77.065p
80.794p
86.195p
88.344p
90.478p
89.018p
89.573p
103.108p
1.265n
1.305n
1.593n
|
[POWER_clamp]
|
|Voltage
|
I(typ)
I(min)
I(max)
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
|
-33.685p -340.944n -20.906p
-72.583p -3.576u -25.110p
-964.564p -33.637u -29.748p
-20.874n -295.354u -34.610p
-432.304n
-2.883m -43.910p
-8.033u -14.319m -258.649p
-85.877u -37.029m
-2.254m -106.839m
-8.593n
-9.999u
-16.024m -146.891m -147.930u
-55.636m -188.327m -845.181u
-116.756m -230.618m
-187.395m -273.482m
-2.370m
-6.612m
-262.067m -316.758m -33.199m
-338.839m -360.342m -95.231m
-416.878m -404.164m -175.533m
-495.760m -448.177m -262.384m
-655.171m -536.642m -443.730m
-735.446m -581.048m -536.295m
-815.997m -625.548m -629.587m
-896.773m -670.127m -723.409m
-977.735m -714.777m -817.634m
-1.059 -759.489m -912.174m
-1.140 -804.256m
-1.221 -849.071m
-1.303 -893.931m
-1.466 -983.765m
-1.007
-1.102
-1.197
-1.388
-1.483
-1.579
-1.675
-1.771
-1.867
-1.548
-1.630
-1.711
-1.793
-1.875
-1.029
-1.074
-1.119
-1.164
-1.209
[Ramp]
|Voltage
|
I(typ)
I(min)
I(max)
dV/dt_f
2.04/134.002p 1.86/235.405p 2.23/85.874p
MOTOROLA
DSP56364 Advance Information
A-21
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
|
dV/dt_r
2.05/194.838p 1.86/341.412p 2.23/118.822p
R_load=10000ohms
| R_load was connected to ground for Ramp_up test and power for Ramp_dn
test
|
|End model
[Model]
ipada_3st
3-state
typ
2.32p
typ
| ""
Model_type
| variable
C_comp
| variable
[Temperature Range] 40.0
min
2.17p
min
max
2.48p
max
120.0
0.0
| variable
[Voltage Range]
|
typ
3.30V
min
3.00V
max
3.60V
[Pulldown]
| pulldown in the table = pulldown subtract gnd_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
-157.134u -99.256u -219.000u
-165.037u -104.127u -230.250u
-173.749u -109.479u -242.685u
-183.400u -115.386u -256.500u
-194.148u -121.936u -271.934u
-206.189u -129.240u -289.286u
-219.766u -137.431u -308.933u
-235.190u -146.680u -331.355u
-252.856u -157.199u -357.176u
-273.283u -169.265u -387.219u
-297.162u -183.236u -422.595u
-325.427u -199.590u -464.837u
-359.384u -218.976u -516.117u
-400.901u -242.299u -579.623u
-452.750u -270.851u -660.217u
-519.217u -306.549u -765.681u
-607.277u -352.346u -909.270u
-729.045u -413.024u
-907.407u -496.811u
-1.191m -619.011u
-1.699m -811.079u
-1.115m
-1.434m
-1.987m
-3.133m
-6.243m
-2.799m
-5.689m
-10.416m
-12.342m
-11.672m
-10.528m
-9.204m
-7.770m
-6.286m
-4.766m
-3.214m
-1.146m
-1.822m -12.974m
-3.302m -17.948m
-5.449m -17.964m
-6.479m -16.692m
-6.146m -15.152m
-5.387m -13.338m
-4.535m -11.313m
-3.652m
-2.754m
-1.846m
-9.190m
-6.999m
-4.740m
-2.410m
-1.627m -928.990u
A-22
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
32.871e-18 18.541e-18
1.604m 910.814u
-1.607f
2.391m
4.661m
6.817m
8.858m
10.784m
12.593m
14.284m
15.855m
17.306m
18.639m
19.856m
20.957m
21.944m
22.817m
23.575m
3.124m
4.566m
5.928m
7.210m
8.411m
1.775m
2.595m
3.372m
4.105m
4.792m
5.432m
6.023m
6.563m
7.051m
7.486m
7.865m
8.189m
64.562m
66.208m
9.529m
10.562m
11.508m
12.367m
13.138m
13.821m
14.417m
14.930m
117.094m
119.708m
121.667m
123.055m
124.020m
124.711m
125.232m
125.650m
126.000m
126.305m
126.577m
126.823m
127.050m
127.260m
127.457m
127.643m
127.818m
127.986m
128.147m
128.304m
128.458m
128.614m
128.776m
128.948m
129.140m
129.361m
129.621m
129.934m
130.316m
130.784m
131.358m
132.060m
132.912m
133.939m
135.166m
136.619m
138.324m
140.308m
67.513m 184.138m
68.498m 187.874m
69.206m 190.647m
69.710m 192.621m
70.083m 194.017m
70.374m 195.034m
70.612m 195.815m
70.814m 196.447m
70.992m 196.983m
71.151m 197.453m
71.296m 197.876m
71.428m 198.263m
71.551m 198.622m
71.666m 198.958m
71.774m 199.275m
71.876m 199.576m
71.973m 199.863m
72.066m 200.138m
72.156m 200.405m
72.245m 200.667m
72.335m 200.928m
72.428m 201.194m
72.527m 201.472m
72.638m 201.774m
72.764m 202.113m
72.914m 202.503m
73.093m 202.966m
73.311m 203.524m
73.579m 204.203m
73.906m 205.033m
74.304m 206.045m
74.787m 207.276m
75.368m 208.763m
76.060m 210.544m
76.878m 212.659m
77.836m 215.149m
78.948m 218.056m
MOTOROLA
DSP56364 Advance Information
A-23
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
142.597m
145.217m
148.192m
151.545m
155.300m
159.478m
164.097m
169.177m
174.734m
180.781m 101.465m 278.065m
187.333m 105.096m 287.810m
194.400m 109.009m 298.319m
201.993m 113.211m 309.602m
210.118m 117.705m 321.670m
80.230m 221.419m
81.694m 225.277m
83.355m 229.669m
85.224m 234.630m
87.316m 240.194m
89.640m 246.393m
92.208m 253.255m
95.029m 260.806m
98.112m 269.070m
|
[Pullup]
| pullup in the table = pullup subtract power_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
-0.00V
132.979u 100.794u 170.075u
138.984u 105.115u 178.000u
145.559u 109.825u 186.702u
152.789u 114.981u 196.300u
160.778u 120.648u 206.941u
169.651u 126.906u 218.803u
179.562u 133.852u 232.110u
190.706u 141.605u 247.141u
203.326u 150.317u 264.253u
217.736u 160.174u 283.910u
234.344u 171.418u 306.723u
253.692u 184.362u 333.513u
276.513u 199.421u 365.415u
303.830u 217.155u 404.033u
337.102u 238.340u 451.722u
378.494u 264.081u 512.067u
431.351u 296.004u 590.810u
501.113u 336.601u 697.730u
597.240u 389.880u 850.877u
737.641u 462.700u
960.395u 567.748u
1.361m 731.012u
1.087m
1.497m
2.348m
4.712m
10.148m
12.062m
11.029m
9.778m
8.443m
7.052m
5.644m
4.233m
2.821m
1.410m
2.237m
4.644m
8.090m
8.032m
7.118m
6.128m
5.109m
4.082m
3.056m
2.033m
1.013m
1.583m
2.907m
4.727m
4.754m
4.128m
3.441m
2.746m
2.053m
1.363m
1.014m 678.856u
58.687e-18 58.622e-18 117.504e-18
A-24
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
5.30V
-987.106u -655.604u
-1.381m
-2.709m
-3.988m
-5.216m
-6.392m
-7.516m
-8.587m
-9.602m
-1.928m
-2.828m
-3.685m
-4.499m
-5.269m
-5.994m
-6.673m
-7.306m
-7.890m
-8.424m
-8.907m
-1.274m
-1.859m
-2.412m
-2.931m
-3.416m
-3.866m
-4.280m
-4.658m -10.561m
-4.999m -11.461m
-5.301m -12.302m
-5.563m -13.081m
-9.339m -65.539m -13.798m
-110.103m -67.611m -154.438m
-113.807m -69.311m -170.370m
-117.010m -70.713m -176.323m
-119.783m -71.893m -181.647m
-122.195m -72.910m -186.387m
-124.297m -73.804m -190.581m
-126.131m -74.599m -194.261m
-127.733m -75.311m -197.468m
-129.139m -75.954m -200.255m
-130.384m -76.540m -202.683m
-131.498m -77.077m -204.814m
-132.504m -77.575m -206.704m
-133.423m -78.037m -208.399m
-134.270m -78.470m -209.937m
-135.057m -78.877m -211.346m
-135.792m -79.261m -212.650m
-136.483m -79.625m -213.864m
-137.136m -79.971m -215.004m
-137.756m -80.302m -216.079m
-138.345m -80.617m -217.098m
-138.908m -80.920m -218.067m
-139.447m -81.210m -218.993m
-139.964m -81.490m -219.880m
-140.462m -81.761m -220.732m
-140.943m -82.022m -221.552m
-141.408m -82.277m -222.344m
-141.860m -82.525m -223.112m
-142.300m -82.769m -223.858m
-142.733m -83.010m -224.586m
-143.159m -83.250m -225.300m
-143.585m -83.493m -226.006m
-144.013m -83.740m -226.709m
-144.449m -83.996m -227.417m
-144.899m -84.265m -228.137m
-145.370m -84.551m -228.879m
-145.871m -84.861m -229.656m
-146.411m -85.200m -230.481m
-147.001m -85.575m -231.368m
-147.652m -85.993m -232.336m
-148.379m -86.464m -233.404m
MOTOROLA
DSP56364 Advance Information
A-25
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-149.195m -86.995m -234.592m
-150.115m -87.597m -235.924m
-151.157m -88.280m -237.426m
-152.339m -89.054m -239.124m
-153.678m -89.930m -241.046m
-155.194m -90.921m -243.223m
-156.907m -92.038m -245.685m
-158.839m -93.294m -248.465m
-161.011m -94.701m -251.595m
-163.444m -96.273m -255.109m
-166.160m -98.023m -259.041m
-169.182m -99.963m -263.425m
-172.531m -102.106m -268.293m
|
[GND_clamp]
|
|Voltage
|
I(typ)
-2.637
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
-1.514
-1.451
-1.387
-1.259
-1.195
-1.132
-1.068
-1.004
-3.063
-2.926
-2.789
-2.515
-2.378
-2.242
-2.105
-1.969
-1.833
-1.697
-1.561
-1.425
-1.155
-1.021
-2.521
-2.406
-2.174
-2.059
-1.943
-1.828
-1.713
-1.598 -941.073m
-1.483 -877.750m
-1.368 -814.544m
-1.254 -751.475m
-1.026 -625.847m
-912.311m -563.357m
-799.377m -501.149m -886.904m
-687.103m -439.297m -753.859m
-575.715m -377.904m -621.897m
-465.583m -317.129m -491.519m
-357.354m -257.221m -363.667m
-252.314m -198.614m -240.395m
-153.494m -142.138m -127.373m
-19.457m -45.305m -11.215m
-3.535m -16.226m
-877.640u -3.288m
-156.838u -397.909u -271.662u
-14.514u -53.601u -18.044u
-780.351n
-37.668n -598.098n -15.437n
-1.699n -55.739n -411.332p
-4.650m
-1.613m
-6.086u -560.308n
-92.071p
-27.709p
-5.410n -29.683p
-1.212n -18.939p
0.10V
0.20V
0.30V
-22.802p -890.771p -16.163p
-19.598p -810.054p -13.516p
-16.468p -745.765p -10.874p
0.40V
-13.353p -683.799p
-8.234p
A-26
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
0.50V
0.60V
0.70V
0.80V
0.90V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.10V
3.20V
3.30V
-10.247p -622.802p
-7.147p -562.404p
-4.050p -502.414p -318.962f
-955.896f -442.712p
2.136p -383.217p
8.315p -264.634p
11.404p -205.467p
14.492p -146.346p
17.579p -87.245p
20.666p -28.141p
-5.595p
-2.956p
2.318p
4.954p
10.227p
12.862p
15.498p
18.133p
20.768p
23.404p
26.039p
28.674p
31.310p
36.581p
39.216p
41.852p
44.489p
47.125p
49.762p
52.401p
55.040p
57.675p
61.928p
63.585p
65.236p
23.754p
26.841p
30.987p
90.164p
29.929p 149.414p
33.018p 208.769p
39.198p 327.949p
42.291p 387.873p
45.385p 448.012p
48.483p 507.296p
51.583p 563.856p
54.673p 619.785p
57.468p 676.156p
59.647p 733.868p
61.717p 807.258p
65.859p
68.003p
5.906n
59.801n
72.601p 620.266n
|
[POWER_clamp]
|
|Voltage
|
I(typ)
I(min)
I(max)
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
-27.709p -598.098n -10.874p
-92.071p -6.086u -13.516p
-1.699n -53.601u -16.163p
-37.668n -397.909u -18.939p
-780.351n
-3.288m -29.683p
-14.514u -16.226m -411.332p
-156.838u -45.305m -15.437n
-3.535m -142.138m -18.044u
-19.457m -198.614m -271.662u
-69.631m -257.221m
-153.494m -317.129m
-1.613m
-4.650m
-252.314m -377.904m -11.215m
-357.354m -439.297m -43.562m
-465.583m -501.149m -127.373m
-575.715m -563.357m -240.395m
-687.103m -625.847m -363.667m
-912.311m -751.475m -621.897m
-1.026 -814.544m -753.859m
-1.140 -877.750m -886.904m
-1.254 -941.073m
-1.021
-1.155
-1.290
-1.368
-1.483
-1.004
-1.068
MOTOROLA
DSP56364 Advance Information
A-27
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
5.70V
5.80V
5.90V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-1.598
-1.713
-1.828
-2.059
-2.174
-2.290
-2.406
-2.521
-2.637
-1.132
-1.195
-1.259
-1.387
-1.451
-1.514
-1.578
-1.642
-1.706
-1.425
-1.561
-1.697
-1.969
-2.105
-2.242
-2.378
-2.515
-2.652
|
[Ramp]
|Voltage
|
I(typ)
I(min)
I(max)
dV/dt_f
|
dV/dt_r
1.99/110.010p 1.81/184.463p 2.17/69.974p
2.04/120.172p 1.85/212.126p 2.21/73.179p
R_load=10000ohms
| R_load was connected to ground for Ramp_up test and power for Ramp_dn
test
|
|End model
[Model]
ipadd_io
I/O
| ""
Model_type
Vinl = 0.8
Vinh = 2
| variable
C_comp
typ
2.34p
typ
min
2.21p
min
max
2.52p
max
120.0
| variable
[Temperature Range] 40.0
0.0
| variable
[Voltage Range]
|
typ
3.30V
min
3.00V
max
3.60V
[Pulldown]
| pulldown in the table = pulldown subtract gnd_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-157.134u -99.256u -219.000u
-165.037u -104.127u -230.250u
-173.749u -109.479u -242.685u
-183.400u -115.386u -256.500u
-194.148u -121.936u -271.934u
-206.189u -129.240u -289.286u
-219.766u -137.431u -308.933u
-235.190u -146.680u -331.355u
-252.856u -157.199u -357.176u
-273.283u -169.265u -387.219u
-297.162u -183.236u -422.595u
-325.427u -199.590u -464.837u
-359.384u -218.976u -516.117u
-400.901u -242.299u -579.623u
-452.750u -270.851u -660.217u
-519.217u -306.549u -765.681u
-607.277u -352.346u -909.270u
A-28
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
-729.045u -413.024u
-907.407u -496.811u
-1.191m -619.011u
-1.699m -811.079u
-1.115m
-1.434m
-1.987m
-3.133m
-6.243m
-2.799m
-5.689m
-10.416m
-12.342m
-11.672m
-10.528m
-9.204m
-7.770m
-6.286m
-4.766m
-3.214m
-1.146m
-1.822m -12.974m
-3.302m -17.948m
-5.449m -17.964m
-6.479m -16.692m
-6.146m -15.152m
-5.387m -13.338m
-4.535m -11.313m
-3.652m
-2.754m
-1.846m
-9.190m
-6.999m
-4.740m
-2.410m
-1.607f
2.391m
4.661m
6.817m
8.858m
10.784m
12.593m
14.284m
15.855m
17.306m
18.639m
19.856m
20.957m
21.944m
22.817m
23.575m
-1.627m -928.990u
32.871e-18 18.540e-18
1.604m 910.814u
3.124m
4.566m
5.928m
7.210m
8.411m
1.775m
2.595m
3.372m
4.105m
4.792m
5.432m
6.023m
6.563m
7.051m
7.486m
7.865m
8.189m
64.562m
66.208m
67.513m 184.138m
68.498m 187.874m
69.206m 190.647m
69.710m 192.621m
70.083m 194.017m
70.374m 195.034m
70.612m 195.815m
70.814m 196.447m
70.992m 196.983m
71.151m 197.453m
71.296m 197.876m
71.428m 198.263m
71.551m 198.622m
71.666m 198.958m
71.774m 199.275m
71.876m 199.576m
71.973m 199.863m
72.066m 200.138m
72.156m 200.405m
72.245m 200.667m
72.335m 200.928m
9.529m
10.562m
11.508m
12.367m
13.138m
13.821m
14.417m
14.930m
117.094m
119.708m
121.667m
123.055m
124.020m
124.711m
125.232m
125.650m
126.000m
126.305m
126.577m
126.823m
127.050m
127.260m
127.457m
127.643m
127.818m
127.986m
128.147m
128.304m
128.458m
128.614m
MOTOROLA
DSP56364 Advance Information
A-29
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
128.776m
128.948m
129.140m
129.361m
129.621m
129.934m
130.316m
130.784m
131.358m
132.060m
132.912m
133.939m
135.166m
136.619m
138.324m
140.308m
142.597m
145.217m
148.192m
151.545m
155.300m
159.478m
164.097m
169.177m
174.734m
72.428m 201.194m
72.527m 201.472m
72.638m 201.774m
72.764m 202.113m
72.914m 202.503m
73.093m 202.966m
73.311m 203.524m
73.579m 204.203m
73.906m 205.033m
74.304m 206.045m
74.787m 207.276m
75.368m 208.763m
76.060m 210.544m
76.878m 212.659m
77.836m 215.149m
78.948m 218.056m
80.230m 221.419m
81.694m 225.277m
83.355m 229.669m
85.224m 234.630m
87.316m 240.194m
89.640m 246.393m
92.208m 253.255m
95.029m 260.806m
98.112m 269.070m
180.781m 101.465m 278.065m
187.333m 105.096m 287.810m
194.400m 109.009m 298.319m
201.993m 113.211m 309.602m
210.118m 117.705m 321.670m
|
[Pullup]
| pullup in the table = pullup subtract power_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
132.979u 100.794u 170.075u
138.984u 105.115u 178.000u
145.559u 109.825u 186.702u
152.789u 114.981u 196.300u
160.778u 120.648u 206.941u
169.651u 126.906u 218.803u
179.562u 133.852u 232.110u
190.706u 141.605u 247.141u
203.326u 150.317u 264.253u
217.736u 160.174u 283.910u
234.344u 171.418u 306.723u
253.692u 184.362u 333.513u
276.513u 199.421u 365.415u
303.830u 217.155u 404.033u
337.102u 238.340u 451.722u
378.494u 264.081u 512.067u
431.351u 296.004u 590.810u
501.113u 336.601u 697.730u
A-30
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
-0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
3.70V
597.240u 389.880u 850.877u
737.641u 462.700u
960.395u 567.748u
1.361m 731.012u
1.087m
1.497m
2.348m
4.712m
10.148m
12.062m
11.029m
9.778m
8.443m
7.052m
5.644m
4.233m
2.821m
1.410m
2.237m
4.644m
8.090m
8.032m
7.118m
6.128m
5.109m
4.082m
3.056m
2.033m
1.013m
1.583m
2.907m
4.727m
4.754m
4.128m
3.441m
2.746m
2.053m
1.363m
1.014m 678.856u
58.687e-18 58.622e-18 117.504e-18
-987.106u -655.604u
-1.381m
-2.709m
-3.988m
-5.216m
-6.392m
-7.516m
-8.587m
-9.602m
-1.928m
-2.828m
-3.685m
-4.499m
-5.269m
-5.994m
-6.673m
-7.306m
-7.890m
-8.424m
-8.907m
-1.274m
-1.859m
-2.412m
-2.931m
-3.416m
-3.866m
-4.280m
-4.658m -10.561m
-4.999m -11.461m
-5.301m -12.302m
-5.563m -13.081m
-9.339m -65.539m -13.798m
-110.103m -67.611m -154.438m
-113.807m -69.311m -170.370m
-117.010m -70.713m -176.323m
-119.783m -71.893m -181.647m
-122.195m -72.910m -186.387m
-124.297m -73.804m -190.581m
-126.131m -74.599m -194.261m
-127.733m -75.311m -197.468m
-129.139m -75.954m -200.255m
-130.384m -76.540m -202.683m
-131.498m -77.077m -204.814m
-132.504m -77.575m -206.704m
-133.423m -78.037m -208.399m
-134.270m -78.470m -209.937m
-135.057m -78.877m -211.346m
-135.792m -79.261m -212.650m
-136.483m -79.625m -213.864m
-137.136m -79.971m -215.004m
-137.756m -80.302m -216.079m
-138.345m -80.617m -217.098m
-138.908m -80.920m -218.067m
-139.447m -81.210m -218.993m
-139.964m -81.490m -219.880m
-140.462m -81.761m -220.732m
MOTOROLA
DSP56364 Advance Information
A-31
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-140.943m -82.022m -221.552m
-141.408m -82.277m -222.344m
-141.860m -82.525m -223.112m
-142.300m -82.769m -223.858m
-142.733m -83.010m -224.586m
-143.159m -83.250m -225.300m
-143.585m -83.493m -226.006m
-144.013m -83.740m -226.709m
-144.449m -83.996m -227.417m
-144.899m -84.265m -228.137m
-145.370m -84.551m -228.879m
-145.871m -84.861m -229.656m
-146.411m -85.200m -230.481m
-147.001m -85.575m -231.368m
-147.652m -85.993m -232.336m
-148.379m -86.464m -233.404m
-149.195m -86.995m -234.592m
-150.115m -87.597m -235.924m
-151.157m -88.280m -237.426m
-152.339m -89.054m -239.124m
-153.678m -89.930m -241.046m
-155.194m -90.921m -243.223m
-156.907m -92.038m -245.685m
-158.839m -93.294m -248.465m
-161.011m -94.701m -251.595m
-163.444m -96.273m -255.109m
-166.160m -98.023m -259.041m
-169.182m -99.963m -263.425m
-172.531m -102.106m -268.293m
|
[GND_clamp]
|
|Voltage
|
I(typ)
-2.637
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.514
-1.451
-1.387
-1.259
-1.195
-1.132
-1.068
-1.004
-3.063
-2.926
-2.789
-2.515
-2.378
-2.242
-2.105
-1.969
-1.833
-1.697
-1.561
-1.425
-1.155
-1.021
-2.521
-2.406
-2.174
-2.059
-1.943
-1.828
-1.713
-1.598 -941.073m
-1.483 -877.750m
-1.368 -814.544m
-1.254 -751.475m
-1.026 -625.847m
-912.311m -563.357m
-799.377m -501.149m -886.904m
-687.103m -439.297m -753.859m
-575.715m -377.904m -621.897m
-465.583m -317.129m -491.519m
-357.354m -257.221m -363.667m
A-32
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-1.20V
-1.10V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.10V
3.20V
3.30V
-252.314m -198.614m -240.395m
-153.494m -142.138m -127.373m
-19.457m -45.305m -11.215m
-3.535m -16.226m
-877.640u -3.288m
-4.650m
-1.613m
-156.838u -397.909u -271.662u
-14.514u -53.601u -18.044u
-780.351n
-6.086u -560.308n
-37.668n -598.098n -15.437n
-1.699n -55.739n -411.332p
-92.071p
-27.709p
-5.410n -29.683p
-1.212n -18.939p
-22.802p -890.771p -16.163p
-19.598p -810.054p -13.516p
-16.468p -745.765p -10.874p
-13.353p -683.799p
-10.247p -622.802p
-7.147p -562.404p
-8.234p
-5.595p
-2.956p
-4.050p -502.414p -318.962f
-955.896f -442.712p
2.136p -383.217p
8.315p -264.634p
11.404p -205.467p
14.492p -146.346p
17.579p -87.245p
20.666p -28.141p
2.318p
4.954p
10.227p
12.862p
15.498p
18.133p
20.768p
23.404p
26.039p
28.674p
31.310p
36.581p
39.216p
41.852p
44.489p
47.125p
49.762p
52.401p
55.040p
57.675p
61.928p
63.585p
65.236p
23.754p
26.841p
30.987p
90.164p
29.929p 149.414p
33.018p 208.769p
39.198p 327.949p
42.291p 387.873p
45.385p 448.012p
48.483p 507.296p
51.583p 563.856p
54.673p 619.785p
57.468p 676.156p
59.647p 733.868p
61.717p 807.258p
65.859p
68.003p
5.906n
59.801n
72.601p 620.266n
|
[POWER_clamp]
|
|Voltage
|
I(typ)
I(min)
I(max)
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
-27.709p -598.098n -10.874p
-92.071p -6.086u -13.516p
-1.699n -53.601u -16.163p
-37.668n -397.909u -18.939p
-780.351n
-3.288m -29.683p
-14.514u -16.226m -411.332p
MOTOROLA
DSP56364 Advance Information
A-33
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
3.90V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-156.838u -45.305m -15.437n
-3.535m -142.138m -18.044u
-19.457m -198.614m -271.662u
-69.631m -257.221m
-153.494m -317.129m
-1.613m
-4.650m
-252.314m -377.904m -11.215m
-357.354m -439.297m -43.562m
-465.583m -501.149m -127.373m
-575.715m -563.357m -240.395m
-687.103m -625.847m -363.667m
-912.311m -751.475m -621.897m
-1.026 -814.544m -753.859m
-1.140 -877.750m -886.904m
-1.254 -941.073m
-1.021
-1.155
-1.290
-1.425
-1.561
-1.697
-1.969
-2.105
-2.242
-2.378
-2.515
-2.652
-1.368
-1.483
-1.598
-1.713
-1.828
-2.059
-2.174
-2.290
-2.406
-2.521
-2.637
-1.004
-1.068
-1.132
-1.195
-1.259
-1.387
-1.451
-1.514
-1.578
-1.642
-1.706
|
[Ramp]
|Voltage
|
I(typ)
I(min)
I(max)
dV/dt_f
|
dV/dt_r
1.99/104.603p 1.81/183.924p 2.18/69.643p
2.04/123.810p 1.85/215.062p 2.20/73.602p
R_load=10000ohms
| R_load was connected to ground for Ramp_up test and power for Ramp_dn
test
|
|End model
[Model]
ipadex_i
Input
| ""
Model_type
Vinl = 0.8
Vinh = 2
| variable
C_comp
typ
2.92p
typ
min
2.78p
min
max
2.96p
max
120.0
| variable
[Temperature Range] 40.0
0.0
| variable
typ
min
max
[Voltage Range]
3.30V
3.00V
3.60V
|
[GND_clamp]
|
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-831.819m -473.616m -909.150m
A-34
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-3.20V
-3.10V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
-796.528m -454.528m -869.534m
-761.255m -435.451m -829.938m
-690.773m -397.335m -750.811m
-655.569m -378.299m -711.286m
-620.391m -359.279m -671.789m
-585.244m -340.277m -632.324m
-550.131m -321.295m -592.895m
-515.057m -302.336m -553.507m
-480.027m -283.402m -514.167m
-445.047m -264.496m -474.880m
-410.126m -245.624m -435.657m
-340.501m -207.998m -357.451m
-305.826m -189.259m -318.503m
-271.273m -170.582m -279.692m
-236.871m -151.981m -241.057m
-202.665m -133.474m -202.657m
-168.722m -115.088m -164.583m
-135.151m -96.861m -126.991m
-102.140m -78.852m -90.181m
-70.064m -61.160m -54.834m
-14.097m -27.650m
-1.307m -13.160m -53.501u
-36.639u -3.159m -768.589n
-2.799m
-903.944n -256.975u -10.997n
-22.242n -13.934u -172.415p
-567.014p -730.372n -16.888p
-32.976p -38.990n -13.767p
-18.575p
-2.810n -12.822p
-16.945p -867.431p -11.909p
-15.630p -713.428p -10.996p
-14.322p -652.886p -10.084p
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
-13.014p -597.227p
-11.707p -541.823p
-10.399p -486.432p
-9.092p -431.043p
-7.784p -375.653p
-6.477p -320.263p
-5.169p -264.873p
-3.862p -209.483p
-9.171p
-8.258p
-7.345p
-6.432p
-5.520p
-4.607p
-3.694p
-2.781p
1.10V
1.20V
-1.246p -98.704p -955.508f
61.165f -43.314p -42.711f
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.10V
2.20V
2.30V
2.40V
2.50V
1.369p
2.676p
12.076p 870.085f
67.466p
1.783p
2.696p
3.609p
4.521p
5.434p
6.347p
8.173p
9.085p
9.998p
10.911p
11.824p
3.984p 122.856p
5.291p 178.246p
6.599p 233.635p
7.906p 289.025p
9.214p 344.415p
11.829p 455.195p
13.137p 510.585p
14.444p 565.974p
15.752p 621.364p
17.059p 676.754p
MOTOROLA
DSP56364 Advance Information
A-35
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
2.60V
2.70V
2.80V
2.90V
3.10V
3.20V
3.30V
18.367p 732.144p
19.674p 787.535p
20.982p 842.946p
22.290p 898.735p
12.736p
13.649p
14.562p
15.475p
17.301p
18.213p
19.126p
24.905p
26.212p
27.520p
1.163n
4.019n
57.671n
|
[POWER_clamp]
|
|Voltage
|
I(typ)
I(min)
I(max)
3.30V
3.40V
-15.630p -38.990n
-16.945p -730.372n
-8.258p
-9.171p
3.50V
3.60V
-18.575p -13.934u -10.084p
-32.976p -256.975u -10.996p
3.70V
-567.014p
-3.159m -11.909p
3.80V
3.90V
4.10V
4.20V
4.30V
4.40V
-22.242n -13.160m -12.822p
-903.944n -27.650m -13.767p
-1.307m -61.160m -172.415p
-14.097m -78.852m -10.997n
-39.803m -96.861m -768.589n
-70.064m -115.088m -53.501u
4.50V
-102.140m -133.474m
-2.799m
4.60V
4.70V
4.80V
4.90V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.10V
6.20V
6.30V
-135.151m -151.981m -22.990m
-168.722m -170.582m -54.834m
-202.665m -189.259m -90.181m
-236.871m -207.998m -126.991m
-305.826m -245.624m -202.657m
-340.501m -264.496m -241.057m
-375.273m -283.402m -279.692m
-410.126m -302.336m -318.503m
-445.047m -321.295m -357.451m
-480.027m -340.277m -396.509m
-515.057m -359.279m -435.657m
-550.131m -378.299m -474.880m
-585.244m -397.335m -514.167m
-655.569m -435.451m -592.895m
-690.773m -454.528m -632.324m
-726.003m -473.616m -671.789m
-761.255m -492.715m -711.286m
-796.528m -511.823m -750.811m
-831.819m -530.941m -790.363m
6.40V
6.50V
6.60V
|
|End model
[Model]
Model_type
| variable
C_comp
| variable
ipadm_3st
3-state
typ
1.99p
typ
| ""
min
1.86p
min
max
2.15p
max
120.0
[Temperature Range] 40.0
0.0
| variable
typ
min
max
[Voltage Range]
3.30V
3.00V
3.60V
A-36
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
|
[Pulldown]
| pulldown in the table = pulldown subtract gnd_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
-157.134u -99.256u -219.000u
-165.037u -104.127u -230.250u
-173.749u -109.479u -242.685u
-183.400u -115.386u -256.500u
-194.148u -121.936u -271.934u
-206.189u -129.240u -289.286u
-219.766u -137.431u -308.933u
-235.190u -146.680u -331.355u
-252.856u -157.199u -357.176u
-273.283u -169.265u -387.219u
-297.162u -183.236u -422.595u
-325.427u -199.590u -464.837u
-359.384u -218.976u -516.117u
-400.901u -242.299u -579.623u
-452.750u -270.851u -660.217u
-519.217u -306.549u -765.681u
-607.277u -352.346u -909.270u
-729.045u -413.024u
-907.407u -496.811u
-1.191m -619.011u
-1.699m -811.079u
-1.115m
-1.434m
-1.987m
-3.133m
-6.243m
-2.799m
-5.689m
-10.416m
-12.342m
-11.672m
-10.528m
-9.204m
-7.770m
-6.286m
-4.766m
-3.214m
-1.146m
-1.822m -12.974m
-3.302m -17.948m
-5.449m -17.964m
-6.479m -16.692m
-6.146m -15.152m
-5.387m -13.338m
-4.535m -11.313m
-3.652m
-2.754m
-1.846m
-9.190m
-6.999m
-4.740m
-2.410m
-1.607f
2.391m
-1.627m -928.990u
32.755e-18 18.548e-18
1.604m 910.814u
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
3.124m
4.566m
5.928m
7.210m
8.411m
1.775m
2.595m
3.372m
4.105m
4.792m
5.432m
6.023m
6.563m
7.051m
7.486m
7.865m
8.189m
47.725m
4.661m
6.817m
8.858m
10.784m
12.593m
14.284m
15.855m
17.306m
18.639m
19.856m
20.957m
21.944m
22.817m
9.529m
10.562m
11.508m
12.367m
13.138m
13.821m
14.417m
14.930m
1.40V
MOTOROLA
DSP56364 Advance Information
A-37
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
86.564m
88.497m
89.946m
90.974m
91.689m
92.200m
92.586m
92.895m
93.154m
93.380m
93.581m
93.764m
93.931m
94.087m
94.233m
94.370m
94.500m
94.624m
94.744m
94.859m
94.974m
95.089m
95.208m
95.336m
95.478m
95.641m
95.833m
96.065m
96.347m
96.693m
97.117m
97.636m
98.266m
99.024m
99.931m
101.005m
102.264m
103.730m
105.422m
107.357m
109.556m
112.034m
114.809m
117.897m
121.311m
125.066m
129.172m
133.642m
138.485m
143.709m
149.320m
155.326m
48.943m
23.575m
49.908m 136.139m
50.637m 138.902m
51.160m 140.954m
51.534m 142.415m
51.810m 143.449m
52.024m 144.201m
52.201m 144.779m
52.351m 145.246m
52.482m 145.642m
52.600m 145.990m
52.706m 146.303m
52.804m 146.590m
52.895m 146.855m
52.980m 147.104m
53.060m 147.338m
53.135m 147.560m
53.207m 147.772m
53.276m 147.976m
53.343m 148.174m
53.408m 148.367m
53.475m 148.560m
53.543m 148.757m
53.617m 148.963m
53.699m 149.186m
53.792m 149.436m
53.902m 149.725m
54.035m 150.067m
54.196m 150.479m
54.394m 150.981m
54.635m 151.594m
54.930m 152.342m
55.287m 153.252m
55.716m 154.350m
56.227m 155.666m
56.831m 157.230m
57.539m 159.070m
58.361m 161.218m
59.308m 163.704m
60.391m 166.555m
61.618m 169.801m
63.000m 173.468m
64.545m 177.581m
66.263m 182.163m
68.160m 187.235m
70.245m 192.816m
72.524m 198.924m
75.002m 205.573m
77.685m 212.776m
80.578m 220.544m
83.683m 228.885m
87.004m 237.805m
|
A-38
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
[Pullup]
| pullup in the table = pullup subtract power_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
-0.00V
0.10V
132.979u 100.794u 170.075u
138.984u 105.115u 178.000u
145.559u 109.825u 186.702u
152.789u 114.981u 196.300u
160.778u 120.648u 206.941u
169.651u 126.906u 218.803u
179.562u 133.852u 232.110u
190.706u 141.605u 247.141u
203.326u 150.317u 264.253u
217.736u 160.174u 283.910u
234.344u 171.418u 306.723u
253.692u 184.362u 333.513u
276.513u 199.421u 365.415u
303.830u 217.155u 404.033u
337.102u 238.340u 451.722u
378.494u 264.081u 512.067u
431.351u 296.004u 590.810u
501.113u 336.601u 697.730u
597.240u 389.880u 850.877u
737.641u 462.700u
960.396u 567.748u
1.361m 731.012u
1.087m
1.497m
2.348m
4.712m
10.148m
12.062m
11.029m
9.778m
8.443m
7.052m
5.644m
4.233m
2.821m
1.410m
2.237m
4.644m
8.090m
8.032m
7.118m
6.128m
5.109m
4.082m
3.056m
2.033m
1.013m
1.583m
2.907m
4.727m
4.754m
4.128m
3.441m
2.746m
2.053m
1.363m
1.014m 678.856u
58.687e-18 58.622e-18 117.504e-18
-987.106u -655.604u
-1.381m
-2.709m
-3.988m
-5.216m
-6.392m
-7.516m
-8.587m
-9.602m
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
-1.928m
-2.828m
-3.685m
-4.499m
-5.269m
-5.994m
-6.673m
-7.306m
-7.890m
-8.424m
-8.907m
-1.274m
-1.859m
-2.412m
-2.931m
-3.416m
-3.866m
-4.280m
-4.658m -10.561m
-4.999m -11.461m
-5.301m -12.302m
-5.563m -13.081m
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
-9.339m -47.451m -13.837m
-79.705m -48.954m -118.519m
-82.391m -50.187m -123.324m
MOTOROLA
DSP56364 Advance Information
A-39
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-84.713m -51.203m -127.640m
-86.724m -52.057m -131.501m
-88.472m -52.794m -134.939m
-89.996m -53.442m -137.982m
-91.327m -54.017m -140.655m
-92.489m -54.533m -142.987m
-93.511m -54.999m -145.014m
-94.415m -55.424m -146.781m
-95.224m -55.814m -148.333m
-95.955m -56.174m -149.709m
-96.623m -56.510m -150.943m
-97.238m -56.824m -152.063m
-97.809m -57.119m -153.088m
-98.343m -57.398m -154.036m
-98.846m -57.662m -154.920m
-99.320m -57.913m -155.749m
-99.770m -58.152m -156.531m
-100.198m -58.381m -157.272m
-100.607m -58.601m -157.977m
-100.998m -58.812m -158.650m
-101.374m -59.015m -159.295m
-101.735m -59.211m -159.914m
-102.084m -59.401m -160.510m
-102.422m -59.585m -161.086m
-102.750m -59.766m -161.644m
-103.070m -59.942m -162.186m
-103.384m -60.117m -162.715m
-103.694m -60.291m -163.234m
-104.002m -60.467m -163.747m
-104.313m -60.647m -164.257m
-104.629m -60.832m -164.770m
-104.955m -61.027m -165.293m
-105.296m -61.234m -165.831m
-105.659m -61.459m -166.394m
-106.050m -61.704m -166.991m
-106.477m -61.975m -167.634m
-106.949m -62.278m -168.334m
-107.474m -62.619m -169.106m
-108.064m -63.003m -169.965m
-108.730m -63.439m -170.928m
-109.483m -63.932m -172.012m
-110.337m -64.492m -173.239m
-111.305m -65.126m -174.627m
-112.401m -65.843m -176.199m
-113.640m -66.651m -177.978m
-115.036m -67.560m -179.986m
-116.606m -68.578m -182.247m
-118.365m -69.715m -184.785m
-120.329m -70.981m -187.626m
-122.513m -72.384m -190.793m
-124.935m -73.935m -194.311m
|
[GND_clamp]
A-40
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
|
|Voltage
|
I(typ)
-2.165
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.10V
-1.242
-1.190
-1.138
-1.033
-2.500
-2.388
-2.277
-2.054
-1.942
-1.831
-1.720
-1.609
-1.498
-1.387
-1.276
-1.166
-2.070
-1.975
-1.786
-1.691 -981.185m
-1.597 -929.174m
-1.503 -877.220m
-1.408 -825.330m
-1.314 -773.514m
-1.220 -721.779m
-1.126 -670.140m
-1.032 -618.610m
-845.771m -515.958m -945.908m
-752.887m -464.892m -836.403m
-660.410m -414.052m -727.373m
-568.461m -363.494m -618.970m
-477.221m -313.301m -511.430m
-386.980m -263.597m -405.149m
-298.248m -214.579m -300.867m
-212.028m -166.582m -200.187m
-130.668m -120.248m -107.496m
-17.375m -40.029m
-2.837m -14.886m
-656.331u
-116.521u -336.317u -201.636u
-10.789u -41.964u -13.420u
-580.051n
-27.994n -450.005n -11.484n
-1.269n -41.862n -311.158p
-74.463p
-26.215p
-22.114p -826.325p -16.303p
-19.278p -754.146p -13.966p
-16.497p -694.188p -11.632p
-13.726p -635.953p
-10.963p -578.437p
-8.203p -521.365p
-5.446p -464.595p
-2.691p -408.039p
62.079f -351.636p
5.566p -239.133p
8.316p -182.975p
11.067p -126.851p
13.817p -70.743p
16.567p -14.634p
19.317p
22.067p
24.817p 153.868p
27.568p 210.159p
33.072p 323.083p
-8.803m
-3.451m
-1.195m
-3.014m
-4.632u -416.799n
-4.218n -27.092p
-1.078n -18.737p
-9.300p
-6.968p
-4.637p
-2.307p
22.980f
2.353p
7.011p
9.340p
11.669p
13.998p
16.327p
18.656p
20.985p
23.313p
25.642p
30.300p
41.493p
97.654p
MOTOROLA
DSP56364 Advance Information
A-41
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.10V
3.20V
3.30V
35.825p 379.789p
38.581p 436.650p
41.339p 492.867p
44.098p 547.026p
46.849p 600.695p
49.356p 654.682p
51.378p 709.650p
53.315p 776.122p
32.629p
34.958p
37.288p
39.618p
41.948p
44.279p
46.611p
48.939p
52.772p
54.319p
55.861p
57.193p
59.183p
4.552n
44.522n
62.959p 466.732n
|
[POWER_clamp]
|
|Voltage
|
I(typ)
I(min)
I(max)
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
|
-26.215p -450.005n -11.632p
-74.463p -4.632u -13.966p
-1.269n -41.964u -16.303p
-27.994n -336.317u -18.737p
-580.051n
-3.014m -27.092p
-10.789u -14.886m -311.158p
-116.521u -40.029m -11.484n
-2.837m -120.248m -13.420u
-17.375m -166.582m -201.636u
-60.888m -214.579m
-130.668m -263.597m
-212.028m -313.301m
-1.195m
-3.451m
-8.803m
-298.248m -363.494m -37.420m
-386.980m -414.052m -107.496m
-477.221m -464.892m -200.187m
-568.461m -515.958m -300.867m
-752.887m -618.610m -511.430m
-845.771m -670.140m -618.970m
-938.979m -721.779m -727.373m
-1.032 -773.514m -836.403m
-1.126 -825.330m -945.908m
-1.220 -877.220m
-1.314 -929.174m
-1.408 -981.185m
-1.056
-1.166
-1.276
-1.387
-1.609
-1.720
-1.831
-1.942
-2.054
-2.165
-1.503
-1.691
-1.786
-1.881
-1.975
-2.070
-2.165
-1.033
-1.138
-1.190
-1.242
-1.294
-1.346
-1.399
[Ramp]
|Voltage
|
I(typ)
I(min)
I(max)
dV/dt_f
1.99/116.478p 1.81/206.384p 2.17/80.687p
|
A-42
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
dV/dt_r
2.02/147.722p 1.84/253.853p 2.19/93.030p
R_load=10000ohms
| R_load was connected to ground for Ramp_up test and power for Ramp_dn
test
|
|End model
[Model]
ipadn_io
I/O
| ""
Model_type
Vinl = 0.8
Vinh = 2
| variable
C_comp
typ
2.03p
typ
min
1.90p
min
max
2.18p
max
120.0
| variable
[Temperature Range] 40.0
0.0
| variable
[Voltage Range]
|
typ
3.30V
min
3.00V
max
3.60V
[Pulldown]
| pulldown in the table = pulldown subtract gnd_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-157.134u -99.256u -219.000u
-165.037u -104.127u -230.250u
-173.749u -109.479u -242.685u
-183.400u -115.386u -256.500u
-194.148u -121.936u -271.934u
-206.189u -129.240u -289.286u
-219.766u -137.431u -308.933u
-235.190u -146.680u -331.355u
-252.856u -157.199u -357.176u
-273.283u -169.265u -387.219u
-297.162u -183.236u -422.595u
-325.427u -199.590u -464.837u
-359.384u -218.976u -516.117u
-400.901u -242.299u -579.623u
-452.750u -270.851u -660.217u
-519.217u -306.549u -765.681u
-607.277u -352.346u -909.270u
-729.045u -413.024u
-907.407u -496.811u
-1.191m -619.011u
-1.699m -811.079u
-1.115m
-1.434m
-1.987m
-3.133m
-6.243m
-2.799m
-5.689m
-10.416m
-12.342m
-11.672m
-10.528m
-9.204m
-7.770m
-6.286m
-4.766m
-3.214m
-1.146m
-1.822m -12.974m
-3.302m -17.948m
-5.449m -17.964m
-6.479m -16.692m
-6.146m -15.152m
-5.387m -13.338m
-4.535m -11.313m
-3.652m
-2.754m
-1.846m
-9.190m
-6.999m
-4.740m
MOTOROLA
DSP56364 Advance Information
A-43
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-0.10V
0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
-1.627m -928.990u
32.755e-18 18.548e-18
1.604m 910.814u
-2.410m
-1.607f
2.391m
4.661m
6.817m
3.124m
4.566m
5.928m
7.210m
8.411m
1.775m
2.595m
3.372m
4.105m
4.792m
5.432m
6.023m
6.563m
7.051m
7.486m
7.865m
8.189m
47.725m
48.943m
8.858m
10.784m
12.593m
14.284m
15.855m
17.306m
18.639m
19.856m
20.957m
21.944m
22.817m
23.575m
9.529m
10.562m
11.508m
12.367m
13.138m
13.821m
14.417m
14.930m
86.564m
88.497m
89.946m
90.974m
91.689m
92.200m
92.586m
92.895m
93.154m
93.380m
93.581m
93.764m
93.931m
94.087m
94.233m
94.370m
94.500m
94.624m
94.744m
94.859m
94.974m
95.089m
95.208m
95.336m
95.478m
95.641m
95.833m
96.065m
96.347m
96.693m
97.117m
97.636m
98.266m
99.024m
99.931m
101.005m
102.264m
49.908m 136.139m
50.637m 138.902m
51.160m 140.954m
51.534m 142.415m
51.810m 143.449m
52.024m 144.201m
52.201m 144.779m
52.351m 145.246m
52.482m 145.642m
52.600m 145.990m
52.706m 146.303m
52.804m 146.590m
52.895m 146.855m
52.980m 147.104m
53.060m 147.338m
53.135m 147.560m
53.207m 147.772m
53.276m 147.976m
53.343m 148.174m
53.408m 148.367m
53.475m 148.560m
53.543m 148.757m
53.617m 148.963m
53.699m 149.186m
53.792m 149.436m
53.902m 149.725m
54.035m 150.067m
54.196m 150.479m
54.394m 150.981m
54.635m 151.594m
54.930m 152.342m
55.287m 153.252m
55.716m 154.350m
56.227m 155.666m
56.831m 157.230m
57.539m 159.070m
A-44
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
103.730m
105.422m
107.357m
109.556m
112.034m
114.809m
117.897m
121.311m
125.066m
129.172m
133.642m
138.485m
143.709m
149.320m
155.326m
58.361m 161.218m
59.308m 163.704m
60.391m 166.555m
61.618m 169.801m
63.000m 173.468m
64.545m 177.581m
66.263m 182.163m
68.160m 187.235m
70.245m 192.816m
72.524m 198.924m
75.002m 205.573m
77.685m 212.776m
80.578m 220.544m
83.683m 228.885m
87.004m 237.805m
|
[Pullup]
| pullup in the table = pullup subtract power_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
132.979u 100.794u 170.075u
138.984u 105.115u 178.000u
145.559u 109.825u 186.702u
152.789u 114.981u 196.300u
160.778u 120.648u 206.941u
169.651u 126.906u 218.803u
179.562u 133.852u 232.110u
190.706u 141.605u 247.141u
203.326u 150.317u 264.253u
217.736u 160.174u 283.910u
234.344u 171.418u 306.723u
253.692u 184.362u 333.513u
276.513u 199.421u 365.415u
303.830u 217.155u 404.033u
337.102u 238.340u 451.722u
378.494u 264.081u 512.067u
431.351u 296.004u 590.810u
501.113u 336.601u 697.730u
597.240u 389.880u 850.877u
737.641u 462.700u
960.396u 567.748u
1.361m 731.012u
1.087m
1.497m
2.348m
4.712m
10.148m
12.062m
11.029m
9.778m
8.443m
7.052m
5.644m
4.233m
2.821m
1.410m
2.237m
4.644m
8.090m
8.032m
7.118m
6.128m
5.109m
4.082m
3.056m
2.033m
1.013m
1.583m
2.907m
4.727m
4.754m
4.128m
3.441m
2.746m
2.053m
1.363m
1.014m 678.856u
MOTOROLA
DSP56364 Advance Information
A-45
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
58.687e-18 58.622e-18 117.504e-18
-987.106u -655.604u
-1.381m
-2.709m
-3.988m
-5.216m
-6.392m
-7.516m
-8.587m
-9.602m
-1.928m
-2.828m
-3.685m
-4.499m
-5.269m
-5.994m
-6.673m
-7.306m
-7.890m
-8.424m
-8.907m
-1.274m
-1.859m
-2.412m
-2.931m
-3.416m
-3.866m
-4.280m
-4.658m -10.561m
-4.999m -11.461m
-5.301m -12.302m
-5.563m -13.081m
-9.339m -47.451m -13.901m
-79.705m -48.954m -118.519m
-82.391m -50.187m -123.324m
-84.713m -51.203m -127.640m
-86.724m -52.057m -131.501m
-88.472m -52.794m -134.939m
-89.996m -53.442m -137.982m
-91.327m -54.017m -140.655m
-92.489m -54.533m -142.987m
-93.511m -54.999m -145.014m
-94.415m -55.424m -146.781m
-95.224m -55.814m -148.333m
-95.955m -56.174m -149.709m
-96.623m -56.510m -150.943m
-97.238m -56.824m -152.063m
-97.809m -57.119m -153.088m
-98.343m -57.398m -154.036m
-98.846m -57.662m -154.920m
-99.320m -57.913m -155.749m
-99.770m -58.152m -156.531m
-100.198m -58.381m -157.272m
-100.607m -58.601m -157.977m
-100.998m -58.812m -158.650m
-101.374m -59.015m -159.295m
-101.735m -59.211m -159.914m
-102.084m -59.401m -160.510m
-102.422m -59.585m -161.086m
-102.750m -59.766m -161.644m
-103.070m -59.942m -162.186m
-103.384m -60.117m -162.715m
-103.694m -60.291m -163.234m
-104.002m -60.467m -163.747m
-104.313m -60.647m -164.257m
-104.629m -60.832m -164.770m
-104.955m -61.027m -165.293m
-105.296m -61.234m -165.831m
-105.659m -61.459m -166.394m
-106.050m -61.704m -166.991m
-106.477m -61.975m -167.634m
-106.949m -62.278m -168.334m
A-46
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-107.474m -62.619m -169.106m
-108.064m -63.003m -169.965m
-108.730m -63.439m -170.928m
-109.483m -63.932m -172.012m
-110.337m -64.492m -173.239m
-111.305m -65.126m -174.627m
-112.401m -65.843m -176.199m
-113.640m -66.651m -177.978m
-115.036m -67.560m -179.986m
-116.606m -68.578m -182.247m
-118.365m -69.715m -184.785m
-120.329m -70.981m -187.626m
-122.513m -72.384m -190.793m
-124.935m -73.935m -194.311m
|
[GND_clamp]
|
|Voltage
|
I(typ)
-2.165
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
-1.242
-1.190
-1.138
-1.033
-2.500
-2.388
-2.277
-2.054
-1.942
-1.831
-1.720
-1.609
-1.498
-1.387
-1.276
-1.166
-2.070
-1.975
-1.786
-1.691 -981.185m
-1.597 -929.174m
-1.503 -877.220m
-1.408 -825.330m
-1.314 -773.514m
-1.220 -721.779m
-1.126 -670.140m
-1.032 -618.610m
-845.771m -515.958m -945.908m
-752.887m -464.892m -836.403m
-660.410m -414.052m -727.373m
-568.461m -363.494m -618.970m
-477.221m -313.301m -511.430m
-386.980m -263.597m -405.149m
-298.248m -214.579m -300.867m
-212.028m -166.582m -200.187m
-130.668m -120.248m -107.496m
-17.375m -40.029m
-2.837m -14.886m
-656.331u
-116.521u -336.317u -201.636u
-10.789u -41.964u -13.420u
-580.051n
-8.803m
-3.451m
-1.195m
-3.014m
-4.632u -416.799n
-27.994n -450.005n -11.484n
-1.269n -41.862n -311.158p
-74.463p
-26.215p
-4.218n -27.092p
-1.078n -18.737p
0.10V
0.20V
0.30V
-22.114p -826.325p -16.303p
-19.278p -754.146p -13.966p
-16.497p -694.188p -11.632p
MOTOROLA
DSP56364 Advance Information
A-47
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.10V
3.20V
3.30V
-13.726p -635.953p
-10.963p -578.437p
-8.203p -521.365p
-5.446p -464.595p
-2.691p -408.039p
62.079f -351.636p
5.566p -239.133p
8.316p -182.975p
11.067p -126.851p
13.817p -70.743p
16.567p -14.634p
-9.300p
-6.968p
-4.637p
-2.307p
22.980f
2.353p
7.011p
9.340p
11.669p
13.998p
16.327p
18.656p
20.985p
23.313p
25.642p
30.300p
32.629p
34.958p
37.288p
39.618p
41.948p
44.279p
46.611p
48.939p
52.772p
54.319p
55.861p
19.317p
22.067p
41.493p
97.654p
24.817p 153.868p
27.568p 210.159p
33.072p 323.083p
35.825p 379.789p
38.581p 436.650p
41.339p 492.867p
44.098p 547.026p
46.849p 600.695p
49.356p 654.682p
51.378p 709.650p
53.315p 776.122p
57.193p
59.183p
4.552n
44.522n
62.959p 466.732n
|
[POWER_clamp]
|
|Voltage
|
I(typ)
I(min)
I(max)
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.10V
5.20V
5.30V
5.40V
5.50V
-26.215p -450.005n -11.632p
-74.463p -4.632u -13.966p
-1.269n -41.964u -16.303p
-27.994n -336.317u -18.737p
-580.051n
-3.014m -27.092p
-10.789u -14.886m -311.158p
-116.521u -40.029m -11.484n
-2.837m -120.248m -13.420u
-17.375m -166.582m -201.636u
-60.888m -214.579m
-130.668m -263.597m
-212.028m -313.301m
-1.195m
-3.451m
-8.803m
-298.248m -363.494m -37.420m
-386.980m -414.052m -107.496m
-477.221m -464.892m -200.187m
-568.461m -515.958m -300.867m
-752.887m -618.610m -511.430m
-845.771m -670.140m -618.970m
-938.979m -721.779m -727.373m
-1.032 -773.514m -836.403m
-1.126 -825.330m -945.908m
A-48
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
5.60V
5.70V
5.80V
5.90V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-1.220 -877.220m
-1.314 -929.174m
-1.408 -981.185m
-1.056
-1.166
-1.276
-1.387
-1.609
-1.720
-1.831
-1.942
-2.054
-2.165
-1.503
-1.691
-1.786
-1.881
-1.975
-2.070
-2.165
-1.033
-1.138
-1.190
-1.242
-1.294
-1.346
-1.399
|
[Ramp]
|Voltage
|
I(typ)
I(min)
I(max)
dV/dt_f
|
2.00/112.556p 1.82/199.937p 2.17/74.356p
dV/dt_r
2.02/146.245p 1.84/252.851p 2.20/93.872p
R_load=10000ohms
| R_load was connected to ground for Ramp_up test and power for Ramp_dn
test
|
|End model
[Model]
ipadni_io
I/O
| ""
Model_type
Vinl = 0.8
Vinh = 2
| variable
C_comp
typ
2.01p
typ
min
1.89p
min
max
2.17p
max
120.0
| variable
[Temperature Range] 40.0
0.0
| variable
[Voltage Range]
|
typ
3.30V
min
3.00V
max
3.60V
[Pulldown]
| pulldown in the table = pulldown subtract gnd_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-157.134u -99.256u -219.000u
-165.037u -104.127u -230.250u
-173.749u -109.479u -242.685u
-183.400u -115.386u -256.500u
-194.148u -121.936u -271.934u
-206.189u -129.240u -289.286u
-219.766u -137.431u -308.933u
-235.190u -146.680u -331.355u
-252.856u -157.199u -357.176u
-273.283u -169.265u -387.219u
-297.162u -183.236u -422.595u
-325.427u -199.590u -464.837u
-359.384u -218.976u -516.117u
-400.901u -242.299u -579.623u
-452.750u -270.851u -660.217u
-519.217u -306.549u -765.681u
MOTOROLA
DSP56364 Advance Information
A-49
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
-607.277u -352.346u -909.270u
-729.045u -413.024u
-907.407u -496.811u
-1.191m -619.011u
-1.699m -811.079u
-1.115m
-1.434m
-1.987m
-3.133m
-6.243m
-2.799m
-5.689m
-10.416m
-12.342m
-11.672m
-10.528m
-9.204m
-7.770m
-6.286m
-4.766m
-3.214m
-1.146m
-1.822m -12.974m
-3.302m -17.948m
-5.449m -17.964m
-6.479m -16.692m
-6.146m -15.152m
-5.387m -13.338m
-4.535m -11.313m
-3.652m
-2.754m
-1.846m
-9.190m
-6.999m
-4.740m
-2.410m
-1.607f
2.391m
-1.627m -928.990u
32.755e-18 18.548e-18
1.604m 910.814u
3.124m
4.566m
5.928m
7.210m
8.411m
1.775m
2.595m
3.372m
4.105m
4.792m
5.432m
6.023m
6.563m
7.051m
7.486m
7.865m
8.189m
47.725m
48.943m
49.908m 136.139m
50.637m 138.902m
51.160m 140.954m
51.534m 142.415m
51.810m 143.449m
52.024m 144.201m
52.201m 144.779m
52.351m 145.246m
52.482m 145.642m
52.600m 145.990m
52.706m 146.303m
52.804m 146.590m
52.895m 146.855m
52.980m 147.104m
53.060m 147.338m
53.135m 147.560m
53.207m 147.772m
53.276m 147.976m
53.343m 148.174m
53.408m 148.367m
4.661m
6.817m
8.858m
10.784m
12.593m
14.284m
15.855m
17.306m
18.639m
19.856m
20.957m
21.944m
22.817m
23.575m
9.529m
10.562m
11.508m
12.367m
13.138m
13.821m
14.417m
14.930m
86.564m
88.497m
89.946m
90.974m
91.689m
92.200m
92.586m
92.895m
93.154m
93.380m
93.581m
93.764m
93.931m
94.087m
94.233m
94.370m
94.500m
94.624m
94.744m
94.859m
94.974m
A-50
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
95.089m
95.208m
95.336m
95.478m
95.641m
95.833m
96.065m
96.347m
96.693m
97.117m
97.636m
98.266m
99.024m
99.931m
101.005m
102.264m
103.730m
105.422m
107.357m
109.556m
112.034m
114.809m
117.897m
121.311m
125.066m
129.172m
133.642m
138.485m
143.709m
149.320m
155.326m
53.475m 148.560m
53.543m 148.757m
53.617m 148.963m
53.699m 149.186m
53.792m 149.436m
53.902m 149.725m
54.035m 150.067m
54.196m 150.479m
54.394m 150.981m
54.635m 151.594m
54.930m 152.342m
55.287m 153.252m
55.716m 154.350m
56.227m 155.666m
56.831m 157.230m
57.539m 159.070m
58.361m 161.218m
59.308m 163.704m
60.391m 166.555m
61.618m 169.801m
63.000m 173.468m
64.545m 177.581m
66.263m 182.163m
68.160m 187.235m
70.245m 192.816m
72.524m 198.924m
75.002m 205.573m
77.685m 212.776m
80.578m 220.544m
83.683m 228.885m
87.004m 237.805m
|
[Pullup]
| pullup in the table = pullup subtract power_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
132.979u 100.794u 170.075u
138.984u 105.115u 178.000u
145.559u 109.825u 186.702u
152.789u 114.981u 196.300u
160.778u 120.648u 206.941u
169.651u 126.906u 218.803u
179.562u 133.852u 232.110u
190.706u 141.605u 247.141u
203.326u 150.317u 264.253u
217.736u 160.174u 283.910u
234.344u 171.418u 306.723u
253.692u 184.362u 333.513u
276.513u 199.421u 365.415u
303.830u 217.155u 404.033u
337.102u 238.340u 451.722u
378.494u 264.081u 512.067u
431.351u 296.004u 590.810u
MOTOROLA
DSP56364 Advance Information
A-51
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
-0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
501.113u 336.601u 697.730u
597.240u 389.880u 850.877u
737.641u 462.700u
960.396u 567.748u
1.361m 731.012u
1.087m
1.497m
2.348m
4.712m
10.148m
12.062m
11.029m
9.778m
8.443m
7.052m
5.644m
4.233m
2.821m
1.410m
2.237m
4.644m
8.090m
8.032m
7.118m
6.128m
5.109m
4.082m
3.056m
2.033m
1.013m
1.583m
2.907m
4.727m
4.754m
4.128m
3.441m
2.746m
2.053m
1.363m
1.014m 678.856u
58.687e-18 58.622e-18 117.504e-18
-987.106u -655.604u
-1.381m
-2.709m
-3.988m
-5.216m
-6.392m
-7.516m
-8.587m
-9.602m
-1.928m
-2.828m
-3.685m
-4.499m
-5.269m
-5.994m
-6.673m
-7.306m
-7.890m
-8.424m
-8.907m
-1.274m
-1.859m
-2.412m
-2.931m
-3.416m
-3.866m
-4.280m
-4.658m -10.561m
-4.999m -11.461m
-5.301m -12.302m
-5.563m -13.081m
-9.339m -47.451m -13.901m
-79.705m -48.954m -118.519m
-82.391m -50.187m -123.324m
-84.713m -51.203m -127.640m
-86.724m -52.057m -131.501m
-88.472m -52.794m -134.939m
-89.996m -53.442m -137.982m
-91.327m -54.017m -140.655m
-92.489m -54.533m -142.987m
-93.511m -54.999m -145.014m
-94.415m -55.424m -146.781m
-95.224m -55.814m -148.333m
-95.955m -56.174m -149.709m
-96.623m -56.510m -150.943m
-97.238m -56.824m -152.063m
-97.809m -57.119m -153.088m
-98.343m -57.398m -154.036m
-98.846m -57.662m -154.920m
-99.320m -57.913m -155.749m
-99.770m -58.152m -156.531m
-100.198m -58.381m -157.272m
-100.607m -58.601m -157.977m
-100.998m -58.812m -158.650m
-101.374m -59.015m -159.295m
A-52
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-101.735m -59.211m -159.914m
-102.084m -59.401m -160.510m
-102.422m -59.585m -161.086m
-102.750m -59.766m -161.644m
-103.070m -59.942m -162.186m
-103.384m -60.117m -162.715m
-103.694m -60.291m -163.234m
-104.002m -60.467m -163.747m
-104.313m -60.647m -164.257m
-104.629m -60.832m -164.770m
-104.955m -61.027m -165.293m
-105.296m -61.234m -165.831m
-105.659m -61.459m -166.394m
-106.050m -61.704m -166.991m
-106.477m -61.975m -167.634m
-106.949m -62.278m -168.334m
-107.474m -62.619m -169.106m
-108.064m -63.003m -169.965m
-108.730m -63.439m -170.928m
-109.483m -63.932m -172.012m
-110.337m -64.492m -173.239m
-111.305m -65.126m -174.627m
-112.401m -65.843m -176.199m
-113.640m -66.651m -177.978m
-115.036m -67.560m -179.986m
-116.606m -68.578m -182.247m
-118.365m -69.715m -184.785m
-120.329m -70.981m -187.626m
-122.513m -72.384m -190.793m
-124.935m -73.935m -194.311m
|
[GND_clamp]
|
|Voltage
|
I(typ)
-2.165
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.242
-1.190
-1.138
-1.033
-2.500
-2.388
-2.277
-2.054
-1.942
-1.831
-1.720
-1.609
-1.498
-1.387
-1.276
-1.166
-2.070
-1.975
-1.786
-1.691 -981.185m
-1.597 -929.174m
-1.503 -877.220m
-1.408 -825.330m
-1.314 -773.514m
-1.220 -721.779m
-1.126 -670.140m
-1.032 -618.610m
-845.771m -515.958m -945.908m
-752.887m -464.892m -836.403m
-660.410m -414.052m -727.373m
-568.461m -363.494m -618.970m
-477.221m -313.301m -511.430m
-386.980m -263.597m -405.149m
MOTOROLA
DSP56364 Advance Information
A-53
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-1.30V
-1.20V
-1.10V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.10V
3.20V
3.30V
-298.248m -214.579m -300.867m
-212.028m -166.582m -200.187m
-130.668m -120.248m -107.496m
-17.375m -40.029m
-2.837m -14.886m
-8.803m
-3.451m
-1.195m
-656.331u
-3.014m
-116.521u -336.317u -201.636u
-10.789u -41.964u -13.420u
-580.051n
-4.632u -416.799n
-27.994n -450.005n -11.484n
-1.269n -41.862n -311.158p
-74.463p
-26.215p
-4.218n -27.092p
-1.078n -18.737p
-22.114p -826.325p -16.303p
-19.278p -754.146p -13.966p
-16.497p -694.188p -11.632p
-13.726p -635.953p
-10.963p -578.437p
-8.203p -521.365p
-5.446p -464.595p
-2.691p -408.039p
62.079f -351.636p
5.566p -239.133p
8.316p -182.975p
11.067p -126.851p
13.817p -70.743p
16.567p -14.634p
-9.300p
-6.968p
-4.637p
-2.307p
22.980f
2.353p
7.011p
9.340p
11.669p
13.998p
16.327p
18.656p
20.985p
23.313p
25.642p
30.300p
32.629p
34.958p
37.288p
39.618p
41.948p
44.279p
46.611p
48.939p
52.772p
54.319p
55.861p
19.317p
22.067p
41.493p
97.654p
24.817p 153.868p
27.568p 210.159p
33.072p 323.083p
35.825p 379.789p
38.581p 436.650p
41.339p 492.867p
44.098p 547.026p
46.849p 600.695p
49.356p 654.682p
51.378p 709.650p
53.315p 776.122p
57.193p
59.183p
4.552n
44.522n
62.959p 466.732n
|
[POWER_clamp]
|
|Voltage
|
I(typ)
I(min)
I(max)
3.30V
3.40V
3.50V
3.60V
3.70V
-26.215p -450.005n -11.632p
-74.463p -4.632u -13.966p
-1.269n -41.964u -16.303p
-27.994n -336.317u -18.737p
-580.051n
-3.014m -27.092p
A-54
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
3.80V
3.90V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-10.789u -14.886m -311.158p
-116.521u -40.029m -11.484n
-2.837m -120.248m -13.420u
-17.375m -166.582m -201.636u
-60.888m -214.579m
-130.668m -263.597m
-212.028m -313.301m
-1.195m
-3.451m
-8.803m
-298.248m -363.494m -37.420m
-386.980m -414.052m -107.496m
-477.221m -464.892m -200.187m
-568.461m -515.958m -300.867m
-752.887m -618.610m -511.430m
-845.771m -670.140m -618.970m
-938.979m -721.779m -727.373m
-1.032 -773.514m -836.403m
-1.126 -825.330m -945.908m
-1.220 -877.220m
-1.314 -929.174m
-1.408 -981.185m
-1.056
-1.166
-1.276
-1.387
-1.609
-1.720
-1.831
-1.942
-2.054
-2.165
-1.503
-1.691
-1.786
-1.881
-1.975
-2.070
-2.165
-1.033
-1.138
-1.190
-1.242
-1.294
-1.346
-1.399
|
[Ramp]
|Voltage
|
I(typ)
I(min)
I(max)
dV/dt_f
|
dV/dt_r
2.00/113.266p 1.82/197.371p 2.17/74.028p
2.02/147.014p 1.84/251.849p 2.20/93.411p
R_load=10000ohms
| R_load was connected to ground for Ramp_up test and power for Ramp_dn
test
|
|End model
[Model]
ipado_3st
3-state
typ
1.99p
typ
| ""
Model_type
| variable
C_comp
| variable
[Temperature Range] 40.0
min
1.86p
min
max
2.15p
max
120.0
0.0
| variable
[Voltage Range]
|
typ
3.30V
min
3.00V
max
3.60V
[Pulldown]
| pulldown in the table = pulldown subtract gnd_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-157.134u -99.256u -219.000u
-165.037u -104.127u -230.250u
MOTOROLA
DSP56364 Advance Information
A-55
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-3.10V
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
-173.749u -109.479u -242.685u
-183.400u -115.386u -256.500u
-194.148u -121.936u -271.934u
-206.189u -129.240u -289.286u
-219.766u -137.431u -308.933u
-235.190u -146.680u -331.355u
-252.856u -157.199u -357.176u
-273.283u -169.265u -387.219u
-297.162u -183.236u -422.595u
-325.427u -199.590u -464.837u
-359.384u -218.976u -516.117u
-400.901u -242.299u -579.623u
-452.750u -270.851u -660.217u
-519.217u -306.549u -765.681u
-607.277u -352.346u -909.270u
-729.045u -413.024u
-907.407u -496.811u
-1.191m -619.011u
-1.699m -811.079u
-1.115m
-1.434m
-1.987m
-3.133m
-6.243m
-2.799m
-5.689m
-10.416m
-12.342m
-11.672m
-10.528m
-9.204m
-7.770m
-6.286m
-4.766m
-3.214m
-1.146m
-1.822m -12.974m
-3.302m -17.948m
-5.449m -17.964m
-6.479m -16.692m
-6.146m -15.152m
-5.387m -13.338m
-4.535m -11.313m
-3.652m
-2.754m
-1.846m
-9.190m
-6.999m
-4.740m
-2.410m
-1.607f
2.391m
-1.627m -928.990u
32.755e-18 18.548e-18
1.604m 910.814u
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
3.124m
4.566m
5.928m
7.210m
8.411m
1.775m
2.595m
3.372m
4.105m
4.792m
5.432m
6.023m
6.563m
7.051m
7.486m
7.865m
8.189m
47.725m
48.943m
49.908m 136.139m
50.637m 138.902m
51.160m 140.954m
51.534m 142.415m
51.810m 143.449m
52.024m 144.201m
4.661m
6.817m
8.858m
10.784m
12.593m
14.284m
15.855m
17.306m
18.639m
19.856m
20.957m
21.944m
22.817m
23.575m
9.529m
10.562m
11.508m
12.367m
13.138m
13.821m
14.417m
14.930m
86.564m
88.497m
89.946m
90.974m
91.689m
92.200m
92.586m
1.80V
1.90V
2.00V
2.10V
A-56
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
92.895m
93.154m
93.380m
93.581m
93.764m
93.931m
94.087m
94.233m
94.370m
94.500m
94.624m
94.744m
94.859m
94.974m
95.089m
95.208m
95.336m
95.478m
95.641m
95.833m
96.065m
96.347m
96.693m
97.117m
97.636m
98.266m
99.024m
99.931m
101.005m
102.264m
103.730m
105.422m
107.357m
109.556m
112.034m
114.809m
117.897m
121.311m
125.066m
129.172m
133.642m
138.485m
143.709m
149.320m
155.326m
52.201m 144.779m
52.351m 145.246m
52.482m 145.642m
52.600m 145.990m
52.706m 146.303m
52.804m 146.590m
52.895m 146.855m
52.980m 147.104m
53.060m 147.338m
53.135m 147.560m
53.207m 147.772m
53.276m 147.976m
53.343m 148.174m
53.408m 148.367m
53.475m 148.560m
53.543m 148.757m
53.617m 148.963m
53.699m 149.186m
53.792m 149.436m
53.902m 149.725m
54.035m 150.067m
54.196m 150.479m
54.394m 150.981m
54.635m 151.594m
54.930m 152.342m
55.287m 153.252m
55.716m 154.350m
56.227m 155.666m
56.831m 157.230m
57.539m 159.070m
58.361m 161.218m
59.308m 163.704m
60.391m 166.555m
61.618m 169.801m
63.000m 173.468m
64.545m 177.581m
66.263m 182.163m
68.160m 187.235m
70.245m 192.816m
72.524m 198.924m
75.002m 205.573m
77.685m 212.776m
80.578m 220.544m
83.683m 228.885m
87.004m 237.805m
|
[Pullup]
| pullup in the table = pullup subtract power_clamp
|Voltage
|
I(typ)
I(min)
I(max)
-3.30V
-3.20V
-3.10V
132.979u 100.794u 170.075u
138.984u 105.115u 178.000u
145.559u 109.825u 186.702u
MOTOROLA
DSP56364 Advance Information
A-57
For More Information On This Product,
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Freescale Semiconductor, Inc.
IBIS Model
-3.00V
-2.90V
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-2.00V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-1.00V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
-0.00V
0.10V
152.789u 114.981u 196.300u
160.778u 120.648u 206.941u
169.651u 126.906u 218.803u
179.562u 133.852u 232.110u
190.706u 141.605u 247.141u
203.326u 150.317u 264.253u
217.736u 160.174u 283.910u
234.344u 171.418u 306.723u
253.692u 184.362u 333.513u
276.513u 199.421u 365.415u
303.830u 217.155u 404.033u
337.102u 238.340u 451.722u
378.494u 264.081u 512.067u
431.351u 296.004u 590.810u
501.113u 336.601u 697.730u
597.240u 389.880u 850.877u
737.641u 462.700u
960.396u 567.748u
1.361m 731.012u
1.087m
1.497m
2.348m
4.712m
10.148m
12.062m
11.029m
9.778m
8.443m
7.052m
5.644m
4.233m
2.821m
1.410m
2.237m
4.644m
8.090m
8.032m
7.118m
6.128m
5.109m
4.082m
3.056m
2.033m
1.013m
1.583m
2.907m
4.727m
4.754m
4.128m
3.441m
2.746m
2.053m
1.363m
1.014m 678.856u
58.687e-18 58.622e-18 117.504e-18
-987.106u -655.604u
-1.381m
-2.709m
-3.988m
-5.216m
-6.392m
-7.516m
-8.587m
-9.602m
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
-1.928m
-2.828m
-3.685m
-4.499m
-5.269m
-5.994m
-6.673m
-7.306m
-7.890m
-8.424m
-8.907m
-1.274m
-1.859m
-2.412m
-2.931m
-3.416m
-3.866m
-4.280m
-4.658m -10.561m
-4.999m -11.461m
-5.301m -12.302m
-5.563m -13.081m
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.00V
-9.339m -47.451m -13.837m
-79.705m -48.954m -118.519m
-82.391m -50.187m -123.324m
-84.713m -51.203m -127.640m
-86.724m -52.057m -131.501m
-88.472m -52.794m -134.939m
-89.996m -53.442m -137.982m
-91.327m -54.017m -140.655m
-92.489m -54.533m -142.987m
-93.511m -54.999m -145.014m
2.10V
2.20V
A-58
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
2.90V
3.00V
3.10V
3.20V
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.00V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.00V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.00V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
-94.415m -55.424m -146.781m
-95.224m -55.814m -148.333m
-95.955m -56.174m -149.709m
-96.623m -56.510m -150.943m
-97.238m -56.824m -152.063m
-97.809m -57.119m -153.088m
-98.343m -57.398m -154.036m
-98.846m -57.662m -154.920m
-99.320m -57.913m -155.749m
-99.770m -58.152m -156.531m
-100.198m -58.381m -157.272m
-100.607m -58.601m -157.977m
-100.998m -58.812m -158.650m
-101.374m -59.015m -159.295m
-101.735m -59.211m -159.914m
-102.084m -59.401m -160.510m
-102.422m -59.585m -161.086m
-102.750m -59.766m -161.644m
-103.070m -59.942m -162.186m
-103.384m -60.117m -162.715m
-103.694m -60.291m -163.234m
-104.002m -60.467m -163.747m
-104.313m -60.647m -164.257m
-104.629m -60.832m -164.770m
-104.955m -61.027m -165.293m
-105.296m -61.234m -165.831m
-105.659m -61.459m -166.394m
-106.050m -61.704m -166.991m
-106.477m -61.975m -167.634m
-106.949m -62.278m -168.334m
-107.474m -62.619m -169.106m
-108.064m -63.003m -169.965m
-108.730m -63.439m -170.928m
-109.483m -63.932m -172.012m
-110.337m -64.492m -173.239m
-111.305m -65.126m -174.627m
-112.401m -65.843m -176.199m
-113.640m -66.651m -177.978m
-115.036m -67.560m -179.986m
-116.606m -68.578m -182.247m
-118.365m -69.715m -184.785m
-120.329m -70.981m -187.626m
-122.513m -72.384m -190.793m
-124.935m -73.935m -194.311m
|
[GND_clamp]
|
|Voltage
|
I(typ)
-2.165
I(min)
I(max)
-3.30V
-3.20V
-3.10V
-2.90V
-1.242
-1.190
-1.138
-1.033
-2.500
-2.388
-2.277
-2.054
-2.070
-1.975
-1.786
MOTOROLA
DSP56364 Advance Information
A-59
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
-2.80V
-2.70V
-2.60V
-2.50V
-2.40V
-2.30V
-2.20V
-2.10V
-1.90V
-1.80V
-1.70V
-1.60V
-1.50V
-1.40V
-1.30V
-1.20V
-1.10V
-0.90V
-0.80V
-0.70V
-0.60V
-0.50V
-0.40V
-0.30V
-0.20V
-0.10V
0.00V
0.10V
0.20V
0.30V
0.40V
0.50V
0.60V
0.70V
0.80V
0.90V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.90V
2.10V
2.20V
2.30V
2.40V
2.50V
2.60V
2.70V
2.80V
-1.691 -981.185m
-1.597 -929.174m
-1.503 -877.220m
-1.408 -825.330m
-1.314 -773.514m
-1.220 -721.779m
-1.126 -670.140m
-1.032 -618.610m
-1.942
-1.831
-1.720
-1.609
-1.498
-1.387
-1.276
-1.166
-845.771m -515.958m -945.908m
-752.887m -464.892m -836.403m
-660.410m -414.052m -727.373m
-568.461m -363.494m -618.970m
-477.221m -313.301m -511.430m
-386.980m -263.597m -405.149m
-298.248m -214.579m -300.867m
-212.028m -166.582m -200.187m
-130.668m -120.248m -107.496m
-17.375m -40.029m
-2.837m -14.886m
-8.803m
-3.451m
-1.195m
-656.331u
-3.014m
-116.521u -336.317u -201.636u
-10.789u -41.964u -13.420u
-580.051n
-4.632u -416.799n
-27.994n -450.005n -11.484n
-1.269n -41.862n -311.158p
-74.463p
-26.215p
-4.218n -27.092p
-1.078n -18.737p
-22.114p -826.325p -16.303p
-19.278p -754.146p -13.966p
-16.497p -694.188p -11.632p
-13.726p -635.953p
-10.963p -578.437p
-8.203p -521.365p
-5.446p -464.595p
-2.691p -408.039p
62.079f -351.636p
5.566p -239.133p
8.316p -182.975p
11.067p -126.851p
13.817p -70.743p
16.567p -14.634p
-9.300p
-6.968p
-4.637p
-2.307p
22.980f
2.353p
7.011p
9.340p
11.669p
13.998p
16.327p
18.656p
20.985p
23.313p
25.642p
30.300p
32.629p
34.958p
37.288p
39.618p
41.948p
44.279p
46.611p
19.317p
22.067p
41.493p
97.654p
24.817p 153.868p
27.568p 210.159p
33.072p 323.083p
35.825p 379.789p
38.581p 436.650p
41.339p 492.867p
44.098p 547.026p
46.849p 600.695p
49.356p 654.682p
51.378p 709.650p
A-60
DSP56364 Advance Information
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IBIS Model
2.90V
3.10V
3.20V
3.30V
53.315p 776.122p
48.939p
52.772p
54.319p
55.861p
57.193p
59.183p
4.552n
44.522n
62.959p 466.732n
|
[POWER_clamp]
|
|Voltage
|
I(typ)
I(min)
I(max)
3.30V
3.40V
3.50V
3.60V
3.70V
3.80V
3.90V
4.10V
4.20V
4.30V
4.40V
4.50V
4.60V
4.70V
4.80V
4.90V
5.10V
5.20V
5.30V
5.40V
5.50V
5.60V
5.70V
5.80V
5.90V
6.10V
6.20V
6.30V
6.40V
6.50V
6.60V
|
-26.215p -450.005n -11.632p
-74.463p -4.632u -13.966p
-1.269n -41.964u -16.303p
-27.994n -336.317u -18.737p
-580.051n
-3.014m -27.092p
-10.789u -14.886m -311.158p
-116.521u -40.029m -11.484n
-2.837m -120.248m -13.420u
-17.375m -166.582m -201.636u
-60.888m -214.579m
-130.668m -263.597m
-212.028m -313.301m
-1.195m
-3.451m
-8.803m
-298.248m -363.494m -37.420m
-386.980m -414.052m -107.496m
-477.221m -464.892m -200.187m
-568.461m -515.958m -300.867m
-752.887m -618.610m -511.430m
-845.771m -670.140m -618.970m
-938.979m -721.779m -727.373m
-1.032 -773.514m -836.403m
-1.126 -825.330m -945.908m
-1.220 -877.220m
-1.314 -929.174m
-1.408 -981.185m
-1.056
-1.166
-1.276
-1.387
-1.609
-1.720
-1.831
-1.942
-2.054
-2.165
-1.503
-1.691
-1.786
-1.881
-1.975
-2.070
-2.165
-1.033
-1.138
-1.190
-1.242
-1.294
-1.346
-1.399
[Ramp]
|Voltage
|
I(typ)
I(min)
I(max)
dV/dt_f
|
dV/dt_r
1.99/130.331p 1.81/220.000p 2.17/83.712p
2.03/153.657p 1.84/260.814p 2.20/92.663p
R_load=10000ohms
| R_load was connected to ground for Ramp_up test and power for Ramp_dn
test
|
|End model
[End]
MOTOROLA
DSP56364 Advance Information
A-61
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INDEX
A
E
ac electrical characteristics 4
electrical design considerations 2, 3
emory 3
B
Enhanced Serial Audio Interface 11
ESAI 11
receiver timing 60, 61
timings 56
transmitter timing 59
EXTAL jitter 4
external address bus 6
external bus control 6, 7
external clock operation 5
external data bus 6
Boundary Scan (JTAG Port) timing diagram 64
bus
external address 6
external data 6
C
case outline drawing 6
Clock 5
clock
external interrupt timing (negative edge-triggered)
14
external level-sensitive fast interrupt timing 13
external memory access (DMA Source) timing 15
External Memory Expansion Port 6, 16
external 5
operation 6
clocks
internal 5
configuration 3
F
D
functional signal groups 1
dc electrical characteristics 3
design considerations
electrical 2, 3
G
GPIO timing 61
Ground 4
PLL 4
PLL 4
power consumption 3
thermal 1
DRAM
I
out of page
wait states selection guide 32
write access 44
internal clocks 5
interrupt and mode control 8
interrupt control 8
out of page and refresh timings
11 wait states 39
15 wait states 41
4 wait states 32
8 wait states 35
Page mode
interrupt timing 8
external level-sensitive fast 13
external negative edge-triggered 14
J
read accesses 31
wait states selection guide 21
write accesses 30
Page mode timings
1 wait state 22
Jitter 4
JTAG 15
JTAG Port
timing 63, 64
M
2 wait states 24
3 wait states 26
maximum ratings 1, 2
mechanical drawings 6
Memory 3
4 wait states 28
refresh access 45
Memory Configuration 3
Mfax system 6
MOTOROLA
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For More Information On This Product,
Index-i
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Index
mode control 8
Enhanced Serial Audio Interface (ESAI) 59
Mode select timing 8
General Purpose I/O (GPIO) Timing 56
OnCE™ (On Chip Emulator) Timing 56
Serial Host Interface (SHI) SPI Protocol
Timing 46
O
OnCE module 15
operating mode select timing 14
ordering drawings 6
Serial Host Interface (SHI) Timing 46
timing
interrupt 8
mode select 8
Reset 8
P
package
Stop 8
TQFP description 1, 3
Peripheral modules 3
Phase Lock Loop 7
PLL 5, 7
TQFP
pin list by number 3
pin-out drawing (top) 1
TQFP package drawing 6
Characteristics 7
performance issues 4
PLL design considerations 4
PLL performance issues 4
Port A 6
Port C 11
Power 2
power consumption design considerations 3
R
recovery from Stop state using IRQA 14, 15
RESET 8
Reset timing 8, 12
S
Serial Audio Interface (ESAI) 3
Serial Host Interface 9
Serial Host Interface (SHI) 3
SHI 9
signal groupings 1
signals 1
SRAM
read access 19
read and write accesses 16
write access 20
Stop state
recovery from 14, 15
Stop timing 8
supply voltage 2
T
Test Access Port timing diagram 64
Test Clock (TCLK) input timing diagram 63
thermal characteristics 2
thermal design considerations 1
Timing
Index-ii
DSP56364 Advance Information
MOTOROLA
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HOW TO REACH US:
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HOME PAGE:
http://motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to use Motorola products.
There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or
integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume
any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical
experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not
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names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
© Motorola Inc. 2003
DSP56364/D
Rev. 3.2
09/2003
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