SG1577A_10_技术文档

August 2010

SG1577A

Dual Synchronous DC/DC Controller

Features

Description

The SG1577A is a high-efficiency, voltage-mode, dual-

channel, synchronous DC/DC PWM controller for two

independent outputs. The two channels are operated

out of phase. The internal reference voltage is trimmed

to 0.7V±1.5%. It is connected to the error amplifier’s

positive terminal for voltage feedback regulation.

Integrated Two Sets of MOSFET Drivers

Two Independent PWM Controllers

Constant Frequency Operation: Free-Running

Fixed Frequency Oscillator Programmable:

61kHz to 340kHz

The soft-start circuit ensures the output voltage can be

gradually and smoothly increased from zero to its final

regulated value. The soft-start pin can also be used for

chip-enable function. When two soft-start pins are

grounded, the chip is disabled and the total operation

current can be reduced to under 0.7mA.

Maximum Input Supply Voltage: 15V

Programmable Output as Low as 0.7V

Internal Error Amplifier Reference Voltage:

0.7V±1.5%

Two Soft-Start / EN Functions

The fixed-frequency is programmable from 60kHz to

340kHz. The Over-Current Protection (OCP) level can

be programmed by an external current-sense resistor. It

has two integrated sets of internal MOSFET drivers.

Programmable Over-Current Protection (OCP)

30V HIGH Voltage Pin for Bootstrap Voltage

Output Over-Voltage Protection (OVP)

20-Pin SOP

SG1577A is available in a 20-pin SOP package.

Applications

CPU and GPU Vcore Power Supply

Power Supply Requiring Two Independent Outputs

Ordering Information

Part Number

Operating Temperature Range

-40°C to +105°C

Package

Packing Method

20-Lead, Small Outline Package

(SOP-20)

SG1577ASY

Tape & Reel

SG1577A • Rev. 1.0.2

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Application Diagram

Figure 1.

Typical Application

Internal Block Diagram

Figure 2.

Functional Block Diagram

SG1577A • Rev. 1.0.2

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2

Marking Diagram

SOP-20

F: Fairchild Logo

Z: Assembly Plant Code

X: Year Code

Y: Week Code

TT: Die Run Code

T: S = SOP

20

ZXYTT

SG1577A

TPM

P: Y=Green Package

M: Mask Version

1

SG1577A • Rev. 1.0.2

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3

Pin Configuration

Figure 3. SOP-20 Pin Configuration (Top View)

Pin Definitions

Name

Pin #

Type

Description

Switching frequency programming pin. An external resistor connecting

this pin to GND can program the switching frequency. The switching

frequency is 61kHz when RT is open and becomes 340kHz when RT is

shorted to ground.

RT

1

Frequency Select

Inverting input of the error amplifier. It is normally connected to the

switching power supply output through a resistor divider.

IN1

2

3

4

5

Feedback

Output of the error amplifier and input to the PWM comparator. It is used

for feedback loop compensation.

COMP1

SS1/ENB

CLP1

Compensation

Soft Start/Enable

A 35/15µA internal current source charging an external capacitor for soft-

start. Pull down this pin and pin 17 to disable the chip.

Over Current

Protection

Over-current protection for high-side MOSFET. Connect a resistor from

this pin to the high-side supply voltage to program the OCP level.

BST1

DH1

6

7

Boost Supply

Supply for high-side driver. Connect to the internal bootstrap circuit.

High-Side Drive Channel 1, high-side MOSFET gate driver pin.

Switch-node connection to inductor. For channel 1 high-side driver’s

reference ground.

Low-Side Drive Low-side MOSFET gate driver pin.

CLN1

8

Switch Node

DL1

PGND

VCC

DL2

9

10

11

12

Driver Ground

Power Supply

Driver circuit reference. Connect to low-side MOSFET GND.

Supply voltage input.

Low-Side Drive Low-side MOSFET gate driver pin.

Switch-node connection to inductor. For channel 2, high-side driver’s

reference ground.

High-Side Drive Channel 2 high-side MOSFET gate driver pin.

CLN2

13

Switch Node

DH2

14

15

BST2

Boost Supply

Supply for high-side driver. Connect to the internal bootstrap circuit.

Over-Current

Protection

Over-current protection for the high-side MOSFET. Connect a resistor

from this pin to the high-side supply voltage to program the OCP level.

CLP2

16

17

18

A 35/15µA internal current source charging an external capacitor for soft-

start. Pull down this pin and pin 4 to disable the chip.

SS2/ENB

COMP2

Soft-Start/Enable

Compensation

Feedback

Output of the error amplifier and input to the PWM comparator. It is used

for feedback-loop compensation.

Inverting input of the error amplifier. It is normally connected to the

switching power supply output through a resistor divider.

IN2

19

20

GND

Analog Ground The reference of internal control circuits.

SG1577A • Rev. 1.0.2

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4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are

given with respect to the network ground terminal. Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device.

Symbol

Parameter

Supply Voltage, VCC to GND

Min.

Max.

Unit

V_CC

16

V

BST1(or 2) -

CLN1(or 2)

BST1(2) to CLN1(2)

16

18

V

CLN1(or 2) -

GND

CLN1(2) to GND for 100ns Transient

BST1(2) to GND for 100ns Transient

-4

BST1(or 2) -

GND

30

DH1(or 2) -

CLN1(or 2)

16

CLN1(or 2),

DL1(or 2)

-0.3

V_CC+0.3

PGND

Θ_JA

PGND to GND

± 1

90

V

°C/W

°C

Thermal Resistance, Junction-Air

Operating Junction Temperature

Storage Temperature Range

T_J

-40

-65

+125

+150

2

T_STG

°C

Human Body Model (HBM)

Charged Device Model (CDM)

Electrostatic Discharge

Protection Level

ESD

kV

1

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol

V_CC

Parameter

Min.

Max.

+15

Unit

V

Supply Voltage

Operating Ambient Temperature

-40

T_A

+105

°C

SG1577A • Rev. 1.0.2

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5

Electrical Characteristics

V_CC=12V, T_A=25°C, unless otherwise noted.

Symbol

VCC UVLO

V_{CC_ON}

Parameter

Conditions

Min.

Typ.

Max.

Unit

Turn-On Threshold

UVLO Hysteresis

VCC Ramp-Up

9.5

1.5

10.0

2.0

10.5

2.5

V

VCC Ramp-Down

V_{CC_HYS}

Oscillator

R_RT=OPEN

R_RT=GND

55

308

-10

85

61

67

372

10

Oscillator Frequency

f_osc

KHz

340

20kΩ＜R_RT

Total Accuracy

f_osc,rt

%

90

95

Maximum Duty Cycle

D_{ON_MAX}

Error Amplifier

Internal Reference Voltage

V_REFTemperature Coefficient T_A=0~85^oC

V_CC=8V, V_CC=15V

V_REF

△V_REF

A_VOL

0.6895 0.7000 0.7105

V

mV/^oC

dB

(1)

0.03

77

Open-loop Voltage Gain

Unity Gain Bandwidth

Output Source Current

Output Sink Current

The Peak of VRAMP

BW

3.5

MHz

µA

IN1=IN2=0.6V

I_SOURCE

I_SINK

V_{RAMP_Peak}

V _{RAMP_Valley}

60

80

400

2.8

1.2

100

550

IN1=IN2=0.8V

250

2.45

1.05

µA

Gate Output=D_{ON_MAX}

No Gate Output

3.15

1.35

V

The Valley of VRAMP

Two-Stage Soft-Start

1^stSoft-start Charge Current

^ndSoft-start Charge Current

st

V

_CLP＜V_CLN, VSS_Transition＞V_SS

_CLP＜V_CLN, VSS_Transition＜V_SS

I_{SOURCE_1}

28

13

35

16

42

19

µA

nd

V

2

I_{SOURCE_2}

nd

I_{SOURCE_1}^stTransit to I_{SOURCE_2}

Soft-start Transition Point

VSS_Transition

1.40

1.42

50

1.44

V

See Figure 4

V_CLP＞V_CLN

Soft-start Discharge Current

I_SINK

Protections

I_OCSET

µA

90

120

150

20

150

126

3.8

µA

°C

%

OC Sink Current

V_CC=12V

T_OT

Over-Temperature

T_{OT_hys}

V_OVP

Over-Temperature Hysteresis

118

1.0

50

122

Over-Voltage Protection of IN V_OVP/V_IN

Output

I_DH

1.8

2.8

1.8

2.8

70

A

Ω

A

High-Side Current Source

High-Side Sink Resistor

Low-Side Current Source

Low-Side Sink Resistor

Dead Time

V_BST- V_CLN=12V, V_DH- V_CLN=6V

V_BST- V_CLN=12V

R_DH

I_DL

V_CC=12V, V_DL=6V

R_DL

3.8

90

Ω

ns

V_CC=12V

(2)

T_DT

V_CC=12V, D_H& D_L=1000pF

Total Operating Current

I_{CC_OP}

3.3

4.3

0.7

5.3

1.0

mA

Operating Supply Current

Standby Current (Disabled)

V_CC=12V, No load

I_{CC_SBY}

SS1/ENB=SS2/ENB=0V

Notes:

1. Not tested in production, 30pcs sample.

2. When V_DLfalls less than 2V relative to V_DHrising to 2V.

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SG1577A • Rev. 1.0.2

6

Timing Diagrams

Figure 4. Timing Chart of Two-Stage Soft-Start

SG1577A • Rev. 1.0.2

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7

Typical Performance Characteristics

Unless otherwise noted, values are for V_CC=12V, T_A=+25°C, C_SS1/ENB=150nF and C_SS2/ENB=168nF.

Figure 5. Power On at 0.3A Load

Figure 7. Power On at 9A Load

Figure 9. Power Off with 0.3A Load

Figure 6. Power On at 3.6A Load

Figure 8. Power On at 18A Load

Figure 10. Power Off with 18A Load

SG1577A • Rev. 1.0.2

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Typical Performance Characteristics (Continued)

Unless otherwise noted, values are for V_CC=12V, T_A=+25°C, C_SS1/ENB=150nF and C_SS2/ENB=168nF.

Figure 11. Phase Shift at 0.3A Load

Figure 12. Phase Shift at 18A Load

Figure 13. Dead Time at 0.3A Load (Rising Edge)

Figure 14. Dead Time at 0.3A Load (Falling Edge)

Figure 15. Dead Time at 18A Load (Rising Edge)

Figure 16. Dead Time at 18A Load (Falling Edge)

SG1577A • Rev. 1.0.2

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9

Typical Performance Characteristics (Continued)

Unless otherwise noted, values are for V_CC=12V, T_A=+25°C, C_SS1/ENB=150nF and C_SS2/ENB=168nF.

Figure 17. Load Transient Response (Step-Up)

Figure 18. Load Transient Response (Step-Down)

20kΩ/22nF in Compensation Loop

Figure 19. Over-Current Protection (OCP)

Figure 20. Over-Current Protection (“Hiccup” Mode)

150

Iocset 1

140

130

120

110

100

90

Iocset 2

-40

-25

-10

5

20

35

50

65

80

95

Temperature (^oC)

Figure 21. Over-Voltage Protection (OVP)

Figure 22. I_OCSETvs. Temperature

SG1577A • Rev. 1.0.2

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10

Functional Description

The SG1577A is a dual-channel voltage-mode PWM

controller. It has two sets of synchronous MOSFET

driving circuits. The two channels are running 180-

degrees out of phase. The following descriptions

highlight the advantages of the SG1577A design.

compensation externally. Non-inverting inputs are

internally tied to a fixed 0.7V ± 1.5% reference voltage.

Oscillator Operation

The SG1577A has

a

frequency-programmable

oscillator. The oscillator is running at 61kHz when the

RT pin is floating. The oscillator frequency can be

adjusted from 61kHz up to 340kHz by an external

resistor R^RTbetween RT pin and the ground. The

oscillator generates a sawtooth wave that has 90%

rising duty. Sawtooth wave voltage threshold is from

1.2V to 2.8V. The frequency of oscillator can be

programmed according to the following equation:

Soft Start

An internal start-up current (35/15µA) flows out of

SS/EN pin to charge an external capacitor. During the

startup sequence, SG1577A isn’t enabled until the

SS/ENB pin is higher than 1.2V. From 1.2V to (1.2 + 1.6

x D_ON/ D_{ON_MAX}) V, the PWM duty cycle gradually

increases following the SS/ENB pin voltage to bring

output rising. After (1.2 + 1.6 x D_ON/ D_{ON_MAX}) V, the

soft-start period ends and SS/ENB pin continually rises

to 4.8V. When input power is abnormal, the external

capacitor on the SS pin is shorted to ground and the

chip is disabled.

(3)

f_OSC, RT(kHz) = 61kHz + 8522 / R_RT(kΩ)

Output Driver

The high-side gate drivers need an external

bootstrapping circuit to provide the required boost

voltage. The highest gate driver’s output (15V is the

allowed) on high-side and low-side MOSFETs forces

external MOSFETs to have the lowest R_DS(ON), which

results in higher efficiency.

5

12

0.9

C_SS1× (1.4V - 1.2V) =35μA × t₁; C_SS1×(1.2V +1.6 ×

- 1.4V) =15μA × t₂

; t₁+ t₂= t_SS1

3.3

12

0.9

C_SS2×(1.4V -1.2V) = 35μA × t₁; C_SS2× (1.2V +1.6 ×

- 1.4V) =15μA × t₂

(1)

; t₁+ t₂= t_SS2

C_SS2×0.3V C_SS2×(1.2V - 0.3V)

Over-Temperature Protection (OTP)

The device is over-temperature protected. When chip

temperature is over 150^oC, the chip enters tri-state

(high-side driver is turned off). The hysteresis is 20^oC.

C_SS1×1.2V = 35μA × t₃;

+

= t₄

15μA

35μA

;t₄- t₃= t_time-shift

Over-Current Protection (OCP)

Over-current protection is implemented by sensing the

voltage drop across the drain and the source of external

high-side MOSFET. Over-current protection is triggered

when the voltage drop on external high-side MOSFET’s

R^DS(ON)is greater than the programmable current limit

voltage threshold. 120µA flowing through an external

resistor between input voltage and the CLP pin sets the

threshold of current limit voltage. When over-current

condition is true, the system is protected against the

cycle-by-cycle current limit. A counter counts a series of

over-current peak values to eight cycles; the soft-start

capacitor is discharged by a 50µA current until the

voltage on SS pin reaches 1.2V. During the discharge

period, the high-side driver is turned off and the low-

side driver is turned on. Once the voltage on SS/ENB

pin is under 1.2V, the normal soft-start sequence is

initiated and the 35/15µA current charges the soft-start

capacitor again.

Type II Compensation Design

(for Output Capacitors with High ESR)

SG1577A is a voltage-mode controller; the control loop

is a single voltage feedback path, including an error

amplifier and PWM comparator, as shown in Figure 23.

To achieve fast transient response and accurate output

regulation, an adequate compensator design is

necessary. A stable control loop has a 0dB gain

crossing with -20dB/decade slope and a phase margin

greater than 45°.

I_L(OCP)= [(R_SENSEx I_OCSET+ V_OFFSET) / R_DS(ON)

(V_IN- V_OUT) x V_OUT/ (f_OSCx L_OUTx V_INx 2) ]

-

(2)

where VOFFSET ( ≒ 10mV) is the offset voltage

contributed by the internal OCP comparator.

Error Amplifier

The IN1 and IN2 pins are connected to the

corresponding internal error amplifier’s inverting input

and the outputs of the error amplifiers are connected to

the corresponding COMP1 and COMP2 pins. The

COMP1 and COMP2 pins are available for control-loop

Figure 23. Closed Loop

SG1577A • Rev. 1.0.2

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11

1. Modulator Frequency Equations

The modulator transfer function is the small-signal

transfer function of V_OUT/V_E/A. This transfer function is

dominated by a DC gain and the output filter (L_Oand

C_O) with a double-pole frequency at f_LCand a zero at

f_P1= 0

f_Z1

1

=

2π × R₂× C₂

(6)

1

f

_ESR. The DC gain of the modulator is the input voltage

f_P2

=

2π × R₂× (C₁//C₂)

(V_IN) divided by the peak-to-peak oscillator voltage

ΔV_RAMP(=1.6V). The first step is to calculate the complex

conjugate poles contributed by the LC output filter. The

Figure 25 shows the DC-DC converter gain vs.

frequency. The compensation gain uses external

impedance networks Z_Cand Z_fto provide a stable, high-

bandwidth loop.

output LC filter introduces

a

double pole,

-40dB / decade gain slope above its corner resonant

frequency, and a total phase lag of 180 degrees. The

resonant frequency of the LC filter expressed as:

High crossover frequency is desirable for fast transient

response, but often jeopardizes system stability. To

cancel one of the LC filter poles, place the zero before

the LC filter resonant frequency. Place the zero at 75%

of the LC filter resonant frequency. Crossover frequency

should be higher than the ESR zero, but less than 1/5

of the switching frequency. The second pole should be

placed at half the switching frequency.

1

f

=

P(LC)

(4)

2π ×

L × C

O O

The next step of compensation design is to calculate

the ESR zero. The ESR zero is contributed by the ESR

associated with the output capacitance. Note that this

requires that the output capacitor should have enough

ESR to satisfy stability requirements. The ESR zero of

the output capacitor is expressed as:

1

f

=

(5)

Z(ESR)

2π × C × ESR

O

2. Compensation Frequency Equations

The compensation network consists of the error

amplifier and the impedance networks Z_Cand Z_f, as

Figure 24 shows.

Figure 25. Bode Plot

Figure 24. Compensation Loop

SG1577A • Rev. 1.0.2

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12

Layout Considerations

Layout is important in high-frequency switching converter

design. If designed improperly, PCB can radiate

excessive noise and contribute to converter instability.

Place the bootstrap capacitor near the BSTx and

CLNx pins.

The resistor on the RT pin should be near this pin

and the GND return should be short and kept away

from the noisy MOSFET’s GND (which is shorted

together with IC’s PGND pin to GND plane on back

side of PCB).

Place the PWM power stage components first. Mount

all the power components and connections in the top

layer with wide copper areas. The MOSFETs of buck,

inductor, and output capacitor should be as close to

each other as possible to reduce the radiation of EMI

due to the high-frequency current loop. If the output

capacitors are placed in parallel to reduce the ESR of

capacitor, equal sharing ripple current should be

considered. Place the input capacitor near the drain of

high-side MOSFET. In multi-layer PCB, use one layer

as power ground and have a separate control signal

ground as the reference for all signals. To avoid the

signal ground being affected by noise and to achieve

the best load regulation, it should be connected to the

ground terminal of output.

Place the compensation components close to the

INx and COMPx pins.

The feedback resistors for both regulators should

be located as close as possible to the relevant INx

pin with vias tied straight to the ground plane as

required.

Minimize the length of the connections between the

input capacitors, CIN, and the power switchers

(MOSFETs) by placing them nearby.

Position both the ceramic and bulk input capacitors

as close to the upper MOSFET drain as possible

and make the GND returns short (from the source

of lower MOSFET to V_INcapacitor GND).

Follow the below guidelines for best performance:

A two-layer printed circuit board is recommended.

Use the bottom layer of the PCB as a ground plane

and make all critical component ground

connections through vias to this layer.

Position the output inductor and output capacitors

between the upper MOSFET and lower MOSFET

and the load.

Keep the metal running from the CLNx terminal to

the output inductor short.

Keep AGND on the clearer plane and away from

the noisy MOSFET GND.

Use copper-filled polygons on the top (and bottom,

if two-layer PCB) circuit layers for the CLN node.

PGND should be short, together with MOSFET

GND, then through vias to GND plane on the

bottom of PCB.

The small-signal wiring traces from the DLx and

DHx pins to the MOSFET gates should be kept

short and wide enough to easily handle the several

amps of drive current.

Prevent a spike on the CLN pin with a proper

snubber circuit for CLN and GND.

The critical, small-signal components include any

bypass capacitors (SMD-type of capacitors applied

at VCC and SSx/ENB pins), feedback components

(resistor divider), and compensation components

(between INx and COMPx pins). Position those

components close to their pins with a local, clear,

GND connection or directly to the ground plane.

SG1577A • Rev. 1.0.2

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13

Physical Dimensions

13.00

12.60

A

11.43

20

11

B

9.50

10.65 7.60

10.00 7.40

2.25

1

PIN ONE

INDICATOR

10

0.65

0.51

0.35

1.27

M

0.25

C B A

LAND PATTERN RECOMMENDATION

SEE DETAIL A

2.65 MAX

0.33

0.20

C

0.10

C

0.30

0.10

SEATING PLANE

0.75

0.25

X 45°

NOTES: UNLESS OTHERWISE SPECIFIED

(R0.10)

A) THIS PACKAGE CONFORMS TO JEDEC

MS-013, VARIATION AC, ISSUE E

GAGE PLANE

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

0.25

8°

0°

D) CONFORMS TO ASME Y14.5M-1994

1.27

0.40

SEATING PLANE

E) LANDPATTERN STANDARD: SOIC127P1030X265-20L

F) DRAWING FILENAME: MKT-M20BREV3

(1.40)

DETAIL A

SCALE: 2:1

Figure 26. 20-Lead Small Outline Package (SOP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

SG1577A • Rev. 1.0.2

www.fairchildsemi.com

14

SG1577A • Rev. 1.0.2

www.fairchildsemi.com

15


型号：	SG1577A_10
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Dual Synchronous DC/DC Controller 双同步DC / DC控制器控制器
文件：	总15页 (文件大小：850K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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